1#ifndef __SOUND_ICE1712_H
2#define __SOUND_ICE1712_H
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25#include <linux/io.h>
26#include <sound/control.h>
27#include <sound/ac97_codec.h>
28#include <sound/rawmidi.h>
29#include <sound/i2c.h>
30#include <sound/ak4xxx-adda.h>
31#include <sound/ak4114.h>
32#include <sound/pt2258.h>
33#include <sound/pcm.h>
34#include <sound/mpu401.h>
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39
40
41#define ICEREG(ice, x) ((ice)->port + ICE1712_REG_##x)
42
43#define ICE1712_REG_CONTROL 0x00
44#define ICE1712_RESET 0x80
45#define ICE1712_SERR_LEVEL 0x04
46#define ICE1712_NATIVE 0x01
47#define ICE1712_REG_IRQMASK 0x01
48#define ICE1712_IRQ_MPU1 0x80
49#define ICE1712_IRQ_TIMER 0x40
50#define ICE1712_IRQ_MPU2 0x20
51#define ICE1712_IRQ_PROPCM 0x10
52#define ICE1712_IRQ_FM 0x08
53#define ICE1712_IRQ_PBKDS 0x04
54#define ICE1712_IRQ_CONCAP 0x02
55#define ICE1712_IRQ_CONPBK 0x01
56#define ICE1712_REG_IRQSTAT 0x02
57
58#define ICE1712_REG_INDEX 0x03
59#define ICE1712_REG_DATA 0x04
60#define ICE1712_REG_NMI_STAT1 0x05
61#define ICE1712_REG_NMI_DATA 0x06
62#define ICE1712_REG_NMI_INDEX 0x07
63#define ICE1712_REG_AC97_INDEX 0x08
64#define ICE1712_REG_AC97_CMD 0x09
65#define ICE1712_AC97_COLD 0x80
66#define ICE1712_AC97_WARM 0x40
67#define ICE1712_AC97_WRITE 0x20
68#define ICE1712_AC97_READ 0x10
69#define ICE1712_AC97_READY 0x08
70#define ICE1712_AC97_PBK_VSR 0x02
71#define ICE1712_AC97_CAP_VSR 0x01
72#define ICE1712_REG_AC97_DATA 0x0a
73#define ICE1712_REG_MPU1_CTRL 0x0c
74#define ICE1712_REG_MPU1_DATA 0x0d
75#define ICE1712_REG_I2C_DEV_ADDR 0x10
76#define ICE1712_I2C_WRITE 0x01
77#define ICE1712_REG_I2C_BYTE_ADDR 0x11
78#define ICE1712_REG_I2C_DATA 0x12
79#define ICE1712_REG_I2C_CTRL 0x13
80#define ICE1712_I2C_EEPROM 0x80
81#define ICE1712_I2C_BUSY 0x01
82#define ICE1712_REG_CONCAP_ADDR 0x14
83#define ICE1712_REG_CONCAP_COUNT 0x18
84#define ICE1712_REG_SERR_SHADOW 0x1b
85#define ICE1712_REG_MPU2_CTRL 0x1c
86#define ICE1712_REG_MPU2_DATA 0x1d
87#define ICE1712_REG_TIMER 0x1e
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92
93#define ICE1712_IREG_PBK_COUNT_LO 0x00
94#define ICE1712_IREG_PBK_COUNT_HI 0x01
95#define ICE1712_IREG_PBK_CTRL 0x02
96#define ICE1712_IREG_PBK_LEFT 0x03
97#define ICE1712_IREG_PBK_RIGHT 0x04
98#define ICE1712_IREG_PBK_SOFT 0x05
99#define ICE1712_IREG_PBK_RATE_LO 0x06
100#define ICE1712_IREG_PBK_RATE_MID 0x07
101#define ICE1712_IREG_PBK_RATE_HI 0x08
102#define ICE1712_IREG_CAP_COUNT_LO 0x10
103#define ICE1712_IREG_CAP_COUNT_HI 0x11
104#define ICE1712_IREG_CAP_CTRL 0x12
105#define ICE1712_IREG_GPIO_DATA 0x20
106#define ICE1712_IREG_GPIO_WRITE_MASK 0x21
107#define ICE1712_IREG_GPIO_DIRECTION 0x22
108#define ICE1712_IREG_CONSUMER_POWERDOWN 0x30
109#define ICE1712_IREG_PRO_POWERDOWN 0x31
110
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114
115#define ICEDS(ice, x) ((ice)->dmapath_port + ICE1712_DS_##x)
116
117#define ICE1712_DS_INTMASK 0x00
118#define ICE1712_DS_INTSTAT 0x02
119#define ICE1712_DS_DATA 0x04
120#define ICE1712_DS_INDEX 0x08
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125
126#define ICE1712_DSC_ADDR0 0x00
127#define ICE1712_DSC_COUNT0 0x01
128#define ICE1712_DSC_ADDR1 0x02
129#define ICE1712_DSC_COUNT1 0x03
130#define ICE1712_DSC_CONTROL 0x04
131#define ICE1712_BUFFER1 0x80
132#define ICE1712_BUFFER1_AUTO 0x40
133#define ICE1712_BUFFER0_AUTO 0x20
134#define ICE1712_FLUSH 0x10
135#define ICE1712_STEREO 0x08
136#define ICE1712_16BIT 0x04
137#define ICE1712_PAUSE 0x02
138#define ICE1712_START 0x01
139#define ICE1712_DSC_RATE 0x05
140#define ICE1712_DSC_VOLUME 0x06
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145
146#define ICEMT(ice, x) ((ice)->profi_port + ICE1712_MT_##x)
147
148#define ICE1712_MT_IRQ 0x00
149#define ICE1712_MULTI_CAPTURE 0x80
150#define ICE1712_MULTI_PLAYBACK 0x40
151#define ICE1712_MULTI_CAPSTATUS 0x02
152#define ICE1712_MULTI_PBKSTATUS 0x01
153#define ICE1712_MT_RATE 0x01
154#define ICE1712_SPDIF_MASTER 0x10
155#define ICE1712_MT_I2S_FORMAT 0x02
156#define ICE1712_MT_AC97_INDEX 0x04
157#define ICE1712_MT_AC97_CMD 0x05
158
159#define ICE1712_MT_AC97_DATA 0x06
160#define ICE1712_MT_PLAYBACK_ADDR 0x10
161#define ICE1712_MT_PLAYBACK_SIZE 0x14
162#define ICE1712_MT_PLAYBACK_COUNT 0x16
163#define ICE1712_MT_PLAYBACK_CONTROL 0x18
164#define ICE1712_CAPTURE_START_SHADOW 0x04
165#define ICE1712_PLAYBACK_PAUSE 0x02
166#define ICE1712_PLAYBACK_START 0x01
167#define ICE1712_MT_CAPTURE_ADDR 0x20
168#define ICE1712_MT_CAPTURE_SIZE 0x24
169#define ICE1712_MT_CAPTURE_COUNT 0x26
170#define ICE1712_MT_CAPTURE_CONTROL 0x28
171#define ICE1712_CAPTURE_START 0x01
172#define ICE1712_MT_ROUTE_PSDOUT03 0x30
173#define ICE1712_MT_ROUTE_SPDOUT 0x32
174#define ICE1712_MT_ROUTE_CAPTURE 0x34
175#define ICE1712_MT_MONITOR_VOLUME 0x38
176#define ICE1712_MT_MONITOR_INDEX 0x3a
177#define ICE1712_MT_MONITOR_RATE 0x3b
178#define ICE1712_MT_MONITOR_ROUTECTRL 0x3c
179#define ICE1712_ROUTE_AC97 0x01
180#define ICE1712_MT_MONITOR_PEAKINDEX 0x3e
181#define ICE1712_MT_MONITOR_PEAKDATA 0x3f
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187
188#define ICE1712_CFG_CLOCK 0xc0
189#define ICE1712_CFG_CLOCK512 0x00
190#define ICE1712_CFG_CLOCK384 0x40
191#define ICE1712_CFG_EXT 0x80
192#define ICE1712_CFG_2xMPU401 0x20
193#define ICE1712_CFG_NO_CON_AC97 0x10
194#define ICE1712_CFG_ADC_MASK 0x0c
195#define ICE1712_CFG_DAC_MASK 0x03
196
197#define ICE1712_CFG_PRO_I2S 0x80
198#define ICE1712_CFG_AC97_PACKED 0x01
199
200#define ICE1712_CFG_I2S_VOLUME 0x80
201#define ICE1712_CFG_I2S_96KHZ 0x40
202#define ICE1712_CFG_I2S_RESMASK 0x30
203#define ICE1712_CFG_I2S_OTHER 0x0f
204
205#define ICE1712_CFG_I2S_CHIPID 0xfc
206#define ICE1712_CFG_SPDIF_IN 0x02
207#define ICE1712_CFG_SPDIF_OUT 0x01
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212
213#define ICE1712_DMA_MODE_WRITE 0x48
214#define ICE1712_DMA_AUTOINIT 0x10
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220
221struct snd_ice1712;
222
223struct snd_ice1712_eeprom {
224 unsigned int subvendor;
225 unsigned char size;
226 unsigned char version;
227 unsigned char data[32];
228 unsigned int gpiomask;
229 unsigned int gpiostate;
230 unsigned int gpiodir;
231};
232
233enum {
234 ICE_EEP1_CODEC = 0,
235 ICE_EEP1_ACLINK,
236 ICE_EEP1_I2SID,
237 ICE_EEP1_SPDIF,
238 ICE_EEP1_GPIO_MASK,
239 ICE_EEP1_GPIO_STATE,
240 ICE_EEP1_GPIO_DIR,
241 ICE_EEP1_AC97_MAIN_LO,
242 ICE_EEP1_AC97_MAIN_HI,
243 ICE_EEP1_AC97_PCM_LO,
244 ICE_EEP1_AC97_PCM_HI,
245 ICE_EEP1_AC97_REC_LO,
246 ICE_EEP1_AC97_REC_HI,
247 ICE_EEP1_AC97_RECSRC,
248 ICE_EEP1_DAC_ID,
249 ICE_EEP1_DAC_ID1,
250 ICE_EEP1_DAC_ID2,
251 ICE_EEP1_DAC_ID3,
252 ICE_EEP1_ADC_ID,
253 ICE_EEP1_ADC_ID1,
254 ICE_EEP1_ADC_ID2,
255 ICE_EEP1_ADC_ID3
256};
257
258#define ice_has_con_ac97(ice) (!((ice)->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_NO_CON_AC97))
259
260
261struct snd_ak4xxx_private {
262 unsigned int cif:1;
263 unsigned char caddr;
264 unsigned int data_mask;
265 unsigned int clk_mask;
266 unsigned int cs_mask;
267 unsigned int cs_addr;
268 unsigned int cs_none;
269 unsigned int add_flags;
270 unsigned int mask_flags;
271 struct snd_akm4xxx_ops {
272 void (*set_rate_val)(struct snd_akm4xxx *ak, unsigned int rate);
273 } ops;
274};
275
276struct snd_ice1712_spdif {
277 unsigned char cs8403_bits;
278 unsigned char cs8403_stream_bits;
279 struct snd_kcontrol *stream_ctl;
280
281 struct snd_ice1712_spdif_ops {
282 void (*open)(struct snd_ice1712 *, struct snd_pcm_substream *);
283 void (*setup_rate)(struct snd_ice1712 *, int rate);
284 void (*close)(struct snd_ice1712 *, struct snd_pcm_substream *);
285 void (*default_get)(struct snd_ice1712 *, struct snd_ctl_elem_value *ucontrol);
286 int (*default_put)(struct snd_ice1712 *, struct snd_ctl_elem_value *ucontrol);
287 void (*stream_get)(struct snd_ice1712 *, struct snd_ctl_elem_value *ucontrol);
288 int (*stream_put)(struct snd_ice1712 *, struct snd_ctl_elem_value *ucontrol);
289 } ops;
290};
291
292struct snd_ice1712_card_info;
293
294struct snd_ice1712 {
295 unsigned long conp_dma_size;
296 unsigned long conc_dma_size;
297 unsigned long prop_dma_size;
298 unsigned long proc_dma_size;
299 int irq;
300
301 unsigned long port;
302 unsigned long ddma_port;
303 unsigned long dmapath_port;
304 unsigned long profi_port;
305
306 struct pci_dev *pci;
307 struct snd_card *card;
308 struct snd_pcm *pcm;
309 struct snd_pcm *pcm_ds;
310 struct snd_pcm *pcm_pro;
311 struct snd_pcm_substream *playback_con_substream;
312 struct snd_pcm_substream *playback_con_substream_ds[6];
313 struct snd_pcm_substream *capture_con_substream;
314 struct snd_pcm_substream *playback_pro_substream;
315 struct snd_pcm_substream *capture_pro_substream;
316 unsigned int playback_pro_size;
317 unsigned int capture_pro_size;
318 unsigned int playback_con_virt_addr[6];
319 unsigned int playback_con_active_buf[6];
320 unsigned int capture_con_virt_addr;
321 unsigned int ac97_ext_id;
322 struct snd_ac97 *ac97;
323 struct snd_rawmidi *rmidi[2];
324
325 spinlock_t reg_lock;
326 struct snd_info_entry *proc_entry;
327
328 struct snd_ice1712_eeprom eeprom;
329 struct snd_ice1712_card_info *card_info;
330
331 unsigned int pro_volumes[20];
332 unsigned int omni:1;
333 unsigned int dxr_enable:1;
334 unsigned int vt1724:1;
335 unsigned int vt1720:1;
336 unsigned int has_spdif:1;
337 unsigned int force_pdma4:1;
338 unsigned int force_rdma1:1;
339 unsigned int midi_output:1;
340 unsigned int midi_input:1;
341 unsigned int own_routing:1;
342 unsigned int num_total_dacs;
343 unsigned int num_total_adcs;
344 unsigned int cur_rate;
345
346 struct mutex open_mutex;
347 struct snd_pcm_substream *pcm_reserved[4];
348 struct snd_pcm_hw_constraint_list *hw_rates;
349
350 unsigned int akm_codecs;
351 struct snd_akm4xxx *akm;
352 struct snd_ice1712_spdif spdif;
353
354 struct mutex i2c_mutex;
355 struct snd_i2c_bus *i2c;
356 struct snd_i2c_device *cs8427;
357 unsigned int cs8427_timeout;
358
359 struct ice1712_gpio {
360 unsigned int direction;
361 unsigned int write_mask;
362 unsigned int saved[2];
363
364 void (*set_mask)(struct snd_ice1712 *ice, unsigned int data);
365 unsigned int (*get_mask)(struct snd_ice1712 *ice);
366 void (*set_dir)(struct snd_ice1712 *ice, unsigned int data);
367 unsigned int (*get_dir)(struct snd_ice1712 *ice);
368 void (*set_data)(struct snd_ice1712 *ice, unsigned int data);
369 unsigned int (*get_data)(struct snd_ice1712 *ice);
370
371 void (*set_pro_rate)(struct snd_ice1712 *ice, unsigned int rate);
372 void (*i2s_mclk_changed)(struct snd_ice1712 *ice);
373 } gpio;
374 struct mutex gpio_mutex;
375
376
377 void *spec;
378
379
380 int pro_rate_default;
381 int (*is_spdif_master)(struct snd_ice1712 *ice);
382 unsigned int (*get_rate)(struct snd_ice1712 *ice);
383 void (*set_rate)(struct snd_ice1712 *ice, unsigned int rate);
384 unsigned char (*set_mclk)(struct snd_ice1712 *ice, unsigned int rate);
385 int (*set_spdif_clock)(struct snd_ice1712 *ice, int type);
386 int (*get_spdif_master_type)(struct snd_ice1712 *ice);
387 const char * const *ext_clock_names;
388 int ext_clock_count;
389 void (*pro_open)(struct snd_ice1712 *, struct snd_pcm_substream *);
390#ifdef CONFIG_PM_SLEEP
391 int (*pm_suspend)(struct snd_ice1712 *);
392 int (*pm_resume)(struct snd_ice1712 *);
393 unsigned int pm_suspend_enabled:1;
394 unsigned int pm_saved_is_spdif_master:1;
395 unsigned int pm_saved_spdif_ctrl;
396 unsigned char pm_saved_spdif_cfg;
397 unsigned int pm_saved_route;
398#endif
399};
400
401
402
403
404
405static inline void snd_ice1712_gpio_set_dir(struct snd_ice1712 *ice, unsigned int bits)
406{
407 ice->gpio.set_dir(ice, bits);
408}
409
410static inline unsigned int snd_ice1712_gpio_get_dir(struct snd_ice1712 *ice)
411{
412 return ice->gpio.get_dir(ice);
413}
414
415static inline void snd_ice1712_gpio_set_mask(struct snd_ice1712 *ice, unsigned int bits)
416{
417 ice->gpio.set_mask(ice, bits);
418}
419
420static inline void snd_ice1712_gpio_write(struct snd_ice1712 *ice, unsigned int val)
421{
422 ice->gpio.set_data(ice, val);
423}
424
425static inline unsigned int snd_ice1712_gpio_read(struct snd_ice1712 *ice)
426{
427 return ice->gpio.get_data(ice);
428}
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430
431
432
433
434
435static inline void snd_ice1712_save_gpio_status(struct snd_ice1712 *ice)
436{
437 mutex_lock(&ice->gpio_mutex);
438 ice->gpio.saved[0] = ice->gpio.direction;
439 ice->gpio.saved[1] = ice->gpio.write_mask;
440}
441
442static inline void snd_ice1712_restore_gpio_status(struct snd_ice1712 *ice)
443{
444 ice->gpio.set_dir(ice, ice->gpio.saved[0]);
445 ice->gpio.set_mask(ice, ice->gpio.saved[1]);
446 ice->gpio.direction = ice->gpio.saved[0];
447 ice->gpio.write_mask = ice->gpio.saved[1];
448 mutex_unlock(&ice->gpio_mutex);
449}
450
451
452#define ICE1712_GPIO(xiface, xname, xindex, mask, invert, xaccess) \
453{ .iface = xiface, .name = xname, .access = xaccess, .info = snd_ctl_boolean_mono_info, \
454 .get = snd_ice1712_gpio_get, .put = snd_ice1712_gpio_put, \
455 .private_value = mask | (invert << 24) }
456
457int snd_ice1712_gpio_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
458int snd_ice1712_gpio_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
459
460
461
462
463static inline void snd_ice1712_gpio_write_bits(struct snd_ice1712 *ice,
464 unsigned int mask, unsigned int bits)
465{
466 unsigned val;
467
468 ice->gpio.direction |= mask;
469 snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
470 val = snd_ice1712_gpio_read(ice);
471 val &= ~mask;
472 val |= mask & bits;
473 snd_ice1712_gpio_write(ice, val);
474}
475
476static inline int snd_ice1712_gpio_read_bits(struct snd_ice1712 *ice,
477 unsigned int mask)
478{
479 ice->gpio.direction &= ~mask;
480 snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
481 return snd_ice1712_gpio_read(ice) & mask;
482}
483
484
485int snd_ice1724_get_route_val(struct snd_ice1712 *ice, int shift);
486int snd_ice1724_put_route_val(struct snd_ice1712 *ice, unsigned int val,
487 int shift);
488
489int snd_ice1712_spdif_build_controls(struct snd_ice1712 *ice);
490
491int snd_ice1712_akm4xxx_init(struct snd_akm4xxx *ak,
492 const struct snd_akm4xxx *template,
493 const struct snd_ak4xxx_private *priv,
494 struct snd_ice1712 *ice);
495void snd_ice1712_akm4xxx_free(struct snd_ice1712 *ice);
496int snd_ice1712_akm4xxx_build_controls(struct snd_ice1712 *ice);
497
498int snd_ice1712_init_cs8427(struct snd_ice1712 *ice, int addr);
499
500static inline void snd_ice1712_write(struct snd_ice1712 *ice, u8 addr, u8 data)
501{
502 outb(addr, ICEREG(ice, INDEX));
503 outb(data, ICEREG(ice, DATA));
504}
505
506static inline u8 snd_ice1712_read(struct snd_ice1712 *ice, u8 addr)
507{
508 outb(addr, ICEREG(ice, INDEX));
509 return inb(ICEREG(ice, DATA));
510}
511
512
513
514
515
516
517struct snd_ice1712_card_info {
518 unsigned int subvendor;
519 const char *name;
520 const char *model;
521 const char *driver;
522 int (*chip_init)(struct snd_ice1712 *);
523 void (*chip_exit)(struct snd_ice1712 *);
524 int (*build_controls)(struct snd_ice1712 *);
525 unsigned int no_mpu401:1;
526 unsigned int mpu401_1_info_flags;
527 unsigned int mpu401_2_info_flags;
528 const char *mpu401_1_name;
529 const char *mpu401_2_name;
530 const unsigned int eeprom_size;
531 const unsigned char *eeprom_data;
532};
533
534
535#endif
536