LXR linux/arch/arm/mach-clps711x/include/mach/clps711x.h

   1/*
   2 *  This file contains the hardware definitions of the Cirrus Logic
   3 *  ARM7 CLPS711X internal registers.
   4 *
   5 *  Copyright (C) 2000 Deep Blue Solutions Ltd.
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License as published by
   9 * the Free Software Foundation; either version 2 of the License, or
  10 * (at your option) any later version.
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License
  18 * along with this program; if not, write to the Free Software
  19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20 */
  21#ifndef __MACH_CLPS711X_H
  22#define __MACH_CLPS711X_H
  23
  24#include <linux/mfd/syscon/clps711x.h>
  25
  26#define CLPS711X_PHYS_BASE      (0x80000000)
  27
  28#define PADR            (0x0000)
  29#define PBDR            (0x0001)
  30#define PCDR            (0x0002)
  31#define PDDR            (0x0003)
  32#define PADDR           (0x0040)
  33#define PBDDR           (0x0041)
  34#define PCDDR           (0x0042)
  35#define PDDDR           (0x0043)
  36#define PEDR            (0x0083)
  37#define PEDDR           (0x00c3)
  38#define SYSCON1         (0x0100)
  39#define SYSFLG1         (0x0140)
  40#define MEMCFG1         (0x0180)
  41#define MEMCFG2         (0x01c0)
  42#define DRFPR           (0x0200)
  43#define LCDCON          (0x02c0)
  44#define TC1D            (0x0300)
  45#define TC2D            (0x0340)
  46#define RTCDR           (0x0380)
  47#define RTCMR           (0x03c0)
  48#define PMPCON          (0x0400)
  49#define CODR            (0x0440)
  50#define UARTDR1         (0x0480)
  51#define UBRLCR1         (0x04c0)
  52#define SYNCIO          (0x0500)
  53#define PALLSW          (0x0540)
  54#define PALMSW          (0x0580)
  55#define STFCLR          (0x05c0)
  56#define HALT            (0x0800)
  57#define STDBY           (0x0840)
  58
  59#define FBADDR          (0x1000)
  60#define SYSCON2         (0x1100)
  61#define SYSFLG2         (0x1140)
  62#define UARTDR2         (0x1480)
  63#define UBRLCR2         (0x14c0)
  64#define SS2DR           (0x1500)
  65#define SS2POP          (0x16c0)
  66
  67#define DAIR            (0x2000)
  68#define DAIDR0          (0x2040)
  69#define DAIDR1          (0x2080)
  70#define DAIDR2          (0x20c0)
  71#define DAISR           (0x2100)
  72#define SYSCON3         (0x2200)
  73#define LEDFLSH         (0x22c0)
  74#define SDCONF          (0x2300)
  75#define SDRFPR          (0x2340)
  76#define UNIQID          (0x2440)
  77#define DAI64FS         (0x2600)
  78#define PLLW            (0x2610)
  79#define PLLR            (0xa5a8)
  80#define RANDID0         (0x2700)
  81#define RANDID1         (0x2704)
  82#define RANDID2         (0x2708)
  83#define RANDID3         (0x270c)
  84
  85#define LCDCON_GSEN             (1 << 30)
  86#define LCDCON_GSMD             (1 << 31)
  87
  88/* common bits: UARTDR1 / UARTDR2 */
  89#define UARTDR_FRMERR           (1 << 8)
  90#define UARTDR_PARERR           (1 << 9)
  91#define UARTDR_OVERR            (1 << 10)
  92
  93/* common bits: UBRLCR1 / UBRLCR2 */
  94#define UBRLCR_BAUD_MASK        ((1 << 12) - 1)
  95#define UBRLCR_BREAK            (1 << 12)
  96#define UBRLCR_PRTEN            (1 << 13)
  97#define UBRLCR_EVENPRT          (1 << 14)
  98#define UBRLCR_XSTOP            (1 << 15)
  99#define UBRLCR_FIFOEN           (1 << 16)
 100#define UBRLCR_WRDLEN5          (0 << 17)
 101#define UBRLCR_WRDLEN6          (1 << 17)
 102#define UBRLCR_WRDLEN7          (2 << 17)
 103#define UBRLCR_WRDLEN8          (3 << 17)
 104#define UBRLCR_WRDLEN_MASK      (3 << 17)
 105
 106#define SYNCIO_FRMLEN(x)        (((x) & 0x1f) << 8)
 107#define SYNCIO_SMCKEN           (1 << 13)
 108#define SYNCIO_TXFRMEN          (1 << 14)
 109
 110#define DAIR_RESERVED           (0x0404)
 111#define DAIR_DAIEN              (1 << 16)
 112#define DAIR_ECS                (1 << 17)
 113#define DAIR_LCTM               (1 << 19)
 114#define DAIR_LCRM               (1 << 20)
 115#define DAIR_RCTM               (1 << 21)
 116#define DAIR_RCRM               (1 << 22)
 117#define DAIR_LBM                (1 << 23)
 118
 119#define DAIDR2_FIFOEN           (1 << 15)
 120#define DAIDR2_FIFOLEFT         (0x0d << 16)
 121#define DAIDR2_FIFORIGHT        (0x11 << 16)
 122
 123#define DAISR_RCTS              (1 << 0)
 124#define DAISR_RCRS              (1 << 1)
 125#define DAISR_LCTS              (1 << 2)
 126#define DAISR_LCRS              (1 << 3)
 127#define DAISR_RCTU              (1 << 4)
 128#define DAISR_RCRO              (1 << 5)
 129#define DAISR_LCTU              (1 << 6)
 130#define DAISR_LCRO              (1 << 7)
 131#define DAISR_RCNF              (1 << 8)
 132#define DAISR_RCNE              (1 << 9)
 133#define DAISR_LCNF              (1 << 10)
 134#define DAISR_LCNE              (1 << 11)
 135#define DAISR_FIFO              (1 << 12)
 136
 137#define DAI64FS_I2SF64          (1 << 0)
 138#define DAI64FS_AUDIOCLKEN      (1 << 1)
 139#define DAI64FS_AUDIOCLKSRC     (1 << 2)
 140#define DAI64FS_MCLK256EN       (1 << 3)
 141#define DAI64FS_LOOPBACK        (1 << 5)
 142
 143#define SDCONF_ACTIVE           (1 << 10)
 144#define SDCONF_CLKCTL           (1 << 9)
 145#define SDCONF_WIDTH_4          (0 << 7)
 146#define SDCONF_WIDTH_8          (1 << 7)
 147#define SDCONF_WIDTH_16         (2 << 7)
 148#define SDCONF_WIDTH_32         (3 << 7)
 149#define SDCONF_SIZE_16          (0 << 5)
 150#define SDCONF_SIZE_64          (1 << 5)
 151#define SDCONF_SIZE_128         (2 << 5)
 152#define SDCONF_SIZE_256         (3 << 5)
 153#define SDCONF_CASLAT_2         (2)
 154#define SDCONF_CASLAT_3         (3)
 155
 156#define MEMCFG_BUS_WIDTH_32     (1)
 157#define MEMCFG_BUS_WIDTH_16     (0)
 158#define MEMCFG_BUS_WIDTH_8      (3)
 159
 160#define MEMCFG_SQAEN            (1 << 6)
 161#define MEMCFG_CLKENB           (1 << 7)
 162
 163#define MEMCFG_WAITSTATE_8_3    (0 << 2)
 164#define MEMCFG_WAITSTATE_7_3    (1 << 2)
 165#define MEMCFG_WAITSTATE_6_3    (2 << 2)
 166#define MEMCFG_WAITSTATE_5_3    (3 << 2)
 167#define MEMCFG_WAITSTATE_4_2    (4 << 2)
 168#define MEMCFG_WAITSTATE_3_2    (5 << 2)
 169#define MEMCFG_WAITSTATE_2_2    (6 << 2)
 170#define MEMCFG_WAITSTATE_1_2    (7 << 2)
 171#define MEMCFG_WAITSTATE_8_1    (8 << 2)
 172#define MEMCFG_WAITSTATE_7_1    (9 << 2)
 173#define MEMCFG_WAITSTATE_6_1    (10 << 2)
 174#define MEMCFG_WAITSTATE_5_1    (11 << 2)
 175#define MEMCFG_WAITSTATE_4_0    (12 << 2)
 176#define MEMCFG_WAITSTATE_3_0    (13 << 2)
 177#define MEMCFG_WAITSTATE_2_0    (14 << 2)
 178#define MEMCFG_WAITSTATE_1_0    (15 << 2)
 179
 180/* INTSR1 Interrupts */
 181#define IRQ_CSINT               (4)
 182#define IRQ_EINT1               (5)
 183#define IRQ_EINT2               (6)
 184#define IRQ_EINT3               (7)
 185#define IRQ_TC1OI               (8)
 186#define IRQ_TC2OI               (9)
 187#define IRQ_RTCMI               (10)
 188#define IRQ_TINT                (11)
 189#define IRQ_UTXINT1             (12)
 190#define IRQ_URXINT1             (13)
 191#define IRQ_UMSINT              (14)
 192#define IRQ_SSEOTI              (15)
 193
 194/* INTSR2 Interrupts */
 195#define IRQ_KBDINT              (16 + 0)
 196#define IRQ_SS2RX               (16 + 1)
 197#define IRQ_SS2TX               (16 + 2)
 198#define IRQ_UTXINT2             (16 + 12)
 199#define IRQ_URXINT2             (16 + 13)
 200
 201/* INTSR3 Interrupts */
 202#define IRQ_DAIINT              (32 + 0)
 203
 204#endif /* __MACH_CLPS711X_H */
 205