1/* 2 * This file contains the hardware definitions for Gemini. 3 * 4 * Copyright (C) 2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11#ifndef __MACH_GLOBAL_REG_H 12#define __MACH_GLOBAL_REG_H 13 14/* Global Word ID Register*/ 15#define GLOBAL_ID 0x00 16 17#define CHIP_ID(reg) ((reg) >> 8) 18#define CHIP_REVISION(reg) ((reg) & 0xFF) 19 20/* Global Status Register */ 21#define GLOBAL_STATUS 0x04 22 23#define CPU_BIG_ENDIAN (1 << 31) 24#define PLL_OSC_30M (1 << 30) /* else 60MHz */ 25 26#define OPERATION_MODE_MASK (0xF << 26) 27#define OPM_IDDQ (0xF << 26) 28#define OPM_NAND (0xE << 26) 29#define OPM_RING (0xD << 26) 30#define OPM_DIRECT_BOOT (0xC << 26) 31#define OPM_USB1_PHY_TEST (0xB << 26) 32#define OPM_USB0_PHY_TEST (0xA << 26) 33#define OPM_SATA1_PHY_TEST (0x9 << 26) 34#define OPM_SATA0_PHY_TEST (0x8 << 26) 35#define OPM_ICE_ARM (0x7 << 26) 36#define OPM_ICE_FARADAY (0x6 << 26) 37#define OPM_PLL_BYPASS (0x5 << 26) 38#define OPM_DEBUG (0x4 << 26) 39#define OPM_BURN_IN (0x3 << 26) 40#define OPM_MBIST (0x2 << 26) 41#define OPM_SCAN (0x1 << 26) 42#define OPM_REAL (0x0 << 26) 43 44#define FLASH_TYPE_MASK (0x3 << 24) 45#define FLASH_TYPE_NAND_2K (0x3 << 24) 46#define FLASH_TYPE_NAND_512 (0x2 << 24) 47#define FLASH_TYPE_PARALLEL (0x1 << 24) 48#define FLASH_TYPE_SERIAL (0x0 << 24) 49/* if parallel */ 50#define FLASH_WIDTH_16BIT (1 << 23) /* else 8 bit */ 51/* if serial */ 52#define FLASH_ATMEL (1 << 23) /* else STM */ 53 54#define FLASH_SIZE_MASK (0x3 << 21) 55#define NAND_256M (0x3 << 21) /* and more */ 56#define NAND_128M (0x2 << 21) 57#define NAND_64M (0x1 << 21) 58#define NAND_32M (0x0 << 21) 59#define ATMEL_16M (0x3 << 21) /* and more */ 60#define ATMEL_8M (0x2 << 21) 61#define ATMEL_4M_2M (0x1 << 21) 62#define ATMEL_1M (0x0 << 21) /* and less */ 63#define STM_32M (1 << 22) /* and more */ 64#define STM_16M (0 << 22) /* and less */ 65 66#define FLASH_PARALLEL_HIGH_PIN_CNT (1 << 20) /* else low pin cnt */ 67 68#define CPU_AHB_RATIO_MASK (0x3 << 18) 69#define CPU_AHB_1_1 (0x0 << 18) 70#define CPU_AHB_3_2 (0x1 << 18) 71#define CPU_AHB_24_13 (0x2 << 18) 72#define CPU_AHB_2_1 (0x3 << 18) 73 74#define REG_TO_AHB_SPEED(reg) ((((reg) >> 15) & 0x7) * 10 + 130) 75#define AHB_SPEED_TO_REG(x) ((((x - 130)) / 10) << 15) 76 77/* it is posible to override some settings, use >> OVERRIDE_xxxx_SHIFT */ 78#define OVERRIDE_FLASH_TYPE_SHIFT 16 79#define OVERRIDE_FLASH_WIDTH_SHIFT 16 80#define OVERRIDE_FLASH_SIZE_SHIFT 16 81#define OVERRIDE_CPU_AHB_RATIO_SHIFT 15 82#define OVERRIDE_AHB_SPEED_SHIFT 15 83 84/* Global PLL Control Register */ 85#define GLOBAL_PLL_CTRL 0x08 86 87#define PLL_BYPASS (1 << 31) 88#define PLL_POWER_DOWN (1 << 8) 89#define PLL_CONTROL_Q (0x1F << 0) 90 91/* Global Soft Reset Control Register */ 92#define GLOBAL_RESET 0x0C 93 94#define RESET_GLOBAL (1 << 31) 95#define RESET_CPU1 (1 << 30) 96#define RESET_TVE (1 << 28) 97#define RESET_SATA1 (1 << 27) 98#define RESET_SATA0 (1 << 26) 99#define RESET_CIR (1 << 25) 100#define RESET_EXT_DEV (1 << 24) 101#define RESET_WD (1 << 23) 102#define RESET_GPIO2 (1 << 22) 103#define RESET_GPIO1 (1 << 21) 104#define RESET_GPIO0 (1 << 20) 105#define RESET_SSP (1 << 19) 106#define RESET_UART (1 << 18) 107#define RESET_TIMER (1 << 17) 108#define RESET_RTC (1 << 16) 109#define RESET_INT1 (1 << 15) 110#define RESET_INT0 (1 << 14) 111#define RESET_LCD (1 << 13) 112#define RESET_LPC (1 << 12) 113#define RESET_APB (1 << 11) 114#define RESET_DMA (1 << 10) 115#define RESET_USB1 (1 << 9) 116#define RESET_USB0 (1 << 8) 117#define RESET_PCI (1 << 7) 118#define RESET_GMAC1 (1 << 6) 119#define RESET_GMAC0 (1 << 5) 120#define RESET_SECURITY (1 << 4) 121#define RESET_RAID (1 << 3) 122#define RESET_IDE (1 << 2) 123#define RESET_FLASH (1 << 1) 124#define RESET_DRAM (1 << 0) 125 126/* Global IO Pad Driving Capability Control Register */ 127#define GLOBAL_IO_DRIVING_CTRL 0x10 128 129#define DRIVING_CURRENT_MASK 0x3 130 131/* here 00-4mA, 01-8mA, 10-12mA, 11-16mA */ 132#define GPIO1_PADS_31_28_SHIFT 28 133#define GPIO0_PADS_31_16_SHIFT 26 134#define GPIO0_PADS_15_0_SHIFT 24 135#define PCI_AND_EXT_RESET_PADS_SHIFT 22 136#define IDE_PADS_SHIFT 20 137#define GMAC1_PADS_SHIFT 18 138#define GMAC0_PADS_SHIFT 16 139/* DRAM is not in mA and poorly documented */ 140#define DRAM_CLOCK_PADS_SHIFT 8 141#define DRAM_DATA_PADS_SHIFT 4 142#define DRAM_CONTROL_PADS_SHIFT 0 143 144/* Global IO Pad Slew Rate Control Register */ 145#define GLOBAL_IO_SLEW_RATE_CTRL 0x14 146 147#define GPIO1_PADS_31_28_SLOW (1 << 10) 148#define GPIO0_PADS_31_16_SLOW (1 << 9) 149#define GPIO0_PADS_15_0_SLOW (1 << 8) 150#define PCI_PADS_SLOW (1 << 7) 151#define IDE_PADS_SLOW (1 << 6) 152#define GMAC1_PADS_SLOW (1 << 5) 153#define GMAC0_PADS_SLOW (1 << 4) 154#define DRAM_CLOCK_PADS_SLOW (1 << 1) 155#define DRAM_IO_PADS_SLOW (1 << 0) 156 157/* 158 * General skew control defines 159 * 16 steps, each step is around 0.2ns 160 */ 161#define SKEW_MASK 0xF 162 163/* Global IDE PAD Skew Control Register */ 164#define GLOBAL_IDE_SKEW_CTRL 0x18 165 166#define IDE1_HOST_STROBE_DELAY_SHIFT 28 167#define IDE1_DEVICE_STROBE_DELAY_SHIFT 24 168#define IDE1_OUTPUT_IO_SKEW_SHIFT 20 169#define IDE1_INPUT_IO_SKEW_SHIFT 16 170#define IDE0_HOST_STROBE_DELAY_SHIFT 12 171#define IDE0_DEVICE_STROBE_DELAY_SHIFT 8 172#define IDE0_OUTPUT_IO_SKEW_SHIFT 4 173#define IDE0_INPUT_IO_SKEW_SHIFT 0 174 175/* Global GMAC Control Pad Skew Control Register */ 176#define GLOBAL_GMAC_CTRL_SKEW_CTRL 0x1C 177 178#define GMAC1_TXC_SKEW_SHIFT 28 179#define GMAC1_TXEN_SKEW_SHIFT 24 180#define GMAC1_RXC_SKEW_SHIFT 20 181#define GMAC1_RXDV_SKEW_SHIFT 16 182#define GMAC0_TXC_SKEW_SHIFT 12 183#define GMAC0_TXEN_SKEW_SHIFT 8 184#define GMAC0_RXC_SKEW_SHIFT 4 185#define GMAC0_RXDV_SKEW_SHIFT 0 186 187/* Global GMAC0 Data PAD Skew Control Register */ 188#define GLOBAL_GMAC0_DATA_SKEW_CTRL 0x20 189/* Global GMAC1 Data PAD Skew Control Register */ 190#define GLOBAL_GMAC1_DATA_SKEW_CTRL 0x24 191 192#define GMAC_TXD_SKEW_SHIFT(x) (((x) * 4) + 16) 193#define GMAC_RXD_SKEW_SHIFT(x) ((x) * 4) 194 195/* CPU has two AHB busses. */ 196 197/* Global Arbitration0 Control Register */ 198#define GLOBAL_ARBITRATION0_CTRL 0x28 199 200#define BOOT_CONTROLLER_HIGH_PRIO (1 << 3) 201#define DMA_BUS1_HIGH_PRIO (1 << 2) 202#define CPU0_HIGH_PRIO (1 << 0) 203 204/* Global Arbitration1 Control Register */ 205#define GLOBAL_ARBITRATION1_CTRL 0x2C 206 207#define TVE_HIGH_PRIO (1 << 9) 208#define PCI_HIGH_PRIO (1 << 8) 209#define USB1_HIGH_PRIO (1 << 7) 210#define USB0_HIGH_PRIO (1 << 6) 211#define GMAC1_HIGH_PRIO (1 << 5) 212#define GMAC0_HIGH_PRIO (1 << 4) 213#define SECURITY_HIGH_PRIO (1 << 3) 214#define RAID_HIGH_PRIO (1 << 2) 215#define IDE_HIGH_PRIO (1 << 1) 216#define DMA_BUS2_HIGH_PRIO (1 << 0) 217 218/* Common bits for both arbitration registers */ 219#define BURST_LENGTH_SHIFT 16 220#define BURST_LENGTH_MASK (0x3F << 16) 221 222/* Miscellaneous Control Register */ 223#define GLOBAL_MISC_CTRL 0x30 224 225#define MEMORY_SPACE_SWAP (1 << 31) 226#define USB1_PLUG_MINIB (1 << 30) /* else plug is mini-A */ 227#define USB0_PLUG_MINIB (1 << 29) 228#define GMAC_GMII (1 << 28) 229#define GMAC_1_ENABLE (1 << 27) 230/* TODO: define ATA/SATA bits */ 231#define USB1_VBUS_ON (1 << 23) 232#define USB0_VBUS_ON (1 << 22) 233#define APB_CLKOUT_ENABLE (1 << 21) 234#define TVC_CLKOUT_ENABLE (1 << 20) 235#define EXT_CLKIN_ENABLE (1 << 19) 236#define PCI_66MHZ (1 << 18) /* else 33 MHz */ 237#define PCI_CLKOUT_ENABLE (1 << 17) 238#define LPC_CLKOUT_ENABLE (1 << 16) 239#define USB1_WAKEUP_ON (1 << 15) 240#define USB0_WAKEUP_ON (1 << 14) 241/* TODO: define PCI idle detect bits */ 242#define TVC_PADS_ENABLE (1 << 9) 243#define SSP_PADS_ENABLE (1 << 8) 244#define LCD_PADS_ENABLE (1 << 7) 245#define LPC_PADS_ENABLE (1 << 6) 246#define PCI_PADS_ENABLE (1 << 5) 247#define IDE_PADS_ENABLE (1 << 4) 248#define DRAM_PADS_POWER_DOWN (1 << 3) 249#define NAND_PADS_DISABLE (1 << 2) 250#define PFLASH_PADS_DISABLE (1 << 1) 251#define SFLASH_PADS_DISABLE (1 << 0) 252 253/* Global Clock Control Register */ 254#define GLOBAL_CLOCK_CTRL 0x34 255 256#define POWER_STATE_G0 (1 << 31) 257#define POWER_STATE_S1 (1 << 30) /* else it is S3/S4 state */ 258#define SECURITY_APB_AHB (1 << 29) 259/* else Security APB clk will be 0.75xAHB */ 260/* TODO: TVC clock divider */ 261#define PCI_CLKRUN_ENABLE (1 << 16) 262#define BOOT_CLK_DISABLE (1 << 13) 263#define TVC_CLK_DISABLE (1 << 12) 264#define FLASH_CLK_DISABLE (1 << 11) 265#define DDR_CLK_DISABLE (1 << 10) 266#define PCI_CLK_DISABLE (1 << 9) 267#define IDE_CLK_DISABLE (1 << 8) 268#define USB1_CLK_DISABLE (1 << 7) 269#define USB0_CLK_DISABLE (1 << 6) 270#define SATA1_CLK_DISABLE (1 << 5) 271#define SATA0_CLK_DISABLE (1 << 4) 272#define GMAC1_CLK_DISABLE (1 << 3) 273#define GMAC0_CLK_DISABLE (1 << 2) 274#define SECURITY_CLK_DISABLE (1 << 1) 275 276/* TODO: other registers definitions if needed */ 277 278#endif /* __MACH_GLOBAL_REG_H */ 279