1/* 2 * arch/arm/mach-kirkwood/include/mach/kirkwood.h 3 * 4 * Generic definitions for Marvell Kirkwood SoC flavors: 5 * 88F6180, 88F6192 and 88F6281. 6 * 7 * This file is licensed under the terms of the GNU General Public 8 * License version 2. This program is licensed "as is" without any 9 * warranty of any kind, whether express or implied. 10 */ 11 12#ifndef __ASM_ARCH_KIRKWOOD_H 13#define __ASM_ARCH_KIRKWOOD_H 14 15/* 16 * Marvell Kirkwood address maps. 17 * 18 * phys 19 * e0000000 PCIe #0 Memory space 20 * e8000000 PCIe #1 Memory space 21 * f1000000 on-chip peripheral registers 22 * f2000000 PCIe #0 I/O space 23 * f3000000 PCIe #1 I/O space 24 * f4000000 NAND controller address window 25 * f5000000 Security Accelerator SRAM 26 * 27 * virt phys size 28 * fed00000 f1000000 1M on-chip peripheral registers 29 * fee00000 f2000000 1M PCIe #0 I/O space 30 * fef00000 f3000000 1M PCIe #1 I/O space 31 */ 32 33#define KIRKWOOD_SRAM_PHYS_BASE 0xf5000000 34#define KIRKWOOD_SRAM_SIZE SZ_2K 35 36#define KIRKWOOD_NAND_MEM_PHYS_BASE 0xf4000000 37#define KIRKWOOD_NAND_MEM_SIZE SZ_1K 38 39#define KIRKWOOD_PCIE1_IO_PHYS_BASE 0xf3000000 40#define KIRKWOOD_PCIE1_IO_BUS_BASE 0x00010000 41#define KIRKWOOD_PCIE1_IO_SIZE SZ_64K 42 43#define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000 44#define KIRKWOOD_PCIE_IO_BUS_BASE 0x00000000 45#define KIRKWOOD_PCIE_IO_SIZE SZ_64K 46 47#define KIRKWOOD_REGS_PHYS_BASE 0xf1000000 48#define KIRKWOOD_REGS_VIRT_BASE IOMEM(0xfed00000) 49#define KIRKWOOD_REGS_SIZE SZ_1M 50 51#define KIRKWOOD_PCIE_MEM_PHYS_BASE 0xe0000000 52#define KIRKWOOD_PCIE_MEM_BUS_BASE 0xe0000000 53#define KIRKWOOD_PCIE_MEM_SIZE SZ_128M 54 55#define KIRKWOOD_PCIE1_MEM_PHYS_BASE 0xe8000000 56#define KIRKWOOD_PCIE1_MEM_BUS_BASE 0xe8000000 57#define KIRKWOOD_PCIE1_MEM_SIZE SZ_128M 58 59/* 60 * Register Map 61 */ 62#define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x00000) 63#define DDR_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x00000) 64#define DDR_WINDOW_CPU_BASE (DDR_PHYS_BASE + 0x1500) 65#define DDR_WINDOW_CPU_SZ (0x20) 66#define DDR_OPERATION_BASE (DDR_PHYS_BASE + 0x1418) 67 68#define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x10000) 69#define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x10000) 70#define SAMPLE_AT_RESET (DEV_BUS_VIRT_BASE + 0x0030) 71#define DEVICE_ID (DEV_BUS_VIRT_BASE + 0x0034) 72#define GPIO_LOW_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0100) 73#define GPIO_HIGH_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0140) 74#define RTC_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x0300) 75#define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x0600) 76#define I2C_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1000) 77#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2000) 78#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2000) 79#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2100) 80#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2100) 81 82#define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x20000) 83#define BRIDGE_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x20000) 84#define BRIDGE_WINS_BASE (BRIDGE_PHYS_BASE) 85#define BRIDGE_WINS_SZ (0x80) 86 87#define CRYPTO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x30000) 88 89#define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x40000) 90#define PCIE_LINK_CTRL (PCIE_VIRT_BASE + 0x70) 91#define PCIE_STATUS (PCIE_VIRT_BASE + 0x1a04) 92#define PCIE1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x44000) 93#define PCIE1_LINK_CTRL (PCIE1_VIRT_BASE + 0x70) 94#define PCIE1_STATUS (PCIE1_VIRT_BASE + 0x1a04) 95 96#define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x50000) 97 98#define XOR0_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60800) 99#define XOR0_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60800) 100#define XOR1_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60900) 101#define XOR1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60900) 102#define XOR0_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60A00) 103#define XOR0_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60A00) 104#define XOR1_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60B00) 105#define XOR1_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60B00) 106 107#define GE00_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x70000) 108#define GE01_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x74000) 109 110#define SATA_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x80000) 111#define SATA_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x80000) 112#define SATA0_IF_CTRL (SATA_VIRT_BASE + 0x2050) 113#define SATA0_PHY_MODE_2 (SATA_VIRT_BASE + 0x2330) 114#define SATA1_IF_CTRL (SATA_VIRT_BASE + 0x4050) 115#define SATA1_PHY_MODE_2 (SATA_VIRT_BASE + 0x4330) 116 117#define SDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x90000) 118 119#define AUDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0xA0000) 120#define AUDIO_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0xA0000) 121 122/* 123 * Supported devices and revisions. 124 */ 125#define MV88F6281_DEV_ID 0x6281 126#define MV88F6281_REV_Z0 0 127#define MV88F6281_REV_A0 2 128#define MV88F6281_REV_A1 3 129 130#define MV88F6192_DEV_ID 0x6192 131#define MV88F6192_REV_Z0 0 132#define MV88F6192_REV_A0 2 133#define MV88F6192_REV_A1 3 134 135#define MV88F6180_DEV_ID 0x6180 136#define MV88F6180_REV_A0 2 137#define MV88F6180_REV_A1 3 138 139#define MV88F6282_DEV_ID 0x6282 140#define MV88F6282_REV_A0 0 141#define MV88F6282_REV_A1 1 142#endif 143