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38#include <linux/suspend.h>
39#include <linux/sched.h>
40#include <linux/debugfs.h>
41#include <linux/seq_file.h>
42#include <linux/interrupt.h>
43#include <linux/sysfs.h>
44#include <linux/module.h>
45#include <linux/io.h>
46#include <linux/atomic.h>
47#include <linux/cpu.h>
48
49#include <asm/fncpy.h>
50#include <asm/system_misc.h>
51#include <asm/irq.h>
52#include <asm/mach/time.h>
53#include <asm/mach/irq.h>
54
55#include <mach/tc.h>
56#include <mach/mux.h>
57#include <linux/omap-dma.h>
58#include <plat/dmtimer.h>
59
60#include <mach/irqs.h>
61
62#include "iomap.h"
63#include "clock.h"
64#include "pm.h"
65#include "sram.h"
66
67static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
68static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE];
69static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
70static unsigned int mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_SIZE];
71static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
72static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
73
74#ifndef CONFIG_OMAP_32K_TIMER
75
76static unsigned short enable_dyn_sleep = 0;
77
78#else
79
80static unsigned short enable_dyn_sleep = 1;
81
82static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr,
83 char *buf)
84{
85 return sprintf(buf, "%hu\n", enable_dyn_sleep);
86}
87
88static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
89 const char * buf, size_t n)
90{
91 unsigned short value;
92 if (sscanf(buf, "%hu", &value) != 1 ||
93 (value != 0 && value != 1)) {
94 printk(KERN_ERR "idle_sleep_store: Invalid value\n");
95 return -EINVAL;
96 }
97 enable_dyn_sleep = value;
98 return n;
99}
100
101static struct kobj_attribute sleep_while_idle_attr =
102 __ATTR(sleep_while_idle, 0644, idle_show, idle_store);
103
104#endif
105
106static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
107
108
109
110
111
112
113
114void omap1_pm_idle(void)
115{
116 extern __u32 arm_idlect1_mask;
117 __u32 use_idlect1 = arm_idlect1_mask;
118 int do_sleep = 0;
119
120 local_fiq_disable();
121
122#if defined(CONFIG_OMAP_MPU_TIMER) && !defined(CONFIG_OMAP_DM_TIMER)
123#warning Enable 32kHz OS timer in order to allow sleep states in idle
124 use_idlect1 = use_idlect1 & ~(1 << 9);
125#else
126
127 while (enable_dyn_sleep) {
128
129#ifdef CONFIG_CBUS_TAHVO_USB
130 extern int vbus_active;
131
132 if (vbus_active)
133 break;
134#endif
135 do_sleep = 1;
136 break;
137 }
138
139#endif
140
141#ifdef CONFIG_OMAP_DM_TIMER
142 use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1);
143#endif
144
145 if (omap_dma_running())
146 use_idlect1 &= ~(1 << 6);
147
148
149
150
151 if ((use_idlect1 != ~0) || !do_sleep) {
152
153 __u32 saved_idlect1 = omap_readl(ARM_IDLECT1);
154 if (cpu_is_omap15xx())
155 use_idlect1 &= OMAP1510_BIG_SLEEP_REQUEST;
156 else
157 use_idlect1 &= OMAP1610_IDLECT1_SLEEP_VAL;
158 omap_writel(use_idlect1, ARM_IDLECT1);
159 __asm__ volatile ("mcr p15, 0, r0, c7, c0, 4");
160 omap_writel(saved_idlect1, ARM_IDLECT1);
161
162 local_fiq_enable();
163 return;
164 }
165 omap_sram_suspend(omap_readl(ARM_IDLECT1),
166 omap_readl(ARM_IDLECT2));
167
168 local_fiq_enable();
169}
170
171
172
173
174
175
176static void omap_pm_wakeup_setup(void)
177{
178 u32 level1_wake = 0;
179 u32 level2_wake = OMAP_IRQ_BIT(INT_UART2);
180
181
182
183
184
185
186
187 if (cpu_is_omap7xx())
188 level1_wake = OMAP_IRQ_BIT(INT_7XX_GPIO_BANK1) |
189 OMAP_IRQ_BIT(INT_7XX_IH2_IRQ);
190 else if (cpu_is_omap15xx())
191 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
192 OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
193 else if (cpu_is_omap16xx())
194 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
195 OMAP_IRQ_BIT(INT_1610_IH2_IRQ);
196
197 omap_writel(~level1_wake, OMAP_IH1_MIR);
198
199 if (cpu_is_omap7xx()) {
200 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
201 omap_writel(~(OMAP_IRQ_BIT(INT_7XX_WAKE_UP_REQ) |
202 OMAP_IRQ_BIT(INT_7XX_MPUIO_KEYPAD)),
203 OMAP_IH2_1_MIR);
204 } else if (cpu_is_omap15xx()) {
205 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
206 omap_writel(~level2_wake, OMAP_IH2_MIR);
207 } else if (cpu_is_omap16xx()) {
208 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
209 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
210
211
212 omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ),
213 OMAP_IH2_1_MIR);
214 omap_writel(~0x0, OMAP_IH2_2_MIR);
215 omap_writel(~0x0, OMAP_IH2_3_MIR);
216 }
217
218
219 omap_writel(1, OMAP_IH2_CONTROL);
220 omap_writel(1, OMAP_IH1_CONTROL);
221}
222
223#define EN_DSPCK 13
224#define EN_APICK 6
225#define DSP_EN 1
226
227void omap1_pm_suspend(void)
228{
229 unsigned long arg0 = 0, arg1 = 0;
230
231 printk(KERN_INFO "PM: OMAP%x is trying to enter deep sleep...\n",
232 omap_rev());
233
234 omap_serial_wake_trigger(1);
235
236 if (!cpu_is_omap15xx())
237 omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG);
238
239
240
241
242
243 local_irq_disable();
244 local_fiq_disable();
245
246
247
248
249
250
251
252
253
254
255
256
257 if (cpu_is_omap7xx()) {
258 MPUI7XX_SAVE(OMAP_IH1_MIR);
259 MPUI7XX_SAVE(OMAP_IH2_0_MIR);
260 MPUI7XX_SAVE(OMAP_IH2_1_MIR);
261 MPUI7XX_SAVE(MPUI_CTRL);
262 MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG);
263 MPUI7XX_SAVE(MPUI_DSP_API_CONFIG);
264 MPUI7XX_SAVE(EMIFS_CONFIG);
265 MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG);
266
267 } else if (cpu_is_omap15xx()) {
268 MPUI1510_SAVE(OMAP_IH1_MIR);
269 MPUI1510_SAVE(OMAP_IH2_MIR);
270 MPUI1510_SAVE(MPUI_CTRL);
271 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
272 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
273 MPUI1510_SAVE(EMIFS_CONFIG);
274 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
275 } else if (cpu_is_omap16xx()) {
276 MPUI1610_SAVE(OMAP_IH1_MIR);
277 MPUI1610_SAVE(OMAP_IH2_0_MIR);
278 MPUI1610_SAVE(OMAP_IH2_1_MIR);
279 MPUI1610_SAVE(OMAP_IH2_2_MIR);
280 MPUI1610_SAVE(OMAP_IH2_3_MIR);
281 MPUI1610_SAVE(MPUI_CTRL);
282 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
283 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
284 MPUI1610_SAVE(EMIFS_CONFIG);
285 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
286 }
287
288 ARM_SAVE(ARM_CKCTL);
289 ARM_SAVE(ARM_IDLECT1);
290 ARM_SAVE(ARM_IDLECT2);
291 if (!(cpu_is_omap15xx()))
292 ARM_SAVE(ARM_IDLECT3);
293 ARM_SAVE(ARM_EWUPCT);
294 ARM_SAVE(ARM_RSTCT1);
295 ARM_SAVE(ARM_RSTCT2);
296 ARM_SAVE(ARM_SYSST);
297 ULPD_SAVE(ULPD_CLOCK_CTRL);
298 ULPD_SAVE(ULPD_STATUS_REQ);
299
300
301
302
303
304
305
306
307 omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1);
308
309
310 if (!cpu_is_omap7xx())
311 omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL);
312
313
314 omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
315
316
317 DSP_SAVE(DSP_IDLECT2);
318
319
320 __raw_writew(0, DSP_IDLECT2);
321
322
323
324
325
326 omap_pm_wakeup_setup();
327
328
329
330
331
332
333 omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
334 omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
335
336
337
338
339
340
341
342
343
344
345
346
347
348 arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
349 arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
350
351
352
353
354
355
356
357 omap_sram_suspend(arg0, arg1);
358
359
360
361
362
363
364
365
366
367
368 omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
369
370
371 DSP_RESTORE(DSP_IDLECT2);
372
373
374
375
376
377 if (!(cpu_is_omap15xx()))
378 ARM_RESTORE(ARM_IDLECT3);
379 ARM_RESTORE(ARM_CKCTL);
380 ARM_RESTORE(ARM_EWUPCT);
381 ARM_RESTORE(ARM_RSTCT1);
382 ARM_RESTORE(ARM_RSTCT2);
383 ARM_RESTORE(ARM_SYSST);
384 ULPD_RESTORE(ULPD_CLOCK_CTRL);
385 ULPD_RESTORE(ULPD_STATUS_REQ);
386
387 if (cpu_is_omap7xx()) {
388 MPUI7XX_RESTORE(EMIFS_CONFIG);
389 MPUI7XX_RESTORE(EMIFF_SDRAM_CONFIG);
390 MPUI7XX_RESTORE(OMAP_IH1_MIR);
391 MPUI7XX_RESTORE(OMAP_IH2_0_MIR);
392 MPUI7XX_RESTORE(OMAP_IH2_1_MIR);
393 } else if (cpu_is_omap15xx()) {
394 MPUI1510_RESTORE(MPUI_CTRL);
395 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
396 MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
397 MPUI1510_RESTORE(EMIFS_CONFIG);
398 MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
399 MPUI1510_RESTORE(OMAP_IH1_MIR);
400 MPUI1510_RESTORE(OMAP_IH2_MIR);
401 } else if (cpu_is_omap16xx()) {
402 MPUI1610_RESTORE(MPUI_CTRL);
403 MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
404 MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
405 MPUI1610_RESTORE(EMIFS_CONFIG);
406 MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
407
408 MPUI1610_RESTORE(OMAP_IH1_MIR);
409 MPUI1610_RESTORE(OMAP_IH2_0_MIR);
410 MPUI1610_RESTORE(OMAP_IH2_1_MIR);
411 MPUI1610_RESTORE(OMAP_IH2_2_MIR);
412 MPUI1610_RESTORE(OMAP_IH2_3_MIR);
413 }
414
415 if (!cpu_is_omap15xx())
416 omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
417
418
419
420
421
422 local_irq_enable();
423 local_fiq_enable();
424
425 omap_serial_wake_trigger(0);
426
427 printk(KERN_INFO "PM: OMAP%x is re-starting from deep sleep...\n",
428 omap_rev());
429}
430
431#ifdef CONFIG_DEBUG_FS
432
433
434
435static int omap_pm_debug_show(struct seq_file *m, void *v)
436{
437 ARM_SAVE(ARM_CKCTL);
438 ARM_SAVE(ARM_IDLECT1);
439 ARM_SAVE(ARM_IDLECT2);
440 if (!(cpu_is_omap15xx()))
441 ARM_SAVE(ARM_IDLECT3);
442 ARM_SAVE(ARM_EWUPCT);
443 ARM_SAVE(ARM_RSTCT1);
444 ARM_SAVE(ARM_RSTCT2);
445 ARM_SAVE(ARM_SYSST);
446
447 ULPD_SAVE(ULPD_IT_STATUS);
448 ULPD_SAVE(ULPD_CLOCK_CTRL);
449 ULPD_SAVE(ULPD_SOFT_REQ);
450 ULPD_SAVE(ULPD_STATUS_REQ);
451 ULPD_SAVE(ULPD_DPLL_CTRL);
452 ULPD_SAVE(ULPD_POWER_CTRL);
453
454 if (cpu_is_omap7xx()) {
455 MPUI7XX_SAVE(MPUI_CTRL);
456 MPUI7XX_SAVE(MPUI_DSP_STATUS);
457 MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG);
458 MPUI7XX_SAVE(MPUI_DSP_API_CONFIG);
459 MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG);
460 MPUI7XX_SAVE(EMIFS_CONFIG);
461 } else if (cpu_is_omap15xx()) {
462 MPUI1510_SAVE(MPUI_CTRL);
463 MPUI1510_SAVE(MPUI_DSP_STATUS);
464 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
465 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
466 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
467 MPUI1510_SAVE(EMIFS_CONFIG);
468 } else if (cpu_is_omap16xx()) {
469 MPUI1610_SAVE(MPUI_CTRL);
470 MPUI1610_SAVE(MPUI_DSP_STATUS);
471 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
472 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
473 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
474 MPUI1610_SAVE(EMIFS_CONFIG);
475 }
476
477 seq_printf(m,
478 "ARM_CKCTL_REG: 0x%-8x \n"
479 "ARM_IDLECT1_REG: 0x%-8x \n"
480 "ARM_IDLECT2_REG: 0x%-8x \n"
481 "ARM_IDLECT3_REG: 0x%-8x \n"
482 "ARM_EWUPCT_REG: 0x%-8x \n"
483 "ARM_RSTCT1_REG: 0x%-8x \n"
484 "ARM_RSTCT2_REG: 0x%-8x \n"
485 "ARM_SYSST_REG: 0x%-8x \n"
486 "ULPD_IT_STATUS_REG: 0x%-4x \n"
487 "ULPD_CLOCK_CTRL_REG: 0x%-4x \n"
488 "ULPD_SOFT_REQ_REG: 0x%-4x \n"
489 "ULPD_DPLL_CTRL_REG: 0x%-4x \n"
490 "ULPD_STATUS_REQ_REG: 0x%-4x \n"
491 "ULPD_POWER_CTRL_REG: 0x%-4x \n",
492 ARM_SHOW(ARM_CKCTL),
493 ARM_SHOW(ARM_IDLECT1),
494 ARM_SHOW(ARM_IDLECT2),
495 ARM_SHOW(ARM_IDLECT3),
496 ARM_SHOW(ARM_EWUPCT),
497 ARM_SHOW(ARM_RSTCT1),
498 ARM_SHOW(ARM_RSTCT2),
499 ARM_SHOW(ARM_SYSST),
500 ULPD_SHOW(ULPD_IT_STATUS),
501 ULPD_SHOW(ULPD_CLOCK_CTRL),
502 ULPD_SHOW(ULPD_SOFT_REQ),
503 ULPD_SHOW(ULPD_DPLL_CTRL),
504 ULPD_SHOW(ULPD_STATUS_REQ),
505 ULPD_SHOW(ULPD_POWER_CTRL));
506
507 if (cpu_is_omap7xx()) {
508 seq_printf(m,
509 "MPUI7XX_CTRL_REG 0x%-8x \n"
510 "MPUI7XX_DSP_STATUS_REG: 0x%-8x \n"
511 "MPUI7XX_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
512 "MPUI7XX_DSP_API_CONFIG_REG: 0x%-8x \n"
513 "MPUI7XX_SDRAM_CONFIG_REG: 0x%-8x \n"
514 "MPUI7XX_EMIFS_CONFIG_REG: 0x%-8x \n",
515 MPUI7XX_SHOW(MPUI_CTRL),
516 MPUI7XX_SHOW(MPUI_DSP_STATUS),
517 MPUI7XX_SHOW(MPUI_DSP_BOOT_CONFIG),
518 MPUI7XX_SHOW(MPUI_DSP_API_CONFIG),
519 MPUI7XX_SHOW(EMIFF_SDRAM_CONFIG),
520 MPUI7XX_SHOW(EMIFS_CONFIG));
521 } else if (cpu_is_omap15xx()) {
522 seq_printf(m,
523 "MPUI1510_CTRL_REG 0x%-8x \n"
524 "MPUI1510_DSP_STATUS_REG: 0x%-8x \n"
525 "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
526 "MPUI1510_DSP_API_CONFIG_REG: 0x%-8x \n"
527 "MPUI1510_SDRAM_CONFIG_REG: 0x%-8x \n"
528 "MPUI1510_EMIFS_CONFIG_REG: 0x%-8x \n",
529 MPUI1510_SHOW(MPUI_CTRL),
530 MPUI1510_SHOW(MPUI_DSP_STATUS),
531 MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
532 MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
533 MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
534 MPUI1510_SHOW(EMIFS_CONFIG));
535 } else if (cpu_is_omap16xx()) {
536 seq_printf(m,
537 "MPUI1610_CTRL_REG 0x%-8x \n"
538 "MPUI1610_DSP_STATUS_REG: 0x%-8x \n"
539 "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
540 "MPUI1610_DSP_API_CONFIG_REG: 0x%-8x \n"
541 "MPUI1610_SDRAM_CONFIG_REG: 0x%-8x \n"
542 "MPUI1610_EMIFS_CONFIG_REG: 0x%-8x \n",
543 MPUI1610_SHOW(MPUI_CTRL),
544 MPUI1610_SHOW(MPUI_DSP_STATUS),
545 MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
546 MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
547 MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
548 MPUI1610_SHOW(EMIFS_CONFIG));
549 }
550
551 return 0;
552}
553
554static int omap_pm_debug_open(struct inode *inode, struct file *file)
555{
556 return single_open(file, omap_pm_debug_show,
557 &inode->i_private);
558}
559
560static const struct file_operations omap_pm_debug_fops = {
561 .open = omap_pm_debug_open,
562 .read = seq_read,
563 .llseek = seq_lseek,
564 .release = single_release,
565};
566
567static void omap_pm_init_debugfs(void)
568{
569 struct dentry *d;
570
571 d = debugfs_create_dir("pm_debug", NULL);
572 if (!d)
573 return;
574
575 (void) debugfs_create_file("omap_pm", S_IWUSR | S_IRUGO,
576 d, NULL, &omap_pm_debug_fops);
577}
578
579#endif
580
581
582
583
584
585static int omap_pm_prepare(void)
586{
587
588 cpu_idle_poll_ctrl(true);
589 return 0;
590}
591
592
593
594
595
596
597
598
599static int omap_pm_enter(suspend_state_t state)
600{
601 switch (state)
602 {
603 case PM_SUSPEND_STANDBY:
604 case PM_SUSPEND_MEM:
605 omap1_pm_suspend();
606 break;
607 default:
608 return -EINVAL;
609 }
610
611 return 0;
612}
613
614
615
616
617
618
619
620
621
622static void omap_pm_finish(void)
623{
624 cpu_idle_poll_ctrl(false);
625}
626
627
628static irqreturn_t omap_wakeup_interrupt(int irq, void *dev)
629{
630 return IRQ_HANDLED;
631}
632
633static struct irqaction omap_wakeup_irq = {
634 .name = "peripheral wakeup",
635 .handler = omap_wakeup_interrupt
636};
637
638
639
640static const struct platform_suspend_ops omap_pm_ops = {
641 .prepare = omap_pm_prepare,
642 .enter = omap_pm_enter,
643 .finish = omap_pm_finish,
644 .valid = suspend_valid_only_mem,
645};
646
647static int __init omap_pm_init(void)
648{
649
650#ifdef CONFIG_OMAP_32K_TIMER
651 int error;
652#endif
653
654 if (!cpu_class_is_omap1())
655 return -ENODEV;
656
657 printk("Power Management for TI OMAP.\n");
658
659
660
661
662
663
664 if (cpu_is_omap7xx()) {
665 omap_sram_suspend = omap_sram_push(omap7xx_cpu_suspend,
666 omap7xx_cpu_suspend_sz);
667 } else if (cpu_is_omap15xx()) {
668 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
669 omap1510_cpu_suspend_sz);
670 } else if (cpu_is_omap16xx()) {
671 omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,
672 omap1610_cpu_suspend_sz);
673 }
674
675 if (omap_sram_suspend == NULL) {
676 printk(KERN_ERR "PM not initialized: Missing SRAM support\n");
677 return -ENODEV;
678 }
679
680 arm_pm_idle = omap1_pm_idle;
681
682 if (cpu_is_omap7xx())
683 setup_irq(INT_7XX_WAKE_UP_REQ, &omap_wakeup_irq);
684 else if (cpu_is_omap16xx())
685 setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
686
687
688
689
690 omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3);
691
692
693 omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
694
695
696 if (cpu_is_omap7xx())
697 omap_writel(OMAP7XX_IDLECT3_VAL, OMAP7XX_IDLECT3);
698 else if (cpu_is_omap16xx())
699 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
700
701 suspend_set_ops(&omap_pm_ops);
702
703#ifdef CONFIG_DEBUG_FS
704 omap_pm_init_debugfs();
705#endif
706
707#ifdef CONFIG_OMAP_32K_TIMER
708 error = sysfs_create_file(power_kobj, &sleep_while_idle_attr.attr);
709 if (error)
710 printk(KERN_ERR "sysfs_create_file failed: %d\n", error);
711#endif
712
713 if (cpu_is_omap16xx()) {
714
715 omap_cfg_reg(T20_1610_LOW_PWR);
716 }
717
718 return 0;
719}
720__initcall(omap_pm_init);
721