LXR linux/arch/mips/include/uapi/asm/inst.h

   1/*
   2 * Format of an instruction in memory.
   3 *
   4 * This file is subject to the terms and conditions of the GNU General Public
   5 * License.  See the file "COPYING" in the main directory of this archive
   6 * for more details.
   7 *
   8 * Copyright (C) 1996, 2000 by Ralf Baechle
   9 * Copyright (C) 2006 by Thiemo Seufer
  10 * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
  11 * Copyright (C) 2014 Imagination Technologies Ltd.
  12 */
  13#ifndef _UAPI_ASM_INST_H
  14#define _UAPI_ASM_INST_H
  15
  16/*
  17 * Major opcodes; before MIPS IV cop1x was called cop3.
  18 */
  19enum major_op {
  20        spec_op, bcond_op, j_op, jal_op,
  21        beq_op, bne_op, blez_op, bgtz_op,
  22        addi_op, addiu_op, slti_op, sltiu_op,
  23        andi_op, ori_op, xori_op, lui_op,
  24        cop0_op, cop1_op, cop2_op, cop1x_op,
  25        beql_op, bnel_op, blezl_op, bgtzl_op,
  26        daddi_op, daddiu_op, ldl_op, ldr_op,
  27        spec2_op, jalx_op, mdmx_op, spec3_op,
  28        lb_op, lh_op, lwl_op, lw_op,
  29        lbu_op, lhu_op, lwr_op, lwu_op,
  30        sb_op, sh_op, swl_op, sw_op,
  31        sdl_op, sdr_op, swr_op, cache_op,
  32        ll_op, lwc1_op, lwc2_op, pref_op,
  33        lld_op, ldc1_op, ldc2_op, ld_op,
  34        sc_op, swc1_op, swc2_op, major_3b_op,
  35        scd_op, sdc1_op, sdc2_op, sd_op
  36};
  37
  38/*
  39 * func field of spec opcode.
  40 */
  41enum spec_op {
  42        sll_op, movc_op, srl_op, sra_op,
  43        sllv_op, pmon_op, srlv_op, srav_op,
  44        jr_op, jalr_op, movz_op, movn_op,
  45        syscall_op, break_op, spim_op, sync_op,
  46        mfhi_op, mthi_op, mflo_op, mtlo_op,
  47        dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op,
  48        mult_op, multu_op, div_op, divu_op,
  49        dmult_op, dmultu_op, ddiv_op, ddivu_op,
  50        add_op, addu_op, sub_op, subu_op,
  51        and_op, or_op, xor_op, nor_op,
  52        spec3_unused_op, spec4_unused_op, slt_op, sltu_op,
  53        dadd_op, daddu_op, dsub_op, dsubu_op,
  54        tge_op, tgeu_op, tlt_op, tltu_op,
  55        teq_op, spec5_unused_op, tne_op, spec6_unused_op,
  56        dsll_op, spec7_unused_op, dsrl_op, dsra_op,
  57        dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op
  58};
  59
  60/*
  61 * func field of spec2 opcode.
  62 */
  63enum spec2_op {
  64        madd_op, maddu_op, mul_op, spec2_3_unused_op,
  65        msub_op, msubu_op, /* more unused ops */
  66        clz_op = 0x20, clo_op,
  67        dclz_op = 0x24, dclo_op,
  68        sdbpp_op = 0x3f
  69};
  70
  71/*
  72 * func field of spec3 opcode.
  73 */
  74enum spec3_op {
  75        ext_op, dextm_op, dextu_op, dext_op,
  76        ins_op, dinsm_op, dinsu_op, dins_op,
  77        lx_op     = 0x0a, lwle_op   = 0x19,
  78        lwre_op   = 0x1a, cachee_op = 0x1b,
  79        sbe_op    = 0x1c, she_op    = 0x1d,
  80        sce_op    = 0x1e, swe_op    = 0x1f,
  81        bshfl_op  = 0x20, swle_op   = 0x21,
  82        swre_op   = 0x22, prefe_op  = 0x23,
  83        dbshfl_op = 0x24, lbue_op   = 0x28,
  84        lhue_op   = 0x29, lbe_op    = 0x2c,
  85        lhe_op    = 0x2d, lle_op    = 0x2e,
  86        lwe_op    = 0x2f, rdhwr_op  = 0x3b
  87};
  88
  89/*
  90 * rt field of bcond opcodes.
  91 */
  92enum rt_op {
  93        bltz_op, bgez_op, bltzl_op, bgezl_op,
  94        spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,
  95        tgei_op, tgeiu_op, tlti_op, tltiu_op,
  96        teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,
  97        bltzal_op, bgezal_op, bltzall_op, bgezall_op,
  98        rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17,
  99        rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b,
 100        bposge32_op, rt_op_0x1d, rt_op_0x1e, rt_op_0x1f
 101};
 102
 103/*
 104 * rs field of cop opcodes.
 105 */
 106enum cop_op {
 107        mfc_op        = 0x00, dmfc_op       = 0x01,
 108        cfc_op        = 0x02, mfhc_op       = 0x03,
 109        mtc_op        = 0x04, dmtc_op       = 0x05,
 110        ctc_op        = 0x06, mthc_op       = 0x07,
 111        bc_op         = 0x08, cop_op        = 0x10,
 112        copm_op       = 0x18
 113};
 114
 115/*
 116 * rt field of cop.bc_op opcodes
 117 */
 118enum bcop_op {
 119        bcf_op, bct_op, bcfl_op, bctl_op
 120};
 121
 122/*
 123 * func field of cop0 coi opcodes.
 124 */
 125enum cop0_coi_func {
 126        tlbr_op       = 0x01, tlbwi_op      = 0x02,
 127        tlbwr_op      = 0x06, tlbp_op       = 0x08,
 128        rfe_op        = 0x10, eret_op       = 0x18
 129};
 130
 131/*
 132 * func field of cop0 com opcodes.
 133 */
 134enum cop0_com_func {
 135        tlbr1_op      = 0x01, tlbw_op       = 0x02,
 136        tlbp1_op      = 0x08, dctr_op       = 0x09,
 137        dctw_op       = 0x0a
 138};
 139
 140/*
 141 * fmt field of cop1 opcodes.
 142 */
 143enum cop1_fmt {
 144        s_fmt, d_fmt, e_fmt, q_fmt,
 145        w_fmt, l_fmt
 146};
 147
 148/*
 149 * func field of cop1 instructions using d, s or w format.
 150 */
 151enum cop1_sdw_func {
 152        fadd_op      =  0x00, fsub_op      =  0x01,
 153        fmul_op      =  0x02, fdiv_op      =  0x03,
 154        fsqrt_op     =  0x04, fabs_op      =  0x05,
 155        fmov_op      =  0x06, fneg_op      =  0x07,
 156        froundl_op   =  0x08, ftruncl_op   =  0x09,
 157        fceill_op    =  0x0a, ffloorl_op   =  0x0b,
 158        fround_op    =  0x0c, ftrunc_op    =  0x0d,
 159        fceil_op     =  0x0e, ffloor_op    =  0x0f,
 160        fmovc_op     =  0x11, fmovz_op     =  0x12,
 161        fmovn_op     =  0x13, frecip_op    =  0x15,
 162        frsqrt_op    =  0x16, fcvts_op     =  0x20,
 163        fcvtd_op     =  0x21, fcvte_op     =  0x22,
 164        fcvtw_op     =  0x24, fcvtl_op     =  0x25,
 165        fcmp_op      =  0x30
 166};
 167
 168/*
 169 * func field of cop1x opcodes (MIPS IV).
 170 */
 171enum cop1x_func {
 172        lwxc1_op     =  0x00, ldxc1_op     =  0x01,
 173        swxc1_op     =  0x08, sdxc1_op     =  0x09,
 174        pfetch_op    =  0x0f, madd_s_op    =  0x20,
 175        madd_d_op    =  0x21, madd_e_op    =  0x22,
 176        msub_s_op    =  0x28, msub_d_op    =  0x29,
 177        msub_e_op    =  0x2a, nmadd_s_op   =  0x30,
 178        nmadd_d_op   =  0x31, nmadd_e_op   =  0x32,
 179        nmsub_s_op   =  0x38, nmsub_d_op   =  0x39,
 180        nmsub_e_op   =  0x3a
 181};
 182
 183/*
 184 * func field for mad opcodes (MIPS IV).
 185 */
 186enum mad_func {
 187        madd_fp_op      = 0x08, msub_fp_op      = 0x0a,
 188        nmadd_fp_op     = 0x0c, nmsub_fp_op     = 0x0e
 189};
 190
 191/*
 192 * func field for special3 lx opcodes (Cavium Octeon).
 193 */
 194enum lx_func {
 195        lwx_op  = 0x00,
 196        lhx_op  = 0x04,
 197        lbux_op = 0x06,
 198        ldx_op  = 0x08,
 199        lwux_op = 0x10,
 200        lhux_op = 0x14,
 201        lbx_op  = 0x16,
 202};
 203
 204/*
 205 * (microMIPS) Major opcodes.
 206 */
 207enum mm_major_op {
 208        mm_pool32a_op, mm_pool16a_op, mm_lbu16_op, mm_move16_op,
 209        mm_addi32_op, mm_lbu32_op, mm_sb32_op, mm_lb32_op,
 210        mm_pool32b_op, mm_pool16b_op, mm_lhu16_op, mm_andi16_op,
 211        mm_addiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op,
 212        mm_pool32i_op, mm_pool16c_op, mm_lwsp16_op, mm_pool16d_op,
 213        mm_ori32_op, mm_pool32f_op, mm_reserved1_op, mm_reserved2_op,
 214        mm_pool32c_op, mm_lwgp16_op, mm_lw16_op, mm_pool16e_op,
 215        mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserved3_op,
 216        mm_reserved4_op, mm_pool16f_op, mm_sb16_op, mm_beqz16_op,
 217        mm_slti32_op, mm_beq32_op, mm_swc132_op, mm_lwc132_op,
 218        mm_reserved5_op, mm_reserved6_op, mm_sh16_op, mm_bnez16_op,
 219        mm_sltiu32_op, mm_bne32_op, mm_sdc132_op, mm_ldc132_op,
 220        mm_reserved7_op, mm_reserved8_op, mm_swsp16_op, mm_b16_op,
 221        mm_andi32_op, mm_j32_op, mm_sd32_op, mm_ld32_op,
 222        mm_reserved11_op, mm_reserved12_op, mm_sw16_op, mm_li16_op,
 223        mm_jalx32_op, mm_jal32_op, mm_sw32_op, mm_lw32_op,
 224};
 225
 226/*
 227 * (microMIPS) POOL32I minor opcodes.
 228 */
 229enum mm_32i_minor_op {
 230        mm_bltz_op, mm_bltzal_op, mm_bgez_op, mm_bgezal_op,
 231        mm_blez_op, mm_bnezc_op, mm_bgtz_op, mm_beqzc_op,
 232        mm_tlti_op, mm_tgei_op, mm_tltiu_op, mm_tgeiu_op,
 233        mm_tnei_op, mm_lui_op, mm_teqi_op, mm_reserved13_op,
 234        mm_synci_op, mm_bltzals_op, mm_reserved14_op, mm_bgezals_op,
 235        mm_bc2f_op, mm_bc2t_op, mm_reserved15_op, mm_reserved16_op,
 236        mm_reserved17_op, mm_reserved18_op, mm_bposge64_op, mm_bposge32_op,
 237        mm_bc1f_op, mm_bc1t_op, mm_reserved19_op, mm_reserved20_op,
 238        mm_bc1any2f_op, mm_bc1any2t_op, mm_bc1any4f_op, mm_bc1any4t_op,
 239};
 240
 241/*
 242 * (microMIPS) POOL32A minor opcodes.
 243 */
 244enum mm_32a_minor_op {
 245        mm_sll32_op = 0x000,
 246        mm_ins_op = 0x00c,
 247        mm_ext_op = 0x02c,
 248        mm_pool32axf_op = 0x03c,
 249        mm_srl32_op = 0x040,
 250        mm_sra_op = 0x080,
 251        mm_rotr_op = 0x0c0,
 252        mm_lwxs_op = 0x118,
 253        mm_addu32_op = 0x150,
 254        mm_subu32_op = 0x1d0,
 255        mm_and_op = 0x250,
 256        mm_or32_op = 0x290,
 257        mm_xor32_op = 0x310,
 258};
 259
 260/*
 261 * (microMIPS) POOL32B functions.
 262 */
 263enum mm_32b_func {
 264        mm_lwc2_func = 0x0,
 265        mm_lwp_func = 0x1,
 266        mm_ldc2_func = 0x2,
 267        mm_ldp_func = 0x4,
 268        mm_lwm32_func = 0x5,
 269        mm_cache_func = 0x6,
 270        mm_ldm_func = 0x7,
 271        mm_swc2_func = 0x8,
 272        mm_swp_func = 0x9,
 273        mm_sdc2_func = 0xa,
 274        mm_sdp_func = 0xc,
 275        mm_swm32_func = 0xd,
 276        mm_sdm_func = 0xf,
 277};
 278
 279/*
 280 * (microMIPS) POOL32C functions.
 281 */
 282enum mm_32c_func {
 283        mm_pref_func = 0x2,
 284        mm_ll_func = 0x3,
 285        mm_swr_func = 0x9,
 286        mm_sc_func = 0xb,
 287        mm_lwu_func = 0xe,
 288};
 289
 290/*
 291 * (microMIPS) POOL32AXF minor opcodes.
 292 */
 293enum mm_32axf_minor_op {
 294        mm_mfc0_op = 0x003,
 295        mm_mtc0_op = 0x00b,
 296        mm_tlbp_op = 0x00d,
 297        mm_jalr_op = 0x03c,
 298        mm_tlbr_op = 0x04d,
 299        mm_jalrhb_op = 0x07c,
 300        mm_tlbwi_op = 0x08d,
 301        mm_tlbwr_op = 0x0cd,
 302        mm_jalrs_op = 0x13c,
 303        mm_jalrshb_op = 0x17c,
 304        mm_syscall_op = 0x22d,
 305        mm_eret_op = 0x3cd,
 306};
 307
 308/*
 309 * (microMIPS) POOL32F minor opcodes.
 310 */
 311enum mm_32f_minor_op {
 312        mm_32f_00_op = 0x00,
 313        mm_32f_01_op = 0x01,
 314        mm_32f_02_op = 0x02,
 315        mm_32f_10_op = 0x08,
 316        mm_32f_11_op = 0x09,
 317        mm_32f_12_op = 0x0a,
 318        mm_32f_20_op = 0x10,
 319        mm_32f_30_op = 0x18,
 320        mm_32f_40_op = 0x20,
 321        mm_32f_41_op = 0x21,
 322        mm_32f_42_op = 0x22,
 323        mm_32f_50_op = 0x28,
 324        mm_32f_51_op = 0x29,
 325        mm_32f_52_op = 0x2a,
 326        mm_32f_60_op = 0x30,
 327        mm_32f_70_op = 0x38,
 328        mm_32f_73_op = 0x3b,
 329        mm_32f_74_op = 0x3c,
 330};
 331
 332/*
 333 * (microMIPS) POOL32F secondary minor opcodes.
 334 */
 335enum mm_32f_10_minor_op {
 336        mm_lwxc1_op = 0x1,
 337        mm_swxc1_op,
 338        mm_ldxc1_op,
 339        mm_sdxc1_op,
 340        mm_luxc1_op,
 341        mm_suxc1_op,
 342};
 343
 344enum mm_32f_func {
 345        mm_lwxc1_func = 0x048,
 346        mm_swxc1_func = 0x088,
 347        mm_ldxc1_func = 0x0c8,
 348        mm_sdxc1_func = 0x108,
 349};
 350
 351/*
 352 * (microMIPS) POOL32F secondary minor opcodes.
 353 */
 354enum mm_32f_40_minor_op {
 355        mm_fmovf_op,
 356        mm_fmovt_op,
 357};
 358
 359/*
 360 * (microMIPS) POOL32F secondary minor opcodes.
 361 */
 362enum mm_32f_60_minor_op {
 363        mm_fadd_op,
 364        mm_fsub_op,
 365        mm_fmul_op,
 366        mm_fdiv_op,
 367};
 368
 369/*
 370 * (microMIPS) POOL32F secondary minor opcodes.
 371 */
 372enum mm_32f_70_minor_op {
 373        mm_fmovn_op,
 374        mm_fmovz_op,
 375};
 376
 377/*
 378 * (microMIPS) POOL32FXF secondary minor opcodes for POOL32F.
 379 */
 380enum mm_32f_73_minor_op {
 381        mm_fmov0_op = 0x01,
 382        mm_fcvtl_op = 0x04,
 383        mm_movf0_op = 0x05,
 384        mm_frsqrt_op = 0x08,
 385        mm_ffloorl_op = 0x0c,
 386        mm_fabs0_op = 0x0d,
 387        mm_fcvtw_op = 0x24,
 388        mm_movt0_op = 0x25,
 389        mm_fsqrt_op = 0x28,
 390        mm_ffloorw_op = 0x2c,
 391        mm_fneg0_op = 0x2d,
 392        mm_cfc1_op = 0x40,
 393        mm_frecip_op = 0x48,
 394        mm_fceill_op = 0x4c,
 395        mm_fcvtd0_op = 0x4d,
 396        mm_ctc1_op = 0x60,
 397        mm_fceilw_op = 0x6c,
 398        mm_fcvts0_op = 0x6d,
 399        mm_mfc1_op = 0x80,
 400        mm_fmov1_op = 0x81,
 401        mm_movf1_op = 0x85,
 402        mm_ftruncl_op = 0x8c,
 403        mm_fabs1_op = 0x8d,
 404        mm_mtc1_op = 0xa0,
 405        mm_movt1_op = 0xa5,
 406        mm_ftruncw_op = 0xac,
 407        mm_fneg1_op = 0xad,
 408        mm_mfhc1_op = 0xc0,
 409        mm_froundl_op = 0xcc,
 410        mm_fcvtd1_op = 0xcd,
 411        mm_mthc1_op = 0xe0,
 412        mm_froundw_op = 0xec,
 413        mm_fcvts1_op = 0xed,
 414};
 415
 416/*
 417 * (microMIPS) POOL16C minor opcodes.
 418 */
 419enum mm_16c_minor_op {
 420        mm_lwm16_op = 0x04,
 421        mm_swm16_op = 0x05,
 422        mm_jr16_op = 0x0c,
 423        mm_jrc_op = 0x0d,
 424        mm_jalr16_op = 0x0e,
 425        mm_jalrs16_op = 0x0f,
 426        mm_jraddiusp_op = 0x18,
 427};
 428
 429/*
 430 * (microMIPS) POOL16D minor opcodes.
 431 */
 432enum mm_16d_minor_op {
 433        mm_addius5_func,
 434        mm_addiusp_func,
 435};
 436
 437/*
 438 * (MIPS16e) opcodes.
 439 */
 440enum MIPS16e_ops {
 441        MIPS16e_jal_op = 003,
 442        MIPS16e_ld_op = 007,
 443        MIPS16e_i8_op = 014,
 444        MIPS16e_sd_op = 017,
 445        MIPS16e_lb_op = 020,
 446        MIPS16e_lh_op = 021,
 447        MIPS16e_lwsp_op = 022,
 448        MIPS16e_lw_op = 023,
 449        MIPS16e_lbu_op = 024,
 450        MIPS16e_lhu_op = 025,
 451        MIPS16e_lwpc_op = 026,
 452        MIPS16e_lwu_op = 027,
 453        MIPS16e_sb_op = 030,
 454        MIPS16e_sh_op = 031,
 455        MIPS16e_swsp_op = 032,
 456        MIPS16e_sw_op = 033,
 457        MIPS16e_rr_op = 035,
 458        MIPS16e_extend_op = 036,
 459        MIPS16e_i64_op = 037,
 460};
 461
 462enum MIPS16e_i64_func {
 463        MIPS16e_ldsp_func,
 464        MIPS16e_sdsp_func,
 465        MIPS16e_sdrasp_func,
 466        MIPS16e_dadjsp_func,
 467        MIPS16e_ldpc_func,
 468};
 469
 470enum MIPS16e_rr_func {
 471        MIPS16e_jr_func,
 472};
 473
 474enum MIPS6e_i8_func {
 475        MIPS16e_swrasp_func = 02,
 476};
 477
 478/*
 479 * (microMIPS & MIPS16e) NOP instruction.
 480 */
 481#define MM_NOP16        0x0c00
 482
 483/*
 484 * Damn ...  bitfields depend from byteorder :-(
 485 */
 486#ifdef __MIPSEB__
 487#define __BITFIELD_FIELD(field, more)                                   \
 488        field;                                                          \
 489        more
 490
 491#elif defined(__MIPSEL__)
 492
 493#define __BITFIELD_FIELD(field, more)                                   \
 494        more                                                            \
 495        field;
 496
 497#else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */
 498#error "MIPS but neither __MIPSEL__ nor __MIPSEB__?"
 499#endif
 500
 501struct j_format {
 502        __BITFIELD_FIELD(unsigned int opcode : 6, /* Jump format */
 503        __BITFIELD_FIELD(unsigned int target : 26,
 504        ;))
 505};
 506
 507struct i_format {                       /* signed immediate format */
 508        __BITFIELD_FIELD(unsigned int opcode : 6,
 509        __BITFIELD_FIELD(unsigned int rs : 5,
 510        __BITFIELD_FIELD(unsigned int rt : 5,
 511        __BITFIELD_FIELD(signed int simmediate : 16,
 512        ;))))
 513};
 514
 515struct u_format {                       /* unsigned immediate format */
 516        __BITFIELD_FIELD(unsigned int opcode : 6,
 517        __BITFIELD_FIELD(unsigned int rs : 5,
 518        __BITFIELD_FIELD(unsigned int rt : 5,
 519        __BITFIELD_FIELD(unsigned int uimmediate : 16,
 520        ;))))
 521};
 522
 523struct c_format {                       /* Cache (>= R6000) format */
 524        __BITFIELD_FIELD(unsigned int opcode : 6,
 525        __BITFIELD_FIELD(unsigned int rs : 5,
 526        __BITFIELD_FIELD(unsigned int c_op : 3,
 527        __BITFIELD_FIELD(unsigned int cache : 2,
 528        __BITFIELD_FIELD(unsigned int simmediate : 16,
 529        ;)))))
 530};
 531
 532struct r_format {                       /* Register format */
 533        __BITFIELD_FIELD(unsigned int opcode : 6,
 534        __BITFIELD_FIELD(unsigned int rs : 5,
 535        __BITFIELD_FIELD(unsigned int rt : 5,
 536        __BITFIELD_FIELD(unsigned int rd : 5,
 537        __BITFIELD_FIELD(unsigned int re : 5,
 538        __BITFIELD_FIELD(unsigned int func : 6,
 539        ;))))))
 540};
 541
 542struct p_format {               /* Performance counter format (R10000) */
 543        __BITFIELD_FIELD(unsigned int opcode : 6,
 544        __BITFIELD_FIELD(unsigned int rs : 5,
 545        __BITFIELD_FIELD(unsigned int rt : 5,
 546        __BITFIELD_FIELD(unsigned int rd : 5,
 547        __BITFIELD_FIELD(unsigned int re : 5,
 548        __BITFIELD_FIELD(unsigned int func : 6,
 549        ;))))))
 550};
 551
 552struct f_format {                       /* FPU register format */
 553        __BITFIELD_FIELD(unsigned int opcode : 6,
 554        __BITFIELD_FIELD(unsigned int : 1,
 555        __BITFIELD_FIELD(unsigned int fmt : 4,
 556        __BITFIELD_FIELD(unsigned int rt : 5,
 557        __BITFIELD_FIELD(unsigned int rd : 5,
 558        __BITFIELD_FIELD(unsigned int re : 5,
 559        __BITFIELD_FIELD(unsigned int func : 6,
 560        ;)))))))
 561};
 562
 563struct ma_format {              /* FPU multiply and add format (MIPS IV) */
 564        __BITFIELD_FIELD(unsigned int opcode : 6,
 565        __BITFIELD_FIELD(unsigned int fr : 5,
 566        __BITFIELD_FIELD(unsigned int ft : 5,
 567        __BITFIELD_FIELD(unsigned int fs : 5,
 568        __BITFIELD_FIELD(unsigned int fd : 5,
 569        __BITFIELD_FIELD(unsigned int func : 4,
 570        __BITFIELD_FIELD(unsigned int fmt : 2,
 571        ;)))))))
 572};
 573
 574struct b_format {                       /* BREAK and SYSCALL */
 575        __BITFIELD_FIELD(unsigned int opcode : 6,
 576        __BITFIELD_FIELD(unsigned int code : 20,
 577        __BITFIELD_FIELD(unsigned int func : 6,
 578        ;)))
 579};
 580
 581struct ps_format {                      /* MIPS-3D / paired single format */
 582        __BITFIELD_FIELD(unsigned int opcode : 6,
 583        __BITFIELD_FIELD(unsigned int rs : 5,
 584        __BITFIELD_FIELD(unsigned int ft : 5,
 585        __BITFIELD_FIELD(unsigned int fs : 5,
 586        __BITFIELD_FIELD(unsigned int fd : 5,
 587        __BITFIELD_FIELD(unsigned int func : 6,
 588        ;))))))
 589};
 590
 591struct v_format {                               /* MDMX vector format */
 592        __BITFIELD_FIELD(unsigned int opcode : 6,
 593        __BITFIELD_FIELD(unsigned int sel : 4,
 594        __BITFIELD_FIELD(unsigned int fmt : 1,
 595        __BITFIELD_FIELD(unsigned int vt : 5,
 596        __BITFIELD_FIELD(unsigned int vs : 5,
 597        __BITFIELD_FIELD(unsigned int vd : 5,
 598        __BITFIELD_FIELD(unsigned int func : 6,
 599        ;)))))))
 600};
 601
 602struct spec3_format {   /* SPEC3 */
 603        __BITFIELD_FIELD(unsigned int opcode:6,
 604        __BITFIELD_FIELD(unsigned int rs:5,
 605        __BITFIELD_FIELD(unsigned int rt:5,
 606        __BITFIELD_FIELD(signed int simmediate:9,
 607        __BITFIELD_FIELD(unsigned int func:7,
 608        ;)))))
 609};
 610
 611/*
 612 * microMIPS instruction formats (32-bit length)
 613 *
 614 * NOTE:
 615 *      Parenthesis denote whether the format is a microMIPS instruction or
 616 *      if it is MIPS32 instruction re-encoded for use in the microMIPS ASE.
 617 */
 618struct fb_format {              /* FPU branch format (MIPS32) */
 619        __BITFIELD_FIELD(unsigned int opcode : 6,
 620        __BITFIELD_FIELD(unsigned int bc : 5,
 621        __BITFIELD_FIELD(unsigned int cc : 3,
 622        __BITFIELD_FIELD(unsigned int flag : 2,
 623        __BITFIELD_FIELD(signed int simmediate : 16,
 624        ;)))))
 625};
 626
 627struct fp0_format {             /* FPU multiply and add format (MIPS32) */
 628        __BITFIELD_FIELD(unsigned int opcode : 6,
 629        __BITFIELD_FIELD(unsigned int fmt : 5,
 630        __BITFIELD_FIELD(unsigned int ft : 5,
 631        __BITFIELD_FIELD(unsigned int fs : 5,
 632        __BITFIELD_FIELD(unsigned int fd : 5,
 633        __BITFIELD_FIELD(unsigned int func : 6,
 634        ;))))))
 635};
 636
 637struct mm_fp0_format {          /* FPU multipy and add format (microMIPS) */
 638        __BITFIELD_FIELD(unsigned int opcode : 6,
 639        __BITFIELD_FIELD(unsigned int ft : 5,
 640        __BITFIELD_FIELD(unsigned int fs : 5,
 641        __BITFIELD_FIELD(unsigned int fd : 5,
 642        __BITFIELD_FIELD(unsigned int fmt : 3,
 643        __BITFIELD_FIELD(unsigned int op : 2,
 644        __BITFIELD_FIELD(unsigned int func : 6,
 645        ;)))))))
 646};
 647
 648struct fp1_format {             /* FPU mfc1 and cfc1 format (MIPS32) */
 649        __BITFIELD_FIELD(unsigned int opcode : 6,
 650        __BITFIELD_FIELD(unsigned int op : 5,
 651        __BITFIELD_FIELD(unsigned int rt : 5,
 652        __BITFIELD_FIELD(unsigned int fs : 5,
 653        __BITFIELD_FIELD(unsigned int fd : 5,
 654        __BITFIELD_FIELD(unsigned int func : 6,
 655        ;))))))
 656};
 657
 658struct mm_fp1_format {          /* FPU mfc1 and cfc1 format (microMIPS) */
 659        __BITFIELD_FIELD(unsigned int opcode : 6,
 660        __BITFIELD_FIELD(unsigned int rt : 5,
 661        __BITFIELD_FIELD(unsigned int fs : 5,
 662        __BITFIELD_FIELD(unsigned int fmt : 2,
 663        __BITFIELD_FIELD(unsigned int op : 8,
 664        __BITFIELD_FIELD(unsigned int func : 6,
 665        ;))))))
 666};
 667
 668struct mm_fp2_format {          /* FPU movt and movf format (microMIPS) */
 669        __BITFIELD_FIELD(unsigned int opcode : 6,
 670        __BITFIELD_FIELD(unsigned int fd : 5,
 671        __BITFIELD_FIELD(unsigned int fs : 5,
 672        __BITFIELD_FIELD(unsigned int cc : 3,
 673        __BITFIELD_FIELD(unsigned int zero : 2,
 674        __BITFIELD_FIELD(unsigned int fmt : 2,
 675        __BITFIELD_FIELD(unsigned int op : 3,
 676        __BITFIELD_FIELD(unsigned int func : 6,
 677        ;))))))))
 678};
 679
 680struct mm_fp3_format {          /* FPU abs and neg format (microMIPS) */
 681        __BITFIELD_FIELD(unsigned int opcode : 6,
 682        __BITFIELD_FIELD(unsigned int rt : 5,
 683        __BITFIELD_FIELD(unsigned int fs : 5,
 684        __BITFIELD_FIELD(unsigned int fmt : 3,
 685        __BITFIELD_FIELD(unsigned int op : 7,
 686        __BITFIELD_FIELD(unsigned int func : 6,
 687        ;))))))
 688};
 689
 690struct mm_fp4_format {          /* FPU c.cond format (microMIPS) */
 691        __BITFIELD_FIELD(unsigned int opcode : 6,
 692        __BITFIELD_FIELD(unsigned int rt : 5,
 693        __BITFIELD_FIELD(unsigned int fs : 5,
 694        __BITFIELD_FIELD(unsigned int cc : 3,
 695        __BITFIELD_FIELD(unsigned int fmt : 3,
 696        __BITFIELD_FIELD(unsigned int cond : 4,
 697        __BITFIELD_FIELD(unsigned int func : 6,
 698        ;)))))))
 699};
 700
 701struct mm_fp5_format {          /* FPU lwxc1 and swxc1 format (microMIPS) */
 702        __BITFIELD_FIELD(unsigned int opcode : 6,
 703        __BITFIELD_FIELD(unsigned int index : 5,
 704        __BITFIELD_FIELD(unsigned int base : 5,
 705        __BITFIELD_FIELD(unsigned int fd : 5,
 706        __BITFIELD_FIELD(unsigned int op : 5,
 707        __BITFIELD_FIELD(unsigned int func : 6,
 708        ;))))))
 709};
 710
 711struct fp6_format {             /* FPU madd and msub format (MIPS IV) */
 712        __BITFIELD_FIELD(unsigned int opcode : 6,
 713        __BITFIELD_FIELD(unsigned int fr : 5,
 714        __BITFIELD_FIELD(unsigned int ft : 5,
 715        __BITFIELD_FIELD(unsigned int fs : 5,
 716        __BITFIELD_FIELD(unsigned int fd : 5,
 717        __BITFIELD_FIELD(unsigned int func : 6,
 718        ;))))))
 719};
 720
 721struct mm_fp6_format {          /* FPU madd and msub format (microMIPS) */
 722        __BITFIELD_FIELD(unsigned int opcode : 6,
 723        __BITFIELD_FIELD(unsigned int ft : 5,
 724        __BITFIELD_FIELD(unsigned int fs : 5,
 725        __BITFIELD_FIELD(unsigned int fd : 5,
 726        __BITFIELD_FIELD(unsigned int fr : 5,
 727        __BITFIELD_FIELD(unsigned int func : 6,
 728        ;))))))
 729};
 730
 731struct mm_i_format {            /* Immediate format (microMIPS) */
 732        __BITFIELD_FIELD(unsigned int opcode : 6,
 733        __BITFIELD_FIELD(unsigned int rt : 5,
 734        __BITFIELD_FIELD(unsigned int rs : 5,
 735        __BITFIELD_FIELD(signed int simmediate : 16,
 736        ;))))
 737};
 738
 739struct mm_m_format {            /* Multi-word load/store format (microMIPS) */
 740        __BITFIELD_FIELD(unsigned int opcode : 6,
 741        __BITFIELD_FIELD(unsigned int rd : 5,
 742        __BITFIELD_FIELD(unsigned int base : 5,
 743        __BITFIELD_FIELD(unsigned int func : 4,
 744        __BITFIELD_FIELD(signed int simmediate : 12,
 745        ;)))))
 746};
 747
 748struct mm_x_format {            /* Scaled indexed load format (microMIPS) */
 749        __BITFIELD_FIELD(unsigned int opcode : 6,
 750        __BITFIELD_FIELD(unsigned int index : 5,
 751        __BITFIELD_FIELD(unsigned int base : 5,
 752        __BITFIELD_FIELD(unsigned int rd : 5,
 753        __BITFIELD_FIELD(unsigned int func : 11,
 754        ;)))))
 755};
 756
 757/*
 758 * microMIPS instruction formats (16-bit length)
 759 */
 760struct mm_b0_format {           /* Unconditional branch format (microMIPS) */
 761        __BITFIELD_FIELD(unsigned int opcode : 6,
 762        __BITFIELD_FIELD(signed int simmediate : 10,
 763        __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
 764        ;)))
 765};
 766
 767struct mm_b1_format {           /* Conditional branch format (microMIPS) */
 768        __BITFIELD_FIELD(unsigned int opcode : 6,
 769        __BITFIELD_FIELD(unsigned int rs : 3,
 770        __BITFIELD_FIELD(signed int simmediate : 7,
 771        __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
 772        ;))))
 773};
 774
 775struct mm16_m_format {          /* Multi-word load/store format */
 776        __BITFIELD_FIELD(unsigned int opcode : 6,
 777        __BITFIELD_FIELD(unsigned int func : 4,
 778        __BITFIELD_FIELD(unsigned int rlist : 2,
 779        __BITFIELD_FIELD(unsigned int imm : 4,
 780        __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
 781        ;)))))
 782};
 783
 784struct mm16_rb_format {         /* Signed immediate format */
 785        __BITFIELD_FIELD(unsigned int opcode : 6,
 786        __BITFIELD_FIELD(unsigned int rt : 3,
 787        __BITFIELD_FIELD(unsigned int base : 3,
 788        __BITFIELD_FIELD(signed int simmediate : 4,
 789        __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
 790        ;)))))
 791};
 792
 793struct mm16_r3_format {         /* Load from global pointer format */
 794        __BITFIELD_FIELD(unsigned int opcode : 6,
 795        __BITFIELD_FIELD(unsigned int rt : 3,
 796        __BITFIELD_FIELD(signed int simmediate : 7,
 797        __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
 798        ;))))
 799};
 800
 801struct mm16_r5_format {         /* Load/store from stack pointer format */
 802        __BITFIELD_FIELD(unsigned int opcode : 6,
 803        __BITFIELD_FIELD(unsigned int rt : 5,
 804        __BITFIELD_FIELD(signed int simmediate : 5,
 805        __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
 806        ;))))
 807};
 808
 809/*
 810 * MIPS16e instruction formats (16-bit length)
 811 */
 812struct m16e_rr {
 813        __BITFIELD_FIELD(unsigned int opcode : 5,
 814        __BITFIELD_FIELD(unsigned int rx : 3,
 815        __BITFIELD_FIELD(unsigned int nd : 1,
 816        __BITFIELD_FIELD(unsigned int l : 1,
 817        __BITFIELD_FIELD(unsigned int ra : 1,
 818        __BITFIELD_FIELD(unsigned int func : 5,
 819        ;))))))
 820};
 821
 822struct m16e_jal {
 823        __BITFIELD_FIELD(unsigned int opcode : 5,
 824        __BITFIELD_FIELD(unsigned int x : 1,
 825        __BITFIELD_FIELD(unsigned int imm20_16 : 5,
 826        __BITFIELD_FIELD(signed int imm25_21 : 5,
 827        ;))))
 828};
 829
 830struct m16e_i64 {
 831        __BITFIELD_FIELD(unsigned int opcode : 5,
 832        __BITFIELD_FIELD(unsigned int func : 3,
 833        __BITFIELD_FIELD(unsigned int imm : 8,
 834        ;)))
 835};
 836
 837struct m16e_ri64 {
 838        __BITFIELD_FIELD(unsigned int opcode : 5,
 839        __BITFIELD_FIELD(unsigned int func : 3,
 840        __BITFIELD_FIELD(unsigned int ry : 3,
 841        __BITFIELD_FIELD(unsigned int imm : 5,
 842        ;))))
 843};
 844
 845struct m16e_ri {
 846        __BITFIELD_FIELD(unsigned int opcode : 5,
 847        __BITFIELD_FIELD(unsigned int rx : 3,
 848        __BITFIELD_FIELD(unsigned int imm : 8,
 849        ;)))
 850};
 851
 852struct m16e_rri {
 853        __BITFIELD_FIELD(unsigned int opcode : 5,
 854        __BITFIELD_FIELD(unsigned int rx : 3,
 855        __BITFIELD_FIELD(unsigned int ry : 3,
 856        __BITFIELD_FIELD(unsigned int imm : 5,
 857        ;))))
 858};
 859
 860struct m16e_i8 {
 861        __BITFIELD_FIELD(unsigned int opcode : 5,
 862        __BITFIELD_FIELD(unsigned int func : 3,
 863        __BITFIELD_FIELD(unsigned int imm : 8,
 864        ;)))
 865};
 866
 867union mips_instruction {
 868        unsigned int word;
 869        unsigned short halfword[2];
 870        unsigned char byte[4];
 871        struct j_format j_format;
 872        struct i_format i_format;
 873        struct u_format u_format;
 874        struct c_format c_format;
 875        struct r_format r_format;
 876        struct p_format p_format;
 877        struct f_format f_format;
 878        struct ma_format ma_format;
 879        struct b_format b_format;
 880        struct ps_format ps_format;
 881        struct v_format v_format;
 882        struct spec3_format spec3_format;
 883        struct fb_format fb_format;
 884        struct fp0_format fp0_format;
 885        struct mm_fp0_format mm_fp0_format;
 886        struct fp1_format fp1_format;
 887        struct mm_fp1_format mm_fp1_format;
 888        struct mm_fp2_format mm_fp2_format;
 889        struct mm_fp3_format mm_fp3_format;
 890        struct mm_fp4_format mm_fp4_format;
 891        struct mm_fp5_format mm_fp5_format;
 892        struct fp6_format fp6_format;
 893        struct mm_fp6_format mm_fp6_format;
 894        struct mm_i_format mm_i_format;
 895        struct mm_m_format mm_m_format;
 896        struct mm_x_format mm_x_format;
 897        struct mm_b0_format mm_b0_format;
 898        struct mm_b1_format mm_b1_format;
 899        struct mm16_m_format mm16_m_format ;
 900        struct mm16_rb_format mm16_rb_format;
 901        struct mm16_r3_format mm16_r3_format;
 902        struct mm16_r5_format mm16_r5_format;
 903};
 904
 905union mips16e_instruction {
 906        unsigned int full : 16;
 907        struct m16e_rr rr;
 908        struct m16e_jal jal;
 909        struct m16e_i64 i64;
 910        struct m16e_ri64 ri64;
 911        struct m16e_ri ri;
 912        struct m16e_rri rri;
 913        struct m16e_i8 i8;
 914};
 915
 916#endif /* _UAPI_ASM_INST_H */
 917