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23#ifndef _SPU_H
24#define _SPU_H
25#ifdef __KERNEL__
26
27#include <linux/workqueue.h>
28#include <linux/device.h>
29#include <linux/mutex.h>
30
31#define LS_SIZE (256 * 1024)
32#define LS_ADDR_MASK (LS_SIZE - 1)
33
34#define MFC_PUT_CMD 0x20
35#define MFC_PUTS_CMD 0x28
36#define MFC_PUTR_CMD 0x30
37#define MFC_PUTF_CMD 0x22
38#define MFC_PUTB_CMD 0x21
39#define MFC_PUTFS_CMD 0x2A
40#define MFC_PUTBS_CMD 0x29
41#define MFC_PUTRF_CMD 0x32
42#define MFC_PUTRB_CMD 0x31
43#define MFC_PUTL_CMD 0x24
44#define MFC_PUTRL_CMD 0x34
45#define MFC_PUTLF_CMD 0x26
46#define MFC_PUTLB_CMD 0x25
47#define MFC_PUTRLF_CMD 0x36
48#define MFC_PUTRLB_CMD 0x35
49
50#define MFC_GET_CMD 0x40
51#define MFC_GETS_CMD 0x48
52#define MFC_GETF_CMD 0x42
53#define MFC_GETB_CMD 0x41
54#define MFC_GETFS_CMD 0x4A
55#define MFC_GETBS_CMD 0x49
56#define MFC_GETL_CMD 0x44
57#define MFC_GETLF_CMD 0x46
58#define MFC_GETLB_CMD 0x45
59
60#define MFC_SDCRT_CMD 0x80
61#define MFC_SDCRTST_CMD 0x81
62#define MFC_SDCRZ_CMD 0x89
63#define MFC_SDCRS_CMD 0x8D
64#define MFC_SDCRF_CMD 0x8F
65
66#define MFC_GETLLAR_CMD 0xD0
67#define MFC_PUTLLC_CMD 0xB4
68#define MFC_PUTLLUC_CMD 0xB0
69#define MFC_PUTQLLUC_CMD 0xB8
70#define MFC_SNDSIG_CMD 0xA0
71#define MFC_SNDSIGB_CMD 0xA1
72#define MFC_SNDSIGF_CMD 0xA2
73#define MFC_BARRIER_CMD 0xC0
74#define MFC_EIEIO_CMD 0xC8
75#define MFC_SYNC_CMD 0xCC
76
77#define MFC_MIN_DMA_SIZE_SHIFT 4
78#define MFC_MAX_DMA_SIZE_SHIFT 14
79#define MFC_MIN_DMA_SIZE (1 << MFC_MIN_DMA_SIZE_SHIFT)
80#define MFC_MAX_DMA_SIZE (1 << MFC_MAX_DMA_SIZE_SHIFT)
81#define MFC_MIN_DMA_SIZE_MASK (MFC_MIN_DMA_SIZE - 1)
82#define MFC_MAX_DMA_SIZE_MASK (MFC_MAX_DMA_SIZE - 1)
83#define MFC_MIN_DMA_LIST_SIZE 0x0008
84#define MFC_MAX_DMA_LIST_SIZE 0x4000
85
86#define MFC_TAGID_TO_TAGMASK(tag_id) (1 << (tag_id & 0x1F))
87
88
89#define MFC_DMA_TAG_STATUS_UPDATE_EVENT 0x00000001
90#define MFC_DMA_TAG_CMD_STALL_NOTIFY_EVENT 0x00000002
91#define MFC_DMA_QUEUE_AVAILABLE_EVENT 0x00000008
92#define MFC_SPU_MAILBOX_WRITTEN_EVENT 0x00000010
93#define MFC_DECREMENTER_EVENT 0x00000020
94#define MFC_PU_INT_MAILBOX_AVAILABLE_EVENT 0x00000040
95#define MFC_PU_MAILBOX_AVAILABLE_EVENT 0x00000080
96#define MFC_SIGNAL_2_EVENT 0x00000100
97#define MFC_SIGNAL_1_EVENT 0x00000200
98#define MFC_LLR_LOST_EVENT 0x00000400
99#define MFC_PRIV_ATTN_EVENT 0x00000800
100#define MFC_MULTI_SRC_EVENT 0x00001000
101
102
103#define SPU_CONTEXT_SWITCH_PENDING 0UL
104#define SPU_CONTEXT_FAULT_PENDING 1UL
105
106struct spu_context;
107struct spu_runqueue;
108struct spu_lscsa;
109struct device_node;
110
111enum spu_utilization_state {
112 SPU_UTIL_USER,
113 SPU_UTIL_SYSTEM,
114 SPU_UTIL_IOWAIT,
115 SPU_UTIL_IDLE_LOADED,
116 SPU_UTIL_MAX
117};
118
119struct spu {
120 const char *name;
121 unsigned long local_store_phys;
122 u8 *local_store;
123 unsigned long problem_phys;
124 struct spu_problem __iomem *problem;
125 struct spu_priv2 __iomem *priv2;
126 struct list_head cbe_list;
127 struct list_head full_list;
128 enum { SPU_FREE, SPU_USED } alloc_state;
129 int number;
130 unsigned int irqs[3];
131 u32 node;
132 unsigned long flags;
133 u64 class_0_pending;
134 u64 class_0_dar;
135 u64 class_1_dar;
136 u64 class_1_dsisr;
137 size_t ls_size;
138 unsigned int slb_replace;
139 struct mm_struct *mm;
140 struct spu_context *ctx;
141 struct spu_runqueue *rq;
142 unsigned long long timestamp;
143 pid_t pid;
144 pid_t tgid;
145 spinlock_t register_lock;
146
147 void (* wbox_callback)(struct spu *spu);
148 void (* ibox_callback)(struct spu *spu);
149 void (* stop_callback)(struct spu *spu, int irq);
150 void (* mfc_callback)(struct spu *spu);
151
152 char irq_c0[8];
153 char irq_c1[8];
154 char irq_c2[8];
155
156 u64 spe_id;
157
158 void* pdata;
159
160
161 struct device_node *devnode;
162
163
164 struct spu_priv1 __iomem *priv1;
165
166
167 u64 shadow_int_mask_RW[3];
168
169 struct device dev;
170
171 int has_mem_affinity;
172 struct list_head aff_list;
173
174 struct {
175
176 enum spu_utilization_state util_state;
177 unsigned long long tstamp;
178 unsigned long long times[SPU_UTIL_MAX];
179 unsigned long long vol_ctx_switch;
180 unsigned long long invol_ctx_switch;
181 unsigned long long min_flt;
182 unsigned long long maj_flt;
183 unsigned long long hash_flt;
184 unsigned long long slb_flt;
185 unsigned long long class2_intr;
186 unsigned long long libassist;
187 } stats;
188};
189
190struct cbe_spu_info {
191 struct mutex list_mutex;
192 struct list_head spus;
193 int n_spus;
194 int nr_active;
195 atomic_t busy_spus;
196 atomic_t reserved_spus;
197};
198
199extern struct cbe_spu_info cbe_spu_info[];
200
201void spu_init_channels(struct spu *spu);
202void spu_irq_setaffinity(struct spu *spu, int cpu);
203
204void spu_setup_kernel_slbs(struct spu *spu, struct spu_lscsa *lscsa,
205 void *code, int code_size);
206
207extern void spu_invalidate_slbs(struct spu *spu);
208extern void spu_associate_mm(struct spu *spu, struct mm_struct *mm);
209int spu_64k_pages_available(void);
210
211
212struct mm_struct;
213extern void spu_flush_all_slbs(struct mm_struct *mm);
214
215
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217
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219
220
221
222
223void spu_set_profile_private_kref(struct spu_context *ctx,
224 struct kref *prof_info_kref,
225 void ( * prof_info_release) (struct kref *kref));
226
227void *spu_get_profile_private_kref(struct spu_context *ctx);
228
229
230struct spu_syscall_block {
231 u64 nr_ret;
232 u64 parm[6];
233};
234extern long spu_sys_callback(struct spu_syscall_block *s);
235
236
237struct file;
238struct coredump_params;
239struct spufs_calls {
240 long (*create_thread)(const char __user *name,
241 unsigned int flags, umode_t mode,
242 struct file *neighbor);
243 long (*spu_run)(struct file *filp, __u32 __user *unpc,
244 __u32 __user *ustatus);
245 int (*coredump_extra_notes_size)(void);
246 int (*coredump_extra_notes_write)(struct coredump_params *cprm);
247 void (*notify_spus_active)(void);
248 struct module *owner;
249};
250
251
252#define SPE_EVENT_DMA_ALIGNMENT 0x0008
253#define SPE_EVENT_SPE_ERROR 0x0010
254#define SPE_EVENT_SPE_DATA_SEGMENT 0x0020
255#define SPE_EVENT_SPE_DATA_STORAGE 0x0040
256#define SPE_EVENT_INVALID_DMA 0x0800
257
258
259
260
261#define SPU_CREATE_EVENTS_ENABLED 0x0001
262#define SPU_CREATE_GANG 0x0002
263#define SPU_CREATE_NOSCHED 0x0004
264#define SPU_CREATE_ISOLATE 0x0008
265#define SPU_CREATE_AFFINITY_SPU 0x0010
266#define SPU_CREATE_AFFINITY_MEM 0x0020
267
268#define SPU_CREATE_FLAG_ALL 0x003f
269
270
271int register_spu_syscalls(struct spufs_calls *calls);
272void unregister_spu_syscalls(struct spufs_calls *calls);
273
274int spu_add_dev_attr(struct device_attribute *attr);
275void spu_remove_dev_attr(struct device_attribute *attr);
276
277int spu_add_dev_attr_group(struct attribute_group *attrs);
278void spu_remove_dev_attr_group(struct attribute_group *attrs);
279
280int spu_handle_mm_fault(struct mm_struct *mm, unsigned long ea,
281 unsigned long dsisr, unsigned *flt);
282
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295
296
297
298struct notifier_block;
299int spu_switch_event_register(struct notifier_block * n);
300int spu_switch_event_unregister(struct notifier_block * n);
301
302extern void notify_spus_active(void);
303extern void do_notify_spus_active(void);
304
305
306
307
308
309union mfc_tag_size_class_cmd {
310 struct {
311 u16 mfc_size;
312 u16 mfc_tag;
313 u8 pad;
314 u8 mfc_rclassid;
315 u16 mfc_cmd;
316 } u;
317 struct {
318 u32 mfc_size_tag32;
319 u32 mfc_class_cmd32;
320 } by32;
321 u64 all64;
322};
323
324struct mfc_cq_sr {
325 u64 mfc_cq_data0_RW;
326 u64 mfc_cq_data1_RW;
327 u64 mfc_cq_data2_RW;
328 u64 mfc_cq_data3_RW;
329};
330
331struct spu_problem {
332#define MS_SYNC_PENDING 1L
333 u64 spc_mssync_RW;
334 u8 pad_0x0008_0x3000[0x3000 - 0x0008];
335
336
337 u8 pad_0x3000_0x3004[0x4];
338 u32 mfc_lsa_W;
339 u64 mfc_ea_W;
340 union mfc_tag_size_class_cmd mfc_union_W;
341 u8 pad_0x3018_0x3104[0xec];
342 u32 dma_qstatus_R;
343 u8 pad_0x3108_0x3204[0xfc];
344 u32 dma_querytype_RW;
345 u8 pad_0x3208_0x321c[0x14];
346 u32 dma_querymask_RW;
347 u8 pad_0x3220_0x322c[0xc];
348 u32 dma_tagstatus_R;
349#define DMA_TAGSTATUS_INTR_ANY 1u
350#define DMA_TAGSTATUS_INTR_ALL 2u
351 u8 pad_0x3230_0x4000[0x4000 - 0x3230];
352
353
354 u8 pad_0x4000_0x4004[0x4];
355 u32 pu_mb_R;
356 u8 pad_0x4008_0x400c[0x4];
357 u32 spu_mb_W;
358 u8 pad_0x4010_0x4014[0x4];
359 u32 mb_stat_R;
360 u8 pad_0x4018_0x401c[0x4];
361 u32 spu_runcntl_RW;
362#define SPU_RUNCNTL_STOP 0L
363#define SPU_RUNCNTL_RUNNABLE 1L
364#define SPU_RUNCNTL_ISOLATE 2L
365 u8 pad_0x4020_0x4024[0x4];
366 u32 spu_status_R;
367#define SPU_STOP_STATUS_SHIFT 16
368#define SPU_STATUS_STOPPED 0x0
369#define SPU_STATUS_RUNNING 0x1
370#define SPU_STATUS_STOPPED_BY_STOP 0x2
371#define SPU_STATUS_STOPPED_BY_HALT 0x4
372#define SPU_STATUS_WAITING_FOR_CHANNEL 0x8
373#define SPU_STATUS_SINGLE_STEP 0x10
374#define SPU_STATUS_INVALID_INSTR 0x20
375#define SPU_STATUS_INVALID_CH 0x40
376#define SPU_STATUS_ISOLATED_STATE 0x80
377#define SPU_STATUS_ISOLATED_LOAD_STATUS 0x200
378#define SPU_STATUS_ISOLATED_EXIT_STATUS 0x400
379 u8 pad_0x4028_0x402c[0x4];
380 u32 spu_spe_R;
381 u8 pad_0x4030_0x4034[0x4];
382 u32 spu_npc_RW;
383 u8 pad_0x4038_0x14000[0x14000 - 0x4038];
384
385
386 u8 pad_0x14000_0x1400c[0xc];
387 u32 signal_notify1;
388 u8 pad_0x14010_0x1c00c[0x7ffc];
389 u32 signal_notify2;
390} __attribute__ ((aligned(0x20000)));
391
392
393struct spu_priv2 {
394
395 u8 pad_0x0000_0x1100[0x1100 - 0x0000];
396
397
398 u8 pad_0x1100_0x1108[0x8];
399 u64 slb_index_W;
400#define SLB_INDEX_MASK 0x7L
401 u64 slb_esid_RW;
402 u64 slb_vsid_RW;
403#define SLB_VSID_SUPERVISOR_STATE (0x1ull << 11)
404#define SLB_VSID_SUPERVISOR_STATE_MASK (0x1ull << 11)
405#define SLB_VSID_PROBLEM_STATE (0x1ull << 10)
406#define SLB_VSID_PROBLEM_STATE_MASK (0x1ull << 10)
407#define SLB_VSID_EXECUTE_SEGMENT (0x1ull << 9)
408#define SLB_VSID_NO_EXECUTE_SEGMENT (0x1ull << 9)
409#define SLB_VSID_EXECUTE_SEGMENT_MASK (0x1ull << 9)
410#define SLB_VSID_4K_PAGE (0x0 << 8)
411#define SLB_VSID_LARGE_PAGE (0x1ull << 8)
412#define SLB_VSID_PAGE_SIZE_MASK (0x1ull << 8)
413#define SLB_VSID_CLASS_MASK (0x1ull << 7)
414#define SLB_VSID_VIRTUAL_PAGE_SIZE_MASK (0x1ull << 6)
415 u64 slb_invalidate_entry_W;
416 u64 slb_invalidate_all_W;
417 u8 pad_0x1130_0x2000[0x2000 - 0x1130];
418
419
420 struct mfc_cq_sr spuq[16];
421 struct mfc_cq_sr puq[8];
422 u8 pad_0x2300_0x3000[0x3000 - 0x2300];
423
424
425 u64 mfc_control_RW;
426#define MFC_CNTL_RESUME_DMA_QUEUE (0ull << 0)
427#define MFC_CNTL_SUSPEND_DMA_QUEUE (1ull << 0)
428#define MFC_CNTL_SUSPEND_DMA_QUEUE_MASK (1ull << 0)
429#define MFC_CNTL_SUSPEND_MASK (1ull << 4)
430#define MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION (0ull << 8)
431#define MFC_CNTL_SUSPEND_IN_PROGRESS (1ull << 8)
432#define MFC_CNTL_SUSPEND_COMPLETE (3ull << 8)
433#define MFC_CNTL_SUSPEND_DMA_STATUS_MASK (3ull << 8)
434#define MFC_CNTL_DMA_QUEUES_EMPTY (1ull << 14)
435#define MFC_CNTL_DMA_QUEUES_EMPTY_MASK (1ull << 14)
436#define MFC_CNTL_PURGE_DMA_REQUEST (1ull << 15)
437#define MFC_CNTL_PURGE_DMA_IN_PROGRESS (1ull << 24)
438#define MFC_CNTL_PURGE_DMA_COMPLETE (3ull << 24)
439#define MFC_CNTL_PURGE_DMA_STATUS_MASK (3ull << 24)
440#define MFC_CNTL_RESTART_DMA_COMMAND (1ull << 32)
441#define MFC_CNTL_DMA_COMMAND_REISSUE_PENDING (1ull << 32)
442#define MFC_CNTL_DMA_COMMAND_REISSUE_STATUS_MASK (1ull << 32)
443#define MFC_CNTL_MFC_PRIVILEGE_STATE (2ull << 33)
444#define MFC_CNTL_MFC_PROBLEM_STATE (3ull << 33)
445#define MFC_CNTL_MFC_KEY_PROTECTION_STATE_MASK (3ull << 33)
446#define MFC_CNTL_DECREMENTER_HALTED (1ull << 35)
447#define MFC_CNTL_DECREMENTER_RUNNING (1ull << 40)
448#define MFC_CNTL_DECREMENTER_STATUS_MASK (1ull << 40)
449 u8 pad_0x3008_0x4000[0x4000 - 0x3008];
450
451
452 u64 puint_mb_R;
453 u8 pad_0x4008_0x4040[0x4040 - 0x4008];
454
455
456 u64 spu_privcntl_RW;
457#define SPU_PRIVCNTL_MODE_NORMAL (0x0ull << 0)
458#define SPU_PRIVCNTL_MODE_SINGLE_STEP (0x1ull << 0)
459#define SPU_PRIVCNTL_MODE_MASK (0x1ull << 0)
460#define SPU_PRIVCNTL_NO_ATTENTION_EVENT (0x0ull << 1)
461#define SPU_PRIVCNTL_ATTENTION_EVENT (0x1ull << 1)
462#define SPU_PRIVCNTL_ATTENTION_EVENT_MASK (0x1ull << 1)
463#define SPU_PRIVCNT_LOAD_REQUEST_NORMAL (0x0ull << 2)
464#define SPU_PRIVCNT_LOAD_REQUEST_ENABLE_MASK (0x1ull << 2)
465 u8 pad_0x4048_0x4058[0x10];
466 u64 spu_lslr_RW;
467 u64 spu_chnlcntptr_RW;
468 u64 spu_chnlcnt_RW;
469 u64 spu_chnldata_RW;
470 u64 spu_cfg_RW;
471 u8 pad_0x4080_0x5000[0x5000 - 0x4080];
472
473
474 u64 spu_pm_trace_tag_status_RW;
475 u64 spu_tag_status_query_RW;
476#define TAG_STATUS_QUERY_CONDITION_BITS (0x3ull << 32)
477#define TAG_STATUS_QUERY_MASK_BITS (0xffffffffull)
478 u64 spu_cmd_buf1_RW;
479#define SPU_COMMAND_BUFFER_1_LSA_BITS (0x7ffffull << 32)
480#define SPU_COMMAND_BUFFER_1_EAH_BITS (0xffffffffull)
481 u64 spu_cmd_buf2_RW;
482#define SPU_COMMAND_BUFFER_2_EAL_BITS ((0xffffffffull) << 32)
483#define SPU_COMMAND_BUFFER_2_TS_BITS (0xffffull << 16)
484#define SPU_COMMAND_BUFFER_2_TAG_BITS (0x3full)
485 u64 spu_atomic_status_RW;
486} __attribute__ ((aligned(0x20000)));
487
488
489struct spu_priv1 {
490
491 u64 mfc_sr1_RW;
492#define MFC_STATE1_LOCAL_STORAGE_DECODE_MASK 0x01ull
493#define MFC_STATE1_BUS_TLBIE_MASK 0x02ull
494#define MFC_STATE1_REAL_MODE_OFFSET_ENABLE_MASK 0x04ull
495#define MFC_STATE1_PROBLEM_STATE_MASK 0x08ull
496#define MFC_STATE1_RELOCATE_MASK 0x10ull
497#define MFC_STATE1_MASTER_RUN_CONTROL_MASK 0x20ull
498#define MFC_STATE1_TABLE_SEARCH_MASK 0x40ull
499 u64 mfc_lpid_RW;
500 u64 spu_idr_RW;
501 u64 mfc_vr_RO;
502#define MFC_VERSION_BITS (0xffff << 16)
503#define MFC_REVISION_BITS (0xffff)
504#define MFC_GET_VERSION_BITS(vr) (((vr) & MFC_VERSION_BITS) >> 16)
505#define MFC_GET_REVISION_BITS(vr) ((vr) & MFC_REVISION_BITS)
506 u64 spu_vr_RO;
507#define SPU_VERSION_BITS (0xffff << 16)
508#define SPU_REVISION_BITS (0xffff)
509#define SPU_GET_VERSION_BITS(vr) (vr & SPU_VERSION_BITS) >> 16
510#define SPU_GET_REVISION_BITS(vr) (vr & SPU_REVISION_BITS)
511 u8 pad_0x28_0x100[0x100 - 0x28];
512
513
514 u64 int_mask_RW[3];
515#define CLASS0_ENABLE_DMA_ALIGNMENT_INTR 0x1L
516#define CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR 0x2L
517#define CLASS0_ENABLE_SPU_ERROR_INTR 0x4L
518#define CLASS0_ENABLE_MFC_FIR_INTR 0x8L
519#define CLASS1_ENABLE_SEGMENT_FAULT_INTR 0x1L
520#define CLASS1_ENABLE_STORAGE_FAULT_INTR 0x2L
521#define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_GET_INTR 0x4L
522#define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_PUT_INTR 0x8L
523#define CLASS2_ENABLE_MAILBOX_INTR 0x1L
524#define CLASS2_ENABLE_SPU_STOP_INTR 0x2L
525#define CLASS2_ENABLE_SPU_HALT_INTR 0x4L
526#define CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L
527#define CLASS2_ENABLE_MAILBOX_THRESHOLD_INTR 0x10L
528 u8 pad_0x118_0x140[0x28];
529 u64 int_stat_RW[3];
530#define CLASS0_DMA_ALIGNMENT_INTR 0x1L
531#define CLASS0_INVALID_DMA_COMMAND_INTR 0x2L
532#define CLASS0_SPU_ERROR_INTR 0x4L
533#define CLASS0_INTR_MASK 0x7L
534#define CLASS1_SEGMENT_FAULT_INTR 0x1L
535#define CLASS1_STORAGE_FAULT_INTR 0x2L
536#define CLASS1_LS_COMPARE_SUSPEND_ON_GET_INTR 0x4L
537#define CLASS1_LS_COMPARE_SUSPEND_ON_PUT_INTR 0x8L
538#define CLASS1_INTR_MASK 0xfL
539#define CLASS2_MAILBOX_INTR 0x1L
540#define CLASS2_SPU_STOP_INTR 0x2L
541#define CLASS2_SPU_HALT_INTR 0x4L
542#define CLASS2_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L
543#define CLASS2_MAILBOX_THRESHOLD_INTR 0x10L
544#define CLASS2_INTR_MASK 0x1fL
545 u8 pad_0x158_0x180[0x28];
546 u64 int_route_RW;
547
548
549 u8 pad_0x188_0x200[0x200 - 0x188];
550
551
552 u64 mfc_atomic_flush_RW;
553#define mfc_atomic_flush_enable 0x1L
554 u8 pad_0x208_0x280[0x78];
555 u64 resource_allocation_groupID_RW;
556 u64 resource_allocation_enable_RW;
557 u8 pad_0x290_0x3c8[0x3c8 - 0x290];
558
559
560
561 u64 smf_sbi_signal_sel;
562#define smf_sbi_mask_lsb 56
563#define smf_sbi_shift (63 - smf_sbi_mask_lsb)
564#define smf_sbi_mask (0x301LL << smf_sbi_shift)
565#define smf_sbi_bus0_bits (0x001LL << smf_sbi_shift)
566#define smf_sbi_bus2_bits (0x100LL << smf_sbi_shift)
567#define smf_sbi2_bus0_bits (0x201LL << smf_sbi_shift)
568#define smf_sbi2_bus2_bits (0x300LL << smf_sbi_shift)
569 u64 smf_ato_signal_sel;
570#define smf_ato_mask_lsb 35
571#define smf_ato_shift (63 - smf_ato_mask_lsb)
572#define smf_ato_mask (0x3LL << smf_ato_shift)
573#define smf_ato_bus0_bits (0x2LL << smf_ato_shift)
574#define smf_ato_bus2_bits (0x1LL << smf_ato_shift)
575 u8 pad_0x3d8_0x400[0x400 - 0x3d8];
576
577
578 u64 mfc_sdr_RW;
579 u8 pad_0x408_0x500[0xf8];
580 u64 tlb_index_hint_RO;
581 u64 tlb_index_W;
582 u64 tlb_vpn_RW;
583 u64 tlb_rpn_RW;
584 u8 pad_0x520_0x540[0x20];
585 u64 tlb_invalidate_entry_W;
586 u64 tlb_invalidate_all_W;
587 u8 pad_0x550_0x580[0x580 - 0x550];
588
589
590 u64 smm_hid;
591#define PAGE_SIZE_MASK 0xf000000000000000ull
592#define PAGE_SIZE_16MB_64KB 0x2000000000000000ull
593 u8 pad_0x588_0x600[0x600 - 0x588];
594
595
596 u64 mfc_accr_RW;
597#define MFC_ACCR_EA_ACCESS_GET (1 << 0)
598#define MFC_ACCR_EA_ACCESS_PUT (1 << 1)
599#define MFC_ACCR_LS_ACCESS_GET (1 << 3)
600#define MFC_ACCR_LS_ACCESS_PUT (1 << 4)
601 u8 pad_0x608_0x610[0x8];
602 u64 mfc_dsisr_RW;
603#define MFC_DSISR_PTE_NOT_FOUND (1 << 30)
604#define MFC_DSISR_ACCESS_DENIED (1 << 27)
605#define MFC_DSISR_ATOMIC (1 << 26)
606#define MFC_DSISR_ACCESS_PUT (1 << 25)
607#define MFC_DSISR_ADDR_MATCH (1 << 22)
608#define MFC_DSISR_LS (1 << 17)
609#define MFC_DSISR_L (1 << 16)
610#define MFC_DSISR_ADDRESS_OVERFLOW (1 << 0)
611 u8 pad_0x618_0x620[0x8];
612 u64 mfc_dar_RW;
613 u8 pad_0x628_0x700[0x700 - 0x628];
614
615
616 u64 rmt_index_RW;
617 u8 pad_0x708_0x710[0x8];
618 u64 rmt_data1_RW;
619 u8 pad_0x718_0x800[0x800 - 0x718];
620
621
622 u64 mfc_dsir_R;
623#define MFC_DSIR_Q (1 << 31)
624#define MFC_DSIR_SPU_QUEUE MFC_DSIR_Q
625 u64 mfc_lsacr_RW;
626#define MFC_LSACR_COMPARE_MASK ((~0ull) << 32)
627#define MFC_LSACR_COMPARE_ADDR ((~0ull) >> 32)
628 u64 mfc_lscrr_R;
629#define MFC_LSCRR_Q (1 << 31)
630#define MFC_LSCRR_SPU_QUEUE MFC_LSCRR_Q
631#define MFC_LSCRR_QI_SHIFT 32
632#define MFC_LSCRR_QI_MASK ((~0ull) << MFC_LSCRR_QI_SHIFT)
633 u8 pad_0x818_0x820[0x8];
634 u64 mfc_tclass_id_RW;
635#define MFC_TCLASS_ID_ENABLE (1L << 0L)
636#define MFC_TCLASS_SLOT2_ENABLE (1L << 5L)
637#define MFC_TCLASS_SLOT1_ENABLE (1L << 6L)
638#define MFC_TCLASS_SLOT0_ENABLE (1L << 7L)
639#define MFC_TCLASS_QUOTA_2_SHIFT 8L
640#define MFC_TCLASS_QUOTA_1_SHIFT 16L
641#define MFC_TCLASS_QUOTA_0_SHIFT 24L
642#define MFC_TCLASS_QUOTA_2_MASK (0x1FL << MFC_TCLASS_QUOTA_2_SHIFT)
643#define MFC_TCLASS_QUOTA_1_MASK (0x1FL << MFC_TCLASS_QUOTA_1_SHIFT)
644#define MFC_TCLASS_QUOTA_0_MASK (0x1FL << MFC_TCLASS_QUOTA_0_SHIFT)
645 u8 pad_0x828_0x900[0x900 - 0x828];
646
647
648 u64 mfc_rm_boundary;
649 u8 pad_0x908_0x938[0x30];
650 u64 smf_dma_signal_sel;
651#define mfc_dma1_mask_lsb 41
652#define mfc_dma1_shift (63 - mfc_dma1_mask_lsb)
653#define mfc_dma1_mask (0x3LL << mfc_dma1_shift)
654#define mfc_dma1_bits (0x1LL << mfc_dma1_shift)
655#define mfc_dma2_mask_lsb 43
656#define mfc_dma2_shift (63 - mfc_dma2_mask_lsb)
657#define mfc_dma2_mask (0x3LL << mfc_dma2_shift)
658#define mfc_dma2_bits (0x1LL << mfc_dma2_shift)
659 u8 pad_0x940_0xa38[0xf8];
660 u64 smm_signal_sel;
661#define smm_sig_mask_lsb 12
662#define smm_sig_shift (63 - smm_sig_mask_lsb)
663#define smm_sig_mask (0x3LL << smm_sig_shift)
664#define smm_sig_bus0_bits (0x2LL << smm_sig_shift)
665#define smm_sig_bus2_bits (0x1LL << smm_sig_shift)
666 u8 pad_0xa40_0xc00[0xc00 - 0xa40];
667
668
669 u64 mfc_cer_R;
670#define MFC_CER_Q (1 << 31)
671#define MFC_CER_SPU_QUEUE MFC_CER_Q
672 u8 pad_0xc08_0x1000[0x1000 - 0xc08];
673
674
675
676 u64 spu_ecc_cntl_RW;
677#define SPU_ECC_CNTL_E (1ull << 0ull)
678#define SPU_ECC_CNTL_ENABLE SPU_ECC_CNTL_E
679#define SPU_ECC_CNTL_DISABLE (~SPU_ECC_CNTL_E & 1L)
680#define SPU_ECC_CNTL_S (1ull << 1ull)
681#define SPU_ECC_STOP_AFTER_ERROR SPU_ECC_CNTL_S
682#define SPU_ECC_CONTINUE_AFTER_ERROR (~SPU_ECC_CNTL_S & 2L)
683#define SPU_ECC_CNTL_B (1ull << 2ull)
684#define SPU_ECC_BACKGROUND_ENABLE SPU_ECC_CNTL_B
685#define SPU_ECC_BACKGROUND_DISABLE (~SPU_ECC_CNTL_B & 4L)
686#define SPU_ECC_CNTL_I_SHIFT 3ull
687#define SPU_ECC_CNTL_I_MASK (3ull << SPU_ECC_CNTL_I_SHIFT)
688#define SPU_ECC_WRITE_ALWAYS (~SPU_ECC_CNTL_I & 12L)
689#define SPU_ECC_WRITE_CORRECTABLE (1ull << SPU_ECC_CNTL_I_SHIFT)
690#define SPU_ECC_WRITE_UNCORRECTABLE (3ull << SPU_ECC_CNTL_I_SHIFT)
691#define SPU_ECC_CNTL_D (1ull << 5ull)
692#define SPU_ECC_DETECTION_ENABLE SPU_ECC_CNTL_D
693#define SPU_ECC_DETECTION_DISABLE (~SPU_ECC_CNTL_D & 32L)
694 u64 spu_ecc_stat_RW;
695#define SPU_ECC_CORRECTED_ERROR (1ull << 0ul)
696#define SPU_ECC_UNCORRECTED_ERROR (1ull << 1ul)
697#define SPU_ECC_SCRUB_COMPLETE (1ull << 2ul)
698#define SPU_ECC_SCRUB_IN_PROGRESS (1ull << 3ul)
699#define SPU_ECC_INSTRUCTION_ERROR (1ull << 4ul)
700#define SPU_ECC_DATA_ERROR (1ull << 5ul)
701#define SPU_ECC_DMA_ERROR (1ull << 6ul)
702#define SPU_ECC_STATUS_CNT_MASK (256ull << 8)
703 u64 spu_ecc_addr_RW;
704 u64 spu_err_mask_RW;
705#define SPU_ERR_ILLEGAL_INSTR (1ull << 0ul)
706#define SPU_ERR_ILLEGAL_CHANNEL (1ull << 1ul)
707 u8 pad_0x1020_0x1028[0x1028 - 0x1020];
708
709
710 u64 spu_trig0_sel;
711 u64 spu_trig1_sel;
712 u64 spu_trig2_sel;
713 u64 spu_trig3_sel;
714 u64 spu_trace_sel;
715#define spu_trace_sel_mask 0x1f1fLL
716#define spu_trace_sel_bus0_bits 0x1000LL
717#define spu_trace_sel_bus2_bits 0x0010LL
718 u64 spu_event0_sel;
719 u64 spu_event1_sel;
720 u64 spu_event2_sel;
721 u64 spu_event3_sel;
722 u64 spu_trace_cntl;
723} __attribute__ ((aligned(0x2000)));
724
725#endif
726#endif
727