LXR linux/arch/powerpc/kernel/align.c

   1/* align.c - handle alignment exceptions for the Power PC.
   2 *
   3 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
   4 * Copyright (c) 1998-1999 TiVo, Inc.
   5 *   PowerPC 403GCX modifications.
   6 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
   7 *   PowerPC 403GCX/405GP modifications.
   8 * Copyright (c) 2001-2002 PPC64 team, IBM Corp
   9 *   64-bit and Power4 support
  10 * Copyright (c) 2005 Benjamin Herrenschmidt, IBM Corp
  11 *                    <benh@kernel.crashing.org>
  12 *   Merge ppc32 and ppc64 implementations
  13 *
  14 * This program is free software; you can redistribute it and/or
  15 * modify it under the terms of the GNU General Public License
  16 * as published by the Free Software Foundation; either version
  17 * 2 of the License, or (at your option) any later version.
  18 */
  19
  20#include <linux/kernel.h>
  21#include <linux/mm.h>
  22#include <asm/processor.h>
  23#include <asm/uaccess.h>
  24#include <asm/cache.h>
  25#include <asm/cputable.h>
  26#include <asm/emulated_ops.h>
  27#include <asm/switch_to.h>
  28
  29struct aligninfo {
  30        unsigned char len;
  31        unsigned char flags;
  32};
  33
  34#define IS_XFORM(inst)  (((inst) >> 26) == 31)
  35#define IS_DSFORM(inst) (((inst) >> 26) >= 56)
  36
  37#define INVALID { 0, 0 }
  38
  39/* Bits in the flags field */
  40#define LD      0       /* load */
  41#define ST      1       /* store */
  42#define SE      2       /* sign-extend value, or FP ld/st as word */
  43#define F       4       /* to/from fp regs */
  44#define U       8       /* update index register */
  45#define M       0x10    /* multiple load/store */
  46#define SW      0x20    /* byte swap */
  47#define S       0x40    /* single-precision fp or... */
  48#define SX      0x40    /* ... byte count in XER */
  49#define HARD    0x80    /* string, stwcx. */
  50#define E4      0x40    /* SPE endianness is word */
  51#define E8      0x80    /* SPE endianness is double word */
  52#define SPLT    0x80    /* VSX SPLAT load */
  53
  54/* DSISR bits reported for a DCBZ instruction: */
  55#define DCBZ    0x5f    /* 8xx/82xx dcbz faults when cache not enabled */
  56
  57/*
  58 * The PowerPC stores certain bits of the instruction that caused the
  59 * alignment exception in the DSISR register.  This array maps those
  60 * bits to information about the operand length and what the
  61 * instruction would do.
  62 */
  63static struct aligninfo aligninfo[128] = {
  64        { 4, LD },              /* 00 0 0000: lwz / lwarx */
  65        INVALID,                /* 00 0 0001 */
  66        { 4, ST },              /* 00 0 0010: stw */
  67        INVALID,                /* 00 0 0011 */
  68        { 2, LD },              /* 00 0 0100: lhz */
  69        { 2, LD+SE },           /* 00 0 0101: lha */
  70        { 2, ST },              /* 00 0 0110: sth */
  71        { 4, LD+M },            /* 00 0 0111: lmw */
  72        { 4, LD+F+S },          /* 00 0 1000: lfs */
  73        { 8, LD+F },            /* 00 0 1001: lfd */
  74        { 4, ST+F+S },          /* 00 0 1010: stfs */
  75        { 8, ST+F },            /* 00 0 1011: stfd */
  76        { 16, LD },             /* 00 0 1100: lq */
  77        { 8, LD },              /* 00 0 1101: ld/ldu/lwa */
  78        INVALID,                /* 00 0 1110 */
  79        { 8, ST },              /* 00 0 1111: std/stdu */
  80        { 4, LD+U },            /* 00 1 0000: lwzu */
  81        INVALID,                /* 00 1 0001 */
  82        { 4, ST+U },            /* 00 1 0010: stwu */
  83        INVALID,                /* 00 1 0011 */
  84        { 2, LD+U },            /* 00 1 0100: lhzu */
  85        { 2, LD+SE+U },         /* 00 1 0101: lhau */
  86        { 2, ST+U },            /* 00 1 0110: sthu */
  87        { 4, ST+M },            /* 00 1 0111: stmw */
  88        { 4, LD+F+S+U },        /* 00 1 1000: lfsu */
  89        { 8, LD+F+U },          /* 00 1 1001: lfdu */
  90        { 4, ST+F+S+U },        /* 00 1 1010: stfsu */
  91        { 8, ST+F+U },          /* 00 1 1011: stfdu */
  92        { 16, LD+F },           /* 00 1 1100: lfdp */
  93        INVALID,                /* 00 1 1101 */
  94        { 16, ST+F },           /* 00 1 1110: stfdp */
  95        INVALID,                /* 00 1 1111 */
  96        { 8, LD },              /* 01 0 0000: ldx */
  97        INVALID,                /* 01 0 0001 */
  98        { 8, ST },              /* 01 0 0010: stdx */
  99        INVALID,                /* 01 0 0011 */
 100        INVALID,                /* 01 0 0100 */
 101        { 4, LD+SE },           /* 01 0 0101: lwax */
 102        INVALID,                /* 01 0 0110 */
 103        INVALID,                /* 01 0 0111 */
 104        { 4, LD+M+HARD+SX },    /* 01 0 1000: lswx */
 105        { 4, LD+M+HARD },       /* 01 0 1001: lswi */
 106        { 4, ST+M+HARD+SX },    /* 01 0 1010: stswx */
 107        { 4, ST+M+HARD },       /* 01 0 1011: stswi */
 108        INVALID,                /* 01 0 1100 */
 109        { 8, LD+U },            /* 01 0 1101: ldu */
 110        INVALID,                /* 01 0 1110 */
 111        { 8, ST+U },            /* 01 0 1111: stdu */
 112        { 8, LD+U },            /* 01 1 0000: ldux */
 113        INVALID,                /* 01 1 0001 */
 114        { 8, ST+U },            /* 01 1 0010: stdux */
 115        INVALID,                /* 01 1 0011 */
 116        INVALID,                /* 01 1 0100 */
 117        { 4, LD+SE+U },         /* 01 1 0101: lwaux */
 118        INVALID,                /* 01 1 0110 */
 119        INVALID,                /* 01 1 0111 */
 120        INVALID,                /* 01 1 1000 */
 121        INVALID,                /* 01 1 1001 */
 122        INVALID,                /* 01 1 1010 */
 123        INVALID,                /* 01 1 1011 */
 124        INVALID,                /* 01 1 1100 */
 125        INVALID,                /* 01 1 1101 */
 126        INVALID,                /* 01 1 1110 */
 127        INVALID,                /* 01 1 1111 */
 128        INVALID,                /* 10 0 0000 */
 129        INVALID,                /* 10 0 0001 */
 130        INVALID,                /* 10 0 0010: stwcx. */
 131        INVALID,                /* 10 0 0011 */
 132        INVALID,                /* 10 0 0100 */
 133        INVALID,                /* 10 0 0101 */
 134        INVALID,                /* 10 0 0110 */
 135        INVALID,                /* 10 0 0111 */
 136        { 4, LD+SW },           /* 10 0 1000: lwbrx */
 137        INVALID,                /* 10 0 1001 */
 138        { 4, ST+SW },           /* 10 0 1010: stwbrx */
 139        INVALID,                /* 10 0 1011 */
 140        { 2, LD+SW },           /* 10 0 1100: lhbrx */
 141        { 4, LD+SE },           /* 10 0 1101  lwa */
 142        { 2, ST+SW },           /* 10 0 1110: sthbrx */
 143        { 16, ST },             /* 10 0 1111: stq */
 144        INVALID,                /* 10 1 0000 */
 145        INVALID,                /* 10 1 0001 */
 146        INVALID,                /* 10 1 0010 */
 147        INVALID,                /* 10 1 0011 */
 148        INVALID,                /* 10 1 0100 */
 149        INVALID,                /* 10 1 0101 */
 150        INVALID,                /* 10 1 0110 */
 151        INVALID,                /* 10 1 0111 */
 152        INVALID,                /* 10 1 1000 */
 153        INVALID,                /* 10 1 1001 */
 154        INVALID,                /* 10 1 1010 */
 155        INVALID,                /* 10 1 1011 */
 156        INVALID,                /* 10 1 1100 */
 157        INVALID,                /* 10 1 1101 */
 158        INVALID,                /* 10 1 1110 */
 159        { 0, ST+HARD },         /* 10 1 1111: dcbz */
 160        { 4, LD },              /* 11 0 0000: lwzx */
 161        INVALID,                /* 11 0 0001 */
 162        { 4, ST },              /* 11 0 0010: stwx */
 163        INVALID,                /* 11 0 0011 */
 164        { 2, LD },              /* 11 0 0100: lhzx */
 165        { 2, LD+SE },           /* 11 0 0101: lhax */
 166        { 2, ST },              /* 11 0 0110: sthx */
 167        INVALID,                /* 11 0 0111 */
 168        { 4, LD+F+S },          /* 11 0 1000: lfsx */
 169        { 8, LD+F },            /* 11 0 1001: lfdx */
 170        { 4, ST+F+S },          /* 11 0 1010: stfsx */
 171        { 8, ST+F },            /* 11 0 1011: stfdx */
 172        { 16, LD+F },           /* 11 0 1100: lfdpx */
 173        { 4, LD+F+SE },         /* 11 0 1101: lfiwax */
 174        { 16, ST+F },           /* 11 0 1110: stfdpx */
 175        { 4, ST+F },            /* 11 0 1111: stfiwx */
 176        { 4, LD+U },            /* 11 1 0000: lwzux */
 177        INVALID,                /* 11 1 0001 */
 178        { 4, ST+U },            /* 11 1 0010: stwux */
 179        INVALID,                /* 11 1 0011 */
 180        { 2, LD+U },            /* 11 1 0100: lhzux */
 181        { 2, LD+SE+U },         /* 11 1 0101: lhaux */
 182        { 2, ST+U },            /* 11 1 0110: sthux */
 183        INVALID,                /* 11 1 0111 */
 184        { 4, LD+F+S+U },        /* 11 1 1000: lfsux */
 185        { 8, LD+F+U },          /* 11 1 1001: lfdux */
 186        { 4, ST+F+S+U },        /* 11 1 1010: stfsux */
 187        { 8, ST+F+U },          /* 11 1 1011: stfdux */
 188        INVALID,                /* 11 1 1100 */
 189        { 4, LD+F },            /* 11 1 1101: lfiwzx */
 190        INVALID,                /* 11 1 1110 */
 191        INVALID,                /* 11 1 1111 */
 192};
 193
 194/*
 195 * Create a DSISR value from the instruction
 196 */
 197static inline unsigned make_dsisr(unsigned instr)
 198{
 199        unsigned dsisr;
 200
 201
 202        /* bits  6:15 --> 22:31 */
 203        dsisr = (instr & 0x03ff0000) >> 16;
 204
 205        if (IS_XFORM(instr)) {
 206                /* bits 29:30 --> 15:16 */
 207                dsisr |= (instr & 0x00000006) << 14;
 208                /* bit     25 -->    17 */
 209                dsisr |= (instr & 0x00000040) << 8;
 210                /* bits 21:24 --> 18:21 */
 211                dsisr |= (instr & 0x00000780) << 3;
 212        } else {
 213                /* bit      5 -->    17 */
 214                dsisr |= (instr & 0x04000000) >> 12;
 215                /* bits  1: 4 --> 18:21 */
 216                dsisr |= (instr & 0x78000000) >> 17;
 217                /* bits 30:31 --> 12:13 */
 218                if (IS_DSFORM(instr))
 219                        dsisr |= (instr & 0x00000003) << 18;
 220        }
 221
 222        return dsisr;
 223}
 224
 225/*
 226 * The dcbz (data cache block zero) instruction
 227 * gives an alignment fault if used on non-cacheable
 228 * memory.  We handle the fault mainly for the
 229 * case when we are running with the cache disabled
 230 * for debugging.
 231 */
 232static int emulate_dcbz(struct pt_regs *regs, unsigned char __user *addr)
 233{
 234        long __user *p;
 235        int i, size;
 236
 237#ifdef __powerpc64__
 238        size = ppc64_caches.dline_size;
 239#else
 240        size = L1_CACHE_BYTES;
 241#endif
 242        p = (long __user *) (regs->dar & -size);
 243        if (user_mode(regs) && !access_ok(VERIFY_WRITE, p, size))
 244                return -EFAULT;
 245        for (i = 0; i < size / sizeof(long); ++i)
 246                if (__put_user_inatomic(0, p+i))
 247                        return -EFAULT;
 248        return 1;
 249}
 250
 251/*
 252 * Emulate load & store multiple instructions
 253 * On 64-bit machines, these instructions only affect/use the
 254 * bottom 4 bytes of each register, and the loads clear the
 255 * top 4 bytes of the affected register.
 256 */
 257#ifdef __BIG_ENDIAN__
 258#ifdef CONFIG_PPC64
 259#define REG_BYTE(rp, i)         *((u8 *)((rp) + ((i) >> 2)) + ((i) & 3) + 4)
 260#else
 261#define REG_BYTE(rp, i)         *((u8 *)(rp) + (i))
 262#endif
 263#endif
 264
 265#ifdef __LITTLE_ENDIAN__
 266#define REG_BYTE(rp, i)         (*(((u8 *)((rp) + ((i)>>2)) + ((i)&3))))
 267#endif
 268
 269#define SWIZ_PTR(p)             ((unsigned char __user *)((p) ^ swiz))
 270
 271static int emulate_multiple(struct pt_regs *regs, unsigned char __user *addr,
 272                            unsigned int reg, unsigned int nb,
 273                            unsigned int flags, unsigned int instr,
 274                            unsigned long swiz)
 275{
 276        unsigned long *rptr;
 277        unsigned int nb0, i, bswiz;
 278        unsigned long p;
 279
 280        /*
 281         * We do not try to emulate 8 bytes multiple as they aren't really
 282         * available in our operating environments and we don't try to
 283         * emulate multiples operations in kernel land as they should never
 284         * be used/generated there at least not on unaligned boundaries
 285         */
 286        if (unlikely((nb > 4) || !user_mode(regs)))
 287                return 0;
 288
 289        /* lmw, stmw, lswi/x, stswi/x */
 290        nb0 = 0;
 291        if (flags & HARD) {
 292                if (flags & SX) {
 293                        nb = regs->xer & 127;
 294                        if (nb == 0)
 295                                return 1;
 296                } else {
 297                        unsigned long pc = regs->nip ^ (swiz & 4);
 298
 299                        if (__get_user_inatomic(instr,
 300                                                (unsigned int __user *)pc))
 301                                return -EFAULT;
 302                        if (swiz == 0 && (flags & SW))
 303                                instr = cpu_to_le32(instr);
 304                        nb = (instr >> 11) & 0x1f;
 305                        if (nb == 0)
 306                                nb = 32;
 307                }
 308                if (nb + reg * 4 > 128) {
 309                        nb0 = nb + reg * 4 - 128;
 310                        nb = 128 - reg * 4;
 311                }
 312#ifdef __LITTLE_ENDIAN__
 313                /*
 314                 *  String instructions are endian neutral but the code
 315                 *  below is not.  Force byte swapping on so that the
 316                 *  effects of swizzling are undone in the load/store
 317                 *  loops below.
 318                 */
 319                flags ^= SW;
 320#endif
 321        } else {
 322                /* lwm, stmw */
 323                nb = (32 - reg) * 4;
 324        }
 325
 326        if (!access_ok((flags & ST ? VERIFY_WRITE: VERIFY_READ), addr, nb+nb0))
 327                return -EFAULT; /* bad address */
 328
 329        rptr = &regs->gpr[reg];
 330        p = (unsigned long) addr;
 331        bswiz = (flags & SW)? 3: 0;
 332
 333        if (!(flags & ST)) {
 334                /*
 335                 * This zeroes the top 4 bytes of the affected registers
 336                 * in 64-bit mode, and also zeroes out any remaining
 337                 * bytes of the last register for lsw*.
 338                 */
 339                memset(rptr, 0, ((nb + 3) / 4) * sizeof(unsigned long));
 340                if (nb0 > 0)
 341                        memset(&regs->gpr[0], 0,
 342                               ((nb0 + 3) / 4) * sizeof(unsigned long));
 343
 344                for (i = 0; i < nb; ++i, ++p)
 345                        if (__get_user_inatomic(REG_BYTE(rptr, i ^ bswiz),
 346                                                SWIZ_PTR(p)))
 347                                return -EFAULT;
 348                if (nb0 > 0) {
 349                        rptr = &regs->gpr[0];
 350                        addr += nb;
 351                        for (i = 0; i < nb0; ++i, ++p)
 352                                if (__get_user_inatomic(REG_BYTE(rptr,
 353                                                                 i ^ bswiz),
 354                                                        SWIZ_PTR(p)))
 355                                        return -EFAULT;
 356                }
 357
 358        } else {
 359                for (i = 0; i < nb; ++i, ++p)
 360                        if (__put_user_inatomic(REG_BYTE(rptr, i ^ bswiz),
 361                                                SWIZ_PTR(p)))
 362                                return -EFAULT;
 363                if (nb0 > 0) {
 364                        rptr = &regs->gpr[0];
 365                        addr += nb;
 366                        for (i = 0; i < nb0; ++i, ++p)
 367                                if (__put_user_inatomic(REG_BYTE(rptr,
 368                                                                 i ^ bswiz),
 369                                                        SWIZ_PTR(p)))
 370                                        return -EFAULT;
 371                }
 372        }
 373        return 1;
 374}
 375
 376/*
 377 * Emulate floating-point pair loads and stores.
 378 * Only POWER6 has these instructions, and it does true little-endian,
 379 * so we don't need the address swizzling.
 380 */
 381static int emulate_fp_pair(unsigned char __user *addr, unsigned int reg,
 382                           unsigned int flags)
 383{
 384        char *ptr0 = (char *) &current->thread.TS_FPR(reg);
 385        char *ptr1 = (char *) &current->thread.TS_FPR(reg+1);
 386        int i, ret, sw = 0;
 387
 388        if (reg & 1)
 389                return 0;       /* invalid form: FRS/FRT must be even */
 390        if (flags & SW)
 391                sw = 7;
 392        ret = 0;
 393        for (i = 0; i < 8; ++i) {
 394                if (!(flags & ST)) {
 395                        ret |= __get_user(ptr0[i^sw], addr + i);
 396                        ret |= __get_user(ptr1[i^sw], addr + i + 8);
 397                } else {
 398                        ret |= __put_user(ptr0[i^sw], addr + i);
 399                        ret |= __put_user(ptr1[i^sw], addr + i + 8);
 400                }
 401        }
 402        if (ret)
 403                return -EFAULT;
 404        return 1;       /* exception handled and fixed up */
 405}
 406
 407#ifdef CONFIG_PPC64
 408static int emulate_lq_stq(struct pt_regs *regs, unsigned char __user *addr,
 409                          unsigned int reg, unsigned int flags)
 410{
 411        char *ptr0 = (char *)&regs->gpr[reg];
 412        char *ptr1 = (char *)&regs->gpr[reg+1];
 413        int i, ret, sw = 0;
 414
 415        if (reg & 1)
 416                return 0;       /* invalid form: GPR must be even */
 417        if (flags & SW)
 418                sw = 7;
 419        ret = 0;
 420        for (i = 0; i < 8; ++i) {
 421                if (!(flags & ST)) {
 422                        ret |= __get_user(ptr0[i^sw], addr + i);
 423                        ret |= __get_user(ptr1[i^sw], addr + i + 8);
 424                } else {
 425                        ret |= __put_user(ptr0[i^sw], addr + i);
 426                        ret |= __put_user(ptr1[i^sw], addr + i + 8);
 427                }
 428        }
 429        if (ret)
 430                return -EFAULT;
 431        return 1;       /* exception handled and fixed up */
 432}
 433#endif /* CONFIG_PPC64 */
 434
 435#ifdef CONFIG_SPE
 436
 437static struct aligninfo spe_aligninfo[32] = {
 438        { 8, LD+E8 },           /* 0 00 00: evldd[x] */
 439        { 8, LD+E4 },           /* 0 00 01: evldw[x] */
 440        { 8, LD },              /* 0 00 10: evldh[x] */
 441        INVALID,                /* 0 00 11 */
 442        { 2, LD },              /* 0 01 00: evlhhesplat[x] */
 443        INVALID,                /* 0 01 01 */
 444        { 2, LD },              /* 0 01 10: evlhhousplat[x] */
 445        { 2, LD+SE },           /* 0 01 11: evlhhossplat[x] */
 446        { 4, LD },              /* 0 10 00: evlwhe[x] */
 447        INVALID,                /* 0 10 01 */
 448        { 4, LD },              /* 0 10 10: evlwhou[x] */
 449        { 4, LD+SE },           /* 0 10 11: evlwhos[x] */
 450        { 4, LD+E4 },           /* 0 11 00: evlwwsplat[x] */
 451        INVALID,                /* 0 11 01 */
 452        { 4, LD },              /* 0 11 10: evlwhsplat[x] */
 453        INVALID,                /* 0 11 11 */
 454
 455        { 8, ST+E8 },           /* 1 00 00: evstdd[x] */
 456        { 8, ST+E4 },           /* 1 00 01: evstdw[x] */
 457        { 8, ST },              /* 1 00 10: evstdh[x] */
 458        INVALID,                /* 1 00 11 */
 459        INVALID,                /* 1 01 00 */
 460        INVALID,                /* 1 01 01 */
 461        INVALID,                /* 1 01 10 */
 462        INVALID,                /* 1 01 11 */
 463        { 4, ST },              /* 1 10 00: evstwhe[x] */
 464        INVALID,                /* 1 10 01 */
 465        { 4, ST },              /* 1 10 10: evstwho[x] */
 466        INVALID,                /* 1 10 11 */
 467        { 4, ST+E4 },           /* 1 11 00: evstwwe[x] */
 468        INVALID,                /* 1 11 01 */
 469        { 4, ST+E4 },           /* 1 11 10: evstwwo[x] */
 470        INVALID,                /* 1 11 11 */
 471};
 472
 473#define EVLDD           0x00
 474#define EVLDW           0x01
 475#define EVLDH           0x02
 476#define EVLHHESPLAT     0x04
 477#define EVLHHOUSPLAT    0x06
 478#define EVLHHOSSPLAT    0x07
 479#define EVLWHE          0x08
 480#define EVLWHOU         0x0A
 481#define EVLWHOS         0x0B
 482#define EVLWWSPLAT      0x0C
 483#define EVLWHSPLAT      0x0E
 484#define EVSTDD          0x10
 485#define EVSTDW          0x11
 486#define EVSTDH          0x12
 487#define EVSTWHE         0x18
 488#define EVSTWHO         0x1A
 489#define EVSTWWE         0x1C
 490#define EVSTWWO         0x1E
 491
 492/*
 493 * Emulate SPE loads and stores.
 494 * Only Book-E has these instructions, and it does true little-endian,
 495 * so we don't need the address swizzling.
 496 */
 497static int emulate_spe(struct pt_regs *regs, unsigned int reg,
 498                       unsigned int instr)
 499{
 500        int ret;
 501        union {
 502                u64 ll;
 503                u32 w[2];
 504                u16 h[4];
 505                u8 v[8];
 506        } data, temp;
 507        unsigned char __user *p, *addr;
 508        unsigned long *evr = &current->thread.evr[reg];
 509        unsigned int nb, flags;
 510
 511        instr = (instr >> 1) & 0x1f;
 512
 513        /* DAR has the operand effective address */
 514        addr = (unsigned char __user *)regs->dar;
 515
 516        nb = spe_aligninfo[instr].len;
 517        flags = spe_aligninfo[instr].flags;
 518
 519        /* Verify the address of the operand */
 520        if (unlikely(user_mode(regs) &&
 521                     !access_ok((flags & ST ? VERIFY_WRITE : VERIFY_READ),
 522                                addr, nb)))
 523                return -EFAULT;
 524
 525        /* userland only */
 526        if (unlikely(!user_mode(regs)))
 527                return 0;
 528
 529        flush_spe_to_thread(current);
 530
 531        /* If we are loading, get the data from user space, else
 532         * get it from register values
 533         */
 534        if (flags & ST) {
 535                data.ll = 0;
 536                switch (instr) {
 537                case EVSTDD:
 538                case EVSTDW:
 539                case EVSTDH:
 540                        data.w[0] = *evr;
 541                        data.w[1] = regs->gpr[reg];
 542                        break;
 543                case EVSTWHE:
 544                        data.h[2] = *evr >> 16;
 545                        data.h[3] = regs->gpr[reg] >> 16;
 546                        break;
 547                case EVSTWHO:
 548                        data.h[2] = *evr & 0xffff;
 549                        data.h[3] = regs->gpr[reg] & 0xffff;
 550                        break;
 551                case EVSTWWE:
 552                        data.w[1] = *evr;
 553                        break;
 554                case EVSTWWO:
 555                        data.w[1] = regs->gpr[reg];
 556                        break;
 557                default:
 558                        return -EINVAL;
 559                }
 560        } else {
 561                temp.ll = data.ll = 0;
 562                ret = 0;
 563                p = addr;
 564
 565                switch (nb) {
 566                case 8:
 567                        ret |= __get_user_inatomic(temp.v[0], p++);
 568                        ret |= __get_user_inatomic(temp.v[1], p++);
 569                        ret |= __get_user_inatomic(temp.v[2], p++);
 570                        ret |= __get_user_inatomic(temp.v[3], p++);
 571                case 4:
 572                        ret |= __get_user_inatomic(temp.v[4], p++);
 573                        ret |= __get_user_inatomic(temp.v[5], p++);
 574                case 2:
 575                        ret |= __get_user_inatomic(temp.v[6], p++);
 576                        ret |= __get_user_inatomic(temp.v[7], p++);
 577                        if (unlikely(ret))
 578                                return -EFAULT;
 579                }
 580
 581                switch (instr) {
 582                case EVLDD:
 583                case EVLDW:
 584                case EVLDH:
 585                        data.ll = temp.ll;
 586                        break;
 587                case EVLHHESPLAT:
 588                        data.h[0] = temp.h[3];
 589                        data.h[2] = temp.h[3];
 590                        break;
 591                case EVLHHOUSPLAT:
 592                case EVLHHOSSPLAT:
 593                        data.h[1] = temp.h[3];
 594                        data.h[3] = temp.h[3];
 595                        break;
 596                case EVLWHE:
 597                        data.h[0] = temp.h[2];
 598                        data.h[2] = temp.h[3];
 599                        break;
 600                case EVLWHOU:
 601                case EVLWHOS:
 602                        data.h[1] = temp.h[2];
 603                        data.h[3] = temp.h[3];
 604                        break;
 605                case EVLWWSPLAT:
 606                        data.w[0] = temp.w[1];
 607                        data.w[1] = temp.w[1];
 608                        break;
 609                case EVLWHSPLAT:
 610                        data.h[0] = temp.h[2];
 611                        data.h[1] = temp.h[2];
 612                        data.h[2] = temp.h[3];
 613                        data.h[3] = temp.h[3];
 614                        break;
 615                default:
 616                        return -EINVAL;
 617                }
 618        }
 619
 620        if (flags & SW) {
 621                switch (flags & 0xf0) {
 622                case E8:
 623                        data.ll = swab64(data.ll);
 624                        break;
 625                case E4:
 626                        data.w[0] = swab32(data.w[0]);
 627                        data.w[1] = swab32(data.w[1]);
 628                        break;
 629                /* Its half word endian */
 630                default:
 631                        data.h[0] = swab16(data.h[0]);
 632                        data.h[1] = swab16(data.h[1]);
 633                        data.h[2] = swab16(data.h[2]);
 634                        data.h[3] = swab16(data.h[3]);
 635                        break;
 636                }
 637        }
 638
 639        if (flags & SE) {
 640                data.w[0] = (s16)data.h[1];
 641                data.w[1] = (s16)data.h[3];
 642        }
 643
 644        /* Store result to memory or update registers */
 645        if (flags & ST) {
 646                ret = 0;
 647                p = addr;
 648                switch (nb) {
 649                case 8:
 650                        ret |= __put_user_inatomic(data.v[0], p++);
 651                        ret |= __put_user_inatomic(data.v[1], p++);
 652                        ret |= __put_user_inatomic(data.v[2], p++);
 653                        ret |= __put_user_inatomic(data.v[3], p++);
 654                case 4:
 655                        ret |= __put_user_inatomic(data.v[4], p++);
 656                        ret |= __put_user_inatomic(data.v[5], p++);
 657                case 2:
 658                        ret |= __put_user_inatomic(data.v[6], p++);
 659                        ret |= __put_user_inatomic(data.v[7], p++);
 660                }
 661                if (unlikely(ret))
 662                        return -EFAULT;
 663        } else {
 664                *evr = data.w[0];
 665                regs->gpr[reg] = data.w[1];
 666        }
 667
 668        return 1;
 669}
 670#endif /* CONFIG_SPE */
 671
 672#ifdef CONFIG_VSX
 673/*
 674 * Emulate VSX instructions...
 675 */
 676static int emulate_vsx(unsigned char __user *addr, unsigned int reg,
 677                       unsigned int areg, struct pt_regs *regs,
 678                       unsigned int flags, unsigned int length,
 679                       unsigned int elsize)
 680{
 681        char *ptr;
 682        unsigned long *lptr;
 683        int ret = 0;
 684        int sw = 0;
 685        int i, j;
 686
 687        /* userland only */
 688        if (unlikely(!user_mode(regs)))
 689                return 0;
 690
 691        flush_vsx_to_thread(current);
 692
 693        if (reg < 32)
 694                ptr = (char *) &current->thread.fp_state.fpr[reg][0];
 695        else
 696                ptr = (char *) &current->thread.vr_state.vr[reg - 32];
 697
 698        lptr = (unsigned long *) ptr;
 699
 700#ifdef __LITTLE_ENDIAN__
 701        if (flags & SW) {
 702                elsize = length;
 703                sw = length-1;
 704        } else {
 705                /*
 706                 * The elements are BE ordered, even in LE mode, so process
 707                 * them in reverse order.
 708                 */
 709                addr += length - elsize;
 710
 711                /* 8 byte memory accesses go in the top 8 bytes of the VR */
 712                if (length == 8)
 713                        ptr += 8;
 714        }
 715#else
 716        if (flags & SW)
 717                sw = elsize-1;
 718#endif
 719
 720        for (j = 0; j < length; j += elsize) {
 721                for (i = 0; i < elsize; ++i) {
 722                        if (flags & ST)
 723                                ret |= __put_user(ptr[i^sw], addr + i);
 724                        else
 725                                ret |= __get_user(ptr[i^sw], addr + i);
 726                }
 727                ptr  += elsize;
 728#ifdef __LITTLE_ENDIAN__
 729                addr -= elsize;
 730#else
 731                addr += elsize;
 732#endif
 733        }
 734
 735#ifdef __BIG_ENDIAN__
 736#define VSX_HI 0
 737#define VSX_LO 1
 738#else
 739#define VSX_HI 1
 740#define VSX_LO 0
 741#endif
 742
 743        if (!ret) {
 744                if (flags & U)
 745                        regs->gpr[areg] = regs->dar;
 746
 747                /* Splat load copies the same data to top and bottom 8 bytes */
 748                if (flags & SPLT)
 749                        lptr[VSX_LO] = lptr[VSX_HI];
 750                /* For 8 byte loads, zero the low 8 bytes */
 751                else if (!(flags & ST) && (8 == length))
 752                        lptr[VSX_LO] = 0;
 753        } else
 754                return -EFAULT;
 755
 756        return 1;
 757}
 758#endif
 759
 760/*
 761 * Called on alignment exception. Attempts to fixup
 762 *
 763 * Return 1 on success
 764 * Return 0 if unable to handle the interrupt
 765 * Return -EFAULT if data address is bad
 766 */
 767
 768int fix_alignment(struct pt_regs *regs)
 769{
 770        unsigned int instr, nb, flags, instruction = 0;
 771        unsigned int reg, areg;
 772        unsigned int dsisr;
 773        unsigned char __user *addr;
 774        unsigned long p, swiz;
 775        int ret, i;
 776        union data {
 777                u64 ll;
 778                double dd;
 779                unsigned char v[8];
 780                struct {
 781#ifdef __LITTLE_ENDIAN__
 782                        int      low32;
 783                        unsigned hi32;
 784#else
 785                        unsigned hi32;
 786                        int      low32;
 787#endif
 788                } x32;
 789                struct {
 790#ifdef __LITTLE_ENDIAN__
 791                        short         low16;
 792                        unsigned char hi48[6];
 793#else
 794                        unsigned char hi48[6];
 795                        short         low16;
 796#endif
 797                } x16;
 798        } data;
 799
 800        /*
 801         * We require a complete register set, if not, then our assembly
 802         * is broken
 803         */
 804        CHECK_FULL_REGS(regs);
 805
 806        dsisr = regs->dsisr;
 807
 808        /* Some processors don't provide us with a DSISR we can use here,
 809         * let's make one up from the instruction
 810         */
 811        if (cpu_has_feature(CPU_FTR_NODSISRALIGN)) {
 812                unsigned long pc = regs->nip;
 813
 814                if (cpu_has_feature(CPU_FTR_PPC_LE) && (regs->msr & MSR_LE))
 815                        pc ^= 4;
 816                if (unlikely(__get_user_inatomic(instr,
 817                                                 (unsigned int __user *)pc)))
 818                        return -EFAULT;
 819                if (cpu_has_feature(CPU_FTR_REAL_LE) && (regs->msr & MSR_LE))
 820                        instr = cpu_to_le32(instr);
 821                dsisr = make_dsisr(instr);
 822                instruction = instr;
 823        }
 824
 825        /* extract the operation and registers from the dsisr */
 826        reg = (dsisr >> 5) & 0x1f;      /* source/dest register */
 827        areg = dsisr & 0x1f;            /* register to update */
 828
 829#ifdef CONFIG_SPE
 830        if ((instr >> 26) == 0x4) {
 831                PPC_WARN_ALIGNMENT(spe, regs);
 832                return emulate_spe(regs, reg, instr);
 833        }
 834#endif
 835
 836        instr = (dsisr >> 10) & 0x7f;
 837        instr |= (dsisr >> 13) & 0x60;
 838
 839        /* Lookup the operation in our table */
 840        nb = aligninfo[instr].len;
 841        flags = aligninfo[instr].flags;
 842
 843        /* ldbrx/stdbrx overlap lfs/stfs in the DSISR unfortunately */
 844        if (IS_XFORM(instruction) && ((instruction >> 1) & 0x3ff) == 532) {
 845                nb = 8;
 846                flags = LD+SW;
 847        } else if (IS_XFORM(instruction) &&
 848                   ((instruction >> 1) & 0x3ff) == 660) {
 849                nb = 8;
 850                flags = ST+SW;
 851        }
 852
 853        /* Byteswap little endian loads and stores */
 854        swiz = 0;
 855        if ((regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE)) {
 856                flags ^= SW;
 857#ifdef __BIG_ENDIAN__
 858                /*
 859                 * So-called "PowerPC little endian" mode works by
 860                 * swizzling addresses rather than by actually doing
 861                 * any byte-swapping.  To emulate this, we XOR each
 862                 * byte address with 7.  We also byte-swap, because
 863                 * the processor's address swizzling depends on the
 864                 * operand size (it xors the address with 7 for bytes,
 865                 * 6 for halfwords, 4 for words, 0 for doublewords) but
 866                 * we will xor with 7 and load/store each byte separately.
 867                 */
 868                if (cpu_has_feature(CPU_FTR_PPC_LE))
 869                        swiz = 7;
 870#endif
 871        }
 872
 873        /* DAR has the operand effective address */
 874        addr = (unsigned char __user *)regs->dar;
 875
 876#ifdef CONFIG_VSX
 877        if ((instruction & 0xfc00003e) == 0x7c000018) {
 878                unsigned int elsize;
 879
 880                /* Additional register addressing bit (64 VSX vs 32 FPR/GPR) */
 881                reg |= (instruction & 0x1) << 5;
 882                /* Simple inline decoder instead of a table */
 883                /* VSX has only 8 and 16 byte memory accesses */
 884                nb = 8;
 885                if (instruction & 0x200)
 886                        nb = 16;
 887
 888                /* Vector stores in little-endian mode swap individual
 889                   elements, so process them separately */
 890                elsize = 4;
 891                if (instruction & 0x80)
 892                        elsize = 8;
 893
 894                flags = 0;
 895                if ((regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE))
 896                        flags |= SW;
 897                if (instruction & 0x100)
 898                        flags |= ST;
 899                if (instruction & 0x040)
 900                        flags |= U;
 901                /* splat load needs a special decoder */
 902                if ((instruction & 0x400) == 0){
 903                        flags |= SPLT;
 904                        nb = 8;
 905                }
 906                PPC_WARN_ALIGNMENT(vsx, regs);
 907                return emulate_vsx(addr, reg, areg, regs, flags, nb, elsize);
 908        }
 909#endif
 910        /* A size of 0 indicates an instruction we don't support, with
 911         * the exception of DCBZ which is handled as a special case here
 912         */
 913        if (instr == DCBZ) {
 914                PPC_WARN_ALIGNMENT(dcbz, regs);
 915                return emulate_dcbz(regs, addr);
 916        }
 917        if (unlikely(nb == 0))
 918                return 0;
 919
 920        /* Load/Store Multiple instructions are handled in their own
 921         * function
 922         */
 923        if (flags & M) {
 924                PPC_WARN_ALIGNMENT(multiple, regs);
 925                return emulate_multiple(regs, addr, reg, nb,
 926                                        flags, instr, swiz);
 927        }
 928
 929        /* Verify the address of the operand */
 930        if (unlikely(user_mode(regs) &&
 931                     !access_ok((flags & ST ? VERIFY_WRITE : VERIFY_READ),
 932                                addr, nb)))
 933                return -EFAULT;
 934
 935        /* Force the fprs into the save area so we can reference them */
 936        if (flags & F) {
 937                /* userland only */
 938                if (unlikely(!user_mode(regs)))
 939                        return 0;
 940                flush_fp_to_thread(current);
 941        }
 942
 943        if ((nb == 16)) {
 944                if (flags & F) {
 945                        /* Special case for 16-byte FP loads and stores */
 946                        PPC_WARN_ALIGNMENT(fp_pair, regs);
 947                        return emulate_fp_pair(addr, reg, flags);
 948                } else {
 949#ifdef CONFIG_PPC64
 950                        /* Special case for 16-byte loads and stores */
 951                        PPC_WARN_ALIGNMENT(lq_stq, regs);
 952                        return emulate_lq_stq(regs, addr, reg, flags);
 953#else
 954                        return 0;
 955#endif
 956                }
 957        }
 958
 959        PPC_WARN_ALIGNMENT(unaligned, regs);
 960
 961        /* If we are loading, get the data from user space, else
 962         * get it from register values
 963         */
 964        if (!(flags & ST)) {
 965                unsigned int start = 0;
 966
 967                switch (nb) {
 968                case 4:
 969                        start = offsetof(union data, x32.low32);
 970                        break;
 971                case 2:
 972                        start = offsetof(union data, x16.low16);
 973                        break;
 974                }
 975
 976                data.ll = 0;
 977                ret = 0;
 978                p = (unsigned long)addr;
 979
 980                for (i = 0; i < nb; i++)
 981                        ret |= __get_user_inatomic(data.v[start + i],
 982                                                   SWIZ_PTR(p++));
 983
 984                if (unlikely(ret))
 985                        return -EFAULT;
 986
 987        } else if (flags & F) {
 988                data.ll = current->thread.TS_FPR(reg);
 989                if (flags & S) {
 990                        /* Single-precision FP store requires conversion... */
 991#ifdef CONFIG_PPC_FPU
 992                        preempt_disable();
 993                        enable_kernel_fp();
 994                        cvt_df(&data.dd, (float *)&data.x32.low32);
 995                        preempt_enable();
 996#else
 997                        return 0;
 998#endif
 999                }
1000        } else

1001                data.ll = regs->gpr[reg];
1002
1003        if (flags & SW) {
1004                switch (nb) {
1005                case 8:
1006                        data.ll = swab64(data.ll);
1007                        break;
1008                case 4:
1009                        data.x32.low32 = swab32(data.x32.low32);
1010                        break;
1011                case 2:
1012                        data.x16.low16 = swab16(data.x16.low16);
1013                        break;
1014                }
1015        }
1016
1017        /* Perform other misc operations like sign extension
1018         * or floating point single precision conversion
1019         */
1020        switch (flags & ~(U|SW)) {
1021        case LD+SE:     /* sign extending integer loads */
1022        case LD+F+SE:   /* sign extend for lfiwax */
1023                if ( nb == 2 )
1024                        data.ll = data.x16.low16;
1025                else    /* nb must be 4 */
1026                        data.ll = data.x32.low32;
1027                break;
1028
1029        /* Single-precision FP load requires conversion... */
1030        case LD+F+S:
1031#ifdef CONFIG_PPC_FPU
1032                preempt_disable();
1033                enable_kernel_fp();
1034                cvt_fd((float *)&data.x32.low32, &data.dd);
1035                preempt_enable();
1036#else
1037                return 0;
1038#endif
1039                break;
1040        }
1041
1042        /* Store result to memory or update registers */
1043        if (flags & ST) {
1044                unsigned int start = 0;
1045
1046                switch (nb) {
1047                case 4:
1048                        start = offsetof(union data, x32.low32);
1049                        break;
1050                case 2:
1051                        start = offsetof(union data, x16.low16);
1052                        break;
1053                }
1054
1055                ret = 0;
1056                p = (unsigned long)addr;
1057
1058                for (i = 0; i < nb; i++)
1059                        ret |= __put_user_inatomic(data.v[start + i],
1060                                                   SWIZ_PTR(p++));
1061
1062                if (unlikely(ret))
1063                        return -EFAULT;
1064        } else if (flags & F)
1065                current->thread.TS_FPR(reg) = data.ll;
1066        else
1067                regs->gpr[reg] = data.ll;
1068
1069        /* Update RA as needed */
1070        if (flags & U)
1071                regs->gpr[areg] = regs->dar;
1072
1073        return 1;
1074}
1075