LXR linux/arch/powerpc/kvm/book3s_hv

   1/*
   2 * This program is free software; you can redistribute it and/or modify
   3 * it under the terms of the GNU General Public License, version 2, as
   4 * published by the Free Software Foundation.
   5 *
   6 * This program is distributed in the hope that it will be useful,
   7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
   8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   9 * GNU General Public License for more details.
  10 *
  11 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
  12 *
  13 * Derived from book3s_rmhandlers.S and other files, which are:
  14 *
  15 * Copyright SUSE Linux Products GmbH 2009
  16 *
  17 * Authors: Alexander Graf <agraf@suse.de>
  18 */
  19
  20#include <asm/ppc_asm.h>
  21#include <asm/kvm_asm.h>
  22#include <asm/reg.h>
  23#include <asm/mmu.h>
  24#include <asm/page.h>
  25#include <asm/ptrace.h>
  26#include <asm/hvcall.h>
  27#include <asm/asm-offsets.h>
  28#include <asm/exception-64s.h>
  29#include <asm/kvm_book3s_asm.h>
  30#include <asm/mmu-hash64.h>
  31#include <asm/tm.h>
  32
  33#define VCPU_GPRS_TM(reg) (((reg) * ULONG_SIZE) + VCPU_GPR_TM)
  34
  35#ifdef __LITTLE_ENDIAN__
  36#error Need to fix lppaca and SLB shadow accesses in little endian mode
  37#endif
  38
  39/* Values in HSTATE_NAPPING(r13) */
  40#define NAPPING_CEDE    1
  41#define NAPPING_NOVCPU  2
  42
  43/*
  44 * Call kvmppc_hv_entry in real mode.
  45 * Must be called with interrupts hard-disabled.
  46 *
  47 * Input Registers:
  48 *
  49 * LR = return address to continue at after eventually re-enabling MMU
  50 */
  51_GLOBAL(kvmppc_hv_entry_trampoline)
  52        mflr    r0
  53        std     r0, PPC_LR_STKOFF(r1)
  54        stdu    r1, -112(r1)
  55        mfmsr   r10
  56        LOAD_REG_ADDR(r5, kvmppc_call_hv_entry)
  57        li      r0,MSR_RI
  58        andc    r0,r10,r0
  59        li      r6,MSR_IR | MSR_DR
  60        andc    r6,r10,r6
  61        mtmsrd  r0,1            /* clear RI in MSR */
  62        mtsrr0  r5
  63        mtsrr1  r6
  64        RFI
  65
  66kvmppc_call_hv_entry:
  67        ld      r4, HSTATE_KVM_VCPU(r13)
  68        bl      kvmppc_hv_entry
  69
  70        /* Back from guest - restore host state and return to caller */
  71
  72BEGIN_FTR_SECTION
  73        /* Restore host DABR and DABRX */
  74        ld      r5,HSTATE_DABR(r13)
  75        li      r6,7
  76        mtspr   SPRN_DABR,r5
  77        mtspr   SPRN_DABRX,r6
  78END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
  79
  80        /* Restore SPRG3 */
  81        ld      r3,PACA_SPRG_VDSO(r13)
  82        mtspr   SPRN_SPRG_VDSO_WRITE,r3
  83
  84        /* Reload the host's PMU registers */
  85        ld      r3, PACALPPACAPTR(r13)  /* is the host using the PMU? */
  86        lbz     r4, LPPACA_PMCINUSE(r3)
  87        cmpwi   r4, 0
  88        beq     23f                     /* skip if not */
  89        lwz     r3, HSTATE_PMC(r13)
  90        lwz     r4, HSTATE_PMC + 4(r13)
  91        lwz     r5, HSTATE_PMC + 8(r13)
  92        lwz     r6, HSTATE_PMC + 12(r13)
  93        lwz     r8, HSTATE_PMC + 16(r13)
  94        lwz     r9, HSTATE_PMC + 20(r13)
  95BEGIN_FTR_SECTION
  96        lwz     r10, HSTATE_PMC + 24(r13)
  97        lwz     r11, HSTATE_PMC + 28(r13)
  98END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
  99        mtspr   SPRN_PMC1, r3
 100        mtspr   SPRN_PMC2, r4
 101        mtspr   SPRN_PMC3, r5
 102        mtspr   SPRN_PMC4, r6
 103        mtspr   SPRN_PMC5, r8
 104        mtspr   SPRN_PMC6, r9
 105BEGIN_FTR_SECTION
 106        mtspr   SPRN_PMC7, r10
 107        mtspr   SPRN_PMC8, r11
 108END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
 109        ld      r3, HSTATE_MMCR(r13)
 110        ld      r4, HSTATE_MMCR + 8(r13)
 111        ld      r5, HSTATE_MMCR + 16(r13)
 112        ld      r6, HSTATE_MMCR + 24(r13)
 113        ld      r7, HSTATE_MMCR + 32(r13)
 114        mtspr   SPRN_MMCR1, r4
 115        mtspr   SPRN_MMCRA, r5
 116        mtspr   SPRN_SIAR, r6
 117        mtspr   SPRN_SDAR, r7
 118BEGIN_FTR_SECTION
 119        ld      r8, HSTATE_MMCR + 40(r13)
 120        ld      r9, HSTATE_MMCR + 48(r13)
 121        mtspr   SPRN_MMCR2, r8
 122        mtspr   SPRN_SIER, r9
 123END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
 124        mtspr   SPRN_MMCR0, r3
 125        isync
 12623:
 127
 128        /*
 129         * Reload DEC.  HDEC interrupts were disabled when
 130         * we reloaded the host's LPCR value.
 131         */
 132        ld      r3, HSTATE_DECEXP(r13)
 133        mftb    r4
 134        subf    r4, r4, r3
 135        mtspr   SPRN_DEC, r4
 136
 137        /*
 138         * For external and machine check interrupts, we need
 139         * to call the Linux handler to process the interrupt.
 140         * We do that by jumping to absolute address 0x500 for
 141         * external interrupts, or the machine_check_fwnmi label
 142         * for machine checks (since firmware might have patched
 143         * the vector area at 0x200).  The [h]rfid at the end of the
 144         * handler will return to the book3s_hv_interrupts.S code.
 145         * For other interrupts we do the rfid to get back
 146         * to the book3s_hv_interrupts.S code here.
 147         */
 148        ld      r8, 112+PPC_LR_STKOFF(r1)
 149        addi    r1, r1, 112
 150        ld      r7, HSTATE_HOST_MSR(r13)
 151
 152        cmpwi   cr1, r12, BOOK3S_INTERRUPT_MACHINE_CHECK
 153        cmpwi   r12, BOOK3S_INTERRUPT_EXTERNAL
 154BEGIN_FTR_SECTION
 155        beq     11f
 156END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
 157
 158        /* RFI into the highmem handler, or branch to interrupt handler */
 159        mfmsr   r6
 160        li      r0, MSR_RI
 161        andc    r6, r6, r0
 162        mtmsrd  r6, 1                   /* Clear RI in MSR */
 163        mtsrr0  r8
 164        mtsrr1  r7
 165        beqa    0x500                   /* external interrupt (PPC970) */
 166        beq     cr1, 13f                /* machine check */
 167        RFI
 168
 169        /* On POWER7, we have external interrupts set to use HSRR0/1 */
 17011:     mtspr   SPRN_HSRR0, r8
 171        mtspr   SPRN_HSRR1, r7
 172        ba      0x500
 173
 17413:     b       machine_check_fwnmi
 175
 176kvmppc_primary_no_guest:
 177        /* We handle this much like a ceded vcpu */
 178        /* set our bit in napping_threads */
 179        ld      r5, HSTATE_KVM_VCORE(r13)
 180        lbz     r7, HSTATE_PTID(r13)
 181        li      r0, 1
 182        sld     r0, r0, r7
 183        addi    r6, r5, VCORE_NAPPING_THREADS
 1841:      lwarx   r3, 0, r6
 185        or      r3, r3, r0
 186        stwcx.  r3, 0, r6
 187        bne     1b
 188        /* order napping_threads update vs testing entry_exit_count */
 189        isync
 190        li      r12, 0
 191        lwz     r7, VCORE_ENTRY_EXIT(r5)
 192        cmpwi   r7, 0x100
 193        bge     kvm_novcpu_exit /* another thread already exiting */
 194        li      r3, NAPPING_NOVCPU
 195        stb     r3, HSTATE_NAPPING(r13)
 196        li      r3, 1
 197        stb     r3, HSTATE_HWTHREAD_REQ(r13)
 198
 199        b       kvm_do_nap
 200
 201kvm_novcpu_wakeup:
 202        ld      r1, HSTATE_HOST_R1(r13)
 203        ld      r5, HSTATE_KVM_VCORE(r13)
 204        li      r0, 0
 205        stb     r0, HSTATE_NAPPING(r13)
 206        stb     r0, HSTATE_HWTHREAD_REQ(r13)
 207
 208        /* check the wake reason */
 209        bl      kvmppc_check_wake_reason
 210        
 211        /* see if any other thread is already exiting */
 212        lwz     r0, VCORE_ENTRY_EXIT(r5)
 213        cmpwi   r0, 0x100
 214        bge     kvm_novcpu_exit
 215
 216        /* clear our bit in napping_threads */
 217        lbz     r7, HSTATE_PTID(r13)
 218        li      r0, 1
 219        sld     r0, r0, r7
 220        addi    r6, r5, VCORE_NAPPING_THREADS
 2214:      lwarx   r7, 0, r6
 222        andc    r7, r7, r0
 223        stwcx.  r7, 0, r6
 224        bne     4b
 225
 226        /* See if the wake reason means we need to exit */
 227        cmpdi   r3, 0
 228        bge     kvm_novcpu_exit
 229
 230        /* Got an IPI but other vcpus aren't yet exiting, must be a latecomer */
 231        ld      r4, HSTATE_KVM_VCPU(r13)
 232        cmpdi   r4, 0
 233        bne     kvmppc_got_guest
 234
 235kvm_novcpu_exit:
 236        b       hdec_soon
 237
 238/*
 239 * We come in here when wakened from nap mode.
 240 * Relocation is off and most register values are lost.
 241 * r13 points to the PACA.
 242 */
 243        .globl  kvm_start_guest
 244kvm_start_guest:
 245
 246        /* Set runlatch bit the minute you wake up from nap */
 247        mfspr   r1, SPRN_CTRLF
 248        ori     r1, r1, 1
 249        mtspr   SPRN_CTRLT, r1
 250
 251        ld      r2,PACATOC(r13)
 252
 253        li      r0,KVM_HWTHREAD_IN_KVM
 254        stb     r0,HSTATE_HWTHREAD_STATE(r13)
 255
 256        /* NV GPR values from power7_idle() will no longer be valid */
 257        li      r0,1
 258        stb     r0,PACA_NAPSTATELOST(r13)
 259
 260        /* were we napping due to cede? */
 261        lbz     r0,HSTATE_NAPPING(r13)
 262        cmpwi   r0,NAPPING_CEDE
 263        beq     kvm_end_cede
 264        cmpwi   r0,NAPPING_NOVCPU
 265        beq     kvm_novcpu_wakeup
 266
 267        ld      r1,PACAEMERGSP(r13)
 268        subi    r1,r1,STACK_FRAME_OVERHEAD
 269
 270        /*
 271         * We weren't napping due to cede, so this must be a secondary
 272         * thread being woken up to run a guest, or being woken up due
 273         * to a stray IPI.  (Or due to some machine check or hypervisor
 274         * maintenance interrupt while the core is in KVM.)
 275         */
 276
 277        /* Check the wake reason in SRR1 to see why we got here */
 278        bl      kvmppc_check_wake_reason
 279        cmpdi   r3, 0
 280        bge     kvm_no_guest
 281
 282        /* get vcpu pointer, NULL if we have no vcpu to run */
 283        ld      r4,HSTATE_KVM_VCPU(r13)
 284        cmpdi   r4,0
 285        /* if we have no vcpu to run, go back to sleep */
 286        beq     kvm_no_guest
 287
 288        /* Set HSTATE_DSCR(r13) to something sensible */
 289        LOAD_REG_ADDR(r6, dscr_default)
 290        ld      r6, 0(r6)
 291        std     r6, HSTATE_DSCR(r13)
 292
 293        bl      kvmppc_hv_entry
 294
 295        /* Back from the guest, go back to nap */
 296        /* Clear our vcpu pointer so we don't come back in early */
 297        li      r0, 0
 298        std     r0, HSTATE_KVM_VCPU(r13)
 299        /*
 300         * Make sure we clear HSTATE_KVM_VCPU(r13) before incrementing
 301         * the nap_count, because once the increment to nap_count is
 302         * visible we could be given another vcpu.
 303         */
 304        lwsync
 305
 306        /* increment the nap count and then go to nap mode */
 307        ld      r4, HSTATE_KVM_VCORE(r13)
 308        addi    r4, r4, VCORE_NAP_COUNT
 30951:     lwarx   r3, 0, r4
 310        addi    r3, r3, 1
 311        stwcx.  r3, 0, r4
 312        bne     51b
 313
 314kvm_no_guest:
 315        li      r0, KVM_HWTHREAD_IN_NAP
 316        stb     r0, HSTATE_HWTHREAD_STATE(r13)
 317kvm_do_nap:
 318        /* Clear the runlatch bit before napping */
 319        mfspr   r2, SPRN_CTRLF
 320        clrrdi  r2, r2, 1
 321        mtspr   SPRN_CTRLT, r2
 322
 323        li      r3, LPCR_PECE0
 324        mfspr   r4, SPRN_LPCR
 325        rlwimi  r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
 326        mtspr   SPRN_LPCR, r4
 327        isync
 328        std     r0, HSTATE_SCRATCH0(r13)
 329        ptesync
 330        ld      r0, HSTATE_SCRATCH0(r13)
 3311:      cmpd    r0, r0
 332        bne     1b
 333        nap
 334        b       .
 335
 336/******************************************************************************
 337 *                                                                            *
 338 *                               Entry code                                   *
 339 *                                                                            *
 340 *****************************************************************************/
 341
 342.global kvmppc_hv_entry
 343kvmppc_hv_entry:
 344
 345        /* Required state:
 346         *
 347         * R4 = vcpu pointer (or NULL)
 348         * MSR = ~IR|DR
 349         * R13 = PACA
 350         * R1 = host R1
 351         * all other volatile GPRS = free
 352         */
 353        mflr    r0
 354        std     r0, PPC_LR_STKOFF(r1)
 355        stdu    r1, -112(r1)
 356
 357        /* Save R1 in the PACA */
 358        std     r1, HSTATE_HOST_R1(r13)
 359
 360        li      r6, KVM_GUEST_MODE_HOST_HV
 361        stb     r6, HSTATE_IN_GUEST(r13)
 362
 363        /* Clear out SLB */
 364        li      r6,0
 365        slbmte  r6,r6
 366        slbia
 367        ptesync
 368
 369BEGIN_FTR_SECTION
 370        b       30f
 371END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
 372        /*
 373         * POWER7 host -> guest partition switch code.
 374         * We don't have to lock against concurrent tlbies,
 375         * but we do have to coordinate across hardware threads.
 376         */
 377        /* Increment entry count iff exit count is zero. */
 378        ld      r5,HSTATE_KVM_VCORE(r13)
 379        addi    r9,r5,VCORE_ENTRY_EXIT
 38021:     lwarx   r3,0,r9
 381        cmpwi   r3,0x100                /* any threads starting to exit? */
 382        bge     secondary_too_late      /* if so we're too late to the party */
 383        addi    r3,r3,1
 384        stwcx.  r3,0,r9
 385        bne     21b
 386
 387        /* Primary thread switches to guest partition. */
 388        ld      r9,VCORE_KVM(r5)        /* pointer to struct kvm */
 389        lbz     r6,HSTATE_PTID(r13)
 390        cmpwi   r6,0
 391        bne     20f
 392        ld      r6,KVM_SDR1(r9)
 393        lwz     r7,KVM_LPID(r9)
 394        li      r0,LPID_RSVD            /* switch to reserved LPID */
 395        mtspr   SPRN_LPID,r0
 396        ptesync
 397        mtspr   SPRN_SDR1,r6            /* switch to partition page table */
 398        mtspr   SPRN_LPID,r7
 399        isync
 400
 401        /* See if we need to flush the TLB */
 402        lhz     r6,PACAPACAINDEX(r13)   /* test_bit(cpu, need_tlb_flush) */
 403        clrldi  r7,r6,64-6              /* extract bit number (6 bits) */
 404        srdi    r6,r6,6                 /* doubleword number */
 405        sldi    r6,r6,3                 /* address offset */
 406        add     r6,r6,r9
 407        addi    r6,r6,KVM_NEED_FLUSH    /* dword in kvm->arch.need_tlb_flush */
 408        li      r0,1
 409        sld     r0,r0,r7
 410        ld      r7,0(r6)
 411        and.    r7,r7,r0
 412        beq     22f
 41323:     ldarx   r7,0,r6                 /* if set, clear the bit */
 414        andc    r7,r7,r0
 415        stdcx.  r7,0,r6
 416        bne     23b
 417        /* Flush the TLB of any entries for this LPID */
 418        /* use arch 2.07S as a proxy for POWER8 */
 419BEGIN_FTR_SECTION
 420        li      r6,512                  /* POWER8 has 512 sets */
 421FTR_SECTION_ELSE
 422        li      r6,128                  /* POWER7 has 128 sets */
 423ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
 424        mtctr   r6
 425        li      r7,0x800                /* IS field = 0b10 */
 426        ptesync
 42728:     tlbiel  r7
 428        addi    r7,r7,0x1000
 429        bdnz    28b
 430        ptesync
 431
 432        /* Add timebase offset onto timebase */
 43322:     ld      r8,VCORE_TB_OFFSET(r5)
 434        cmpdi   r8,0
 435        beq     37f
 436        mftb    r6              /* current host timebase */
 437        add     r8,r8,r6
 438        mtspr   SPRN_TBU40,r8   /* update upper 40 bits */
 439        mftb    r7              /* check if lower 24 bits overflowed */
 440        clrldi  r6,r6,40
 441        clrldi  r7,r7,40
 442        cmpld   r7,r6
 443        bge     37f
 444        addis   r8,r8,0x100     /* if so, increment upper 40 bits */
 445        mtspr   SPRN_TBU40,r8
 446
 447        /* Load guest PCR value to select appropriate compat mode */
 44837:     ld      r7, VCORE_PCR(r5)
 449        cmpdi   r7, 0
 450        beq     38f
 451        mtspr   SPRN_PCR, r7
 45238:
 453
 454BEGIN_FTR_SECTION
 455        /* DPDES is shared between threads */
 456        ld      r8, VCORE_DPDES(r5)
 457        mtspr   SPRN_DPDES, r8
 458END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
 459
 460        li      r0,1
 461        stb     r0,VCORE_IN_GUEST(r5)   /* signal secondaries to continue */
 462        b       10f
 463
 464        /* Secondary threads wait for primary to have done partition switch */
 46520:     lbz     r0,VCORE_IN_GUEST(r5)
 466        cmpwi   r0,0
 467        beq     20b
 468
 469        /* Set LPCR and RMOR. */
 47010:     ld      r8,VCORE_LPCR(r5)
 471        mtspr   SPRN_LPCR,r8
 472        ld      r8,KVM_RMOR(r9)
 473        mtspr   SPRN_RMOR,r8
 474        isync
 475
 476        /* Check if HDEC expires soon */
 477        mfspr   r3,SPRN_HDEC
 478        cmpwi   r3,512          /* 1 microsecond */
 479        li      r12,BOOK3S_INTERRUPT_HV_DECREMENTER
 480        blt     hdec_soon
 481        b       31f
 482
 483        /*
 484         * PPC970 host -> guest partition switch code.
 485         * We have to lock against concurrent tlbies,
 486         * using native_tlbie_lock to lock against host tlbies
 487         * and kvm->arch.tlbie_lock to lock against guest tlbies.
 488         * We also have to invalidate the TLB since its
 489         * entries aren't tagged with the LPID.
 490         */
 49130:     ld      r5,HSTATE_KVM_VCORE(r13)
 492        ld      r9,VCORE_KVM(r5)        /* pointer to struct kvm */
 493
 494        /* first take native_tlbie_lock */
 495        .section ".toc","aw"
 496toc_tlbie_lock:
 497        .tc     native_tlbie_lock[TC],native_tlbie_lock
 498        .previous
 499        ld      r3,toc_tlbie_lock@toc(2)
 500#ifdef __BIG_ENDIAN__
 501        lwz     r8,PACA_LOCK_TOKEN(r13)
 502#else
 503        lwz     r8,PACAPACAINDEX(r13)
 504#endif
 50524:     lwarx   r0,0,r3
 506        cmpwi   r0,0
 507        bne     24b
 508        stwcx.  r8,0,r3
 509        bne     24b
 510        isync
 511
 512        ld      r5,HSTATE_KVM_VCORE(r13)
 513        ld      r7,VCORE_LPCR(r5)       /* use vcore->lpcr to store HID4 */
 514        li      r0,0x18f
 515        rotldi  r0,r0,HID4_LPID5_SH     /* all lpid bits in HID4 = 1 */
 516        or      r0,r7,r0
 517        ptesync
 518        sync
 519        mtspr   SPRN_HID4,r0            /* switch to reserved LPID */
 520        isync
 521        li      r0,0
 522        stw     r0,0(r3)                /* drop native_tlbie_lock */
 523
 524        /* invalidate the whole TLB */
 525        li      r0,256
 526        mtctr   r0
 527        li      r6,0
 52825:     tlbiel  r6
 529        addi    r6,r6,0x1000
 530        bdnz    25b
 531        ptesync
 532
 533        /* Take the guest's tlbie_lock */
 534        addi    r3,r9,KVM_TLBIE_LOCK
 53524:     lwarx   r0,0,r3
 536        cmpwi   r0,0
 537        bne     24b
 538        stwcx.  r8,0,r3
 539        bne     24b
 540        isync
 541        ld      r6,KVM_SDR1(r9)
 542        mtspr   SPRN_SDR1,r6            /* switch to partition page table */
 543
 544        /* Set up HID4 with the guest's LPID etc. */
 545        sync
 546        mtspr   SPRN_HID4,r7
 547        isync
 548
 549        /* drop the guest's tlbie_lock */
 550        li      r0,0
 551        stw     r0,0(r3)
 552
 553        /* Check if HDEC expires soon */
 554        mfspr   r3,SPRN_HDEC
 555        cmpwi   r3,10
 556        li      r12,BOOK3S_INTERRUPT_HV_DECREMENTER
 557        blt     hdec_soon
 558
 559        /* Enable HDEC interrupts */
 560        mfspr   r0,SPRN_HID0
 561        li      r3,1
 562        rldimi  r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
 563        sync
 564        mtspr   SPRN_HID0,r0
 565        mfspr   r0,SPRN_HID0
 566        mfspr   r0,SPRN_HID0
 567        mfspr   r0,SPRN_HID0
 568        mfspr   r0,SPRN_HID0
 569        mfspr   r0,SPRN_HID0
 570        mfspr   r0,SPRN_HID0
 57131:
 572        /* Do we have a guest vcpu to run? */
 573        cmpdi   r4, 0
 574        beq     kvmppc_primary_no_guest
 575kvmppc_got_guest:
 576
 577        /* Load up guest SLB entries */
 578        lwz     r5,VCPU_SLB_MAX(r4)
 579        cmpwi   r5,0
 580        beq     9f
 581        mtctr   r5
 582        addi    r6,r4,VCPU_SLB
 5831:      ld      r8,VCPU_SLB_E(r6)
 584        ld      r9,VCPU_SLB_V(r6)
 585        slbmte  r9,r8
 586        addi    r6,r6,VCPU_SLB_SIZE
 587        bdnz    1b
 5889:
 589        /* Increment yield count if they have a VPA */
 590        ld      r3, VCPU_VPA(r4)
 591        cmpdi   r3, 0
 592        beq     25f
 593        lwz     r5, LPPACA_YIELDCOUNT(r3)
 594        addi    r5, r5, 1
 595        stw     r5, LPPACA_YIELDCOUNT(r3)
 596        li      r6, 1
 597        stb     r6, VCPU_VPA_DIRTY(r4)
 59825:
 599
 600BEGIN_FTR_SECTION
 601        /* Save purr/spurr */
 602        mfspr   r5,SPRN_PURR
 603        mfspr   r6,SPRN_SPURR
 604        std     r5,HSTATE_PURR(r13)
 605        std     r6,HSTATE_SPURR(r13)
 606        ld      r7,VCPU_PURR(r4)
 607        ld      r8,VCPU_SPURR(r4)
 608        mtspr   SPRN_PURR,r7
 609        mtspr   SPRN_SPURR,r8
 610END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
 611
 612BEGIN_FTR_SECTION
 613        /* Set partition DABR */
 614        /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
 615        lwz     r5,VCPU_DABRX(r4)
 616        ld      r6,VCPU_DABR(r4)
 617        mtspr   SPRN_DABRX,r5
 618        mtspr   SPRN_DABR,r6
 619 BEGIN_FTR_SECTION_NESTED(89)
 620        isync
 621 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_206, CPU_FTR_ARCH_206, 89)
 622END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
 623
 624#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 625BEGIN_FTR_SECTION
 626        b       skip_tm
 627END_FTR_SECTION_IFCLR(CPU_FTR_TM)
 628
 629        /* Turn on TM/FP/VSX/VMX so we can restore them. */
 630        mfmsr   r5
 631        li      r6, MSR_TM >> 32
 632        sldi    r6, r6, 32
 633        or      r5, r5, r6
 634        ori     r5, r5, MSR_FP
 635        oris    r5, r5, (MSR_VEC | MSR_VSX)@h
 636        mtmsrd  r5
 637
 638        /*
 639         * The user may change these outside of a transaction, so they must
 640         * always be context switched.
 641         */
 642        ld      r5, VCPU_TFHAR(r4)
 643        ld      r6, VCPU_TFIAR(r4)
 644        ld      r7, VCPU_TEXASR(r4)
 645        mtspr   SPRN_TFHAR, r5
 646        mtspr   SPRN_TFIAR, r6
 647        mtspr   SPRN_TEXASR, r7
 648
 649        ld      r5, VCPU_MSR(r4)
 650        rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
 651        beq     skip_tm /* TM not active in guest */
 652
 653        /* Make sure the failure summary is set, otherwise we'll program check
 654         * when we trechkpt.  It's possible that this might have been not set
 655         * on a kvmppc_set_one_reg() call but we shouldn't let this crash the
 656         * host.
 657         */
 658        oris    r7, r7, (TEXASR_FS)@h
 659        mtspr   SPRN_TEXASR, r7
 660
 661        /*
 662         * We need to load up the checkpointed state for the guest.
 663         * We need to do this early as it will blow away any GPRs, VSRs and
 664         * some SPRs.
 665         */
 666
 667        mr      r31, r4
 668        addi    r3, r31, VCPU_FPRS_TM
 669        bl      .load_fp_state
 670        addi    r3, r31, VCPU_VRS_TM
 671        bl      .load_vr_state
 672        mr      r4, r31
 673        lwz     r7, VCPU_VRSAVE_TM(r4)
 674        mtspr   SPRN_VRSAVE, r7
 675
 676        ld      r5, VCPU_LR_TM(r4)
 677        lwz     r6, VCPU_CR_TM(r4)
 678        ld      r7, VCPU_CTR_TM(r4)
 679        ld      r8, VCPU_AMR_TM(r4)
 680        ld      r9, VCPU_TAR_TM(r4)
 681        mtlr    r5
 682        mtcr    r6
 683        mtctr   r7
 684        mtspr   SPRN_AMR, r8
 685        mtspr   SPRN_TAR, r9
 686
 687        /*
 688         * Load up PPR and DSCR values but don't put them in the actual SPRs
 689         * till the last moment to avoid running with userspace PPR and DSCR for
 690         * too long.
 691         */
 692        ld      r29, VCPU_DSCR_TM(r4)
 693        ld      r30, VCPU_PPR_TM(r4)
 694
 695        std     r2, PACATMSCRATCH(r13) /* Save TOC */
 696
 697        /* Clear the MSR RI since r1, r13 are all going to be foobar. */
 698        li      r5, 0
 699        mtmsrd  r5, 1
 700
 701        /* Load GPRs r0-r28 */
 702        reg = 0
 703        .rept   29
 704        ld      reg, VCPU_GPRS_TM(reg)(r31)
 705        reg = reg + 1
 706        .endr
 707
 708        mtspr   SPRN_DSCR, r29
 709        mtspr   SPRN_PPR, r30
 710
 711        /* Load final GPRs */
 712        ld      29, VCPU_GPRS_TM(29)(r31)
 713        ld      30, VCPU_GPRS_TM(30)(r31)
 714        ld      31, VCPU_GPRS_TM(31)(r31)
 715
 716        /* TM checkpointed state is now setup.  All GPRs are now volatile. */
 717        TRECHKPT
 718
 719        /* Now let's get back the state we need. */
 720        HMT_MEDIUM
 721        GET_PACA(r13)
 722        ld      r29, HSTATE_DSCR(r13)
 723        mtspr   SPRN_DSCR, r29
 724        ld      r4, HSTATE_KVM_VCPU(r13)
 725        ld      r1, HSTATE_HOST_R1(r13)
 726        ld      r2, PACATMSCRATCH(r13)
 727
 728        /* Set the MSR RI since we have our registers back. */
 729        li      r5, MSR_RI
 730        mtmsrd  r5, 1
 731skip_tm:
 732#endif
 733
 734        /* Load guest PMU registers */
 735        /* R4 is live here (vcpu pointer) */
 736        li      r3, 1
 737        sldi    r3, r3, 31              /* MMCR0_FC (freeze counters) bit */
 738        mtspr   SPRN_MMCR0, r3          /* freeze all counters, disable ints */
 739        isync
 740        lwz     r3, VCPU_PMC(r4)        /* always load up guest PMU registers */
 741        lwz     r5, VCPU_PMC + 4(r4)    /* to prevent information leak */
 742        lwz     r6, VCPU_PMC + 8(r4)
 743        lwz     r7, VCPU_PMC + 12(r4)
 744        lwz     r8, VCPU_PMC + 16(r4)
 745        lwz     r9, VCPU_PMC + 20(r4)
 746BEGIN_FTR_SECTION
 747        lwz     r10, VCPU_PMC + 24(r4)
 748        lwz     r11, VCPU_PMC + 28(r4)
 749END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
 750        mtspr   SPRN_PMC1, r3
 751        mtspr   SPRN_PMC2, r5
 752        mtspr   SPRN_PMC3, r6
 753        mtspr   SPRN_PMC4, r7
 754        mtspr   SPRN_PMC5, r8
 755        mtspr   SPRN_PMC6, r9
 756BEGIN_FTR_SECTION
 757        mtspr   SPRN_PMC7, r10
 758        mtspr   SPRN_PMC8, r11
 759END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
 760        ld      r3, VCPU_MMCR(r4)
 761        ld      r5, VCPU_MMCR + 8(r4)
 762        ld      r6, VCPU_MMCR + 16(r4)
 763        ld      r7, VCPU_SIAR(r4)
 764        ld      r8, VCPU_SDAR(r4)
 765        mtspr   SPRN_MMCR1, r5
 766        mtspr   SPRN_MMCRA, r6
 767        mtspr   SPRN_SIAR, r7
 768        mtspr   SPRN_SDAR, r8
 769BEGIN_FTR_SECTION
 770        ld      r5, VCPU_MMCR + 24(r4)
 771        ld      r6, VCPU_SIER(r4)
 772        lwz     r7, VCPU_PMC + 24(r4)
 773        lwz     r8, VCPU_PMC + 28(r4)
 774        ld      r9, VCPU_MMCR + 32(r4)
 775        mtspr   SPRN_MMCR2, r5
 776        mtspr   SPRN_SIER, r6
 777        mtspr   SPRN_SPMC1, r7
 778        mtspr   SPRN_SPMC2, r8
 779        mtspr   SPRN_MMCRS, r9
 780END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
 781        mtspr   SPRN_MMCR0, r3
 782        isync
 783
 784        /* Load up FP, VMX and VSX registers */
 785        bl      kvmppc_load_fp
 786
 787        ld      r14, VCPU_GPR(R14)(r4)
 788        ld      r15, VCPU_GPR(R15)(r4)
 789        ld      r16, VCPU_GPR(R16)(r4)
 790        ld      r17, VCPU_GPR(R17)(r4)
 791        ld      r18, VCPU_GPR(R18)(r4)
 792        ld      r19, VCPU_GPR(R19)(r4)
 793        ld      r20, VCPU_GPR(R20)(r4)
 794        ld      r21, VCPU_GPR(R21)(r4)
 795        ld      r22, VCPU_GPR(R22)(r4)
 796        ld      r23, VCPU_GPR(R23)(r4)
 797        ld      r24, VCPU_GPR(R24)(r4)
 798        ld      r25, VCPU_GPR(R25)(r4)
 799        ld      r26, VCPU_GPR(R26)(r4)
 800        ld      r27, VCPU_GPR(R27)(r4)
 801        ld      r28, VCPU_GPR(R28)(r4)
 802        ld      r29, VCPU_GPR(R29)(r4)
 803        ld      r30, VCPU_GPR(R30)(r4)
 804        ld      r31, VCPU_GPR(R31)(r4)
 805
 806BEGIN_FTR_SECTION
 807        /* Switch DSCR to guest value */
 808        ld      r5, VCPU_DSCR(r4)
 809        mtspr   SPRN_DSCR, r5
 810END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
 811
 812BEGIN_FTR_SECTION
 813        /* Skip next section on POWER7 or PPC970 */
 814        b       8f
 815END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
 816        /* Turn on TM so we can access TFHAR/TFIAR/TEXASR */
 817        mfmsr   r8
 818        li      r0, 1
 819        rldimi  r8, r0, MSR_TM_LG, 63-MSR_TM_LG
 820        mtmsrd  r8
 821
 822        /* Load up POWER8-specific registers */
 823        ld      r5, VCPU_IAMR(r4)
 824        lwz     r6, VCPU_PSPB(r4)
 825        ld      r7, VCPU_FSCR(r4)
 826        mtspr   SPRN_IAMR, r5
 827        mtspr   SPRN_PSPB, r6
 828        mtspr   SPRN_FSCR, r7
 829        ld      r5, VCPU_DAWR(r4)
 830        ld      r6, VCPU_DAWRX(r4)
 831        ld      r7, VCPU_CIABR(r4)
 832        ld      r8, VCPU_TAR(r4)
 833        mtspr   SPRN_DAWR, r5
 834        mtspr   SPRN_DAWRX, r6
 835        mtspr   SPRN_CIABR, r7
 836        mtspr   SPRN_TAR, r8
 837        ld      r5, VCPU_IC(r4)
 838        ld      r6, VCPU_VTB(r4)
 839        mtspr   SPRN_IC, r5
 840        mtspr   SPRN_VTB, r6
 841        ld      r8, VCPU_EBBHR(r4)
 842        mtspr   SPRN_EBBHR, r8
 843        ld      r5, VCPU_EBBRR(r4)
 844        ld      r6, VCPU_BESCR(r4)
 845        ld      r7, VCPU_CSIGR(r4)
 846        ld      r8, VCPU_TACR(r4)
 847        mtspr   SPRN_EBBRR, r5
 848        mtspr   SPRN_BESCR, r6
 849        mtspr   SPRN_CSIGR, r7
 850        mtspr   SPRN_TACR, r8
 851        ld      r5, VCPU_TCSCR(r4)
 852        ld      r6, VCPU_ACOP(r4)
 853        lwz     r7, VCPU_GUEST_PID(r4)
 854        ld      r8, VCPU_WORT(r4)
 855        mtspr   SPRN_TCSCR, r5
 856        mtspr   SPRN_ACOP, r6
 857        mtspr   SPRN_PID, r7
 858        mtspr   SPRN_WORT, r8
 8598:
 860
 861        /*
 862         * Set the decrementer to the guest decrementer.
 863         */
 864        ld      r8,VCPU_DEC_EXPIRES(r4)
 865        /* r8 is a host timebase value here, convert to guest TB */
 866        ld      r5,HSTATE_KVM_VCORE(r13)
 867        ld      r6,VCORE_TB_OFFSET(r5)
 868        add     r8,r8,r6
 869        mftb    r7
 870        subf    r3,r7,r8
 871        mtspr   SPRN_DEC,r3
 872        stw     r3,VCPU_DEC(r4)
 873
 874        ld      r5, VCPU_SPRG0(r4)
 875        ld      r6, VCPU_SPRG1(r4)
 876        ld      r7, VCPU_SPRG2(r4)
 877        ld      r8, VCPU_SPRG3(r4)
 878        mtspr   SPRN_SPRG0, r5
 879        mtspr   SPRN_SPRG1, r6
 880        mtspr   SPRN_SPRG2, r7
 881        mtspr   SPRN_SPRG3, r8
 882
 883        /* Load up DAR and DSISR */
 884        ld      r5, VCPU_DAR(r4)
 885        lwz     r6, VCPU_DSISR(r4)
 886        mtspr   SPRN_DAR, r5
 887        mtspr   SPRN_DSISR, r6
 888
 889BEGIN_FTR_SECTION
 890        /* Restore AMR and UAMOR, set AMOR to all 1s */
 891        ld      r5,VCPU_AMR(r4)
 892        ld      r6,VCPU_UAMOR(r4)
 893        li      r7,-1
 894        mtspr   SPRN_AMR,r5
 895        mtspr   SPRN_UAMOR,r6
 896        mtspr   SPRN_AMOR,r7
 897END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
 898
 899        /* Restore state of CTRL run bit; assume 1 on entry */
 900        lwz     r5,VCPU_CTRL(r4)
 901        andi.   r5,r5,1
 902        bne     4f
 903        mfspr   r6,SPRN_CTRLF
 904        clrrdi  r6,r6,1
 905        mtspr   SPRN_CTRLT,r6
 9064:
 907        ld      r6, VCPU_CTR(r4)
 908        lwz     r7, VCPU_XER(r4)
 909
 910        mtctr   r6
 911        mtxer   r7
 912
 913kvmppc_cede_reentry:            /* r4 = vcpu, r13 = paca */
 914        ld      r10, VCPU_PC(r4)
 915        ld      r11, VCPU_MSR(r4)
 916        ld      r6, VCPU_SRR0(r4)
 917        ld      r7, VCPU_SRR1(r4)
 918        mtspr   SPRN_SRR0, r6
 919        mtspr   SPRN_SRR1, r7
 920
 921deliver_guest_interrupt:
 922        /* r11 = vcpu->arch.msr & ~MSR_HV */
 923        rldicl  r11, r11, 63 - MSR_HV_LG, 1
 924        rotldi  r11, r11, 1 + MSR_HV_LG
 925        ori     r11, r11, MSR_ME
 926
 927        /* Check if we can deliver an external or decrementer interrupt now */
 928        ld      r0, VCPU_PENDING_EXC(r4)
 929        rldicl  r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63
 930        cmpdi   cr1, r0, 0
 931        andi.   r8, r11, MSR_EE
 932BEGIN_FTR_SECTION
 933        mfspr   r8, SPRN_LPCR
 934        /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */
 935        rldimi  r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH
 936        mtspr   SPRN_LPCR, r8
 937        isync
 938END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
 939        beq     5f
 940        li      r0, BOOK3S_INTERRUPT_EXTERNAL
 941        bne     cr1, 12f
 942        mfspr   r0, SPRN_DEC
 943        cmpwi   r0, 0
 944        li      r0, BOOK3S_INTERRUPT_DECREMENTER
 945        bge     5f
 946
 94712:     mtspr   SPRN_SRR0, r10
 948        mr      r10,r0
 949        mtspr   SPRN_SRR1, r11
 950        mr      r9, r4
 951        bl      kvmppc_msr_interrupt
 9525:
 953
 954/*
 955 * Required state:
 956 * R4 = vcpu
 957 * R10: value for HSRR0
 958 * R11: value for HSRR1
 959 * R13 = PACA
 960 */
 961fast_guest_return:
 962        li      r0,0
 963        stb     r0,VCPU_CEDED(r4)       /* cancel cede */
 964        mtspr   SPRN_HSRR0,r10
 965        mtspr   SPRN_HSRR1,r11
 966
 967        /* Activate guest mode, so faults get handled by KVM */
 968        li      r9, KVM_GUEST_MODE_GUEST_HV
 969        stb     r9, HSTATE_IN_GUEST(r13)
 970
 971        /* Enter guest */
 972
 973BEGIN_FTR_SECTION
 974        ld      r5, VCPU_CFAR(r4)
 975        mtspr   SPRN_CFAR, r5
 976END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
 977BEGIN_FTR_SECTION
 978        ld      r0, VCPU_PPR(r4)
 979END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
 980
 981        ld      r5, VCPU_LR(r4)
 982        lwz     r6, VCPU_CR(r4)
 983        mtlr    r5
 984        mtcr    r6
 985
 986        ld      r1, VCPU_GPR(R1)(r4)
 987        ld      r2, VCPU_GPR(R2)(r4)
 988        ld      r3, VCPU_GPR(R3)(r4)
 989        ld      r5, VCPU_GPR(R5)(r4)
 990        ld      r6, VCPU_GPR(R6)(r4)
 991        ld      r7, VCPU_GPR(R7)(r4)
 992        ld      r8, VCPU_GPR(R8)(r4)
 993        ld      r9, VCPU_GPR(R9)(r4)
 994        ld      r10, VCPU_GPR(R10)(r4)
 995        ld      r11, VCPU_GPR(R11)(r4)
 996        ld      r12, VCPU_GPR(R12)(r4)
 997        ld      r13, VCPU_GPR(R13)(r4)
 998
 999BEGIN_FTR_SECTION
1000        mtspr   SPRN_PPR, r0

1001END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1002        ld      r0, VCPU_GPR(R0)(r4)
1003        ld      r4, VCPU_GPR(R4)(r4)
1004
1005        hrfid
1006        b       .
1007
1008/******************************************************************************
1009 *                                                                            *
1010 *                               Exit code                                    *
1011 *                                                                            *
1012 *****************************************************************************/
1013
1014/*
1015 * We come here from the first-level interrupt handlers.
1016 */
1017        .globl  kvmppc_interrupt_hv
1018kvmppc_interrupt_hv:
1019        /*
1020         * Register contents:
1021         * R12          = interrupt vector
1022         * R13          = PACA
1023         * guest CR, R12 saved in shadow VCPU SCRATCH1/0
1024         * guest R13 saved in SPRN_SCRATCH0
1025         */
1026        std     r9, HSTATE_SCRATCH2(r13)
1027
1028        lbz     r9, HSTATE_IN_GUEST(r13)
1029        cmpwi   r9, KVM_GUEST_MODE_HOST_HV
1030        beq     kvmppc_bad_host_intr
1031#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1032        cmpwi   r9, KVM_GUEST_MODE_GUEST
1033        ld      r9, HSTATE_SCRATCH2(r13)
1034        beq     kvmppc_interrupt_pr
1035#endif
1036        /* We're now back in the host but in guest MMU context */
1037        li      r9, KVM_GUEST_MODE_HOST_HV
1038        stb     r9, HSTATE_IN_GUEST(r13)
1039
1040        ld      r9, HSTATE_KVM_VCPU(r13)
1041
1042        /* Save registers */
1043
1044        std     r0, VCPU_GPR(R0)(r9)
1045        std     r1, VCPU_GPR(R1)(r9)
1046        std     r2, VCPU_GPR(R2)(r9)
1047        std     r3, VCPU_GPR(R3)(r9)
1048        std     r4, VCPU_GPR(R4)(r9)
1049        std     r5, VCPU_GPR(R5)(r9)
1050        std     r6, VCPU_GPR(R6)(r9)
1051        std     r7, VCPU_GPR(R7)(r9)
1052        std     r8, VCPU_GPR(R8)(r9)
1053        ld      r0, HSTATE_SCRATCH2(r13)
1054        std     r0, VCPU_GPR(R9)(r9)
1055        std     r10, VCPU_GPR(R10)(r9)
1056        std     r11, VCPU_GPR(R11)(r9)
1057        ld      r3, HSTATE_SCRATCH0(r13)
1058        lwz     r4, HSTATE_SCRATCH1(r13)
1059        std     r3, VCPU_GPR(R12)(r9)
1060        stw     r4, VCPU_CR(r9)
1061BEGIN_FTR_SECTION
1062        ld      r3, HSTATE_CFAR(r13)
1063        std     r3, VCPU_CFAR(r9)
1064END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1065BEGIN_FTR_SECTION
1066        ld      r4, HSTATE_PPR(r13)
1067        std     r4, VCPU_PPR(r9)
1068END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1069
1070        /* Restore R1/R2 so we can handle faults */
1071        ld      r1, HSTATE_HOST_R1(r13)
1072        ld      r2, PACATOC(r13)
1073
1074        mfspr   r10, SPRN_SRR0
1075        mfspr   r11, SPRN_SRR1
1076        std     r10, VCPU_SRR0(r9)
1077        std     r11, VCPU_SRR1(r9)
1078        andi.   r0, r12, 2              /* need to read HSRR0/1? */
1079        beq     1f
1080        mfspr   r10, SPRN_HSRR0
1081        mfspr   r11, SPRN_HSRR1
1082        clrrdi  r12, r12, 2
10831:      std     r10, VCPU_PC(r9)
1084        std     r11, VCPU_MSR(r9)
1085
1086        GET_SCRATCH0(r3)
1087        mflr    r4
1088        std     r3, VCPU_GPR(R13)(r9)
1089        std     r4, VCPU_LR(r9)
1090
1091        stw     r12,VCPU_TRAP(r9)
1092
1093        /* Save HEIR (HV emulation assist reg) in last_inst
1094           if this is an HEI (HV emulation interrupt, e40) */
1095        li      r3,KVM_INST_FETCH_FAILED
1096BEGIN_FTR_SECTION
1097        cmpwi   r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
1098        bne     11f
1099        mfspr   r3,SPRN_HEIR
1100END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
110111:     stw     r3,VCPU_LAST_INST(r9)
1102
1103        /* these are volatile across C function calls */
1104        mfctr   r3
1105        mfxer   r4
1106        std     r3, VCPU_CTR(r9)
1107        stw     r4, VCPU_XER(r9)
1108
1109BEGIN_FTR_SECTION
1110        /* If this is a page table miss then see if it's theirs or ours */
1111        cmpwi   r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1112        beq     kvmppc_hdsi
1113        cmpwi   r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1114        beq     kvmppc_hisi
1115END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1116
1117        /* See if this is a leftover HDEC interrupt */
1118        cmpwi   r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1119        bne     2f
1120        mfspr   r3,SPRN_HDEC
1121        cmpwi   r3,0
1122        bge     ignore_hdec
11232:
1124        /* See if this is an hcall we can handle in real mode */
1125        cmpwi   r12,BOOK3S_INTERRUPT_SYSCALL
1126        beq     hcall_try_real_mode
1127
1128        /* Only handle external interrupts here on arch 206 and later */
1129BEGIN_FTR_SECTION
1130        b       ext_interrupt_to_host
1131END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
1132
1133        /* External interrupt ? */
1134        cmpwi   r12, BOOK3S_INTERRUPT_EXTERNAL
1135        bne+    ext_interrupt_to_host
1136
1137        /* External interrupt, first check for host_ipi. If this is
1138         * set, we know the host wants us out so let's do it now
1139         */
1140        bl      kvmppc_read_intr
1141        cmpdi   r3, 0
1142        bgt     ext_interrupt_to_host
1143
1144        /* Check if any CPU is heading out to the host, if so head out too */
1145        ld      r5, HSTATE_KVM_VCORE(r13)
1146        lwz     r0, VCORE_ENTRY_EXIT(r5)
1147        cmpwi   r0, 0x100
1148        bge     ext_interrupt_to_host
1149
1150        /* Return to guest after delivering any pending interrupt */
1151        mr      r4, r9
1152        b       deliver_guest_interrupt
1153
1154ext_interrupt_to_host:
1155
1156guest_exit_cont:                /* r9 = vcpu, r12 = trap, r13 = paca */
1157        /* Save more register state  */
1158        mfdar   r6
1159        mfdsisr r7
1160        std     r6, VCPU_DAR(r9)
1161        stw     r7, VCPU_DSISR(r9)
1162BEGIN_FTR_SECTION
1163        /* don't overwrite fault_dar/fault_dsisr if HDSI */
1164        cmpwi   r12,BOOK3S_INTERRUPT_H_DATA_STORAGE
1165        beq     6f
1166END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1167        std     r6, VCPU_FAULT_DAR(r9)
1168        stw     r7, VCPU_FAULT_DSISR(r9)
1169
1170        /* See if it is a machine check */
1171        cmpwi   r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1172        beq     machine_check_realmode
1173mc_cont:
1174
1175        /* Save guest CTRL register, set runlatch to 1 */
11766:      mfspr   r6,SPRN_CTRLF
1177        stw     r6,VCPU_CTRL(r9)
1178        andi.   r0,r6,1
1179        bne     4f
1180        ori     r6,r6,1
1181        mtspr   SPRN_CTRLT,r6
11824:
1183        /* Read the guest SLB and save it away */
1184        lwz     r0,VCPU_SLB_NR(r9)      /* number of entries in SLB */
1185        mtctr   r0
1186        li      r6,0
1187        addi    r7,r9,VCPU_SLB
1188        li      r5,0
11891:      slbmfee r8,r6
1190        andis.  r0,r8,SLB_ESID_V@h
1191        beq     2f
1192        add     r8,r8,r6                /* put index in */
1193        slbmfev r3,r6
1194        std     r8,VCPU_SLB_E(r7)
1195        std     r3,VCPU_SLB_V(r7)
1196        addi    r7,r7,VCPU_SLB_SIZE
1197        addi    r5,r5,1
11982:      addi    r6,r6,1
1199        bdnz    1b
1200        stw     r5,VCPU_SLB_MAX(r9)
1201
1202        /*
1203         * Save the guest PURR/SPURR
1204         */
1205BEGIN_FTR_SECTION
1206        mfspr   r5,SPRN_PURR
1207        mfspr   r6,SPRN_SPURR
1208        ld      r7,VCPU_PURR(r9)
1209        ld      r8,VCPU_SPURR(r9)
1210        std     r5,VCPU_PURR(r9)
1211        std     r6,VCPU_SPURR(r9)
1212        subf    r5,r7,r5
1213        subf    r6,r8,r6
1214
1215        /*
1216         * Restore host PURR/SPURR and add guest times
1217         * so that the time in the guest gets accounted.
1218         */
1219        ld      r3,HSTATE_PURR(r13)
1220        ld      r4,HSTATE_SPURR(r13)
1221        add     r3,r3,r5
1222        add     r4,r4,r6
1223        mtspr   SPRN_PURR,r3
1224        mtspr   SPRN_SPURR,r4
1225END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_201)
1226
1227        /* Save DEC */
1228        mfspr   r5,SPRN_DEC
1229        mftb    r6
1230        extsw   r5,r5
1231        add     r5,r5,r6
1232        /* r5 is a guest timebase value here, convert to host TB */
1233        ld      r3,HSTATE_KVM_VCORE(r13)
1234        ld      r4,VCORE_TB_OFFSET(r3)
1235        subf    r5,r4,r5
1236        std     r5,VCPU_DEC_EXPIRES(r9)
1237
1238BEGIN_FTR_SECTION
1239        b       8f
1240END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1241        /* Save POWER8-specific registers */
1242        mfspr   r5, SPRN_IAMR
1243        mfspr   r6, SPRN_PSPB
1244        mfspr   r7, SPRN_FSCR
1245        std     r5, VCPU_IAMR(r9)
1246        stw     r6, VCPU_PSPB(r9)
1247        std     r7, VCPU_FSCR(r9)
1248        mfspr   r5, SPRN_IC
1249        mfspr   r6, SPRN_VTB
1250        mfspr   r7, SPRN_TAR
1251        std     r5, VCPU_IC(r9)
1252        std     r6, VCPU_VTB(r9)
1253        std     r7, VCPU_TAR(r9)
1254        mfspr   r8, SPRN_EBBHR
1255        std     r8, VCPU_EBBHR(r9)
1256        mfspr   r5, SPRN_EBBRR
1257        mfspr   r6, SPRN_BESCR
1258        mfspr   r7, SPRN_CSIGR
1259        mfspr   r8, SPRN_TACR
1260        std     r5, VCPU_EBBRR(r9)
1261        std     r6, VCPU_BESCR(r9)
1262        std     r7, VCPU_CSIGR(r9)
1263        std     r8, VCPU_TACR(r9)
1264        mfspr   r5, SPRN_TCSCR
1265        mfspr   r6, SPRN_ACOP
1266        mfspr   r7, SPRN_PID
1267        mfspr   r8, SPRN_WORT
1268        std     r5, VCPU_TCSCR(r9)
1269        std     r6, VCPU_ACOP(r9)
1270        stw     r7, VCPU_GUEST_PID(r9)
1271        std     r8, VCPU_WORT(r9)
12728:
1273
1274        /* Save and reset AMR and UAMOR before turning on the MMU */
1275BEGIN_FTR_SECTION
1276        mfspr   r5,SPRN_AMR
1277        mfspr   r6,SPRN_UAMOR
1278        std     r5,VCPU_AMR(r9)
1279        std     r6,VCPU_UAMOR(r9)
1280        li      r6,0
1281        mtspr   SPRN_AMR,r6
1282END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1283
1284        /* Switch DSCR back to host value */
1285BEGIN_FTR_SECTION
1286        mfspr   r8, SPRN_DSCR
1287        ld      r7, HSTATE_DSCR(r13)
1288        std     r8, VCPU_DSCR(r9)
1289        mtspr   SPRN_DSCR, r7
1290END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1291
1292        /* Save non-volatile GPRs */
1293        std     r14, VCPU_GPR(R14)(r9)
1294        std     r15, VCPU_GPR(R15)(r9)
1295        std     r16, VCPU_GPR(R16)(r9)
1296        std     r17, VCPU_GPR(R17)(r9)
1297        std     r18, VCPU_GPR(R18)(r9)
1298        std     r19, VCPU_GPR(R19)(r9)
1299        std     r20, VCPU_GPR(R20)(r9)
1300        std     r21, VCPU_GPR(R21)(r9)
1301        std     r22, VCPU_GPR(R22)(r9)
1302        std     r23, VCPU_GPR(R23)(r9)
1303        std     r24, VCPU_GPR(R24)(r9)
1304        std     r25, VCPU_GPR(R25)(r9)
1305        std     r26, VCPU_GPR(R26)(r9)
1306        std     r27, VCPU_GPR(R27)(r9)
1307        std     r28, VCPU_GPR(R28)(r9)
1308        std     r29, VCPU_GPR(R29)(r9)
1309        std     r30, VCPU_GPR(R30)(r9)
1310        std     r31, VCPU_GPR(R31)(r9)
1311
1312        /* Save SPRGs */
1313        mfspr   r3, SPRN_SPRG0
1314        mfspr   r4, SPRN_SPRG1
1315        mfspr   r5, SPRN_SPRG2
1316        mfspr   r6, SPRN_SPRG3
1317        std     r3, VCPU_SPRG0(r9)
1318        std     r4, VCPU_SPRG1(r9)
1319        std     r5, VCPU_SPRG2(r9)
1320        std     r6, VCPU_SPRG3(r9)
1321
1322        /* save FP state */
1323        mr      r3, r9
1324        bl      kvmppc_save_fp
1325
1326#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1327BEGIN_FTR_SECTION
1328        b       2f
1329END_FTR_SECTION_IFCLR(CPU_FTR_TM)
1330        /* Turn on TM. */
1331        mfmsr   r8
1332        li      r0, 1
1333        rldimi  r8, r0, MSR_TM_LG, 63-MSR_TM_LG
1334        mtmsrd  r8
1335
1336        ld      r5, VCPU_MSR(r9)
1337        rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
1338        beq     1f      /* TM not active in guest. */
1339
1340        li      r3, TM_CAUSE_KVM_RESCHED
1341
1342        /* Clear the MSR RI since r1, r13 are all going to be foobar. */
1343        li      r5, 0
1344        mtmsrd  r5, 1
1345
1346        /* All GPRs are volatile at this point. */
1347        TRECLAIM(R3)
1348
1349        /* Temporarily store r13 and r9 so we have some regs to play with */
1350        SET_SCRATCH0(r13)
1351        GET_PACA(r13)
1352        std     r9, PACATMSCRATCH(r13)
1353        ld      r9, HSTATE_KVM_VCPU(r13)
1354
1355        /* Get a few more GPRs free. */
1356        std     r29, VCPU_GPRS_TM(29)(r9)
1357        std     r30, VCPU_GPRS_TM(30)(r9)
1358        std     r31, VCPU_GPRS_TM(31)(r9)
1359
1360        /* Save away PPR and DSCR soon so don't run with user values. */
1361        mfspr   r31, SPRN_PPR
1362        HMT_MEDIUM
1363        mfspr   r30, SPRN_DSCR
1364        ld      r29, HSTATE_DSCR(r13)
1365        mtspr   SPRN_DSCR, r29
1366
1367        /* Save all but r9, r13 & r29-r31 */
1368        reg = 0
1369        .rept   29
1370        .if (reg != 9) && (reg != 13)
1371        std     reg, VCPU_GPRS_TM(reg)(r9)
1372        .endif
1373        reg = reg + 1
1374        .endr
1375        /* ... now save r13 */
1376        GET_SCRATCH0(r4)
1377        std     r4, VCPU_GPRS_TM(13)(r9)
1378        /* ... and save r9 */
1379        ld      r4, PACATMSCRATCH(r13)
1380        std     r4, VCPU_GPRS_TM(9)(r9)
1381
1382        /* Reload stack pointer and TOC. */
1383        ld      r1, HSTATE_HOST_R1(r13)
1384        ld      r2, PACATOC(r13)
1385
1386        /* Set MSR RI now we have r1 and r13 back. */
1387        li      r5, MSR_RI
1388        mtmsrd  r5, 1
1389
1390        /* Save away checkpinted SPRs. */
1391        std     r31, VCPU_PPR_TM(r9)
1392        std     r30, VCPU_DSCR_TM(r9)
1393        mflr    r5
1394        mfcr    r6
1395        mfctr   r7
1396        mfspr   r8, SPRN_AMR
1397        mfspr   r10, SPRN_TAR
1398        std     r5, VCPU_LR_TM(r9)
1399        stw     r6, VCPU_CR_TM(r9)
1400        std     r7, VCPU_CTR_TM(r9)
1401        std     r8, VCPU_AMR_TM(r9)
1402        std     r10, VCPU_TAR_TM(r9)
1403
1404        /* Restore r12 as trap number. */
1405        lwz     r12, VCPU_TRAP(r9)
1406
1407        /* Save FP/VSX. */
1408        addi    r3, r9, VCPU_FPRS_TM
1409        bl      .store_fp_state
1410        addi    r3, r9, VCPU_VRS_TM
1411        bl      .store_vr_state
1412        mfspr   r6, SPRN_VRSAVE
1413        stw     r6, VCPU_VRSAVE_TM(r9)
14141:
1415        /*
1416         * We need to save these SPRs after the treclaim so that the software
1417         * error code is recorded correctly in the TEXASR.  Also the user may
1418         * change these outside of a transaction, so they must always be
1419         * context switched.
1420         */
1421        mfspr   r5, SPRN_TFHAR
1422        mfspr   r6, SPRN_TFIAR
1423        mfspr   r7, SPRN_TEXASR
1424        std     r5, VCPU_TFHAR(r9)
1425        std     r6, VCPU_TFIAR(r9)
1426        std     r7, VCPU_TEXASR(r9)
14272:
1428#endif
1429
1430        /* Increment yield count if they have a VPA */
1431        ld      r8, VCPU_VPA(r9)        /* do they have a VPA? */
1432        cmpdi   r8, 0
1433        beq     25f
1434        lwz     r3, LPPACA_YIELDCOUNT(r8)
1435        addi    r3, r3, 1
1436        stw     r3, LPPACA_YIELDCOUNT(r8)
1437        li      r3, 1
1438        stb     r3, VCPU_VPA_DIRTY(r9)
143925:
1440        /* Save PMU registers if requested */
1441        /* r8 and cr0.eq are live here */
1442        li      r3, 1
1443        sldi    r3, r3, 31              /* MMCR0_FC (freeze counters) bit */
1444        mfspr   r4, SPRN_MMCR0          /* save MMCR0 */
1445        mtspr   SPRN_MMCR0, r3          /* freeze all counters, disable ints */
1446        mfspr   r6, SPRN_MMCRA
1447BEGIN_FTR_SECTION
1448        /* On P7, clear MMCRA in order to disable SDAR updates */
1449        li      r7, 0
1450        mtspr   SPRN_MMCRA, r7
1451END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1452        isync
1453        beq     21f                     /* if no VPA, save PMU stuff anyway */
1454        lbz     r7, LPPACA_PMCINUSE(r8)
1455        cmpwi   r7, 0                   /* did they ask for PMU stuff to be saved? */
1456        bne     21f
1457        std     r3, VCPU_MMCR(r9)       /* if not, set saved MMCR0 to FC */
1458        b       22f
145921:     mfspr   r5, SPRN_MMCR1
1460        mfspr   r7, SPRN_SIAR
1461        mfspr   r8, SPRN_SDAR
1462        std     r4, VCPU_MMCR(r9)
1463        std     r5, VCPU_MMCR + 8(r9)
1464        std     r6, VCPU_MMCR + 16(r9)
1465        std     r7, VCPU_SIAR(r9)
1466        std     r8, VCPU_SDAR(r9)
1467        mfspr   r3, SPRN_PMC1
1468        mfspr   r4, SPRN_PMC2
1469        mfspr   r5, SPRN_PMC3
1470        mfspr   r6, SPRN_PMC4
1471        mfspr   r7, SPRN_PMC5
1472        mfspr   r8, SPRN_PMC6
1473BEGIN_FTR_SECTION
1474        mfspr   r10, SPRN_PMC7
1475        mfspr   r11, SPRN_PMC8
1476END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1477        stw     r3, VCPU_PMC(r9)
1478        stw     r4, VCPU_PMC + 4(r9)
1479        stw     r5, VCPU_PMC + 8(r9)
1480        stw     r6, VCPU_PMC + 12(r9)
1481        stw     r7, VCPU_PMC + 16(r9)
1482        stw     r8, VCPU_PMC + 20(r9)
1483BEGIN_FTR_SECTION
1484        stw     r10, VCPU_PMC + 24(r9)
1485        stw     r11, VCPU_PMC + 28(r9)
1486END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1487BEGIN_FTR_SECTION
1488        mfspr   r4, SPRN_MMCR2
1489        mfspr   r5, SPRN_SIER
1490        mfspr   r6, SPRN_SPMC1
1491        mfspr   r7, SPRN_SPMC2
1492        mfspr   r8, SPRN_MMCRS
1493        std     r4, VCPU_MMCR + 24(r9)
1494        std     r5, VCPU_SIER(r9)
1495        stw     r6, VCPU_PMC + 24(r9)
1496        stw     r7, VCPU_PMC + 28(r9)
1497        std     r8, VCPU_MMCR + 32(r9)
1498        lis     r4, 0x8000
1499        mtspr   SPRN_MMCRS, r4
1500END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
150122:
1502        /* Clear out SLB */
1503        li      r5,0
1504        slbmte  r5,r5
1505        slbia
1506        ptesync
1507
1508hdec_soon:                      /* r12 = trap, r13 = paca */
1509BEGIN_FTR_SECTION
1510        b       32f
1511END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1512        /*
1513         * POWER7 guest -> host partition switch code.
1514         * We don't have to lock against tlbies but we do
1515         * have to coordinate the hardware threads.
1516         */
1517        /* Increment the threads-exiting-guest count in the 0xff00
1518           bits of vcore->entry_exit_count */
1519        ld      r5,HSTATE_KVM_VCORE(r13)
1520        addi    r6,r5,VCORE_ENTRY_EXIT
152141:     lwarx   r3,0,r6
1522        addi    r0,r3,0x100
1523        stwcx.  r0,0,r6
1524        bne     41b
1525        isync           /* order stwcx. vs. reading napping_threads */
1526
1527        /*
1528         * At this point we have an interrupt that we have to pass
1529         * up to the kernel or qemu; we can't handle it in real mode.
1530         * Thus we have to do a partition switch, so we have to
1531         * collect the other threads, if we are the first thread
1532         * to take an interrupt.  To do this, we set the HDEC to 0,
1533         * which causes an HDEC interrupt in all threads within 2ns
1534         * because the HDEC register is shared between all 4 threads.
1535         * However, we don't need to bother if this is an HDEC
1536         * interrupt, since the other threads will already be on their
1537         * way here in that case.
1538         */
1539        cmpwi   r3,0x100        /* Are we the first here? */
1540        bge     43f
1541        cmpwi   r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1542        beq     40f
1543        li      r0,0
1544        mtspr   SPRN_HDEC,r0
154540:
1546        /*
1547         * Send an IPI to any napping threads, since an HDEC interrupt
1548         * doesn't wake CPUs up from nap.
1549         */
1550        lwz     r3,VCORE_NAPPING_THREADS(r5)
1551        lbz     r4,HSTATE_PTID(r13)
1552        li      r0,1
1553        sld     r0,r0,r4
1554        andc.   r3,r3,r0                /* no sense IPI'ing ourselves */
1555        beq     43f
1556        /* Order entry/exit update vs. IPIs */
1557        sync
1558        mulli   r4,r4,PACA_SIZE         /* get paca for thread 0 */
1559        subf    r6,r4,r13
156042:     andi.   r0,r3,1
1561        beq     44f
1562        ld      r8,HSTATE_XICS_PHYS(r6) /* get thread's XICS reg addr */
1563        li      r0,IPI_PRIORITY
1564        li      r7,XICS_MFRR
1565        stbcix  r0,r7,r8                /* trigger the IPI */
156644:     srdi.   r3,r3,1
1567        addi    r6,r6,PACA_SIZE
1568        bne     42b
1569
1570secondary_too_late:
1571        /* Secondary threads wait for primary to do partition switch */
157243:     ld      r5,HSTATE_KVM_VCORE(r13)
1573        ld      r4,VCORE_KVM(r5)        /* pointer to struct kvm */
1574        lbz     r3,HSTATE_PTID(r13)
1575        cmpwi   r3,0
1576        beq     15f
1577        HMT_LOW
157813:     lbz     r3,VCORE_IN_GUEST(r5)
1579        cmpwi   r3,0
1580        bne     13b
1581        HMT_MEDIUM
1582        b       16f
1583
1584        /* Primary thread waits for all the secondaries to exit guest */
158515:     lwz     r3,VCORE_ENTRY_EXIT(r5)
1586        srwi    r0,r3,8
1587        clrldi  r3,r3,56
1588        cmpw    r3,r0
1589        bne     15b
1590        isync
1591
1592        /* Primary thread switches back to host partition */
1593        ld      r6,KVM_HOST_SDR1(r4)
1594        lwz     r7,KVM_HOST_LPID(r4)
1595        li      r8,LPID_RSVD            /* switch to reserved LPID */
1596        mtspr   SPRN_LPID,r8
1597        ptesync
1598        mtspr   SPRN_SDR1,r6            /* switch to partition page table */
1599        mtspr   SPRN_LPID,r7
1600        isync
1601
1602BEGIN_FTR_SECTION
1603        /* DPDES is shared between threads */
1604        mfspr   r7, SPRN_DPDES
1605        std     r7, VCORE_DPDES(r5)
1606        /* clear DPDES so we don't get guest doorbells in the host */
1607        li      r8, 0
1608        mtspr   SPRN_DPDES, r8
1609END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1610
1611        /* Subtract timebase offset from timebase */
1612        ld      r8,VCORE_TB_OFFSET(r5)
1613        cmpdi   r8,0
1614        beq     17f
1615        mftb    r6                      /* current guest timebase */
1616        subf    r8,r8,r6
1617        mtspr   SPRN_TBU40,r8           /* update upper 40 bits */
1618        mftb    r7                      /* check if lower 24 bits overflowed */
1619        clrldi  r6,r6,40
1620        clrldi  r7,r7,40
1621        cmpld   r7,r6
1622        bge     17f
1623        addis   r8,r8,0x100             /* if so, increment upper 40 bits */
1624        mtspr   SPRN_TBU40,r8
1625
1626        /* Reset PCR */
162717:     ld      r0, VCORE_PCR(r5)
1628        cmpdi   r0, 0
1629        beq     18f
1630        li      r0, 0
1631        mtspr   SPRN_PCR, r0
163218:
1633        /* Signal secondary CPUs to continue */
1634        stb     r0,VCORE_IN_GUEST(r5)
1635        lis     r8,0x7fff               /* MAX_INT@h */
1636        mtspr   SPRN_HDEC,r8
1637
163816:     ld      r8,KVM_HOST_LPCR(r4)
1639        mtspr   SPRN_LPCR,r8
1640        isync
1641        b       33f
1642
1643        /*
1644         * PPC970 guest -> host partition switch code.
1645         * We have to lock against concurrent tlbies, and
1646         * we have to flush the whole TLB.
1647         */
164832:     ld      r5,HSTATE_KVM_VCORE(r13)
1649        ld      r4,VCORE_KVM(r5)        /* pointer to struct kvm */
1650
1651        /* Take the guest's tlbie_lock */
1652#ifdef __BIG_ENDIAN__
1653        lwz     r8,PACA_LOCK_TOKEN(r13)
1654#else
1655        lwz     r8,PACAPACAINDEX(r13)
1656#endif
1657        addi    r3,r4,KVM_TLBIE_LOCK
165824:     lwarx   r0,0,r3
1659        cmpwi   r0,0
1660        bne     24b
1661        stwcx.  r8,0,r3
1662        bne     24b
1663        isync
1664
1665        ld      r7,KVM_HOST_LPCR(r4)    /* use kvm->arch.host_lpcr for HID4 */
1666        li      r0,0x18f
1667        rotldi  r0,r0,HID4_LPID5_SH     /* all lpid bits in HID4 = 1 */
1668        or      r0,r7,r0
1669        ptesync
1670        sync
1671        mtspr   SPRN_HID4,r0            /* switch to reserved LPID */
1672        isync
1673        li      r0,0
1674        stw     r0,0(r3)                /* drop guest tlbie_lock */
1675
1676        /* invalidate the whole TLB */
1677        li      r0,256
1678        mtctr   r0
1679        li      r6,0
168025:     tlbiel  r6
1681        addi    r6,r6,0x1000
1682        bdnz    25b
1683        ptesync
1684
1685        /* take native_tlbie_lock */
1686        ld      r3,toc_tlbie_lock@toc(2)
168724:     lwarx   r0,0,r3
1688        cmpwi   r0,0
1689        bne     24b
1690        stwcx.  r8,0,r3
1691        bne     24b
1692        isync
1693
1694        ld      r6,KVM_HOST_SDR1(r4)
1695        mtspr   SPRN_SDR1,r6            /* switch to host page table */
1696
1697        /* Set up host HID4 value */
1698        sync
1699        mtspr   SPRN_HID4,r7
1700        isync
1701        li      r0,0
1702        stw     r0,0(r3)                /* drop native_tlbie_lock */
1703
1704        lis     r8,0x7fff               /* MAX_INT@h */
1705        mtspr   SPRN_HDEC,r8
1706
1707        /* Disable HDEC interrupts */
1708        mfspr   r0,SPRN_HID0
1709        li      r3,0
1710        rldimi  r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
1711        sync
1712        mtspr   SPRN_HID0,r0
1713        mfspr   r0,SPRN_HID0
1714        mfspr   r0,SPRN_HID0
1715        mfspr   r0,SPRN_HID0
1716        mfspr   r0,SPRN_HID0
1717        mfspr   r0,SPRN_HID0
1718        mfspr   r0,SPRN_HID0
1719
1720        /* load host SLB entries */
172133:     ld      r8,PACA_SLBSHADOWPTR(r13)
1722
1723        .rept   SLB_NUM_BOLTED
1724        ld      r5,SLBSHADOW_SAVEAREA(r8)
1725        ld      r6,SLBSHADOW_SAVEAREA+8(r8)
1726        andis.  r7,r5,SLB_ESID_V@h
1727        beq     1f
1728        slbmte  r6,r5
17291:      addi    r8,r8,16
1730        .endr
1731
1732        /* Unset guest mode */
1733        li      r0, KVM_GUEST_MODE_NONE
1734        stb     r0, HSTATE_IN_GUEST(r13)
1735
1736        ld      r0, 112+PPC_LR_STKOFF(r1)
1737        addi    r1, r1, 112
1738        mtlr    r0
1739        blr
1740
1741/*
1742 * Check whether an HDSI is an HPTE not found fault or something else.
1743 * If it is an HPTE not found fault that is due to the guest accessing
1744 * a page that they have mapped but which we have paged out, then
1745 * we continue on with the guest exit path.  In all other cases,
1746 * reflect the HDSI to the guest as a DSI.
1747 */
1748kvmppc_hdsi:
1749        mfspr   r4, SPRN_HDAR
1750        mfspr   r6, SPRN_HDSISR
1751        /* HPTE not found fault or protection fault? */
1752        andis.  r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
1753        beq     1f                      /* if not, send it to the guest */
1754        andi.   r0, r11, MSR_DR         /* data relocation enabled? */
1755        beq     3f
1756        clrrdi  r0, r4, 28
1757        PPC_SLBFEE_DOT(R5, R0)          /* if so, look up SLB */
1758        bne     1f                      /* if no SLB entry found */
17594:      std     r4, VCPU_FAULT_DAR(r9)
1760        stw     r6, VCPU_FAULT_DSISR(r9)
1761
1762        /* Search the hash table. */
1763        mr      r3, r9                  /* vcpu pointer */
1764        li      r7, 1                   /* data fault */
1765        bl      .kvmppc_hpte_hv_fault
1766        ld      r9, HSTATE_KVM_VCPU(r13)
1767        ld      r10, VCPU_PC(r9)
1768        ld      r11, VCPU_MSR(r9)
1769        li      r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1770        cmpdi   r3, 0                   /* retry the instruction */
1771        beq     6f
1772        cmpdi   r3, -1                  /* handle in kernel mode */
1773        beq     guest_exit_cont
1774        cmpdi   r3, -2                  /* MMIO emulation; need instr word */
1775        beq     2f
1776
1777        /* Synthesize a DSI for the guest */
1778        ld      r4, VCPU_FAULT_DAR(r9)
1779        mr      r6, r3
17801:      mtspr   SPRN_DAR, r4
1781        mtspr   SPRN_DSISR, r6
1782        mtspr   SPRN_SRR0, r10
1783        mtspr   SPRN_SRR1, r11
1784        li      r10, BOOK3S_INTERRUPT_DATA_STORAGE
1785        bl      kvmppc_msr_interrupt
1786fast_interrupt_c_return:
17876:      ld      r7, VCPU_CTR(r9)
1788        lwz     r8, VCPU_XER(r9)
1789        mtctr   r7
1790        mtxer   r8
1791        mr      r4, r9
1792        b       fast_guest_return
1793
17943:      ld      r5, VCPU_KVM(r9)        /* not relocated, use VRMA */
1795        ld      r5, KVM_VRMA_SLB_V(r5)
1796        b       4b
1797
1798        /* If this is for emulated MMIO, load the instruction word */
17992:      li      r8, KVM_INST_FETCH_FAILED       /* In case lwz faults */
1800
1801        /* Set guest mode to 'jump over instruction' so if lwz faults
1802         * we'll just continue at the next IP. */
1803        li      r0, KVM_GUEST_MODE_SKIP
1804        stb     r0, HSTATE_IN_GUEST(r13)
1805
1806        /* Do the access with MSR:DR enabled */
1807        mfmsr   r3
1808        ori     r4, r3, MSR_DR          /* Enable paging for data */
1809        mtmsrd  r4
1810        lwz     r8, 0(r10)
1811        mtmsrd  r3
1812
1813        /* Store the result */
1814        stw     r8, VCPU_LAST_INST(r9)
1815
1816        /* Unset guest mode. */
1817        li      r0, KVM_GUEST_MODE_HOST_HV
1818        stb     r0, HSTATE_IN_GUEST(r13)
1819        b       guest_exit_cont
1820
1821/*
1822 * Similarly for an HISI, reflect it to the guest as an ISI unless
1823 * it is an HPTE not found fault for a page that we have paged out.
1824 */
1825kvmppc_hisi:
1826        andis.  r0, r11, SRR1_ISI_NOPT@h
1827        beq     1f
1828        andi.   r0, r11, MSR_IR         /* instruction relocation enabled? */
1829        beq     3f
1830        clrrdi  r0, r10, 28
1831        PPC_SLBFEE_DOT(R5, R0)          /* if so, look up SLB */
1832        bne     1f                      /* if no SLB entry found */
18334:
1834        /* Search the hash table. */
1835        mr      r3, r9                  /* vcpu pointer */
1836        mr      r4, r10
1837        mr      r6, r11
1838        li      r7, 0                   /* instruction fault */
1839        bl      .kvmppc_hpte_hv_fault
1840        ld      r9, HSTATE_KVM_VCPU(r13)
1841        ld      r10, VCPU_PC(r9)
1842        ld      r11, VCPU_MSR(r9)
1843        li      r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1844        cmpdi   r3, 0                   /* retry the instruction */
1845        beq     fast_interrupt_c_return
1846        cmpdi   r3, -1                  /* handle in kernel mode */
1847        beq     guest_exit_cont
1848
1849        /* Synthesize an ISI for the guest */
1850        mr      r11, r3
18511:      mtspr   SPRN_SRR0, r10
1852        mtspr   SPRN_SRR1, r11
1853        li      r10, BOOK3S_INTERRUPT_INST_STORAGE
1854        bl      kvmppc_msr_interrupt
1855        b       fast_interrupt_c_return
1856
18573:      ld      r6, VCPU_KVM(r9)        /* not relocated, use VRMA */
1858        ld      r5, KVM_VRMA_SLB_V(r6)
1859        b       4b
1860
1861/*
1862 * Try to handle an hcall in real mode.
1863 * Returns to the guest if we handle it, or continues on up to
1864 * the kernel if we can't (i.e. if we don't have a handler for
1865 * it, or if the handler returns H_TOO_HARD).
1866 */
1867        .globl  hcall_try_real_mode
1868hcall_try_real_mode:
1869        ld      r3,VCPU_GPR(R3)(r9)
1870        andi.   r0,r11,MSR_PR
1871        /* sc 1 from userspace - reflect to guest syscall */
1872        bne     sc_1_fast_return
1873        clrrdi  r3,r3,2
1874        cmpldi  r3,hcall_real_table_end - hcall_real_table
1875        bge     guest_exit_cont
1876        LOAD_REG_ADDR(r4, hcall_real_table)
1877        lwax    r3,r3,r4
1878        cmpwi   r3,0
1879        beq     guest_exit_cont
1880        add     r3,r3,r4
1881        mtctr   r3
1882        mr      r3,r9           /* get vcpu pointer */
1883        ld      r4,VCPU_GPR(R4)(r9)
1884        bctrl
1885        cmpdi   r3,H_TOO_HARD
1886        beq     hcall_real_fallback
1887        ld      r4,HSTATE_KVM_VCPU(r13)
1888        std     r3,VCPU_GPR(R3)(r4)
1889        ld      r10,VCPU_PC(r4)
1890        ld      r11,VCPU_MSR(r4)
1891        b       fast_guest_return
1892
1893sc_1_fast_return:
1894        mtspr   SPRN_SRR0,r10
1895        mtspr   SPRN_SRR1,r11
1896        li      r10, BOOK3S_INTERRUPT_SYSCALL
1897        bl      kvmppc_msr_interrupt
1898        mr      r4,r9
1899        b       fast_guest_return
1900
1901        /* We've attempted a real mode hcall, but it's punted it back
1902         * to userspace.  We need to restore some clobbered volatiles
1903         * before resuming the pass-it-to-qemu path */
1904hcall_real_fallback:
1905        li      r12,BOOK3S_INTERRUPT_SYSCALL
1906        ld      r9, HSTATE_KVM_VCPU(r13)
1907
1908        b       guest_exit_cont
1909
1910        .globl  hcall_real_table
1911hcall_real_table:
1912        .long   0               /* 0 - unused */
1913        .long   .kvmppc_h_remove - hcall_real_table
1914        .long   .kvmppc_h_enter - hcall_real_table
1915        .long   .kvmppc_h_read - hcall_real_table
1916        .long   0               /* 0x10 - H_CLEAR_MOD */
1917        .long   0               /* 0x14 - H_CLEAR_REF */
1918        .long   .kvmppc_h_protect - hcall_real_table
1919        .long   .kvmppc_h_get_tce - hcall_real_table
1920        .long   .kvmppc_h_put_tce - hcall_real_table
1921        .long   0               /* 0x24 - H_SET_SPRG0 */
1922        .long   .kvmppc_h_set_dabr - hcall_real_table
1923        .long   0               /* 0x2c */
1924        .long   0               /* 0x30 */
1925        .long   0               /* 0x34 */
1926        .long   0               /* 0x38 */
1927        .long   0               /* 0x3c */
1928        .long   0               /* 0x40 */
1929        .long   0               /* 0x44 */
1930        .long   0               /* 0x48 */
1931        .long   0               /* 0x4c */
1932        .long   0               /* 0x50 */
1933        .long   0               /* 0x54 */
1934        .long   0               /* 0x58 */
1935        .long   0               /* 0x5c */
1936        .long   0               /* 0x60 */
1937#ifdef CONFIG_KVM_XICS
1938        .long   .kvmppc_rm_h_eoi - hcall_real_table
1939        .long   .kvmppc_rm_h_cppr - hcall_real_table
1940        .long   .kvmppc_rm_h_ipi - hcall_real_table
1941        .long   0               /* 0x70 - H_IPOLL */
1942        .long   .kvmppc_rm_h_xirr - hcall_real_table
1943#else
1944        .long   0               /* 0x64 - H_EOI */
1945        .long   0               /* 0x68 - H_CPPR */
1946        .long   0               /* 0x6c - H_IPI */
1947        .long   0               /* 0x70 - H_IPOLL */
1948        .long   0               /* 0x74 - H_XIRR */
1949#endif
1950        .long   0               /* 0x78 */
1951        .long   0               /* 0x7c */
1952        .long   0               /* 0x80 */
1953        .long   0               /* 0x84 */
1954        .long   0               /* 0x88 */
1955        .long   0               /* 0x8c */
1956        .long   0               /* 0x90 */
1957        .long   0               /* 0x94 */
1958        .long   0               /* 0x98 */
1959        .long   0               /* 0x9c */
1960        .long   0               /* 0xa0 */
1961        .long   0               /* 0xa4 */
1962        .long   0               /* 0xa8 */
1963        .long   0               /* 0xac */
1964        .long   0               /* 0xb0 */
1965        .long   0               /* 0xb4 */
1966        .long   0               /* 0xb8 */
1967        .long   0               /* 0xbc */
1968        .long   0               /* 0xc0 */
1969        .long   0               /* 0xc4 */
1970        .long   0               /* 0xc8 */
1971        .long   0               /* 0xcc */
1972        .long   0               /* 0xd0 */
1973        .long   0               /* 0xd4 */
1974        .long   0               /* 0xd8 */
1975        .long   0               /* 0xdc */
1976        .long   .kvmppc_h_cede - hcall_real_table
1977        .long   0               /* 0xe4 */
1978        .long   0               /* 0xe8 */
1979        .long   0               /* 0xec */
1980        .long   0               /* 0xf0 */
1981        .long   0               /* 0xf4 */
1982        .long   0               /* 0xf8 */
1983        .long   0               /* 0xfc */
1984        .long   0               /* 0x100 */
1985        .long   0               /* 0x104 */
1986        .long   0               /* 0x108 */
1987        .long   0               /* 0x10c */
1988        .long   0               /* 0x110 */
1989        .long   0               /* 0x114 */
1990        .long   0               /* 0x118 */
1991        .long   0               /* 0x11c */
1992        .long   0               /* 0x120 */
1993        .long   .kvmppc_h_bulk_remove - hcall_real_table
1994        .long   0               /* 0x128 */
1995        .long   0               /* 0x12c */
1996        .long   0               /* 0x130 */
1997        .long   .kvmppc_h_set_xdabr - hcall_real_table
1998hcall_real_table_end:
1999
2000ignore_hdec:

2001        mr      r4,r9
2002        b       fast_guest_return
2003
2004_GLOBAL(kvmppc_h_set_xdabr)
2005        andi.   r0, r5, DABRX_USER | DABRX_KERNEL
2006        beq     6f
2007        li      r0, DABRX_USER | DABRX_KERNEL | DABRX_BTI
2008        andc.   r0, r5, r0
2009        beq     3f
20106:      li      r3, H_PARAMETER
2011        blr
2012
2013_GLOBAL(kvmppc_h_set_dabr)
2014        li      r5, DABRX_USER | DABRX_KERNEL
20153:
2016BEGIN_FTR_SECTION
2017        b       2f
2018END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2019        std     r4,VCPU_DABR(r3)
2020        stw     r5, VCPU_DABRX(r3)
2021        mtspr   SPRN_DABRX, r5
2022        /* Work around P7 bug where DABR can get corrupted on mtspr */
20231:      mtspr   SPRN_DABR,r4
2024        mfspr   r5, SPRN_DABR
2025        cmpd    r4, r5
2026        bne     1b
2027        isync
2028        li      r3,0
2029        blr
2030
2031        /* Emulate H_SET_DABR/X on P8 for the sake of compat mode guests */
20322:      rlwimi  r5, r4, 5, DAWRX_DR | DAWRX_DW
2033        rlwimi  r5, r4, 1, DAWRX_WT
2034        clrrdi  r4, r4, 3
2035        std     r4, VCPU_DAWR(r3)
2036        std     r5, VCPU_DAWRX(r3)
2037        mtspr   SPRN_DAWR, r4
2038        mtspr   SPRN_DAWRX, r5
2039        li      r3, 0
2040        blr
2041
2042_GLOBAL(kvmppc_h_cede)
2043        ori     r11,r11,MSR_EE
2044        std     r11,VCPU_MSR(r3)
2045        li      r0,1
2046        stb     r0,VCPU_CEDED(r3)
2047        sync                    /* order setting ceded vs. testing prodded */
2048        lbz     r5,VCPU_PRODDED(r3)
2049        cmpwi   r5,0
2050        bne     kvm_cede_prodded
2051        li      r0,0            /* set trap to 0 to say hcall is handled */
2052        stw     r0,VCPU_TRAP(r3)
2053        li      r0,H_SUCCESS
2054        std     r0,VCPU_GPR(R3)(r3)
2055BEGIN_FTR_SECTION
2056        b       kvm_cede_exit   /* just send it up to host on 970 */
2057END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
2058
2059        /*
2060         * Set our bit in the bitmask of napping threads unless all the
2061         * other threads are already napping, in which case we send this
2062         * up to the host.
2063         */
2064        ld      r5,HSTATE_KVM_VCORE(r13)
2065        lbz     r6,HSTATE_PTID(r13)
2066        lwz     r8,VCORE_ENTRY_EXIT(r5)
2067        clrldi  r8,r8,56
2068        li      r0,1
2069        sld     r0,r0,r6
2070        addi    r6,r5,VCORE_NAPPING_THREADS
207131:     lwarx   r4,0,r6
2072        or      r4,r4,r0
2073        PPC_POPCNTW(R7,R4)
2074        cmpw    r7,r8
2075        bge     kvm_cede_exit
2076        stwcx.  r4,0,r6
2077        bne     31b
2078        /* order napping_threads update vs testing entry_exit_count */
2079        isync
2080        li      r0,NAPPING_CEDE
2081        stb     r0,HSTATE_NAPPING(r13)
2082        lwz     r7,VCORE_ENTRY_EXIT(r5)
2083        cmpwi   r7,0x100
2084        bge     33f             /* another thread already exiting */
2085
2086/*
2087 * Although not specifically required by the architecture, POWER7
2088 * preserves the following registers in nap mode, even if an SMT mode
2089 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
2090 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
2091 */
2092        /* Save non-volatile GPRs */
2093        std     r14, VCPU_GPR(R14)(r3)
2094        std     r15, VCPU_GPR(R15)(r3)
2095        std     r16, VCPU_GPR(R16)(r3)
2096        std     r17, VCPU_GPR(R17)(r3)
2097        std     r18, VCPU_GPR(R18)(r3)
2098        std     r19, VCPU_GPR(R19)(r3)
2099        std     r20, VCPU_GPR(R20)(r3)
2100        std     r21, VCPU_GPR(R21)(r3)
2101        std     r22, VCPU_GPR(R22)(r3)
2102        std     r23, VCPU_GPR(R23)(r3)
2103        std     r24, VCPU_GPR(R24)(r3)
2104        std     r25, VCPU_GPR(R25)(r3)
2105        std     r26, VCPU_GPR(R26)(r3)
2106        std     r27, VCPU_GPR(R27)(r3)
2107        std     r28, VCPU_GPR(R28)(r3)
2108        std     r29, VCPU_GPR(R29)(r3)
2109        std     r30, VCPU_GPR(R30)(r3)
2110        std     r31, VCPU_GPR(R31)(r3)
2111
2112        /* save FP state */
2113        bl      kvmppc_save_fp
2114
2115        /*
2116         * Take a nap until a decrementer or external or doobell interrupt
2117         * occurs, with PECE1, PECE0 and PECEDP set in LPCR. Also clear the
2118         * runlatch bit before napping.
2119         */
2120        mfspr   r2, SPRN_CTRLF
2121        clrrdi  r2, r2, 1
2122        mtspr   SPRN_CTRLT, r2
2123
2124        li      r0,1
2125        stb     r0,HSTATE_HWTHREAD_REQ(r13)
2126        mfspr   r5,SPRN_LPCR
2127        ori     r5,r5,LPCR_PECE0 | LPCR_PECE1
2128BEGIN_FTR_SECTION
2129        oris    r5,r5,LPCR_PECEDP@h
2130END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2131        mtspr   SPRN_LPCR,r5
2132        isync
2133        li      r0, 0
2134        std     r0, HSTATE_SCRATCH0(r13)
2135        ptesync
2136        ld      r0, HSTATE_SCRATCH0(r13)
21371:      cmpd    r0, r0
2138        bne     1b
2139        nap
2140        b       .
2141
214233:     mr      r4, r3
2143        li      r3, 0
2144        li      r12, 0
2145        b       34f
2146
2147kvm_end_cede:
2148        /* get vcpu pointer */
2149        ld      r4, HSTATE_KVM_VCPU(r13)
2150
2151        /* Woken by external or decrementer interrupt */
2152        ld      r1, HSTATE_HOST_R1(r13)
2153
2154        /* load up FP state */
2155        bl      kvmppc_load_fp
2156
2157        /* Load NV GPRS */
2158        ld      r14, VCPU_GPR(R14)(r4)
2159        ld      r15, VCPU_GPR(R15)(r4)
2160        ld      r16, VCPU_GPR(R16)(r4)
2161        ld      r17, VCPU_GPR(R17)(r4)
2162        ld      r18, VCPU_GPR(R18)(r4)
2163        ld      r19, VCPU_GPR(R19)(r4)
2164        ld      r20, VCPU_GPR(R20)(r4)
2165        ld      r21, VCPU_GPR(R21)(r4)
2166        ld      r22, VCPU_GPR(R22)(r4)
2167        ld      r23, VCPU_GPR(R23)(r4)
2168        ld      r24, VCPU_GPR(R24)(r4)
2169        ld      r25, VCPU_GPR(R25)(r4)
2170        ld      r26, VCPU_GPR(R26)(r4)
2171        ld      r27, VCPU_GPR(R27)(r4)
2172        ld      r28, VCPU_GPR(R28)(r4)
2173        ld      r29, VCPU_GPR(R29)(r4)
2174        ld      r30, VCPU_GPR(R30)(r4)
2175        ld      r31, VCPU_GPR(R31)(r4)
2176 
2177        /* Check the wake reason in SRR1 to see why we got here */
2178        bl      kvmppc_check_wake_reason
2179
2180        /* clear our bit in vcore->napping_threads */
218134:     ld      r5,HSTATE_KVM_VCORE(r13)
2182        lbz     r7,HSTATE_PTID(r13)
2183        li      r0,1
2184        sld     r0,r0,r7
2185        addi    r6,r5,VCORE_NAPPING_THREADS
218632:     lwarx   r7,0,r6
2187        andc    r7,r7,r0
2188        stwcx.  r7,0,r6
2189        bne     32b
2190        li      r0,0
2191        stb     r0,HSTATE_NAPPING(r13)
2192
2193        /* See if the wake reason means we need to exit */
2194        stw     r12, VCPU_TRAP(r4)
2195        mr      r9, r4
2196        cmpdi   r3, 0
2197        bgt     guest_exit_cont
2198
2199        /* see if any other thread is already exiting */
2200        lwz     r0,VCORE_ENTRY_EXIT(r5)
2201        cmpwi   r0,0x100
2202        bge     guest_exit_cont
2203
2204        b       kvmppc_cede_reentry     /* if not go back to guest */
2205
2206        /* cede when already previously prodded case */
2207kvm_cede_prodded:
2208        li      r0,0
2209        stb     r0,VCPU_PRODDED(r3)
2210        sync                    /* order testing prodded vs. clearing ceded */
2211        stb     r0,VCPU_CEDED(r3)
2212        li      r3,H_SUCCESS
2213        blr
2214
2215        /* we've ceded but we want to give control to the host */
2216kvm_cede_exit:
2217        b       hcall_real_fallback
2218
2219        /* Try to handle a machine check in real mode */
2220machine_check_realmode:
2221        mr      r3, r9          /* get vcpu pointer */
2222        bl      .kvmppc_realmode_machine_check
2223        nop
2224        cmpdi   r3, 0           /* continue exiting from guest? */
2225        ld      r9, HSTATE_KVM_VCPU(r13)
2226        li      r12, BOOK3S_INTERRUPT_MACHINE_CHECK
2227        beq     mc_cont
2228        /* If not, deliver a machine check.  SRR0/1 are already set */
2229        li      r10, BOOK3S_INTERRUPT_MACHINE_CHECK
2230        bl      kvmppc_msr_interrupt
2231        b       fast_interrupt_c_return
2232
2233/*
2234 * Check the reason we woke from nap, and take appropriate action.
2235 * Returns:
2236 *      0 if nothing needs to be done
2237 *      1 if something happened that needs to be handled by the host
2238 *      -1 if there was a guest wakeup (IPI)
2239 *
2240 * Also sets r12 to the interrupt vector for any interrupt that needs
2241 * to be handled now by the host (0x500 for external interrupt), or zero.
2242 */
2243kvmppc_check_wake_reason:
2244        mfspr   r6, SPRN_SRR1
2245BEGIN_FTR_SECTION
2246        rlwinm  r6, r6, 45-31, 0xf      /* extract wake reason field (P8) */
2247FTR_SECTION_ELSE
2248        rlwinm  r6, r6, 45-31, 0xe      /* P7 wake reason field is 3 bits */
2249ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
2250        cmpwi   r6, 8                   /* was it an external interrupt? */
2251        li      r12, BOOK3S_INTERRUPT_EXTERNAL
2252        beq     kvmppc_read_intr        /* if so, see what it was */
2253        li      r3, 0
2254        li      r12, 0
2255        cmpwi   r6, 6                   /* was it the decrementer? */
2256        beq     0f
2257BEGIN_FTR_SECTION
2258        cmpwi   r6, 5                   /* privileged doorbell? */
2259        beq     0f
2260        cmpwi   r6, 3                   /* hypervisor doorbell? */
2261        beq     3f
2262END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2263        li      r3, 1                   /* anything else, return 1 */
22640:      blr
2265
2266        /* hypervisor doorbell */
22673:      li      r12, BOOK3S_INTERRUPT_H_DOORBELL
2268        li      r3, 1
2269        blr
2270
2271/*
2272 * Determine what sort of external interrupt is pending (if any).
2273 * Returns:
2274 *      0 if no interrupt is pending
2275 *      1 if an interrupt is pending that needs to be handled by the host
2276 *      -1 if there was a guest wakeup IPI (which has now been cleared)
2277 */
2278kvmppc_read_intr:
2279        /* see if a host IPI is pending */
2280        li      r3, 1
2281        lbz     r0, HSTATE_HOST_IPI(r13)
2282        cmpwi   r0, 0
2283        bne     1f
2284
2285        /* Now read the interrupt from the ICP */
2286        ld      r6, HSTATE_XICS_PHYS(r13)
2287        li      r7, XICS_XIRR
2288        cmpdi   r6, 0
2289        beq-    1f
2290        lwzcix  r0, r6, r7
2291        rlwinm. r3, r0, 0, 0xffffff
2292        sync
2293        beq     1f                      /* if nothing pending in the ICP */
2294
2295        /* We found something in the ICP...
2296         *
2297         * If it's not an IPI, stash it in the PACA and return to
2298         * the host, we don't (yet) handle directing real external
2299         * interrupts directly to the guest
2300         */
2301        cmpwi   r3, XICS_IPI            /* if there is, is it an IPI? */
2302        bne     42f
2303
2304        /* It's an IPI, clear the MFRR and EOI it */
2305        li      r3, 0xff
2306        li      r8, XICS_MFRR
2307        stbcix  r3, r6, r8              /* clear the IPI */
2308        stwcix  r0, r6, r7              /* EOI it */
2309        sync
2310
2311        /* We need to re-check host IPI now in case it got set in the
2312         * meantime. If it's clear, we bounce the interrupt to the
2313         * guest
2314         */
2315        lbz     r0, HSTATE_HOST_IPI(r13)
2316        cmpwi   r0, 0
2317        bne-    43f
2318
2319        /* OK, it's an IPI for us */
2320        li      r3, -1
23211:      blr
2322
232342:     /* It's not an IPI and it's for the host, stash it in the PACA
2324         * before exit, it will be picked up by the host ICP driver
2325         */
2326        stw     r0, HSTATE_SAVED_XIRR(r13)
2327        li      r3, 1
2328        b       1b
2329
233043:     /* We raced with the host, we need to resend that IPI, bummer */
2331        li      r0, IPI_PRIORITY
2332        stbcix  r0, r6, r8              /* set the IPI */
2333        sync
2334        li      r3, 1
2335        b       1b
2336
2337/*
2338 * Save away FP, VMX and VSX registers.
2339 * r3 = vcpu pointer
2340 * N.B. r30 and r31 are volatile across this function,
2341 * thus it is not callable from C.
2342 */
2343kvmppc_save_fp:
2344        mflr    r30
2345        mr      r31,r3
2346        mfmsr   r5
2347        ori     r8,r5,MSR_FP
2348#ifdef CONFIG_ALTIVEC
2349BEGIN_FTR_SECTION
2350        oris    r8,r8,MSR_VEC@h
2351END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2352#endif
2353#ifdef CONFIG_VSX
2354BEGIN_FTR_SECTION
2355        oris    r8,r8,MSR_VSX@h
2356END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2357#endif
2358        mtmsrd  r8
2359        isync
2360        addi    r3,r3,VCPU_FPRS
2361        bl      .store_fp_state
2362#ifdef CONFIG_ALTIVEC
2363BEGIN_FTR_SECTION
2364        addi    r3,r31,VCPU_VRS
2365        bl      .store_vr_state
2366END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2367#endif
2368        mfspr   r6,SPRN_VRSAVE
2369        stw     r6,VCPU_VRSAVE(r31)
2370        mtlr    r30
2371        blr
2372
2373/*
2374 * Load up FP, VMX and VSX registers
2375 * r4 = vcpu pointer
2376 * N.B. r30 and r31 are volatile across this function,
2377 * thus it is not callable from C.
2378 */
2379kvmppc_load_fp:
2380        mflr    r30
2381        mr      r31,r4
2382        mfmsr   r9
2383        ori     r8,r9,MSR_FP
2384#ifdef CONFIG_ALTIVEC
2385BEGIN_FTR_SECTION
2386        oris    r8,r8,MSR_VEC@h
2387END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2388#endif
2389#ifdef CONFIG_VSX
2390BEGIN_FTR_SECTION
2391        oris    r8,r8,MSR_VSX@h
2392END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2393#endif
2394        mtmsrd  r8
2395        isync
2396        addi    r3,r4,VCPU_FPRS
2397        bl      .load_fp_state
2398#ifdef CONFIG_ALTIVEC
2399BEGIN_FTR_SECTION
2400        addi    r3,r31,VCPU_VRS
2401        bl      .load_vr_state
2402END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2403#endif
2404        lwz     r7,VCPU_VRSAVE(r31)
2405        mtspr   SPRN_VRSAVE,r7
2406        mtlr    r30
2407        mr      r4,r31
2408        blr
2409
2410/*
2411 * We come here if we get any exception or interrupt while we are
2412 * executing host real mode code while in guest MMU context.
2413 * For now just spin, but we should do something better.
2414 */
2415kvmppc_bad_host_intr:
2416        b       .
2417
2418/*
2419 * This mimics the MSR transition on IRQ delivery.  The new guest MSR is taken
2420 * from VCPU_INTR_MSR and is modified based on the required TM state changes.
2421 *   r11 has the guest MSR value (in/out)
2422 *   r9 has a vcpu pointer (in)
2423 *   r0 is used as a scratch register
2424 */
2425kvmppc_msr_interrupt:
2426        rldicl  r0, r11, 64 - MSR_TS_S_LG, 62
2427        cmpwi   r0, 2 /* Check if we are in transactional state..  */
2428        ld      r11, VCPU_INTR_MSR(r9)
2429        bne     1f
2430        /* ... if transactional, change to suspended */
2431        li      r0, 1
24321:      rldimi  r11, r0, MSR_TS_S_LG, 63 - MSR_TS_T_LG
2433        blr
2434