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17#include <asm/pgtable.h>
18#include <asm/mmu.h>
19#include <asm/mmu_context.h>
20#include <asm/paca.h>
21#include <asm/cputable.h>
22#include <asm/cacheflush.h>
23#include <asm/smp.h>
24#include <linux/compiler.h>
25#include <asm/udbg.h>
26#include <asm/code-patching.h>
27
28
29extern void slb_allocate_realmode(unsigned long ea);
30extern void slb_allocate_user(unsigned long ea);
31
32static void slb_allocate(unsigned long ea)
33{
34
35
36
37 slb_allocate_realmode(ea);
38}
39
40#define slb_esid_mask(ssize) \
41 (((ssize) == MMU_SEGSIZE_256M)? ESID_MASK: ESID_MASK_1T)
42
43static inline unsigned long mk_esid_data(unsigned long ea, int ssize,
44 unsigned long slot)
45{
46 return (ea & slb_esid_mask(ssize)) | SLB_ESID_V | slot;
47}
48
49#define slb_vsid_shift(ssize) \
50 ((ssize) == MMU_SEGSIZE_256M? SLB_VSID_SHIFT: SLB_VSID_SHIFT_1T)
51
52static inline unsigned long mk_vsid_data(unsigned long ea, int ssize,
53 unsigned long flags)
54{
55 return (get_kernel_vsid(ea, ssize) << slb_vsid_shift(ssize)) | flags |
56 ((unsigned long) ssize << SLB_VSID_SSIZE_SHIFT);
57}
58
59static inline void slb_shadow_update(unsigned long ea, int ssize,
60 unsigned long flags,
61 unsigned long entry)
62{
63
64
65
66
67
68 get_slb_shadow()->save_area[entry].esid = 0;
69 get_slb_shadow()->save_area[entry].vsid =
70 cpu_to_be64(mk_vsid_data(ea, ssize, flags));
71 get_slb_shadow()->save_area[entry].esid =
72 cpu_to_be64(mk_esid_data(ea, ssize, entry));
73}
74
75static inline void slb_shadow_clear(unsigned long entry)
76{
77 get_slb_shadow()->save_area[entry].esid = 0;
78}
79
80static inline void create_shadowed_slbe(unsigned long ea, int ssize,
81 unsigned long flags,
82 unsigned long entry)
83{
84
85
86
87
88
89 slb_shadow_update(ea, ssize, flags, entry);
90
91 asm volatile("slbmte %0,%1" :
92 : "r" (mk_vsid_data(ea, ssize, flags)),
93 "r" (mk_esid_data(ea, ssize, entry))
94 : "memory" );
95}
96
97static void __slb_flush_and_rebolt(void)
98{
99
100
101 unsigned long linear_llp, vmalloc_llp, lflags, vflags;
102 unsigned long ksp_esid_data, ksp_vsid_data;
103
104 linear_llp = mmu_psize_defs[mmu_linear_psize].sllp;
105 vmalloc_llp = mmu_psize_defs[mmu_vmalloc_psize].sllp;
106 lflags = SLB_VSID_KERNEL | linear_llp;
107 vflags = SLB_VSID_KERNEL | vmalloc_llp;
108
109 ksp_esid_data = mk_esid_data(get_paca()->kstack, mmu_kernel_ssize, 2);
110 if ((ksp_esid_data & ~0xfffffffUL) <= PAGE_OFFSET) {
111 ksp_esid_data &= ~SLB_ESID_V;
112 ksp_vsid_data = 0;
113 slb_shadow_clear(2);
114 } else {
115
116 slb_shadow_update(get_paca()->kstack, mmu_kernel_ssize, lflags, 2);
117 ksp_vsid_data =
118 be64_to_cpu(get_slb_shadow()->save_area[2].vsid);
119 }
120
121
122
123 asm volatile("isync\n"
124 "slbia\n"
125
126 "slbmte %0,%1\n"
127
128 "slbmte %2,%3\n"
129 "isync"
130 :: "r"(mk_vsid_data(VMALLOC_START, mmu_kernel_ssize, vflags)),
131 "r"(mk_esid_data(VMALLOC_START, mmu_kernel_ssize, 1)),
132 "r"(ksp_vsid_data),
133 "r"(ksp_esid_data)
134 : "memory");
135}
136
137void slb_flush_and_rebolt(void)
138{
139
140 WARN_ON(!irqs_disabled());
141
142
143
144
145
146 hard_irq_disable();
147
148 __slb_flush_and_rebolt();
149 get_paca()->slb_cache_ptr = 0;
150}
151
152void slb_vmalloc_update(void)
153{
154 unsigned long vflags;
155
156 vflags = SLB_VSID_KERNEL | mmu_psize_defs[mmu_vmalloc_psize].sllp;
157 slb_shadow_update(VMALLOC_START, mmu_kernel_ssize, vflags, 1);
158 slb_flush_and_rebolt();
159}
160
161
162
163
164
165
166
167static inline int esids_match(unsigned long addr1, unsigned long addr2)
168{
169 int esid_1t_count;
170
171
172 if (!mmu_has_feature(MMU_FTR_1T_SEGMENT))
173 return (GET_ESID(addr1) == GET_ESID(addr2));
174
175 esid_1t_count = (((addr1 >> SID_SHIFT_1T) != 0) +
176 ((addr2 >> SID_SHIFT_1T) != 0));
177
178
179 if (esid_1t_count == 0)
180 return (GET_ESID(addr1) == GET_ESID(addr2));
181
182
183 if (esid_1t_count == 1)
184 return 0;
185
186
187 return (GET_ESID_1T(addr1) == GET_ESID_1T(addr2));
188}
189
190
191void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
192{
193 unsigned long offset;
194 unsigned long slbie_data = 0;
195 unsigned long pc = KSTK_EIP(tsk);
196 unsigned long stack = KSTK_ESP(tsk);
197 unsigned long exec_base;
198
199
200
201
202
203
204
205 hard_irq_disable();
206 offset = get_paca()->slb_cache_ptr;
207 if (!mmu_has_feature(MMU_FTR_NO_SLBIE_B) &&
208 offset <= SLB_CACHE_ENTRIES) {
209 int i;
210 asm volatile("isync" : : : "memory");
211 for (i = 0; i < offset; i++) {
212 slbie_data = (unsigned long)get_paca()->slb_cache[i]
213 << SID_SHIFT;
214 slbie_data |= user_segment_size(slbie_data)
215 << SLBIE_SSIZE_SHIFT;
216 slbie_data |= SLBIE_C;
217 asm volatile("slbie %0" : : "r" (slbie_data));
218 }
219 asm volatile("isync" : : : "memory");
220 } else {
221 __slb_flush_and_rebolt();
222 }
223
224
225 if (offset == 1 || offset > SLB_CACHE_ENTRIES)
226 asm volatile("slbie %0" : : "r" (slbie_data));
227
228 get_paca()->slb_cache_ptr = 0;
229 get_paca()->context = mm->context;
230
231
232
233
234
235
236 exec_base = 0x10000000;
237
238 if (is_kernel_addr(pc) || is_kernel_addr(stack) ||
239 is_kernel_addr(exec_base))
240 return;
241
242 slb_allocate(pc);
243
244 if (!esids_match(pc, stack))
245 slb_allocate(stack);
246
247 if (!esids_match(pc, exec_base) &&
248 !esids_match(stack, exec_base))
249 slb_allocate(exec_base);
250}
251
252static inline void patch_slb_encoding(unsigned int *insn_addr,
253 unsigned int immed)
254{
255 int insn = (*insn_addr & 0xffff0000) | immed;
256 patch_instruction(insn_addr, insn);
257}
258
259void slb_set_size(u16 size)
260{
261 extern unsigned int *slb_compare_rr_to_size;
262
263 if (mmu_slb_size == size)
264 return;
265
266 mmu_slb_size = size;
267 patch_slb_encoding(slb_compare_rr_to_size, mmu_slb_size);
268}
269
270void slb_initialize(void)
271{
272 unsigned long linear_llp, vmalloc_llp, io_llp;
273 unsigned long lflags, vflags;
274 static int slb_encoding_inited;
275 extern unsigned int *slb_miss_kernel_load_linear;
276 extern unsigned int *slb_miss_kernel_load_io;
277 extern unsigned int *slb_compare_rr_to_size;
278#ifdef CONFIG_SPARSEMEM_VMEMMAP
279 extern unsigned int *slb_miss_kernel_load_vmemmap;
280 unsigned long vmemmap_llp;
281#endif
282
283
284 linear_llp = mmu_psize_defs[mmu_linear_psize].sllp;
285 io_llp = mmu_psize_defs[mmu_io_psize].sllp;
286 vmalloc_llp = mmu_psize_defs[mmu_vmalloc_psize].sllp;
287 get_paca()->vmalloc_sllp = SLB_VSID_KERNEL | vmalloc_llp;
288#ifdef CONFIG_SPARSEMEM_VMEMMAP
289 vmemmap_llp = mmu_psize_defs[mmu_vmemmap_psize].sllp;
290#endif
291 if (!slb_encoding_inited) {
292 slb_encoding_inited = 1;
293 patch_slb_encoding(slb_miss_kernel_load_linear,
294 SLB_VSID_KERNEL | linear_llp);
295 patch_slb_encoding(slb_miss_kernel_load_io,
296 SLB_VSID_KERNEL | io_llp);
297 patch_slb_encoding(slb_compare_rr_to_size,
298 mmu_slb_size);
299
300 pr_devel("SLB: linear LLP = %04lx\n", linear_llp);
301 pr_devel("SLB: io LLP = %04lx\n", io_llp);
302
303#ifdef CONFIG_SPARSEMEM_VMEMMAP
304 patch_slb_encoding(slb_miss_kernel_load_vmemmap,
305 SLB_VSID_KERNEL | vmemmap_llp);
306 pr_devel("SLB: vmemmap LLP = %04lx\n", vmemmap_llp);
307#endif
308 }
309
310 get_paca()->stab_rr = SLB_NUM_BOLTED;
311
312 lflags = SLB_VSID_KERNEL | linear_llp;
313 vflags = SLB_VSID_KERNEL | vmalloc_llp;
314
315
316 asm volatile("isync":::"memory");
317 asm volatile("slbmte %0,%0"::"r" (0) : "memory");
318 asm volatile("isync; slbia; isync":::"memory");
319 create_shadowed_slbe(PAGE_OFFSET, mmu_kernel_ssize, lflags, 0);
320
321 create_shadowed_slbe(VMALLOC_START, mmu_kernel_ssize, vflags, 1);
322
323
324
325
326
327
328 slb_shadow_clear(2);
329 if (raw_smp_processor_id() != boot_cpuid &&
330 (get_paca()->kstack & slb_esid_mask(mmu_kernel_ssize)) > PAGE_OFFSET)
331 create_shadowed_slbe(get_paca()->kstack,
332 mmu_kernel_ssize, lflags, 2);
333
334 asm volatile("isync":::"memory");
335}
336