LXR linux/arch/powerpc/net/bpf

   1/* bpf_jit.h: BPF JIT compiler for PPC64
   2 *
   3 * Copyright 2011 Matt Evans <matt@ozlabs.org>, IBM Corporation
   4 *
   5 * This program is free software; you can redistribute it and/or
   6 * modify it under the terms of the GNU General Public License
   7 * as published by the Free Software Foundation; version 2
   8 * of the License.
   9 */
  10#ifndef _BPF_JIT_H
  11#define _BPF_JIT_H
  12
  13#define BPF_PPC_STACK_LOCALS    32
  14#define BPF_PPC_STACK_BASIC     (48+64)
  15#define BPF_PPC_STACK_SAVE      (18*8)
  16#define BPF_PPC_STACKFRAME      (BPF_PPC_STACK_BASIC+BPF_PPC_STACK_LOCALS+ \
  17                                 BPF_PPC_STACK_SAVE)
  18#define BPF_PPC_SLOWPATH_FRAME  (48+64)
  19
  20/*
  21 * Generated code register usage:
  22 *
  23 * As normal PPC C ABI (e.g. r1=sp, r2=TOC), with:
  24 *
  25 * skb          r3      (Entry parameter)
  26 * A register   r4
  27 * X register   r5
  28 * addr param   r6
  29 * r7-r10       scratch
  30 * skb->data    r14
  31 * skb headlen  r15     (skb->len - skb->data_len)
  32 * m[0]         r16
  33 * m[...]       ...
  34 * m[15]        r31
  35 */
  36#define r_skb           3
  37#define r_ret           3
  38#define r_A             4
  39#define r_X             5
  40#define r_addr          6
  41#define r_scratch1      7
  42#define r_scratch2      8
  43#define r_D             14
  44#define r_HL            15
  45#define r_M             16
  46
  47#ifndef __ASSEMBLY__
  48
  49/*
  50 * Assembly helpers from arch/powerpc/net/bpf_jit.S:
  51 */
  52#define DECLARE_LOAD_FUNC(func) \
  53        extern u8 func[], func##_negative_offset[], func##_positive_offset[]
  54
  55DECLARE_LOAD_FUNC(sk_load_word);
  56DECLARE_LOAD_FUNC(sk_load_half);
  57DECLARE_LOAD_FUNC(sk_load_byte);
  58DECLARE_LOAD_FUNC(sk_load_byte_msh);
  59
  60#define FUNCTION_DESCR_SIZE     24
  61
  62/*
  63 * 16-bit immediate helper macros: HA() is for use with sign-extending instrs
  64 * (e.g. LD, ADDI).  If the bottom 16 bits is "-ve", add another bit into the
  65 * top half to negate the effect (i.e. 0xffff + 1 = 0x(1)0000).
  66 */
  67#define IMM_H(i)                ((uintptr_t)(i)>>16)
  68#define IMM_HA(i)               (((uintptr_t)(i)>>16) +                       \
  69                                 (((uintptr_t)(i) & 0x8000) >> 15))
  70#define IMM_L(i)                ((uintptr_t)(i) & 0xffff)
  71
  72#define PLANT_INSTR(d, idx, instr)                                            \
  73        do { if (d) { (d)[idx] = instr; } idx++; } while (0)
  74#define EMIT(instr)             PLANT_INSTR(image, ctx->idx, instr)
  75
  76#define PPC_NOP()               EMIT(PPC_INST_NOP)
  77#define PPC_BLR()               EMIT(PPC_INST_BLR)
  78#define PPC_BLRL()              EMIT(PPC_INST_BLRL)
  79#define PPC_MTLR(r)             EMIT(PPC_INST_MTLR | ___PPC_RT(r))
  80#define PPC_ADDI(d, a, i)       EMIT(PPC_INST_ADDI | ___PPC_RT(d) |           \
  81                                     ___PPC_RA(a) | IMM_L(i))
  82#define PPC_MR(d, a)            PPC_OR(d, a, a)
  83#define PPC_LI(r, i)            PPC_ADDI(r, 0, i)
  84#define PPC_ADDIS(d, a, i)      EMIT(PPC_INST_ADDIS |                         \
  85                                     ___PPC_RS(d) | ___PPC_RA(a) | IMM_L(i))
  86#define PPC_LIS(r, i)           PPC_ADDIS(r, 0, i)
  87#define PPC_STD(r, base, i)     EMIT(PPC_INST_STD | ___PPC_RS(r) |            \
  88                                     ___PPC_RA(base) | ((i) & 0xfffc))
  89
  90#define PPC_LD(r, base, i)      EMIT(PPC_INST_LD | ___PPC_RT(r) |             \
  91                                     ___PPC_RA(base) | IMM_L(i))
  92#define PPC_LWZ(r, base, i)     EMIT(PPC_INST_LWZ | ___PPC_RT(r) |            \
  93                                     ___PPC_RA(base) | IMM_L(i))
  94#define PPC_LHZ(r, base, i)     EMIT(PPC_INST_LHZ | ___PPC_RT(r) |            \
  95                                     ___PPC_RA(base) | IMM_L(i))
  96#define PPC_LHBRX(r, base, b)   EMIT(PPC_INST_LHBRX | ___PPC_RT(r) |          \
  97                                     ___PPC_RA(base) | ___PPC_RB(b))
  98/* Convenience helpers for the above with 'far' offsets: */
  99#define PPC_LD_OFFS(r, base, i) do { if ((i) < 32768) PPC_LD(r, base, i);     \
 100                else {  PPC_ADDIS(r, base, IMM_HA(i));                        \
 101                        PPC_LD(r, r, IMM_L(i)); } } while(0)
 102
 103#define PPC_LWZ_OFFS(r, base, i) do { if ((i) < 32768) PPC_LWZ(r, base, i);   \
 104                else {  PPC_ADDIS(r, base, IMM_HA(i));                        \
 105                        PPC_LWZ(r, r, IMM_L(i)); } } while(0)
 106
 107#define PPC_LHZ_OFFS(r, base, i) do { if ((i) < 32768) PPC_LHZ(r, base, i);   \
 108                else {  PPC_ADDIS(r, base, IMM_HA(i));                        \
 109                        PPC_LHZ(r, r, IMM_L(i)); } } while(0)
 110
 111#define PPC_CMPWI(a, i)         EMIT(PPC_INST_CMPWI | ___PPC_RA(a) | IMM_L(i))
 112#define PPC_CMPDI(a, i)         EMIT(PPC_INST_CMPDI | ___PPC_RA(a) | IMM_L(i))
 113#define PPC_CMPLWI(a, i)        EMIT(PPC_INST_CMPLWI | ___PPC_RA(a) | IMM_L(i))
 114#define PPC_CMPLW(a, b)         EMIT(PPC_INST_CMPLW | ___PPC_RA(a) | ___PPC_RB(b))
 115
 116#define PPC_SUB(d, a, b)        EMIT(PPC_INST_SUB | ___PPC_RT(d) |            \
 117                                     ___PPC_RB(a) | ___PPC_RA(b))
 118#define PPC_ADD(d, a, b)        EMIT(PPC_INST_ADD | ___PPC_RT(d) |            \
 119                                     ___PPC_RA(a) | ___PPC_RB(b))
 120#define PPC_MUL(d, a, b)        EMIT(PPC_INST_MULLW | ___PPC_RT(d) |          \
 121                                     ___PPC_RA(a) | ___PPC_RB(b))
 122#define PPC_MULHWU(d, a, b)     EMIT(PPC_INST_MULHWU | ___PPC_RT(d) |         \
 123                                     ___PPC_RA(a) | ___PPC_RB(b))
 124#define PPC_MULI(d, a, i)       EMIT(PPC_INST_MULLI | ___PPC_RT(d) |          \
 125                                     ___PPC_RA(a) | IMM_L(i))
 126#define PPC_DIVWU(d, a, b)      EMIT(PPC_INST_DIVWU | ___PPC_RT(d) |          \
 127                                     ___PPC_RA(a) | ___PPC_RB(b))
 128#define PPC_AND(d, a, b)        EMIT(PPC_INST_AND | ___PPC_RA(d) |            \
 129                                     ___PPC_RS(a) | ___PPC_RB(b))
 130#define PPC_ANDI(d, a, i)       EMIT(PPC_INST_ANDI | ___PPC_RA(d) |           \
 131                                     ___PPC_RS(a) | IMM_L(i))
 132#define PPC_AND_DOT(d, a, b)    EMIT(PPC_INST_ANDDOT | ___PPC_RA(d) |         \
 133                                     ___PPC_RS(a) | ___PPC_RB(b))
 134#define PPC_OR(d, a, b)         EMIT(PPC_INST_OR | ___PPC_RA(d) |             \
 135                                     ___PPC_RS(a) | ___PPC_RB(b))
 136#define PPC_ORI(d, a, i)        EMIT(PPC_INST_ORI | ___PPC_RA(d) |            \
 137                                     ___PPC_RS(a) | IMM_L(i))
 138#define PPC_ORIS(d, a, i)       EMIT(PPC_INST_ORIS | ___PPC_RA(d) |           \
 139                                     ___PPC_RS(a) | IMM_L(i))
 140#define PPC_XOR(d, a, b)        EMIT(PPC_INST_XOR | ___PPC_RA(d) |            \
 141                                     ___PPC_RS(a) | ___PPC_RB(b))
 142#define PPC_XORI(d, a, i)       EMIT(PPC_INST_XORI | ___PPC_RA(d) |           \
 143                                     ___PPC_RS(a) | IMM_L(i))
 144#define PPC_XORIS(d, a, i)      EMIT(PPC_INST_XORIS | ___PPC_RA(d) |          \
 145                                     ___PPC_RS(a) | IMM_L(i))
 146#define PPC_SLW(d, a, s)        EMIT(PPC_INST_SLW | ___PPC_RA(d) |            \
 147                                     ___PPC_RS(a) | ___PPC_RB(s))
 148#define PPC_SRW(d, a, s)        EMIT(PPC_INST_SRW | ___PPC_RA(d) |            \
 149                                     ___PPC_RS(a) | ___PPC_RB(s))
 150/* slwi = rlwinm Rx, Ry, n, 0, 31-n */
 151#define PPC_SLWI(d, a, i)       EMIT(PPC_INST_RLWINM | ___PPC_RA(d) |         \
 152                                     ___PPC_RS(a) | __PPC_SH(i) |             \
 153                                     __PPC_MB(0) | __PPC_ME(31-(i)))
 154/* srwi = rlwinm Rx, Ry, 32-n, n, 31 */
 155#define PPC_SRWI(d, a, i)       EMIT(PPC_INST_RLWINM | ___PPC_RA(d) |         \
 156                                     ___PPC_RS(a) | __PPC_SH(32-(i)) |        \
 157                                     __PPC_MB(i) | __PPC_ME(31))
 158/* sldi = rldicr Rx, Ry, n, 63-n */
 159#define PPC_SLDI(d, a, i)       EMIT(PPC_INST_RLDICR | ___PPC_RA(d) |         \
 160                                     ___PPC_RS(a) | __PPC_SH(i) |             \
 161                                     __PPC_MB(63-(i)) | (((i) & 0x20) >> 4))
 162#define PPC_NEG(d, a)           EMIT(PPC_INST_NEG | ___PPC_RT(d) | ___PPC_RA(a))
 163
 164/* Long jump; (unconditional 'branch') */
 165#define PPC_JMP(dest)           EMIT(PPC_INST_BRANCH |                        \
 166                                     (((dest) - (ctx->idx * 4)) & 0x03fffffc))
 167/* "cond" here covers BO:BI fields. */
 168#define PPC_BCC_SHORT(cond, dest)       EMIT(PPC_INST_BRANCH_COND |           \
 169                                             (((cond) & 0x3ff) << 16) |       \
 170                                             (((dest) - (ctx->idx * 4)) &     \
 171                                              0xfffc))
 172#define PPC_LI32(d, i)          do { PPC_LI(d, IMM_L(i));                     \
 173                if ((u32)(uintptr_t)(i) >= 32768) {                           \
 174                        PPC_ADDIS(d, d, IMM_HA(i));                           \
 175                } } while(0)
 176#define PPC_LI64(d, i)          do {                                          \
 177                if (!((uintptr_t)(i) & 0xffffffff00000000ULL))                \
 178                        PPC_LI32(d, i);                                       \
 179                else {                                                        \
 180                        PPC_LIS(d, ((uintptr_t)(i) >> 48));                   \
 181                        if ((uintptr_t)(i) & 0x0000ffff00000000ULL)           \
 182                                PPC_ORI(d, d,                                 \
 183                                        ((uintptr_t)(i) >> 32) & 0xffff);     \
 184                        PPC_SLDI(d, d, 32);                                   \
 185                        if ((uintptr_t)(i) & 0x00000000ffff0000ULL)           \
 186                                PPC_ORIS(d, d,                                \
 187                                         ((uintptr_t)(i) >> 16) & 0xffff);    \
 188                        if ((uintptr_t)(i) & 0x000000000000ffffULL)           \
 189                                PPC_ORI(d, d, (uintptr_t)(i) & 0xffff);       \
 190                } } while (0);
 191
 192#define PPC_LHBRX_OFFS(r, base, i) \
 193                do { PPC_LI32(r, i); PPC_LHBRX(r, r, base); } while(0)
 194#ifdef __LITTLE_ENDIAN__
 195#define PPC_NTOHS_OFFS(r, base, i)      PPC_LHBRX_OFFS(r, base, i)
 196#else
 197#define PPC_NTOHS_OFFS(r, base, i)      PPC_LHZ_OFFS(r, base, i)
 198#endif
 199
 200static inline bool is_nearbranch(int offset)
 201{
 202        return (offset < 32768) && (offset >= -32768);
 203}
 204
 205/*
 206 * The fly in the ointment of code size changing from pass to pass is
 207 * avoided by padding the short branch case with a NOP.  If code size differs
 208 * with different branch reaches we will have the issue of code moving from
 209 * one pass to the next and will need a few passes to converge on a stable
 210 * state.
 211 */
 212#define PPC_BCC(cond, dest)     do {                                          \
 213                if (is_nearbranch((dest) - (ctx->idx * 4))) {                 \
 214                        PPC_BCC_SHORT(cond, dest);                            \
 215                        PPC_NOP();                                            \
 216                } else {                                                      \
 217                        /* Flip the 'T or F' bit to invert comparison */      \
 218                        PPC_BCC_SHORT(cond ^ COND_CMP_TRUE, (ctx->idx+2)*4);  \
 219                        PPC_JMP(dest);                                        \
 220                } } while(0)
 221
 222/* To create a branch condition, select a bit of cr0... */
 223#define CR0_LT          0
 224#define CR0_GT          1
 225#define CR0_EQ          2
 226/* ...and modify BO[3] */
 227#define COND_CMP_TRUE   0x100
 228#define COND_CMP_FALSE  0x000
 229/* Together, they make all required comparisons: */
 230#define COND_GT         (CR0_GT | COND_CMP_TRUE)
 231#define COND_GE         (CR0_LT | COND_CMP_FALSE)
 232#define COND_EQ         (CR0_EQ | COND_CMP_TRUE)
 233#define COND_NE         (CR0_EQ | COND_CMP_FALSE)
 234#define COND_LT         (CR0_LT | COND_CMP_TRUE)
 235
 236#define SEEN_DATAREF 0x10000 /* might call external helpers */
 237#define SEEN_XREG    0x20000 /* X reg is used */
 238#define SEEN_MEM     0x40000 /* SEEN_MEM+(1<<n) = use mem[n] for temporary
 239                              * storage */
 240#define SEEN_MEM_MSK 0x0ffff
 241
 242struct codegen_context {
 243        unsigned int seen;
 244        unsigned int idx;
 245        int pc_ret0; /* bpf index of first RET #0 instruction (if any) */
 246};
 247
 248#endif
 249
 250#endif
 251