1#ifndef _SPARC64_TSB_H
2#define _SPARC64_TSB_H
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47#define TSB_TAG_LOCK_BIT 47
48#define TSB_TAG_LOCK_HIGH (1 << (TSB_TAG_LOCK_BIT - 32))
49
50#define TSB_TAG_INVALID_BIT 46
51#define TSB_TAG_INVALID_HIGH (1 << (TSB_TAG_INVALID_BIT - 32))
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60
61#ifndef __ASSEMBLY__
62struct tsb_ldquad_phys_patch_entry {
63 unsigned int addr;
64 unsigned int sun4u_insn;
65 unsigned int sun4v_insn;
66};
67extern struct tsb_ldquad_phys_patch_entry __tsb_ldquad_phys_patch,
68 __tsb_ldquad_phys_patch_end;
69
70struct tsb_phys_patch_entry {
71 unsigned int addr;
72 unsigned int insn;
73};
74extern struct tsb_phys_patch_entry __tsb_phys_patch, __tsb_phys_patch_end;
75#endif
76#define TSB_LOAD_QUAD(TSB, REG) \
77661: ldda [TSB] ASI_NUCLEUS_QUAD_LDD, REG; \
78 .section .tsb_ldquad_phys_patch, "ax"; \
79 .word 661b; \
80 ldda [TSB] ASI_QUAD_LDD_PHYS, REG; \
81 ldda [TSB] ASI_QUAD_LDD_PHYS_4V, REG; \
82 .previous
83
84#define TSB_LOAD_TAG_HIGH(TSB, REG) \
85661: lduwa [TSB] ASI_N, REG; \
86 .section .tsb_phys_patch, "ax"; \
87 .word 661b; \
88 lduwa [TSB] ASI_PHYS_USE_EC, REG; \
89 .previous
90
91#define TSB_LOAD_TAG(TSB, REG) \
92661: ldxa [TSB] ASI_N, REG; \
93 .section .tsb_phys_patch, "ax"; \
94 .word 661b; \
95 ldxa [TSB] ASI_PHYS_USE_EC, REG; \
96 .previous
97
98#define TSB_CAS_TAG_HIGH(TSB, REG1, REG2) \
99661: casa [TSB] ASI_N, REG1, REG2; \
100 .section .tsb_phys_patch, "ax"; \
101 .word 661b; \
102 casa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
103 .previous
104
105#define TSB_CAS_TAG(TSB, REG1, REG2) \
106661: casxa [TSB] ASI_N, REG1, REG2; \
107 .section .tsb_phys_patch, "ax"; \
108 .word 661b; \
109 casxa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
110 .previous
111
112#define TSB_STORE(ADDR, VAL) \
113661: stxa VAL, [ADDR] ASI_N; \
114 .section .tsb_phys_patch, "ax"; \
115 .word 661b; \
116 stxa VAL, [ADDR] ASI_PHYS_USE_EC; \
117 .previous
118
119#define TSB_LOCK_TAG(TSB, REG1, REG2) \
12099: TSB_LOAD_TAG_HIGH(TSB, REG1); \
121 sethi %hi(TSB_TAG_LOCK_HIGH), REG2;\
122 andcc REG1, REG2, %g0; \
123 bne,pn %icc, 99b; \
124 nop; \
125 TSB_CAS_TAG_HIGH(TSB, REG1, REG2); \
126 cmp REG1, REG2; \
127 bne,pn %icc, 99b; \
128 nop; \
129
130#define TSB_WRITE(TSB, TTE, TAG) \
131 add TSB, 0x8, TSB; \
132 TSB_STORE(TSB, TTE); \
133 sub TSB, 0x8, TSB; \
134 TSB_STORE(TSB, TAG);
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139
140#define KERN_PGTABLE_WALK(VADDR, REG1, REG2, FAIL_LABEL) \
141 sethi %hi(swapper_pg_dir), REG1; \
142 or REG1, %lo(swapper_pg_dir), REG1; \
143 sllx VADDR, 64 - (PGDIR_SHIFT + PGDIR_BITS), REG2; \
144 srlx REG2, 64 - PAGE_SHIFT, REG2; \
145 andn REG2, 0x7, REG2; \
146 ldx [REG1 + REG2], REG1; \
147 brz,pn REG1, FAIL_LABEL; \
148 sllx VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \
149 srlx REG2, 64 - PAGE_SHIFT, REG2; \
150 andn REG2, 0x7, REG2; \
151 ldxa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
152 brz,pn REG1, FAIL_LABEL; \
153 sllx VADDR, 64 - PMD_SHIFT, REG2; \
154 srlx REG2, 64 - PAGE_SHIFT, REG2; \
155 andn REG2, 0x7, REG2; \
156 add REG1, REG2, REG1;
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165
166#ifdef CONFIG_TRANSPARENT_HUGEPAGE
167#define USER_PGTABLE_CHECK_PMD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, PTE_LABEL) \
168 brz,pn REG1, FAIL_LABEL; \
169 sethi %uhi(_PAGE_PMD_HUGE), REG2; \
170 sllx REG2, 32, REG2; \
171 andcc REG1, REG2, %g0; \
172 be,pt %xcc, 700f; \
173 sethi %hi(4 * 1024 * 1024), REG2; \
174 brgez,pn REG1, FAIL_LABEL; \
175 andn REG1, REG2, REG1; \
176 and VADDR, REG2, REG2; \
177 brlz,pt REG1, PTE_LABEL; \
178 or REG1, REG2, REG1; \
179700:
180#else
181#define USER_PGTABLE_CHECK_PMD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, PTE_LABEL) \
182 brz,pn REG1, FAIL_LABEL; \
183 nop;
184#endif
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194
195#define USER_PGTABLE_WALK_TL1(VADDR, PHYS_PGD, REG1, REG2, FAIL_LABEL) \
196 sllx VADDR, 64 - (PGDIR_SHIFT + PGDIR_BITS), REG2; \
197 srlx REG2, 64 - PAGE_SHIFT, REG2; \
198 andn REG2, 0x7, REG2; \
199 ldxa [PHYS_PGD + REG2] ASI_PHYS_USE_EC, REG1; \
200 brz,pn REG1, FAIL_LABEL; \
201 sllx VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \
202 srlx REG2, 64 - PAGE_SHIFT, REG2; \
203 andn REG2, 0x7, REG2; \
204 ldxa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
205 USER_PGTABLE_CHECK_PMD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, 800f) \
206 sllx VADDR, 64 - PMD_SHIFT, REG2; \
207 srlx REG2, 64 - PAGE_SHIFT, REG2; \
208 andn REG2, 0x7, REG2; \
209 add REG1, REG2, REG1; \
210 ldxa [REG1] ASI_PHYS_USE_EC, REG1; \
211 brgez,pn REG1, FAIL_LABEL; \
212 nop; \
213800:
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220#define OBP_TRANS_LOOKUP(VADDR, REG1, REG2, REG3, FAIL_LABEL) \
221 sethi %hi(prom_trans), REG1; \
222 or REG1, %lo(prom_trans), REG1; \
22397: ldx [REG1 + 0x00], REG2; \
224 brz,pn REG2, FAIL_LABEL; \
225 nop; \
226 ldx [REG1 + 0x08], REG3; \
227 add REG2, REG3, REG3; \
228 cmp REG2, VADDR; \
229 bgu,pt %xcc, 98f; \
230 cmp VADDR, REG3; \
231 bgeu,pt %xcc, 98f; \
232 ldx [REG1 + 0x10], REG3; \
233 sub VADDR, REG2, REG2; \
234 ba,pt %xcc, 99f; \
235 add REG3, REG2, REG1; \
23698: ba,pt %xcc, 97b; \
237 add REG1, (3 * 8), REG1; \
23899:
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243
244#define KERNEL_TSB_SIZE_BYTES (32 * 1024)
245#define KERNEL_TSB_NENTRIES \
246 (KERNEL_TSB_SIZE_BYTES / 16)
247#define KERNEL_TSB4M_NENTRIES 4096
248
249#define KTSB_PHYS_SHIFT 15
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258#define KERN_TSB_LOOKUP_TL1(VADDR, TAG, REG1, REG2, REG3, REG4, OK_LABEL) \
259661: sethi %hi(swapper_tsb), REG1; \
260 or REG1, %lo(swapper_tsb), REG1; \
261 .section .swapper_tsb_phys_patch, "ax"; \
262 .word 661b; \
263 .previous; \
264661: nop; \
265 .section .tsb_ldquad_phys_patch, "ax"; \
266 .word 661b; \
267 sllx REG1, KTSB_PHYS_SHIFT, REG1; \
268 sllx REG1, KTSB_PHYS_SHIFT, REG1; \
269 .previous; \
270 srlx VADDR, PAGE_SHIFT, REG2; \
271 and REG2, (KERNEL_TSB_NENTRIES - 1), REG2; \
272 sllx REG2, 4, REG2; \
273 add REG1, REG2, REG2; \
274 TSB_LOAD_QUAD(REG2, REG3); \
275 cmp REG3, TAG; \
276 be,a,pt %xcc, OK_LABEL; \
277 mov REG4, REG1;
278
279#ifndef CONFIG_DEBUG_PAGEALLOC
280
281
282
283#define KERN_TSB4M_LOOKUP_TL1(TAG, REG1, REG2, REG3, REG4, OK_LABEL) \
284661: sethi %hi(swapper_4m_tsb), REG1; \
285 or REG1, %lo(swapper_4m_tsb), REG1; \
286 .section .swapper_4m_tsb_phys_patch, "ax"; \
287 .word 661b; \
288 .previous; \
289661: nop; \
290 .section .tsb_ldquad_phys_patch, "ax"; \
291 .word 661b; \
292 sllx REG1, KTSB_PHYS_SHIFT, REG1; \
293 sllx REG1, KTSB_PHYS_SHIFT, REG1; \
294 .previous; \
295 and TAG, (KERNEL_TSB4M_NENTRIES - 1), REG2; \
296 sllx REG2, 4, REG2; \
297 add REG1, REG2, REG2; \
298 TSB_LOAD_QUAD(REG2, REG3); \
299 cmp REG3, TAG; \
300 be,a,pt %xcc, OK_LABEL; \
301 mov REG4, REG1;
302#endif
303
304#endif
305