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20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/gfp.h>
23#include <linux/pci.h>
24#include <linux/blkdev.h>
25#include <linux/delay.h>
26#include <linux/interrupt.h>
27#include <linux/dma-mapping.h>
28#include <linux/device.h>
29#include <scsi/scsi_host.h>
30#include <scsi/scsi_cmnd.h>
31#include <linux/libata.h>
32
33#define DRV_NAME "sata_sil24"
34#define DRV_VERSION "1.1"
35
36
37
38
39struct sil24_prb {
40 __le16 ctrl;
41 __le16 prot;
42 __le32 rx_cnt;
43 u8 fis[6 * 4];
44};
45
46
47
48
49struct sil24_sge {
50 __le64 addr;
51 __le32 cnt;
52 __le32 flags;
53};
54
55
56enum {
57 SIL24_HOST_BAR = 0,
58 SIL24_PORT_BAR = 2,
59
60
61
62
63
64
65 SIL24_PRB_SZ = sizeof(struct sil24_prb)
66 + 2 * sizeof(struct sil24_sge),
67 SIL24_MAX_SGT = (PAGE_SIZE - SIL24_PRB_SZ)
68 / (4 * sizeof(struct sil24_sge)),
69
70
71
72
73 SIL24_MAX_SGE = 4 * SIL24_MAX_SGT + 1,
74
75
76
77
78
79 HOST_SLOT_STAT = 0x00,
80 HOST_CTRL = 0x40,
81 HOST_IRQ_STAT = 0x44,
82 HOST_PHY_CFG = 0x48,
83 HOST_BIST_CTRL = 0x50,
84 HOST_BIST_PTRN = 0x54,
85 HOST_BIST_STAT = 0x58,
86 HOST_MEM_BIST_STAT = 0x5c,
87 HOST_FLASH_CMD = 0x70,
88
89 HOST_FLASH_DATA = 0x74,
90 HOST_TRANSITION_DETECT = 0x75,
91 HOST_GPIO_CTRL = 0x76,
92 HOST_I2C_ADDR = 0x78,
93 HOST_I2C_DATA = 0x7c,
94 HOST_I2C_XFER_CNT = 0x7e,
95 HOST_I2C_CTRL = 0x7f,
96
97
98 HOST_SSTAT_ATTN = (1 << 31),
99
100
101 HOST_CTRL_M66EN = (1 << 16),
102 HOST_CTRL_TRDY = (1 << 17),
103 HOST_CTRL_STOP = (1 << 18),
104 HOST_CTRL_DEVSEL = (1 << 19),
105 HOST_CTRL_REQ64 = (1 << 20),
106 HOST_CTRL_GLOBAL_RST = (1 << 31),
107
108
109
110
111
112 PORT_REGS_SIZE = 0x2000,
113
114 PORT_LRAM = 0x0000,
115 PORT_LRAM_SLOT_SZ = 0x0080,
116
117 PORT_PMP = 0x0f80,
118 PORT_PMP_STATUS = 0x0000,
119 PORT_PMP_QACTIVE = 0x0004,
120 PORT_PMP_SIZE = 0x0008,
121
122
123 PORT_CTRL_STAT = 0x1000,
124 PORT_CTRL_CLR = 0x1004,
125 PORT_IRQ_STAT = 0x1008,
126 PORT_IRQ_ENABLE_SET = 0x1010,
127 PORT_IRQ_ENABLE_CLR = 0x1014,
128 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
129 PORT_EXEC_FIFO = 0x1020,
130 PORT_CMD_ERR = 0x1024,
131 PORT_FIS_CFG = 0x1028,
132 PORT_FIFO_THRES = 0x102c,
133
134 PORT_DECODE_ERR_CNT = 0x1040,
135 PORT_DECODE_ERR_THRESH = 0x1042,
136 PORT_CRC_ERR_CNT = 0x1044,
137 PORT_CRC_ERR_THRESH = 0x1046,
138 PORT_HSHK_ERR_CNT = 0x1048,
139 PORT_HSHK_ERR_THRESH = 0x104a,
140
141 PORT_PHY_CFG = 0x1050,
142 PORT_SLOT_STAT = 0x1800,
143 PORT_CMD_ACTIVATE = 0x1c00,
144 PORT_CONTEXT = 0x1e04,
145 PORT_EXEC_DIAG = 0x1e00,
146 PORT_PSD_DIAG = 0x1e40,
147 PORT_SCONTROL = 0x1f00,
148 PORT_SSTATUS = 0x1f04,
149 PORT_SERROR = 0x1f08,
150 PORT_SACTIVE = 0x1f0c,
151
152
153 PORT_CS_PORT_RST = (1 << 0),
154 PORT_CS_DEV_RST = (1 << 1),
155 PORT_CS_INIT = (1 << 2),
156 PORT_CS_IRQ_WOC = (1 << 3),
157 PORT_CS_CDB16 = (1 << 5),
158 PORT_CS_PMP_RESUME = (1 << 6),
159 PORT_CS_32BIT_ACTV = (1 << 10),
160 PORT_CS_PMP_EN = (1 << 13),
161 PORT_CS_RDY = (1 << 31),
162
163
164
165 PORT_IRQ_COMPLETE = (1 << 0),
166 PORT_IRQ_ERROR = (1 << 1),
167 PORT_IRQ_PORTRDY_CHG = (1 << 2),
168 PORT_IRQ_PWR_CHG = (1 << 3),
169 PORT_IRQ_PHYRDY_CHG = (1 << 4),
170 PORT_IRQ_COMWAKE = (1 << 5),
171 PORT_IRQ_UNK_FIS = (1 << 6),
172 PORT_IRQ_DEV_XCHG = (1 << 7),
173 PORT_IRQ_8B10B = (1 << 8),
174 PORT_IRQ_CRC = (1 << 9),
175 PORT_IRQ_HANDSHAKE = (1 << 10),
176 PORT_IRQ_SDB_NOTIFY = (1 << 11),
177
178 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
179 PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
180 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY,
181
182
183 PORT_IRQ_RAW_SHIFT = 16,
184 PORT_IRQ_MASKED_MASK = 0x7ff,
185 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
186
187
188 PORT_IRQ_STEER_SHIFT = 30,
189 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
190
191
192 PORT_CERR_DEV = 1,
193 PORT_CERR_SDB = 2,
194 PORT_CERR_DATA = 3,
195 PORT_CERR_SEND = 4,
196 PORT_CERR_INCONSISTENT = 5,
197 PORT_CERR_DIRECTION = 6,
198 PORT_CERR_UNDERRUN = 7,
199 PORT_CERR_OVERRUN = 8,
200 PORT_CERR_PKT_PROT = 11,
201 PORT_CERR_SGT_BOUNDARY = 16,
202 PORT_CERR_SGT_TGTABRT = 17,
203 PORT_CERR_SGT_MSTABRT = 18,
204 PORT_CERR_SGT_PCIPERR = 19,
205 PORT_CERR_CMD_BOUNDARY = 24,
206 PORT_CERR_CMD_TGTABRT = 25,
207 PORT_CERR_CMD_MSTABRT = 26,
208 PORT_CERR_CMD_PCIPERR = 27,
209 PORT_CERR_XFR_UNDEF = 32,
210 PORT_CERR_XFR_TGTABRT = 33,
211 PORT_CERR_XFR_MSTABRT = 34,
212 PORT_CERR_XFR_PCIPERR = 35,
213 PORT_CERR_SENDSERVICE = 36,
214
215
216 PRB_CTRL_PROTOCOL = (1 << 0),
217 PRB_CTRL_PACKET_READ = (1 << 4),
218 PRB_CTRL_PACKET_WRITE = (1 << 5),
219 PRB_CTRL_NIEN = (1 << 6),
220 PRB_CTRL_SRST = (1 << 7),
221
222
223 PRB_PROT_PACKET = (1 << 0),
224 PRB_PROT_TCQ = (1 << 1),
225 PRB_PROT_NCQ = (1 << 2),
226 PRB_PROT_READ = (1 << 3),
227 PRB_PROT_WRITE = (1 << 4),
228 PRB_PROT_TRANSPARENT = (1 << 5),
229
230
231
232
233 SGE_TRM = (1 << 31),
234 SGE_LNK = (1 << 30),
235
236 SGE_DRD = (1 << 29),
237
238
239 SIL24_MAX_CMDS = 31,
240
241
242 BID_SIL3124 = 0,
243 BID_SIL3132 = 1,
244 BID_SIL3131 = 2,
245
246
247 SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
248 ATA_FLAG_NCQ | ATA_FLAG_ACPI_SATA |
249 ATA_FLAG_AN | ATA_FLAG_PMP,
250 SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24),
251
252 IRQ_STAT_4PORTS = 0xf,
253};
254
255struct sil24_ata_block {
256 struct sil24_prb prb;
257 struct sil24_sge sge[SIL24_MAX_SGE];
258};
259
260struct sil24_atapi_block {
261 struct sil24_prb prb;
262 u8 cdb[16];
263 struct sil24_sge sge[SIL24_MAX_SGE];
264};
265
266union sil24_cmd_block {
267 struct sil24_ata_block ata;
268 struct sil24_atapi_block atapi;
269};
270
271static const struct sil24_cerr_info {
272 unsigned int err_mask, action;
273 const char *desc;
274} sil24_cerr_db[] = {
275 [0] = { AC_ERR_DEV, 0,
276 "device error" },
277 [PORT_CERR_DEV] = { AC_ERR_DEV, 0,
278 "device error via D2H FIS" },
279 [PORT_CERR_SDB] = { AC_ERR_DEV, 0,
280 "device error via SDB FIS" },
281 [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_RESET,
282 "error in data FIS" },
283 [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_RESET,
284 "failed to transmit command FIS" },
285 [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_RESET,
286 "protocol mismatch" },
287 [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_RESET,
288 "data directon mismatch" },
289 [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_RESET,
290 "ran out of SGEs while writing" },
291 [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_RESET,
292 "ran out of SGEs while reading" },
293 [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_RESET,
294 "invalid data directon for ATAPI CDB" },
295 [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET,
296 "SGT not on qword boundary" },
297 [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
298 "PCI target abort while fetching SGT" },
299 [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
300 "PCI master abort while fetching SGT" },
301 [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
302 "PCI parity error while fetching SGT" },
303 [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET,
304 "PRB not on qword boundary" },
305 [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
306 "PCI target abort while fetching PRB" },
307 [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
308 "PCI master abort while fetching PRB" },
309 [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
310 "PCI parity error while fetching PRB" },
311 [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
312 "undefined error while transferring data" },
313 [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
314 "PCI target abort while transferring data" },
315 [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
316 "PCI master abort while transferring data" },
317 [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
318 "PCI parity error while transferring data" },
319 [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_RESET,
320 "FIS received while sending service FIS" },
321};
322
323
324
325
326
327
328
329struct sil24_port_priv {
330 union sil24_cmd_block *cmd_block;
331 dma_addr_t cmd_block_dma;
332 int do_port_rst;
333};
334
335static void sil24_dev_config(struct ata_device *dev);
336static int sil24_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val);
337static int sil24_scr_write(struct ata_link *link, unsigned sc_reg, u32 val);
338static int sil24_qc_defer(struct ata_queued_cmd *qc);
339static void sil24_qc_prep(struct ata_queued_cmd *qc);
340static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
341static bool sil24_qc_fill_rtf(struct ata_queued_cmd *qc);
342static void sil24_pmp_attach(struct ata_port *ap);
343static void sil24_pmp_detach(struct ata_port *ap);
344static void sil24_freeze(struct ata_port *ap);
345static void sil24_thaw(struct ata_port *ap);
346static int sil24_softreset(struct ata_link *link, unsigned int *class,
347 unsigned long deadline);
348static int sil24_hardreset(struct ata_link *link, unsigned int *class,
349 unsigned long deadline);
350static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class,
351 unsigned long deadline);
352static void sil24_error_handler(struct ata_port *ap);
353static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
354static int sil24_port_start(struct ata_port *ap);
355static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
356#ifdef CONFIG_PM
357static int sil24_pci_device_resume(struct pci_dev *pdev);
358static int sil24_port_resume(struct ata_port *ap);
359#endif
360
361static const struct pci_device_id sil24_pci_tbl[] = {
362 { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 },
363 { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 },
364 { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 },
365 { PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 },
366 { PCI_VDEVICE(CMD, 0x0244), BID_SIL3132 },
367 { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 },
368 { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 },
369
370 { }
371};
372
373static struct pci_driver sil24_pci_driver = {
374 .name = DRV_NAME,
375 .id_table = sil24_pci_tbl,
376 .probe = sil24_init_one,
377 .remove = ata_pci_remove_one,
378#ifdef CONFIG_PM
379 .suspend = ata_pci_device_suspend,
380 .resume = sil24_pci_device_resume,
381#endif
382};
383
384static struct scsi_host_template sil24_sht = {
385 ATA_NCQ_SHT(DRV_NAME),
386 .can_queue = SIL24_MAX_CMDS,
387 .sg_tablesize = SIL24_MAX_SGE,
388 .dma_boundary = ATA_DMA_BOUNDARY,
389};
390
391static struct ata_port_operations sil24_ops = {
392 .inherits = &sata_pmp_port_ops,
393
394 .qc_defer = sil24_qc_defer,
395 .qc_prep = sil24_qc_prep,
396 .qc_issue = sil24_qc_issue,
397 .qc_fill_rtf = sil24_qc_fill_rtf,
398
399 .freeze = sil24_freeze,
400 .thaw = sil24_thaw,
401 .softreset = sil24_softreset,
402 .hardreset = sil24_hardreset,
403 .pmp_softreset = sil24_softreset,
404 .pmp_hardreset = sil24_pmp_hardreset,
405 .error_handler = sil24_error_handler,
406 .post_internal_cmd = sil24_post_internal_cmd,
407 .dev_config = sil24_dev_config,
408
409 .scr_read = sil24_scr_read,
410 .scr_write = sil24_scr_write,
411 .pmp_attach = sil24_pmp_attach,
412 .pmp_detach = sil24_pmp_detach,
413
414 .port_start = sil24_port_start,
415#ifdef CONFIG_PM
416 .port_resume = sil24_port_resume,
417#endif
418};
419
420static bool sata_sil24_msi;
421module_param_named(msi, sata_sil24_msi, bool, S_IRUGO);
422MODULE_PARM_DESC(msi, "Enable MSI (Default: false)");
423
424
425
426
427
428#define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
429#define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
430
431static const struct ata_port_info sil24_port_info[] = {
432
433 {
434 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
435 SIL24_FLAG_PCIX_IRQ_WOC,
436 .pio_mask = ATA_PIO4,
437 .mwdma_mask = ATA_MWDMA2,
438 .udma_mask = ATA_UDMA5,
439 .port_ops = &sil24_ops,
440 },
441
442 {
443 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
444 .pio_mask = ATA_PIO4,
445 .mwdma_mask = ATA_MWDMA2,
446 .udma_mask = ATA_UDMA5,
447 .port_ops = &sil24_ops,
448 },
449
450 {
451 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
452 .pio_mask = ATA_PIO4,
453 .mwdma_mask = ATA_MWDMA2,
454 .udma_mask = ATA_UDMA5,
455 .port_ops = &sil24_ops,
456 },
457};
458
459static int sil24_tag(int tag)
460{
461 if (unlikely(ata_tag_internal(tag)))
462 return 0;
463 return tag;
464}
465
466static unsigned long sil24_port_offset(struct ata_port *ap)
467{
468 return ap->port_no * PORT_REGS_SIZE;
469}
470
471static void __iomem *sil24_port_base(struct ata_port *ap)
472{
473 return ap->host->iomap[SIL24_PORT_BAR] + sil24_port_offset(ap);
474}
475
476static void sil24_dev_config(struct ata_device *dev)
477{
478 void __iomem *port = sil24_port_base(dev->link->ap);
479
480 if (dev->cdb_len == 16)
481 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
482 else
483 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
484}
485
486static void sil24_read_tf(struct ata_port *ap, int tag, struct ata_taskfile *tf)
487{
488 void __iomem *port = sil24_port_base(ap);
489 struct sil24_prb __iomem *prb;
490 u8 fis[6 * 4];
491
492 prb = port + PORT_LRAM + sil24_tag(tag) * PORT_LRAM_SLOT_SZ;
493 memcpy_fromio(fis, prb->fis, sizeof(fis));
494 ata_tf_from_fis(fis, tf);
495}
496
497static int sil24_scr_map[] = {
498 [SCR_CONTROL] = 0,
499 [SCR_STATUS] = 1,
500 [SCR_ERROR] = 2,
501 [SCR_ACTIVE] = 3,
502};
503
504static int sil24_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val)
505{
506 void __iomem *scr_addr = sil24_port_base(link->ap) + PORT_SCONTROL;
507
508 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
509 *val = readl(scr_addr + sil24_scr_map[sc_reg] * 4);
510 return 0;
511 }
512 return -EINVAL;
513}
514
515static int sil24_scr_write(struct ata_link *link, unsigned sc_reg, u32 val)
516{
517 void __iomem *scr_addr = sil24_port_base(link->ap) + PORT_SCONTROL;
518
519 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
520 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
521 return 0;
522 }
523 return -EINVAL;
524}
525
526static void sil24_config_port(struct ata_port *ap)
527{
528 void __iomem *port = sil24_port_base(ap);
529
530
531 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
532 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
533 else
534 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
535
536
537 writew(0x8000, port + PORT_DECODE_ERR_THRESH);
538 writew(0x8000, port + PORT_CRC_ERR_THRESH);
539 writew(0x8000, port + PORT_HSHK_ERR_THRESH);
540 writew(0x0000, port + PORT_DECODE_ERR_CNT);
541 writew(0x0000, port + PORT_CRC_ERR_CNT);
542 writew(0x0000, port + PORT_HSHK_ERR_CNT);
543
544
545 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
546
547
548 writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
549}
550
551static void sil24_config_pmp(struct ata_port *ap, int attached)
552{
553 void __iomem *port = sil24_port_base(ap);
554
555 if (attached)
556 writel(PORT_CS_PMP_EN, port + PORT_CTRL_STAT);
557 else
558 writel(PORT_CS_PMP_EN, port + PORT_CTRL_CLR);
559}
560
561static void sil24_clear_pmp(struct ata_port *ap)
562{
563 void __iomem *port = sil24_port_base(ap);
564 int i;
565
566 writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
567
568 for (i = 0; i < SATA_PMP_MAX_PORTS; i++) {
569 void __iomem *pmp_base = port + PORT_PMP + i * PORT_PMP_SIZE;
570
571 writel(0, pmp_base + PORT_PMP_STATUS);
572 writel(0, pmp_base + PORT_PMP_QACTIVE);
573 }
574}
575
576static int sil24_init_port(struct ata_port *ap)
577{
578 void __iomem *port = sil24_port_base(ap);
579 struct sil24_port_priv *pp = ap->private_data;
580 u32 tmp;
581
582
583 if (sata_pmp_attached(ap))
584 sil24_clear_pmp(ap);
585
586 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
587 ata_wait_register(ap, port + PORT_CTRL_STAT,
588 PORT_CS_INIT, PORT_CS_INIT, 10, 100);
589 tmp = ata_wait_register(ap, port + PORT_CTRL_STAT,
590 PORT_CS_RDY, 0, 10, 100);
591
592 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY) {
593 pp->do_port_rst = 1;
594 ap->link.eh_context.i.action |= ATA_EH_RESET;
595 return -EIO;
596 }
597
598 return 0;
599}
600
601static int sil24_exec_polled_cmd(struct ata_port *ap, int pmp,
602 const struct ata_taskfile *tf,
603 int is_cmd, u32 ctrl,
604 unsigned long timeout_msec)
605{
606 void __iomem *port = sil24_port_base(ap);
607 struct sil24_port_priv *pp = ap->private_data;
608 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
609 dma_addr_t paddr = pp->cmd_block_dma;
610 u32 irq_enabled, irq_mask, irq_stat;
611 int rc;
612
613 prb->ctrl = cpu_to_le16(ctrl);
614 ata_tf_to_fis(tf, pmp, is_cmd, prb->fis);
615
616
617 irq_enabled = readl(port + PORT_IRQ_ENABLE_SET);
618 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
619
620
621
622
623
624 wmb();
625 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
626 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
627
628 irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
629 irq_stat = ata_wait_register(ap, port + PORT_IRQ_STAT, irq_mask, 0x0,
630 10, timeout_msec);
631
632 writel(irq_mask, port + PORT_IRQ_STAT);
633 irq_stat >>= PORT_IRQ_RAW_SHIFT;
634
635 if (irq_stat & PORT_IRQ_COMPLETE)
636 rc = 0;
637 else {
638
639 sil24_init_port(ap);
640
641 if (irq_stat & PORT_IRQ_ERROR)
642 rc = -EIO;
643 else
644 rc = -EBUSY;
645 }
646
647
648 writel(irq_enabled, port + PORT_IRQ_ENABLE_SET);
649
650 return rc;
651}
652
653static int sil24_softreset(struct ata_link *link, unsigned int *class,
654 unsigned long deadline)
655{
656 struct ata_port *ap = link->ap;
657 int pmp = sata_srst_pmp(link);
658 unsigned long timeout_msec = 0;
659 struct ata_taskfile tf;
660 const char *reason;
661 int rc;
662
663 DPRINTK("ENTER\n");
664
665
666 if (sil24_init_port(ap)) {
667 reason = "port not ready";
668 goto err;
669 }
670
671
672 if (time_after(deadline, jiffies))
673 timeout_msec = jiffies_to_msecs(deadline - jiffies);
674
675 ata_tf_init(link->device, &tf);
676 rc = sil24_exec_polled_cmd(ap, pmp, &tf, 0, PRB_CTRL_SRST,
677 timeout_msec);
678 if (rc == -EBUSY) {
679 reason = "timeout";
680 goto err;
681 } else if (rc) {
682 reason = "SRST command error";
683 goto err;
684 }
685
686 sil24_read_tf(ap, 0, &tf);
687 *class = ata_dev_classify(&tf);
688
689 DPRINTK("EXIT, class=%u\n", *class);
690 return 0;
691
692 err:
693 ata_link_err(link, "softreset failed (%s)\n", reason);
694 return -EIO;
695}
696
697static int sil24_hardreset(struct ata_link *link, unsigned int *class,
698 unsigned long deadline)
699{
700 struct ata_port *ap = link->ap;
701 void __iomem *port = sil24_port_base(ap);
702 struct sil24_port_priv *pp = ap->private_data;
703 int did_port_rst = 0;
704 const char *reason;
705 int tout_msec, rc;
706 u32 tmp;
707
708 retry:
709
710
711
712 if (pp->do_port_rst) {
713 ata_port_warn(ap,
714 "controller in dubious state, performing PORT_RST\n");
715
716 writel(PORT_CS_PORT_RST, port + PORT_CTRL_STAT);
717 ata_msleep(ap, 10);
718 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
719 ata_wait_register(ap, port + PORT_CTRL_STAT, PORT_CS_RDY, 0,
720 10, 5000);
721
722
723 sil24_config_port(ap);
724 sil24_config_pmp(ap, ap->nr_pmp_links);
725
726 pp->do_port_rst = 0;
727 did_port_rst = 1;
728 }
729
730
731 sata_set_spd(link);
732
733 tout_msec = 100;
734 if (ata_link_online(link))
735 tout_msec = 5000;
736
737 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
738 tmp = ata_wait_register(ap, port + PORT_CTRL_STAT,
739 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10,
740 tout_msec);
741
742
743
744
745 rc = sata_link_debounce(link, sata_deb_timing_long, deadline);
746 if (rc) {
747 reason = "PHY debouncing failed";
748 goto err;
749 }
750
751 if (tmp & PORT_CS_DEV_RST) {
752 if (ata_link_offline(link))
753 return 0;
754 reason = "link not ready";
755 goto err;
756 }
757
758
759
760
761
762
763
764 return -EAGAIN;
765
766 err:
767 if (!did_port_rst) {
768 pp->do_port_rst = 1;
769 goto retry;
770 }
771
772 ata_link_err(link, "hardreset failed (%s)\n", reason);
773 return -EIO;
774}
775
776static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
777 struct sil24_sge *sge)
778{
779 struct scatterlist *sg;
780 struct sil24_sge *last_sge = NULL;
781 unsigned int si;
782
783 for_each_sg(qc->sg, sg, qc->n_elem, si) {
784 sge->addr = cpu_to_le64(sg_dma_address(sg));
785 sge->cnt = cpu_to_le32(sg_dma_len(sg));
786 sge->flags = 0;
787
788 last_sge = sge;
789 sge++;
790 }
791
792 last_sge->flags = cpu_to_le32(SGE_TRM);
793}
794
795static int sil24_qc_defer(struct ata_queued_cmd *qc)
796{
797 struct ata_link *link = qc->dev->link;
798 struct ata_port *ap = link->ap;
799 u8 prot = qc->tf.protocol;
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820 int is_excl = (ata_is_atapi(prot) ||
821 (qc->flags & ATA_QCFLAG_RESULT_TF));
822
823 if (unlikely(ap->excl_link)) {
824 if (link == ap->excl_link) {
825 if (ap->nr_active_links)
826 return ATA_DEFER_PORT;
827 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
828 } else
829 return ATA_DEFER_PORT;
830 } else if (unlikely(is_excl)) {
831 ap->excl_link = link;
832 if (ap->nr_active_links)
833 return ATA_DEFER_PORT;
834 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
835 }
836
837 return ata_std_qc_defer(qc);
838}
839
840static void sil24_qc_prep(struct ata_queued_cmd *qc)
841{
842 struct ata_port *ap = qc->ap;
843 struct sil24_port_priv *pp = ap->private_data;
844 union sil24_cmd_block *cb;
845 struct sil24_prb *prb;
846 struct sil24_sge *sge;
847 u16 ctrl = 0;
848
849 cb = &pp->cmd_block[sil24_tag(qc->tag)];
850
851 if (!ata_is_atapi(qc->tf.protocol)) {
852 prb = &cb->ata.prb;
853 sge = cb->ata.sge;
854 if (ata_is_data(qc->tf.protocol)) {
855 u16 prot = 0;
856 ctrl = PRB_CTRL_PROTOCOL;
857 if (ata_is_ncq(qc->tf.protocol))
858 prot |= PRB_PROT_NCQ;
859 if (qc->tf.flags & ATA_TFLAG_WRITE)
860 prot |= PRB_PROT_WRITE;
861 else
862 prot |= PRB_PROT_READ;
863 prb->prot = cpu_to_le16(prot);
864 }
865 } else {
866 prb = &cb->atapi.prb;
867 sge = cb->atapi.sge;
868 memset(cb->atapi.cdb, 0, sizeof(cb->atapi.cdb));
869 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
870
871 if (ata_is_data(qc->tf.protocol)) {
872 if (qc->tf.flags & ATA_TFLAG_WRITE)
873 ctrl = PRB_CTRL_PACKET_WRITE;
874 else
875 ctrl = PRB_CTRL_PACKET_READ;
876 }
877 }
878
879 prb->ctrl = cpu_to_le16(ctrl);
880 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, prb->fis);
881
882 if (qc->flags & ATA_QCFLAG_DMAMAP)
883 sil24_fill_sg(qc, sge);
884}
885
886static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
887{
888 struct ata_port *ap = qc->ap;
889 struct sil24_port_priv *pp = ap->private_data;
890 void __iomem *port = sil24_port_base(ap);
891 unsigned int tag = sil24_tag(qc->tag);
892 dma_addr_t paddr;
893 void __iomem *activate;
894
895 paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block);
896 activate = port + PORT_CMD_ACTIVATE + tag * 8;
897
898
899
900
901
902 wmb();
903 writel((u32)paddr, activate);
904 writel((u64)paddr >> 32, activate + 4);
905
906 return 0;
907}
908
909static bool sil24_qc_fill_rtf(struct ata_queued_cmd *qc)
910{
911 sil24_read_tf(qc->ap, qc->tag, &qc->result_tf);
912 return true;
913}
914
915static void sil24_pmp_attach(struct ata_port *ap)
916{
917 u32 *gscr = ap->link.device->gscr;
918
919 sil24_config_pmp(ap, 1);
920 sil24_init_port(ap);
921
922 if (sata_pmp_gscr_vendor(gscr) == 0x11ab &&
923 sata_pmp_gscr_devid(gscr) == 0x4140) {
924 ata_port_info(ap,
925 "disabling NCQ support due to sil24-mv4140 quirk\n");
926 ap->flags &= ~ATA_FLAG_NCQ;
927 }
928}
929
930static void sil24_pmp_detach(struct ata_port *ap)
931{
932 sil24_init_port(ap);
933 sil24_config_pmp(ap, 0);
934
935 ap->flags |= ATA_FLAG_NCQ;
936}
937
938static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class,
939 unsigned long deadline)
940{
941 int rc;
942
943 rc = sil24_init_port(link->ap);
944 if (rc) {
945 ata_link_err(link, "hardreset failed (port not ready)\n");
946 return rc;
947 }
948
949 return sata_std_hardreset(link, class, deadline);
950}
951
952static void sil24_freeze(struct ata_port *ap)
953{
954 void __iomem *port = sil24_port_base(ap);
955
956
957
958
959 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
960}
961
962static void sil24_thaw(struct ata_port *ap)
963{
964 void __iomem *port = sil24_port_base(ap);
965 u32 tmp;
966
967
968 tmp = readl(port + PORT_IRQ_STAT);
969 writel(tmp, port + PORT_IRQ_STAT);
970
971
972 writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
973}
974
975static void sil24_error_intr(struct ata_port *ap)
976{
977 void __iomem *port = sil24_port_base(ap);
978 struct sil24_port_priv *pp = ap->private_data;
979 struct ata_queued_cmd *qc = NULL;
980 struct ata_link *link;
981 struct ata_eh_info *ehi;
982 int abort = 0, freeze = 0;
983 u32 irq_stat;
984
985
986 irq_stat = readl(port + PORT_IRQ_STAT);
987 writel(irq_stat, port + PORT_IRQ_STAT);
988
989
990 link = &ap->link;
991 ehi = &link->eh_info;
992 ata_ehi_clear_desc(ehi);
993
994 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
995
996 if (irq_stat & PORT_IRQ_SDB_NOTIFY) {
997 ata_ehi_push_desc(ehi, "SDB notify");
998 sata_async_notification(ap);
999 }
1000
1001 if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) {
1002 ata_ehi_hotplugged(ehi);
1003 ata_ehi_push_desc(ehi, "%s",
1004 irq_stat & PORT_IRQ_PHYRDY_CHG ?
1005 "PHY RDY changed" : "device exchanged");
1006 freeze = 1;
1007 }
1008
1009 if (irq_stat & PORT_IRQ_UNK_FIS) {
1010 ehi->err_mask |= AC_ERR_HSM;
1011 ehi->action |= ATA_EH_RESET;
1012 ata_ehi_push_desc(ehi, "unknown FIS");
1013 freeze = 1;
1014 }
1015
1016
1017 if (irq_stat & PORT_IRQ_ERROR) {
1018 const struct sil24_cerr_info *ci = NULL;
1019 unsigned int err_mask = 0, action = 0;
1020 u32 context, cerr;
1021 int pmp;
1022
1023 abort = 1;
1024
1025
1026
1027
1028
1029
1030 if (ap->nr_active_links >= 3) {
1031 ehi->err_mask |= AC_ERR_OTHER;
1032 ehi->action |= ATA_EH_RESET;
1033 ata_ehi_push_desc(ehi, "PMP DMA CS errata");
1034 pp->do_port_rst = 1;
1035 freeze = 1;
1036 }
1037
1038
1039 if (sata_pmp_attached(ap)) {
1040 context = readl(port + PORT_CONTEXT);
1041 pmp = (context >> 5) & 0xf;
1042
1043 if (pmp < ap->nr_pmp_links) {
1044 link = &ap->pmp_link[pmp];
1045 ehi = &link->eh_info;
1046 qc = ata_qc_from_tag(ap, link->active_tag);
1047
1048 ata_ehi_clear_desc(ehi);
1049 ata_ehi_push_desc(ehi, "irq_stat 0x%08x",
1050 irq_stat);
1051 } else {
1052 err_mask |= AC_ERR_HSM;
1053 action |= ATA_EH_RESET;
1054 freeze = 1;
1055 }
1056 } else
1057 qc = ata_qc_from_tag(ap, link->active_tag);
1058
1059
1060 cerr = readl(port + PORT_CMD_ERR);
1061 if (cerr < ARRAY_SIZE(sil24_cerr_db))
1062 ci = &sil24_cerr_db[cerr];
1063
1064 if (ci && ci->desc) {
1065 err_mask |= ci->err_mask;
1066 action |= ci->action;
1067 if (action & ATA_EH_RESET)
1068 freeze = 1;
1069 ata_ehi_push_desc(ehi, "%s", ci->desc);
1070 } else {
1071 err_mask |= AC_ERR_OTHER;
1072 action |= ATA_EH_RESET;
1073 freeze = 1;
1074 ata_ehi_push_desc(ehi, "unknown command error %d",
1075 cerr);
1076 }
1077
1078
1079 if (qc)
1080 qc->err_mask |= err_mask;
1081 else
1082 ehi->err_mask |= err_mask;
1083
1084 ehi->action |= action;
1085
1086
1087 if (sata_pmp_attached(ap))
1088 writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_STAT);
1089 }
1090
1091
1092 if (freeze)
1093 ata_port_freeze(ap);
1094 else if (abort) {
1095 if (qc)
1096 ata_link_abort(qc->dev->link);
1097 else
1098 ata_port_abort(ap);
1099 }
1100}
1101
1102static inline void sil24_host_intr(struct ata_port *ap)
1103{
1104 void __iomem *port = sil24_port_base(ap);
1105 u32 slot_stat, qc_active;
1106 int rc;
1107
1108
1109
1110
1111
1112
1113
1114
1115 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
1116 writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
1117
1118 slot_stat = readl(port + PORT_SLOT_STAT);
1119
1120 if (unlikely(slot_stat & HOST_SSTAT_ATTN)) {
1121 sil24_error_intr(ap);
1122 return;
1123 }
1124
1125 qc_active = slot_stat & ~HOST_SSTAT_ATTN;
1126 rc = ata_qc_complete_multiple(ap, qc_active);
1127 if (rc > 0)
1128 return;
1129 if (rc < 0) {
1130 struct ata_eh_info *ehi = &ap->link.eh_info;
1131 ehi->err_mask |= AC_ERR_HSM;
1132 ehi->action |= ATA_EH_RESET;
1133 ata_port_freeze(ap);
1134 return;
1135 }
1136
1137
1138 if (!(ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) && ata_ratelimit())
1139 ata_port_info(ap,
1140 "spurious interrupt (slot_stat 0x%x active_tag %d sactive 0x%x)\n",
1141 slot_stat, ap->link.active_tag, ap->link.sactive);
1142}
1143
1144static irqreturn_t sil24_interrupt(int irq, void *dev_instance)
1145{
1146 struct ata_host *host = dev_instance;
1147 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1148 unsigned handled = 0;
1149 u32 status;
1150 int i;
1151
1152 status = readl(host_base + HOST_IRQ_STAT);
1153
1154 if (status == 0xffffffff) {
1155 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
1156 "PCI fault or device removal?\n");
1157 goto out;
1158 }
1159
1160 if (!(status & IRQ_STAT_4PORTS))
1161 goto out;
1162
1163 spin_lock(&host->lock);
1164
1165 for (i = 0; i < host->n_ports; i++)
1166 if (status & (1 << i)) {
1167 sil24_host_intr(host->ports[i]);
1168 handled++;
1169 }
1170
1171 spin_unlock(&host->lock);
1172 out:
1173 return IRQ_RETVAL(handled);
1174}
1175
1176static void sil24_error_handler(struct ata_port *ap)
1177{
1178 struct sil24_port_priv *pp = ap->private_data;
1179
1180 if (sil24_init_port(ap))
1181 ata_eh_freeze_port(ap);
1182
1183 sata_pmp_error_handler(ap);
1184
1185 pp->do_port_rst = 0;
1186}
1187
1188static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
1189{
1190 struct ata_port *ap = qc->ap;
1191
1192
1193 if ((qc->flags & ATA_QCFLAG_FAILED) && sil24_init_port(ap))
1194 ata_eh_freeze_port(ap);
1195}
1196
1197static int sil24_port_start(struct ata_port *ap)
1198{
1199 struct device *dev = ap->host->dev;
1200 struct sil24_port_priv *pp;
1201 union sil24_cmd_block *cb;
1202 size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS;
1203 dma_addr_t cb_dma;
1204
1205 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1206 if (!pp)
1207 return -ENOMEM;
1208
1209 cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
1210 if (!cb)
1211 return -ENOMEM;
1212 memset(cb, 0, cb_size);
1213
1214 pp->cmd_block = cb;
1215 pp->cmd_block_dma = cb_dma;
1216
1217 ap->private_data = pp;
1218
1219 ata_port_pbar_desc(ap, SIL24_HOST_BAR, -1, "host");
1220 ata_port_pbar_desc(ap, SIL24_PORT_BAR, sil24_port_offset(ap), "port");
1221
1222 return 0;
1223}
1224
1225static void sil24_init_controller(struct ata_host *host)
1226{
1227 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1228 u32 tmp;
1229 int i;
1230
1231
1232 writel(0, host_base + HOST_FLASH_CMD);
1233
1234
1235 writel(0, host_base + HOST_CTRL);
1236
1237
1238 for (i = 0; i < host->n_ports; i++) {
1239 struct ata_port *ap = host->ports[i];
1240 void __iomem *port = sil24_port_base(ap);
1241
1242
1243
1244 writel(0x20c, port + PORT_PHY_CFG);
1245
1246
1247 tmp = readl(port + PORT_CTRL_STAT);
1248 if (tmp & PORT_CS_PORT_RST) {
1249 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
1250 tmp = ata_wait_register(NULL, port + PORT_CTRL_STAT,
1251 PORT_CS_PORT_RST,
1252 PORT_CS_PORT_RST, 10, 100);
1253 if (tmp & PORT_CS_PORT_RST)
1254 dev_err(host->dev,
1255 "failed to clear port RST\n");
1256 }
1257
1258
1259 sil24_config_port(ap);
1260 }
1261
1262
1263 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
1264}
1265
1266static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1267{
1268 extern int __MARKER__sil24_cmd_block_is_sized_wrongly;
1269 struct ata_port_info pi = sil24_port_info[ent->driver_data];
1270 const struct ata_port_info *ppi[] = { &pi, NULL };
1271 void __iomem * const *iomap;
1272 struct ata_host *host;
1273 int rc;
1274 u32 tmp;
1275
1276
1277 if (sizeof(union sil24_cmd_block) != PAGE_SIZE)
1278 __MARKER__sil24_cmd_block_is_sized_wrongly = 1;
1279
1280 ata_print_version_once(&pdev->dev, DRV_VERSION);
1281
1282
1283 rc = pcim_enable_device(pdev);
1284 if (rc)
1285 return rc;
1286
1287 rc = pcim_iomap_regions(pdev,
1288 (1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR),
1289 DRV_NAME);
1290 if (rc)
1291 return rc;
1292 iomap = pcim_iomap_table(pdev);
1293
1294
1295 if (pi.flags & SIL24_FLAG_PCIX_IRQ_WOC) {
1296 tmp = readl(iomap[SIL24_HOST_BAR] + HOST_CTRL);
1297 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
1298 dev_info(&pdev->dev,
1299 "Applying completion IRQ loss on PCI-X errata fix\n");
1300 else
1301 pi.flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
1302 }
1303
1304
1305 host = ata_host_alloc_pinfo(&pdev->dev, ppi,
1306 SIL24_FLAG2NPORTS(ppi[0]->flags));
1307 if (!host)
1308 return -ENOMEM;
1309 host->iomap = iomap;
1310
1311
1312 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1313 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1314 if (rc) {
1315 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1316 if (rc) {
1317 dev_err(&pdev->dev,
1318 "64-bit DMA enable failed\n");
1319 return rc;
1320 }
1321 }
1322 } else {
1323 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1324 if (rc) {
1325 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
1326 return rc;
1327 }
1328 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1329 if (rc) {
1330 dev_err(&pdev->dev,
1331 "32-bit consistent DMA enable failed\n");
1332 return rc;
1333 }
1334 }
1335
1336
1337
1338
1339 pcie_set_readrq(pdev, 4096);
1340
1341 sil24_init_controller(host);
1342
1343 if (sata_sil24_msi && !pci_enable_msi(pdev)) {
1344 dev_info(&pdev->dev, "Using MSI\n");
1345 pci_intx(pdev, 0);
1346 }
1347
1348 pci_set_master(pdev);
1349 return ata_host_activate(host, pdev->irq, sil24_interrupt, IRQF_SHARED,
1350 &sil24_sht);
1351}
1352
1353#ifdef CONFIG_PM
1354static int sil24_pci_device_resume(struct pci_dev *pdev)
1355{
1356 struct ata_host *host = pci_get_drvdata(pdev);
1357 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1358 int rc;
1359
1360 rc = ata_pci_device_do_resume(pdev);
1361 if (rc)
1362 return rc;
1363
1364 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND)
1365 writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL);
1366
1367 sil24_init_controller(host);
1368
1369 ata_host_resume(host);
1370
1371 return 0;
1372}
1373
1374static int sil24_port_resume(struct ata_port *ap)
1375{
1376 sil24_config_pmp(ap, ap->nr_pmp_links);
1377 return 0;
1378}
1379#endif
1380
1381module_pci_driver(sil24_pci_driver);
1382
1383MODULE_AUTHOR("Tejun Heo");
1384MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1385MODULE_LICENSE("GPL");
1386MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
1387