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25#include <linux/dma-mapping.h>
26
27#include <drm/drmP.h>
28#include <drm/drm_crtc_helper.h>
29
30#include "nouveau_drm.h"
31#include "nouveau_dma.h"
32#include "nouveau_gem.h"
33#include "nouveau_connector.h"
34#include "nouveau_encoder.h"
35#include "nouveau_crtc.h"
36#include "nouveau_fence.h"
37#include "nv50_display.h"
38
39#include <core/client.h>
40#include <core/gpuobj.h>
41#include <core/class.h>
42
43#include <subdev/timer.h>
44#include <subdev/bar.h>
45#include <subdev/fb.h>
46#include <subdev/i2c.h>
47
48#define EVO_DMA_NR 9
49
50#define EVO_MASTER (0x00)
51#define EVO_FLIP(c) (0x01 + (c))
52#define EVO_OVLY(c) (0x05 + (c))
53#define EVO_OIMM(c) (0x09 + (c))
54#define EVO_CURS(c) (0x0d + (c))
55
56
57#define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
58#define EVO_MAST_NTFY EVO_SYNC( 0, 0x00)
59#define EVO_FLIP_SEM0(c) EVO_SYNC((c) + 1, 0x00)
60#define EVO_FLIP_SEM1(c) EVO_SYNC((c) + 1, 0x10)
61
62#define EVO_CORE_HANDLE (0xd1500000)
63#define EVO_CHAN_HANDLE(t,i) (0xd15c0000 | (((t) & 0x00ff) << 8) | (i))
64#define EVO_CHAN_OCLASS(t,c) ((nv_hclass(c) & 0xff00) | ((t) & 0x00ff))
65#define EVO_PUSH_HANDLE(t,i) (0xd15b0000 | (i) | \
66 (((NV50_DISP_##t##_CLASS) & 0x00ff) << 8))
67
68
69
70
71
72struct nv50_chan {
73 struct nouveau_object *user;
74 u32 handle;
75};
76
77static int
78nv50_chan_create(struct nouveau_object *core, u32 bclass, u8 head,
79 void *data, u32 size, struct nv50_chan *chan)
80{
81 struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
82 const u32 oclass = EVO_CHAN_OCLASS(bclass, core);
83 const u32 handle = EVO_CHAN_HANDLE(bclass, head);
84 int ret;
85
86 ret = nouveau_object_new(client, EVO_CORE_HANDLE, handle,
87 oclass, data, size, &chan->user);
88 if (ret)
89 return ret;
90
91 chan->handle = handle;
92 return 0;
93}
94
95static void
96nv50_chan_destroy(struct nouveau_object *core, struct nv50_chan *chan)
97{
98 struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
99 if (chan->handle)
100 nouveau_object_del(client, EVO_CORE_HANDLE, chan->handle);
101}
102
103
104
105
106
107struct nv50_pioc {
108 struct nv50_chan base;
109};
110
111static void
112nv50_pioc_destroy(struct nouveau_object *core, struct nv50_pioc *pioc)
113{
114 nv50_chan_destroy(core, &pioc->base);
115}
116
117static int
118nv50_pioc_create(struct nouveau_object *core, u32 bclass, u8 head,
119 void *data, u32 size, struct nv50_pioc *pioc)
120{
121 return nv50_chan_create(core, bclass, head, data, size, &pioc->base);
122}
123
124
125
126
127
128struct nv50_dmac {
129 struct nv50_chan base;
130 dma_addr_t handle;
131 u32 *ptr;
132
133
134
135
136 struct mutex lock;
137};
138
139static void
140nv50_dmac_destroy(struct nouveau_object *core, struct nv50_dmac *dmac)
141{
142 if (dmac->ptr) {
143 struct pci_dev *pdev = nv_device(core)->pdev;
144 pci_free_consistent(pdev, PAGE_SIZE, dmac->ptr, dmac->handle);
145 }
146
147 nv50_chan_destroy(core, &dmac->base);
148}
149
150static int
151nv50_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
152{
153 struct nouveau_fb *pfb = nouveau_fb(core);
154 struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
155 struct nouveau_object *object;
156 int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP,
157 NV_DMA_IN_MEMORY_CLASS,
158 &(struct nv_dma_class) {
159 .flags = NV_DMA_TARGET_VRAM |
160 NV_DMA_ACCESS_RDWR,
161 .start = 0,
162 .limit = pfb->ram->size - 1,
163 .conf0 = NV50_DMA_CONF0_ENABLE |
164 NV50_DMA_CONF0_PART_256,
165 }, sizeof(struct nv_dma_class), &object);
166 if (ret)
167 return ret;
168
169 ret = nouveau_object_new(client, parent, NvEvoFB16,
170 NV_DMA_IN_MEMORY_CLASS,
171 &(struct nv_dma_class) {
172 .flags = NV_DMA_TARGET_VRAM |
173 NV_DMA_ACCESS_RDWR,
174 .start = 0,
175 .limit = pfb->ram->size - 1,
176 .conf0 = NV50_DMA_CONF0_ENABLE | 0x70 |
177 NV50_DMA_CONF0_PART_256,
178 }, sizeof(struct nv_dma_class), &object);
179 if (ret)
180 return ret;
181
182 ret = nouveau_object_new(client, parent, NvEvoFB32,
183 NV_DMA_IN_MEMORY_CLASS,
184 &(struct nv_dma_class) {
185 .flags = NV_DMA_TARGET_VRAM |
186 NV_DMA_ACCESS_RDWR,
187 .start = 0,
188 .limit = pfb->ram->size - 1,
189 .conf0 = NV50_DMA_CONF0_ENABLE | 0x7a |
190 NV50_DMA_CONF0_PART_256,
191 }, sizeof(struct nv_dma_class), &object);
192 return ret;
193}
194
195static int
196nvc0_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
197{
198 struct nouveau_fb *pfb = nouveau_fb(core);
199 struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
200 struct nouveau_object *object;
201 int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP,
202 NV_DMA_IN_MEMORY_CLASS,
203 &(struct nv_dma_class) {
204 .flags = NV_DMA_TARGET_VRAM |
205 NV_DMA_ACCESS_RDWR,
206 .start = 0,
207 .limit = pfb->ram->size - 1,
208 .conf0 = NVC0_DMA_CONF0_ENABLE,
209 }, sizeof(struct nv_dma_class), &object);
210 if (ret)
211 return ret;
212
213 ret = nouveau_object_new(client, parent, NvEvoFB16,
214 NV_DMA_IN_MEMORY_CLASS,
215 &(struct nv_dma_class) {
216 .flags = NV_DMA_TARGET_VRAM |
217 NV_DMA_ACCESS_RDWR,
218 .start = 0,
219 .limit = pfb->ram->size - 1,
220 .conf0 = NVC0_DMA_CONF0_ENABLE | 0xfe,
221 }, sizeof(struct nv_dma_class), &object);
222 if (ret)
223 return ret;
224
225 ret = nouveau_object_new(client, parent, NvEvoFB32,
226 NV_DMA_IN_MEMORY_CLASS,
227 &(struct nv_dma_class) {
228 .flags = NV_DMA_TARGET_VRAM |
229 NV_DMA_ACCESS_RDWR,
230 .start = 0,
231 .limit = pfb->ram->size - 1,
232 .conf0 = NVC0_DMA_CONF0_ENABLE | 0xfe,
233 }, sizeof(struct nv_dma_class), &object);
234 return ret;
235}
236
237static int
238nvd0_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
239{
240 struct nouveau_fb *pfb = nouveau_fb(core);
241 struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
242 struct nouveau_object *object;
243 int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP,
244 NV_DMA_IN_MEMORY_CLASS,
245 &(struct nv_dma_class) {
246 .flags = NV_DMA_TARGET_VRAM |
247 NV_DMA_ACCESS_RDWR,
248 .start = 0,
249 .limit = pfb->ram->size - 1,
250 .conf0 = NVD0_DMA_CONF0_ENABLE |
251 NVD0_DMA_CONF0_PAGE_LP,
252 }, sizeof(struct nv_dma_class), &object);
253 if (ret)
254 return ret;
255
256 ret = nouveau_object_new(client, parent, NvEvoFB32,
257 NV_DMA_IN_MEMORY_CLASS,
258 &(struct nv_dma_class) {
259 .flags = NV_DMA_TARGET_VRAM |
260 NV_DMA_ACCESS_RDWR,
261 .start = 0,
262 .limit = pfb->ram->size - 1,
263 .conf0 = NVD0_DMA_CONF0_ENABLE | 0xfe |
264 NVD0_DMA_CONF0_PAGE_LP,
265 }, sizeof(struct nv_dma_class), &object);
266 return ret;
267}
268
269static int
270nv50_dmac_create(struct nouveau_object *core, u32 bclass, u8 head,
271 void *data, u32 size, u64 syncbuf,
272 struct nv50_dmac *dmac)
273{
274 struct nouveau_fb *pfb = nouveau_fb(core);
275 struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
276 struct nouveau_object *object;
277 u32 pushbuf = *(u32 *)data;
278 int ret;
279
280 mutex_init(&dmac->lock);
281
282 dmac->ptr = pci_alloc_consistent(nv_device(core)->pdev, PAGE_SIZE,
283 &dmac->handle);
284 if (!dmac->ptr)
285 return -ENOMEM;
286
287 ret = nouveau_object_new(client, NVDRM_DEVICE, pushbuf,
288 NV_DMA_FROM_MEMORY_CLASS,
289 &(struct nv_dma_class) {
290 .flags = NV_DMA_TARGET_PCI_US |
291 NV_DMA_ACCESS_RD,
292 .start = dmac->handle + 0x0000,
293 .limit = dmac->handle + 0x0fff,
294 }, sizeof(struct nv_dma_class), &object);
295 if (ret)
296 return ret;
297
298 ret = nv50_chan_create(core, bclass, head, data, size, &dmac->base);
299 if (ret)
300 return ret;
301
302 ret = nouveau_object_new(client, dmac->base.handle, NvEvoSync,
303 NV_DMA_IN_MEMORY_CLASS,
304 &(struct nv_dma_class) {
305 .flags = NV_DMA_TARGET_VRAM |
306 NV_DMA_ACCESS_RDWR,
307 .start = syncbuf + 0x0000,
308 .limit = syncbuf + 0x0fff,
309 }, sizeof(struct nv_dma_class), &object);
310 if (ret)
311 return ret;
312
313 ret = nouveau_object_new(client, dmac->base.handle, NvEvoVRAM,
314 NV_DMA_IN_MEMORY_CLASS,
315 &(struct nv_dma_class) {
316 .flags = NV_DMA_TARGET_VRAM |
317 NV_DMA_ACCESS_RDWR,
318 .start = 0,
319 .limit = pfb->ram->size - 1,
320 }, sizeof(struct nv_dma_class), &object);
321 if (ret)
322 return ret;
323
324 if (nv_device(core)->card_type < NV_C0)
325 ret = nv50_dmac_create_fbdma(core, dmac->base.handle);
326 else
327 if (nv_device(core)->card_type < NV_D0)
328 ret = nvc0_dmac_create_fbdma(core, dmac->base.handle);
329 else
330 ret = nvd0_dmac_create_fbdma(core, dmac->base.handle);
331 return ret;
332}
333
334struct nv50_mast {
335 struct nv50_dmac base;
336};
337
338struct nv50_curs {
339 struct nv50_pioc base;
340};
341
342struct nv50_sync {
343 struct nv50_dmac base;
344 u32 addr;
345 u32 data;
346};
347
348struct nv50_ovly {
349 struct nv50_dmac base;
350};
351
352struct nv50_oimm {
353 struct nv50_pioc base;
354};
355
356struct nv50_head {
357 struct nouveau_crtc base;
358 struct nouveau_bo *image;
359 struct nv50_curs curs;
360 struct nv50_sync sync;
361 struct nv50_ovly ovly;
362 struct nv50_oimm oimm;
363};
364
365#define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c))
366#define nv50_curs(c) (&nv50_head(c)->curs)
367#define nv50_sync(c) (&nv50_head(c)->sync)
368#define nv50_ovly(c) (&nv50_head(c)->ovly)
369#define nv50_oimm(c) (&nv50_head(c)->oimm)
370#define nv50_chan(c) (&(c)->base.base)
371#define nv50_vers(c) nv_mclass(nv50_chan(c)->user)
372
373struct nv50_disp {
374 struct nouveau_object *core;
375 struct nv50_mast mast;
376
377 u32 modeset;
378
379 struct nouveau_bo *sync;
380};
381
382static struct nv50_disp *
383nv50_disp(struct drm_device *dev)
384{
385 return nouveau_display(dev)->priv;
386}
387
388#define nv50_mast(d) (&nv50_disp(d)->mast)
389
390static struct drm_crtc *
391nv50_display_crtc_get(struct drm_encoder *encoder)
392{
393 return nouveau_encoder(encoder)->crtc;
394}
395
396
397
398
399static u32 *
400evo_wait(void *evoc, int nr)
401{
402 struct nv50_dmac *dmac = evoc;
403 u32 put = nv_ro32(dmac->base.user, 0x0000) / 4;
404
405 mutex_lock(&dmac->lock);
406 if (put + nr >= (PAGE_SIZE / 4) - 8) {
407 dmac->ptr[put] = 0x20000000;
408
409 nv_wo32(dmac->base.user, 0x0000, 0x00000000);
410 if (!nv_wait(dmac->base.user, 0x0004, ~0, 0x00000000)) {
411 mutex_unlock(&dmac->lock);
412 NV_ERROR(dmac->base.user, "channel stalled\n");
413 return NULL;
414 }
415
416 put = 0;
417 }
418
419 return dmac->ptr + put;
420}
421
422static void
423evo_kick(u32 *push, void *evoc)
424{
425 struct nv50_dmac *dmac = evoc;
426 nv_wo32(dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
427 mutex_unlock(&dmac->lock);
428}
429
430#define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m))
431#define evo_data(p,d) *((p)++) = (d)
432
433static bool
434evo_sync_wait(void *data)
435{
436 if (nouveau_bo_rd32(data, EVO_MAST_NTFY) != 0x00000000)
437 return true;
438 usleep_range(1, 2);
439 return false;
440}
441
442static int
443evo_sync(struct drm_device *dev)
444{
445 struct nouveau_device *device = nouveau_dev(dev);
446 struct nv50_disp *disp = nv50_disp(dev);
447 struct nv50_mast *mast = nv50_mast(dev);
448 u32 *push = evo_wait(mast, 8);
449 if (push) {
450 nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000);
451 evo_mthd(push, 0x0084, 1);
452 evo_data(push, 0x80000000 | EVO_MAST_NTFY);
453 evo_mthd(push, 0x0080, 2);
454 evo_data(push, 0x00000000);
455 evo_data(push, 0x00000000);
456 evo_kick(push, mast);
457 if (nv_wait_cb(device, evo_sync_wait, disp->sync))
458 return 0;
459 }
460
461 return -EBUSY;
462}
463
464
465
466
467struct nouveau_bo *
468nv50_display_crtc_sema(struct drm_device *dev, int crtc)
469{
470 return nv50_disp(dev)->sync;
471}
472
473struct nv50_display_flip {
474 struct nv50_disp *disp;
475 struct nv50_sync *chan;
476};
477
478static bool
479nv50_display_flip_wait(void *data)
480{
481 struct nv50_display_flip *flip = data;
482 if (nouveau_bo_rd32(flip->disp->sync, flip->chan->addr / 4) ==
483 flip->chan->data)
484 return true;
485 usleep_range(1, 2);
486 return false;
487}
488
489void
490nv50_display_flip_stop(struct drm_crtc *crtc)
491{
492 struct nouveau_device *device = nouveau_dev(crtc->dev);
493 struct nv50_display_flip flip = {
494 .disp = nv50_disp(crtc->dev),
495 .chan = nv50_sync(crtc),
496 };
497 u32 *push;
498
499 push = evo_wait(flip.chan, 8);
500 if (push) {
501 evo_mthd(push, 0x0084, 1);
502 evo_data(push, 0x00000000);
503 evo_mthd(push, 0x0094, 1);
504 evo_data(push, 0x00000000);
505 evo_mthd(push, 0x00c0, 1);
506 evo_data(push, 0x00000000);
507 evo_mthd(push, 0x0080, 1);
508 evo_data(push, 0x00000000);
509 evo_kick(push, flip.chan);
510 }
511
512 nv_wait_cb(device, nv50_display_flip_wait, &flip);
513}
514
515int
516nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
517 struct nouveau_channel *chan, u32 swap_interval)
518{
519 struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
520 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
521 struct nv50_head *head = nv50_head(crtc);
522 struct nv50_sync *sync = nv50_sync(crtc);
523 u32 *push;
524 int ret;
525
526 swap_interval <<= 4;
527 if (swap_interval == 0)
528 swap_interval |= 0x100;
529 if (chan == NULL)
530 evo_sync(crtc->dev);
531
532 push = evo_wait(sync, 128);
533 if (unlikely(push == NULL))
534 return -EBUSY;
535
536 if (chan && nv_mclass(chan->object) < NV84_CHANNEL_IND_CLASS) {
537 ret = RING_SPACE(chan, 8);
538 if (ret)
539 return ret;
540
541 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2);
542 OUT_RING (chan, NvEvoSema0 + nv_crtc->index);
543 OUT_RING (chan, sync->addr ^ 0x10);
544 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1);
545 OUT_RING (chan, sync->data + 1);
546 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET, 2);
547 OUT_RING (chan, sync->addr);
548 OUT_RING (chan, sync->data);
549 } else
550 if (chan && nv_mclass(chan->object) < NVC0_CHANNEL_IND_CLASS) {
551 u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr;
552 ret = RING_SPACE(chan, 12);
553 if (ret)
554 return ret;
555
556 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
557 OUT_RING (chan, chan->vram);
558 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
559 OUT_RING (chan, upper_32_bits(addr ^ 0x10));
560 OUT_RING (chan, lower_32_bits(addr ^ 0x10));
561 OUT_RING (chan, sync->data + 1);
562 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
563 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
564 OUT_RING (chan, upper_32_bits(addr));
565 OUT_RING (chan, lower_32_bits(addr));
566 OUT_RING (chan, sync->data);
567 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL);
568 } else
569 if (chan) {
570 u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr;
571 ret = RING_SPACE(chan, 10);
572 if (ret)
573 return ret;
574
575 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
576 OUT_RING (chan, upper_32_bits(addr ^ 0x10));
577 OUT_RING (chan, lower_32_bits(addr ^ 0x10));
578 OUT_RING (chan, sync->data + 1);
579 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG |
580 NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
581 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
582 OUT_RING (chan, upper_32_bits(addr));
583 OUT_RING (chan, lower_32_bits(addr));
584 OUT_RING (chan, sync->data);
585 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL |
586 NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
587 }
588
589 if (chan) {
590 sync->addr ^= 0x10;
591 sync->data++;
592 FIRE_RING (chan);
593 }
594
595
596 evo_mthd(push, 0x0100, 1);
597 evo_data(push, 0xfffe0000);
598 evo_mthd(push, 0x0084, 1);
599 evo_data(push, swap_interval);
600 if (!(swap_interval & 0x00000100)) {
601 evo_mthd(push, 0x00e0, 1);
602 evo_data(push, 0x40000000);
603 }
604 evo_mthd(push, 0x0088, 4);
605 evo_data(push, sync->addr);
606 evo_data(push, sync->data++);
607 evo_data(push, sync->data);
608 evo_data(push, NvEvoSync);
609 evo_mthd(push, 0x00a0, 2);
610 evo_data(push, 0x00000000);
611 evo_data(push, 0x00000000);
612 evo_mthd(push, 0x00c0, 1);
613 evo_data(push, nv_fb->r_dma);
614 evo_mthd(push, 0x0110, 2);
615 evo_data(push, 0x00000000);
616 evo_data(push, 0x00000000);
617 if (nv50_vers(sync) < NVD0_DISP_SYNC_CLASS) {
618 evo_mthd(push, 0x0800, 5);
619 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
620 evo_data(push, 0);
621 evo_data(push, (fb->height << 16) | fb->width);
622 evo_data(push, nv_fb->r_pitch);
623 evo_data(push, nv_fb->r_format);
624 } else {
625 evo_mthd(push, 0x0400, 5);
626 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
627 evo_data(push, 0);
628 evo_data(push, (fb->height << 16) | fb->width);
629 evo_data(push, nv_fb->r_pitch);
630 evo_data(push, nv_fb->r_format);
631 }
632 evo_mthd(push, 0x0080, 1);
633 evo_data(push, 0x00000000);
634 evo_kick(push, sync);
635
636 nouveau_bo_ref(nv_fb->nvbo, &head->image);
637 return 0;
638}
639
640
641
642
643static int
644nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update)
645{
646 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
647 struct nouveau_connector *nv_connector;
648 struct drm_connector *connector;
649 u32 *push, mode = 0x00;
650
651 nv_connector = nouveau_crtc_connector_get(nv_crtc);
652 connector = &nv_connector->base;
653 if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) {
654 if (nv_crtc->base.primary->fb->depth > connector->display_info.bpc * 3)
655 mode = DITHERING_MODE_DYNAMIC2X2;
656 } else {
657 mode = nv_connector->dithering_mode;
658 }
659
660 if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) {
661 if (connector->display_info.bpc >= 8)
662 mode |= DITHERING_DEPTH_8BPC;
663 } else {
664 mode |= nv_connector->dithering_depth;
665 }
666
667 push = evo_wait(mast, 4);
668 if (push) {
669 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
670 evo_mthd(push, 0x08a0 + (nv_crtc->index * 0x0400), 1);
671 evo_data(push, mode);
672 } else
673 if (nv50_vers(mast) < NVE0_DISP_MAST_CLASS) {
674 evo_mthd(push, 0x0490 + (nv_crtc->index * 0x0300), 1);
675 evo_data(push, mode);
676 } else {
677 evo_mthd(push, 0x04a0 + (nv_crtc->index * 0x0300), 1);
678 evo_data(push, mode);
679 }
680
681 if (update) {
682 evo_mthd(push, 0x0080, 1);
683 evo_data(push, 0x00000000);
684 }
685 evo_kick(push, mast);
686 }
687
688 return 0;
689}
690
691static int
692nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update)
693{
694 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
695 struct drm_display_mode *omode, *umode = &nv_crtc->base.mode;
696 struct drm_crtc *crtc = &nv_crtc->base;
697 struct nouveau_connector *nv_connector;
698 int mode = DRM_MODE_SCALE_NONE;
699 u32 oX, oY, *push;
700
701
702
703
704 nv_connector = nouveau_crtc_connector_get(nv_crtc);
705 if (nv_connector && nv_connector->native_mode)
706 mode = nv_connector->scaling_mode;
707
708 if (mode != DRM_MODE_SCALE_NONE)
709 omode = nv_connector->native_mode;
710 else
711 omode = umode;
712
713 oX = omode->hdisplay;
714 oY = omode->vdisplay;
715 if (omode->flags & DRM_MODE_FLAG_DBLSCAN)
716 oY *= 2;
717
718
719
720
721
722 if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON ||
723 (nv_connector->underscan == UNDERSCAN_AUTO &&
724 nv_connector->edid &&
725 drm_detect_hdmi_monitor(nv_connector->edid)))) {
726 u32 bX = nv_connector->underscan_hborder;
727 u32 bY = nv_connector->underscan_vborder;
728 u32 aspect = (oY << 19) / oX;
729
730 if (bX) {
731 oX -= (bX * 2);
732 if (bY) oY -= (bY * 2);
733 else oY = ((oX * aspect) + (aspect / 2)) >> 19;
734 } else {
735 oX -= (oX >> 4) + 32;
736 if (bY) oY -= (bY * 2);
737 else oY = ((oX * aspect) + (aspect / 2)) >> 19;
738 }
739 }
740
741
742
743
744 switch (mode) {
745 case DRM_MODE_SCALE_CENTER:
746 oX = min((u32)umode->hdisplay, oX);
747 oY = min((u32)umode->vdisplay, oY);
748
749 case DRM_MODE_SCALE_ASPECT:
750 if (oY < oX) {
751 u32 aspect = (umode->hdisplay << 19) / umode->vdisplay;
752 oX = ((oY * aspect) + (aspect / 2)) >> 19;
753 } else {
754 u32 aspect = (umode->vdisplay << 19) / umode->hdisplay;
755 oY = ((oX * aspect) + (aspect / 2)) >> 19;
756 }
757 break;
758 default:
759 break;
760 }
761
762 push = evo_wait(mast, 8);
763 if (push) {
764 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
765
766 evo_mthd(push, 0x08d8 + (nv_crtc->index * 0x400), 2);
767 evo_data(push, (oY << 16) | oX);
768 evo_data(push, (oY << 16) | oX);
769 evo_mthd(push, 0x08a4 + (nv_crtc->index * 0x400), 1);
770 evo_data(push, 0x00000000);
771 evo_mthd(push, 0x08c8 + (nv_crtc->index * 0x400), 1);
772 evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
773 } else {
774 evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3);
775 evo_data(push, (oY << 16) | oX);
776 evo_data(push, (oY << 16) | oX);
777 evo_data(push, (oY << 16) | oX);
778 evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1);
779 evo_data(push, 0x00000000);
780 evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1);
781 evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
782 }
783
784 evo_kick(push, mast);
785
786 if (update) {
787 nv50_display_flip_stop(crtc);
788 nv50_display_flip_next(crtc, crtc->primary->fb,
789 NULL, 1);
790 }
791 }
792
793 return 0;
794}
795
796static int
797nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update)
798{
799 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
800 u32 *push, hue, vib;
801 int adj;
802
803 adj = (nv_crtc->color_vibrance > 0) ? 50 : 0;
804 vib = ((nv_crtc->color_vibrance * 2047 + adj) / 100) & 0xfff;
805 hue = ((nv_crtc->vibrant_hue * 2047) / 100) & 0xfff;
806
807 push = evo_wait(mast, 16);
808 if (push) {
809 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
810 evo_mthd(push, 0x08a8 + (nv_crtc->index * 0x400), 1);
811 evo_data(push, (hue << 20) | (vib << 8));
812 } else {
813 evo_mthd(push, 0x0498 + (nv_crtc->index * 0x300), 1);
814 evo_data(push, (hue << 20) | (vib << 8));
815 }
816
817 if (update) {
818 evo_mthd(push, 0x0080, 1);
819 evo_data(push, 0x00000000);
820 }
821 evo_kick(push, mast);
822 }
823
824 return 0;
825}
826
827static int
828nv50_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb,
829 int x, int y, bool update)
830{
831 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb);
832 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
833 u32 *push;
834
835 push = evo_wait(mast, 16);
836 if (push) {
837 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
838 evo_mthd(push, 0x0860 + (nv_crtc->index * 0x400), 1);
839 evo_data(push, nvfb->nvbo->bo.offset >> 8);
840 evo_mthd(push, 0x0868 + (nv_crtc->index * 0x400), 3);
841 evo_data(push, (fb->height << 16) | fb->width);
842 evo_data(push, nvfb->r_pitch);
843 evo_data(push, nvfb->r_format);
844 evo_mthd(push, 0x08c0 + (nv_crtc->index * 0x400), 1);
845 evo_data(push, (y << 16) | x);
846 if (nv50_vers(mast) > NV50_DISP_MAST_CLASS) {
847 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
848 evo_data(push, nvfb->r_dma);
849 }
850 } else {
851 evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1);
852 evo_data(push, nvfb->nvbo->bo.offset >> 8);
853 evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4);
854 evo_data(push, (fb->height << 16) | fb->width);
855 evo_data(push, nvfb->r_pitch);
856 evo_data(push, nvfb->r_format);
857 evo_data(push, nvfb->r_dma);
858 evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1);
859 evo_data(push, (y << 16) | x);
860 }
861
862 if (update) {
863 evo_mthd(push, 0x0080, 1);
864 evo_data(push, 0x00000000);
865 }
866 evo_kick(push, mast);
867 }
868
869 nv_crtc->fb.tile_flags = nvfb->r_dma;
870 return 0;
871}
872
873static void
874nv50_crtc_cursor_show(struct nouveau_crtc *nv_crtc)
875{
876 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
877 u32 *push = evo_wait(mast, 16);
878 if (push) {
879 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
880 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
881 evo_data(push, 0x85000000);
882 evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
883 } else
884 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
885 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
886 evo_data(push, 0x85000000);
887 evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
888 evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
889 evo_data(push, NvEvoVRAM);
890 } else {
891 evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2);
892 evo_data(push, 0x85000000);
893 evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
894 evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
895 evo_data(push, NvEvoVRAM);
896 }
897 evo_kick(push, mast);
898 }
899}
900
901static void
902nv50_crtc_cursor_hide(struct nouveau_crtc *nv_crtc)
903{
904 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
905 u32 *push = evo_wait(mast, 16);
906 if (push) {
907 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
908 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
909 evo_data(push, 0x05000000);
910 } else
911 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
912 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
913 evo_data(push, 0x05000000);
914 evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
915 evo_data(push, 0x00000000);
916 } else {
917 evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1);
918 evo_data(push, 0x05000000);
919 evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
920 evo_data(push, 0x00000000);
921 }
922 evo_kick(push, mast);
923 }
924}
925
926static void
927nv50_crtc_cursor_show_hide(struct nouveau_crtc *nv_crtc, bool show, bool update)
928{
929 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
930
931 if (show)
932 nv50_crtc_cursor_show(nv_crtc);
933 else
934 nv50_crtc_cursor_hide(nv_crtc);
935
936 if (update) {
937 u32 *push = evo_wait(mast, 2);
938 if (push) {
939 evo_mthd(push, 0x0080, 1);
940 evo_data(push, 0x00000000);
941 evo_kick(push, mast);
942 }
943 }
944}
945
946static void
947nv50_crtc_dpms(struct drm_crtc *crtc, int mode)
948{
949}
950
951static void
952nv50_crtc_prepare(struct drm_crtc *crtc)
953{
954 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
955 struct nv50_mast *mast = nv50_mast(crtc->dev);
956 u32 *push;
957
958 nv50_display_flip_stop(crtc);
959
960 push = evo_wait(mast, 2);
961 if (push) {
962 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
963 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
964 evo_data(push, 0x00000000);
965 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
966 evo_data(push, 0x40000000);
967 } else
968 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
969 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
970 evo_data(push, 0x00000000);
971 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
972 evo_data(push, 0x40000000);
973 evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
974 evo_data(push, 0x00000000);
975 } else {
976 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
977 evo_data(push, 0x00000000);
978 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1);
979 evo_data(push, 0x03000000);
980 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
981 evo_data(push, 0x00000000);
982 }
983
984 evo_kick(push, mast);
985 }
986
987 nv50_crtc_cursor_show_hide(nv_crtc, false, false);
988}
989
990static void
991nv50_crtc_commit(struct drm_crtc *crtc)
992{
993 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
994 struct nv50_mast *mast = nv50_mast(crtc->dev);
995 u32 *push;
996
997 push = evo_wait(mast, 32);
998 if (push) {
999 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
1000 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1001 evo_data(push, NvEvoVRAM_LP);
1002 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
1003 evo_data(push, 0xc0000000);
1004 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1005 } else
1006 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
1007 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1008 evo_data(push, nv_crtc->fb.tile_flags);
1009 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
1010 evo_data(push, 0xc0000000);
1011 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1012 evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
1013 evo_data(push, NvEvoVRAM);
1014 } else {
1015 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
1016 evo_data(push, nv_crtc->fb.tile_flags);
1017 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4);
1018 evo_data(push, 0x83000000);
1019 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1020 evo_data(push, 0x00000000);
1021 evo_data(push, 0x00000000);
1022 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
1023 evo_data(push, NvEvoVRAM);
1024 evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1);
1025 evo_data(push, 0xffffff00);
1026 }
1027
1028 evo_kick(push, mast);
1029 }
1030
1031 nv50_crtc_cursor_show_hide(nv_crtc, nv_crtc->cursor.visible, true);
1032 nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1);
1033}
1034
1035static bool
1036nv50_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode,
1037 struct drm_display_mode *adjusted_mode)
1038{
1039 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
1040 return true;
1041}
1042
1043static int
1044nv50_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
1045{
1046 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->primary->fb);
1047 struct nv50_head *head = nv50_head(crtc);
1048 int ret;
1049
1050 ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM);
1051 if (ret == 0) {
1052 if (head->image)
1053 nouveau_bo_unpin(head->image);
1054 nouveau_bo_ref(nvfb->nvbo, &head->image);
1055 }
1056
1057 return ret;
1058}
1059
1060static int
1061nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
1062 struct drm_display_mode *mode, int x, int y,
1063 struct drm_framebuffer *old_fb)
1064{
1065 struct nv50_mast *mast = nv50_mast(crtc->dev);
1066 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1067 struct nouveau_connector *nv_connector;
1068 u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1;
1069 u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1;
1070 u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks;
1071 u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks;
1072 u32 vblan2e = 0, vblan2s = 1;
1073 u32 *push;
1074 int ret;
1075
1076 hactive = mode->htotal;
1077 hsynce = mode->hsync_end - mode->hsync_start - 1;
1078 hbackp = mode->htotal - mode->hsync_end;
1079 hblanke = hsynce + hbackp;
1080 hfrontp = mode->hsync_start - mode->hdisplay;
1081 hblanks = mode->htotal - hfrontp - 1;
1082
1083 vactive = mode->vtotal * vscan / ilace;
1084 vsynce = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1;
1085 vbackp = (mode->vtotal - mode->vsync_end) * vscan / ilace;
1086 vblanke = vsynce + vbackp;
1087 vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace;
1088 vblanks = vactive - vfrontp - 1;
1089 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1090 vblan2e = vactive + vsynce + vbackp;
1091 vblan2s = vblan2e + (mode->vdisplay * vscan / ilace);
1092 vactive = (vactive * 2) + 1;
1093 }
1094
1095 ret = nv50_crtc_swap_fbs(crtc, old_fb);
1096 if (ret)
1097 return ret;
1098
1099 push = evo_wait(mast, 64);
1100 if (push) {
1101 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
1102 evo_mthd(push, 0x0804 + (nv_crtc->index * 0x400), 2);
1103 evo_data(push, 0x00800000 | mode->clock);
1104 evo_data(push, (ilace == 2) ? 2 : 0);
1105 evo_mthd(push, 0x0810 + (nv_crtc->index * 0x400), 6);
1106 evo_data(push, 0x00000000);
1107 evo_data(push, (vactive << 16) | hactive);
1108 evo_data(push, ( vsynce << 16) | hsynce);
1109 evo_data(push, (vblanke << 16) | hblanke);
1110 evo_data(push, (vblanks << 16) | hblanks);
1111 evo_data(push, (vblan2e << 16) | vblan2s);
1112 evo_mthd(push, 0x082c + (nv_crtc->index * 0x400), 1);
1113 evo_data(push, 0x00000000);
1114 evo_mthd(push, 0x0900 + (nv_crtc->index * 0x400), 2);
1115 evo_data(push, 0x00000311);
1116 evo_data(push, 0x00000100);
1117 } else {
1118 evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 6);
1119 evo_data(push, 0x00000000);
1120 evo_data(push, (vactive << 16) | hactive);
1121 evo_data(push, ( vsynce << 16) | hsynce);
1122 evo_data(push, (vblanke << 16) | hblanke);
1123 evo_data(push, (vblanks << 16) | hblanks);
1124 evo_data(push, (vblan2e << 16) | vblan2s);
1125 evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1);
1126 evo_data(push, 0x00000000);
1127 evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3);
1128 evo_data(push, mode->clock * 1000);
1129 evo_data(push, 0x00200000);
1130 evo_data(push, mode->clock * 1000);
1131 evo_mthd(push, 0x04d0 + (nv_crtc->index * 0x300), 2);
1132 evo_data(push, 0x00000311);
1133 evo_data(push, 0x00000100);
1134 }
1135
1136 evo_kick(push, mast);
1137 }
1138
1139 nv_connector = nouveau_crtc_connector_get(nv_crtc);
1140 nv50_crtc_set_dither(nv_crtc, false);
1141 nv50_crtc_set_scale(nv_crtc, false);
1142 nv50_crtc_set_color_vibrance(nv_crtc, false);
1143 nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, false);
1144 return 0;
1145}
1146
1147static int
1148nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
1149 struct drm_framebuffer *old_fb)
1150{
1151 struct nouveau_drm *drm = nouveau_drm(crtc->dev);
1152 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1153 int ret;
1154
1155 if (!crtc->primary->fb) {
1156 NV_DEBUG(drm, "No FB bound\n");
1157 return 0;
1158 }
1159
1160 ret = nv50_crtc_swap_fbs(crtc, old_fb);
1161 if (ret)
1162 return ret;
1163
1164 nv50_display_flip_stop(crtc);
1165 nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, true);
1166 nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1);
1167 return 0;
1168}
1169
1170static int
1171nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
1172 struct drm_framebuffer *fb, int x, int y,
1173 enum mode_set_atomic state)
1174{
1175 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1176 nv50_display_flip_stop(crtc);
1177 nv50_crtc_set_image(nv_crtc, fb, x, y, true);
1178 return 0;
1179}
1180
1181static void
1182nv50_crtc_lut_load(struct drm_crtc *crtc)
1183{
1184 struct nv50_disp *disp = nv50_disp(crtc->dev);
1185 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1186 void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
1187 int i;
1188
1189 for (i = 0; i < 256; i++) {
1190 u16 r = nv_crtc->lut.r[i] >> 2;
1191 u16 g = nv_crtc->lut.g[i] >> 2;
1192 u16 b = nv_crtc->lut.b[i] >> 2;
1193
1194 if (nv_mclass(disp->core) < NVD0_DISP_CLASS) {
1195 writew(r + 0x0000, lut + (i * 0x08) + 0);
1196 writew(g + 0x0000, lut + (i * 0x08) + 2);
1197 writew(b + 0x0000, lut + (i * 0x08) + 4);
1198 } else {
1199 writew(r + 0x6000, lut + (i * 0x20) + 0);
1200 writew(g + 0x6000, lut + (i * 0x20) + 2);
1201 writew(b + 0x6000, lut + (i * 0x20) + 4);
1202 }
1203 }
1204}
1205
1206static void
1207nv50_crtc_disable(struct drm_crtc *crtc)
1208{
1209 struct nv50_head *head = nv50_head(crtc);
1210 if (head->image)
1211 nouveau_bo_unpin(head->image);
1212 nouveau_bo_ref(NULL, &head->image);
1213}
1214
1215static int
1216nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
1217 uint32_t handle, uint32_t width, uint32_t height)
1218{
1219 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1220 struct drm_device *dev = crtc->dev;
1221 struct drm_gem_object *gem;
1222 struct nouveau_bo *nvbo;
1223 bool visible = (handle != 0);
1224 int i, ret = 0;
1225
1226 if (visible) {
1227 if (width != 64 || height != 64)
1228 return -EINVAL;
1229
1230 gem = drm_gem_object_lookup(dev, file_priv, handle);
1231 if (unlikely(!gem))
1232 return -ENOENT;
1233 nvbo = nouveau_gem_object(gem);
1234
1235 ret = nouveau_bo_map(nvbo);
1236 if (ret == 0) {
1237 for (i = 0; i < 64 * 64; i++) {
1238 u32 v = nouveau_bo_rd32(nvbo, i);
1239 nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, v);
1240 }
1241 nouveau_bo_unmap(nvbo);
1242 }
1243
1244 drm_gem_object_unreference_unlocked(gem);
1245 }
1246
1247 if (visible != nv_crtc->cursor.visible) {
1248 nv50_crtc_cursor_show_hide(nv_crtc, visible, true);
1249 nv_crtc->cursor.visible = visible;
1250 }
1251
1252 return ret;
1253}
1254
1255static int
1256nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1257{
1258 struct nv50_curs *curs = nv50_curs(crtc);
1259 struct nv50_chan *chan = nv50_chan(curs);
1260 nv_wo32(chan->user, 0x0084, (y << 16) | (x & 0xffff));
1261 nv_wo32(chan->user, 0x0080, 0x00000000);
1262 return 0;
1263}
1264
1265static void
1266nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
1267 uint32_t start, uint32_t size)
1268{
1269 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1270 u32 end = min_t(u32, start + size, 256);
1271 u32 i;
1272
1273 for (i = start; i < end; i++) {
1274 nv_crtc->lut.r[i] = r[i];
1275 nv_crtc->lut.g[i] = g[i];
1276 nv_crtc->lut.b[i] = b[i];
1277 }
1278
1279 nv50_crtc_lut_load(crtc);
1280}
1281
1282static void
1283nv50_crtc_destroy(struct drm_crtc *crtc)
1284{
1285 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1286 struct nv50_disp *disp = nv50_disp(crtc->dev);
1287 struct nv50_head *head = nv50_head(crtc);
1288
1289 nv50_dmac_destroy(disp->core, &head->ovly.base);
1290 nv50_pioc_destroy(disp->core, &head->oimm.base);
1291 nv50_dmac_destroy(disp->core, &head->sync.base);
1292 nv50_pioc_destroy(disp->core, &head->curs.base);
1293
1294
1295
1296
1297 if (head->image)
1298 nouveau_bo_unpin(head->image);
1299 nouveau_bo_ref(NULL, &head->image);
1300
1301 nouveau_bo_unmap(nv_crtc->cursor.nvbo);
1302 if (nv_crtc->cursor.nvbo)
1303 nouveau_bo_unpin(nv_crtc->cursor.nvbo);
1304 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
1305
1306 nouveau_bo_unmap(nv_crtc->lut.nvbo);
1307 if (nv_crtc->lut.nvbo)
1308 nouveau_bo_unpin(nv_crtc->lut.nvbo);
1309 nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
1310
1311 drm_crtc_cleanup(crtc);
1312 kfree(crtc);
1313}
1314
1315static const struct drm_crtc_helper_funcs nv50_crtc_hfunc = {
1316 .dpms = nv50_crtc_dpms,
1317 .prepare = nv50_crtc_prepare,
1318 .commit = nv50_crtc_commit,
1319 .mode_fixup = nv50_crtc_mode_fixup,
1320 .mode_set = nv50_crtc_mode_set,
1321 .mode_set_base = nv50_crtc_mode_set_base,
1322 .mode_set_base_atomic = nv50_crtc_mode_set_base_atomic,
1323 .load_lut = nv50_crtc_lut_load,
1324 .disable = nv50_crtc_disable,
1325};
1326
1327static const struct drm_crtc_funcs nv50_crtc_func = {
1328 .cursor_set = nv50_crtc_cursor_set,
1329 .cursor_move = nv50_crtc_cursor_move,
1330 .gamma_set = nv50_crtc_gamma_set,
1331 .set_config = nouveau_crtc_set_config,
1332 .destroy = nv50_crtc_destroy,
1333 .page_flip = nouveau_crtc_page_flip,
1334};
1335
1336static void
1337nv50_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y)
1338{
1339}
1340
1341static void
1342nv50_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset)
1343{
1344}
1345
1346static int
1347nv50_crtc_create(struct drm_device *dev, struct nouveau_object *core, int index)
1348{
1349 struct nv50_disp *disp = nv50_disp(dev);
1350 struct nv50_head *head;
1351 struct drm_crtc *crtc;
1352 int ret, i;
1353
1354 head = kzalloc(sizeof(*head), GFP_KERNEL);
1355 if (!head)
1356 return -ENOMEM;
1357
1358 head->base.index = index;
1359 head->base.set_dither = nv50_crtc_set_dither;
1360 head->base.set_scale = nv50_crtc_set_scale;
1361 head->base.set_color_vibrance = nv50_crtc_set_color_vibrance;
1362 head->base.color_vibrance = 50;
1363 head->base.vibrant_hue = 0;
1364 head->base.cursor.set_offset = nv50_cursor_set_offset;
1365 head->base.cursor.set_pos = nv50_cursor_set_pos;
1366 for (i = 0; i < 256; i++) {
1367 head->base.lut.r[i] = i << 8;
1368 head->base.lut.g[i] = i << 8;
1369 head->base.lut.b[i] = i << 8;
1370 }
1371
1372 crtc = &head->base.base;
1373 drm_crtc_init(dev, crtc, &nv50_crtc_func);
1374 drm_crtc_helper_add(crtc, &nv50_crtc_hfunc);
1375 drm_mode_crtc_set_gamma_size(crtc, 256);
1376
1377 ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM,
1378 0, 0x0000, NULL, &head->base.lut.nvbo);
1379 if (!ret) {
1380 ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM);
1381 if (!ret) {
1382 ret = nouveau_bo_map(head->base.lut.nvbo);
1383 if (ret)
1384 nouveau_bo_unpin(head->base.lut.nvbo);
1385 }
1386 if (ret)
1387 nouveau_bo_ref(NULL, &head->base.lut.nvbo);
1388 }
1389
1390 if (ret)
1391 goto out;
1392
1393 nv50_crtc_lut_load(crtc);
1394
1395
1396 ret = nv50_pioc_create(disp->core, NV50_DISP_CURS_CLASS, index,
1397 &(struct nv50_display_curs_class) {
1398 .head = index,
1399 }, sizeof(struct nv50_display_curs_class),
1400 &head->curs.base);
1401 if (ret)
1402 goto out;
1403
1404 ret = nouveau_bo_new(dev, 64 * 64 * 4, 0x100, TTM_PL_FLAG_VRAM,
1405 0, 0x0000, NULL, &head->base.cursor.nvbo);
1406 if (!ret) {
1407 ret = nouveau_bo_pin(head->base.cursor.nvbo, TTM_PL_FLAG_VRAM);
1408 if (!ret) {
1409 ret = nouveau_bo_map(head->base.cursor.nvbo);
1410 if (ret)
1411 nouveau_bo_unpin(head->base.lut.nvbo);
1412 }
1413 if (ret)
1414 nouveau_bo_ref(NULL, &head->base.cursor.nvbo);
1415 }
1416
1417 if (ret)
1418 goto out;
1419
1420
1421 ret = nv50_dmac_create(disp->core, NV50_DISP_SYNC_CLASS, index,
1422 &(struct nv50_display_sync_class) {
1423 .pushbuf = EVO_PUSH_HANDLE(SYNC, index),
1424 .head = index,
1425 }, sizeof(struct nv50_display_sync_class),
1426 disp->sync->bo.offset, &head->sync.base);
1427 if (ret)
1428 goto out;
1429
1430 head->sync.addr = EVO_FLIP_SEM0(index);
1431 head->sync.data = 0x00000000;
1432
1433
1434 ret = nv50_pioc_create(disp->core, NV50_DISP_OIMM_CLASS, index,
1435 &(struct nv50_display_oimm_class) {
1436 .head = index,
1437 }, sizeof(struct nv50_display_oimm_class),
1438 &head->oimm.base);
1439 if (ret)
1440 goto out;
1441
1442 ret = nv50_dmac_create(disp->core, NV50_DISP_OVLY_CLASS, index,
1443 &(struct nv50_display_ovly_class) {
1444 .pushbuf = EVO_PUSH_HANDLE(OVLY, index),
1445 .head = index,
1446 }, sizeof(struct nv50_display_ovly_class),
1447 disp->sync->bo.offset, &head->ovly.base);
1448 if (ret)
1449 goto out;
1450
1451out:
1452 if (ret)
1453 nv50_crtc_destroy(crtc);
1454 return ret;
1455}
1456
1457
1458
1459
1460static void
1461nv50_dac_dpms(struct drm_encoder *encoder, int mode)
1462{
1463 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1464 struct nv50_disp *disp = nv50_disp(encoder->dev);
1465 int or = nv_encoder->or;
1466 u32 dpms_ctrl;
1467
1468 dpms_ctrl = 0x00000000;
1469 if (mode == DRM_MODE_DPMS_STANDBY || mode == DRM_MODE_DPMS_OFF)
1470 dpms_ctrl |= 0x00000001;
1471 if (mode == DRM_MODE_DPMS_SUSPEND || mode == DRM_MODE_DPMS_OFF)
1472 dpms_ctrl |= 0x00000004;
1473
1474 nv_call(disp->core, NV50_DISP_DAC_PWR + or, dpms_ctrl);
1475}
1476
1477static bool
1478nv50_dac_mode_fixup(struct drm_encoder *encoder,
1479 const struct drm_display_mode *mode,
1480 struct drm_display_mode *adjusted_mode)
1481{
1482 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1483 struct nouveau_connector *nv_connector;
1484
1485 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1486 if (nv_connector && nv_connector->native_mode) {
1487 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
1488 int id = adjusted_mode->base.id;
1489 *adjusted_mode = *nv_connector->native_mode;
1490 adjusted_mode->base.id = id;
1491 }
1492 }
1493
1494 return true;
1495}
1496
1497static void
1498nv50_dac_commit(struct drm_encoder *encoder)
1499{
1500}
1501
1502static void
1503nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
1504 struct drm_display_mode *adjusted_mode)
1505{
1506 struct nv50_mast *mast = nv50_mast(encoder->dev);
1507 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1508 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1509 u32 *push;
1510
1511 nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON);
1512
1513 push = evo_wait(mast, 8);
1514 if (push) {
1515 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
1516 u32 syncs = 0x00000000;
1517
1518 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1519 syncs |= 0x00000001;
1520 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1521 syncs |= 0x00000002;
1522
1523 evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2);
1524 evo_data(push, 1 << nv_crtc->index);
1525 evo_data(push, syncs);
1526 } else {
1527 u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
1528 u32 syncs = 0x00000001;
1529
1530 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1531 syncs |= 0x00000008;
1532 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1533 syncs |= 0x00000010;
1534
1535 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1536 magic |= 0x00000001;
1537
1538 evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
1539 evo_data(push, syncs);
1540 evo_data(push, magic);
1541 evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1);
1542 evo_data(push, 1 << nv_crtc->index);
1543 }
1544
1545 evo_kick(push, mast);
1546 }
1547
1548 nv_encoder->crtc = encoder->crtc;
1549}
1550
1551static void
1552nv50_dac_disconnect(struct drm_encoder *encoder)
1553{
1554 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1555 struct nv50_mast *mast = nv50_mast(encoder->dev);
1556 const int or = nv_encoder->or;
1557 u32 *push;
1558
1559 if (nv_encoder->crtc) {
1560 nv50_crtc_prepare(nv_encoder->crtc);
1561
1562 push = evo_wait(mast, 4);
1563 if (push) {
1564 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
1565 evo_mthd(push, 0x0400 + (or * 0x080), 1);
1566 evo_data(push, 0x00000000);
1567 } else {
1568 evo_mthd(push, 0x0180 + (or * 0x020), 1);
1569 evo_data(push, 0x00000000);
1570 }
1571 evo_kick(push, mast);
1572 }
1573 }
1574
1575 nv_encoder->crtc = NULL;
1576}
1577
1578static enum drm_connector_status
1579nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1580{
1581 struct nv50_disp *disp = nv50_disp(encoder->dev);
1582 int ret, or = nouveau_encoder(encoder)->or;
1583 u32 load = nouveau_drm(encoder->dev)->vbios.dactestval;
1584 if (load == 0)
1585 load = 340;
1586
1587 ret = nv_exec(disp->core, NV50_DISP_DAC_LOAD + or, &load, sizeof(load));
1588 if (ret || !load)
1589 return connector_status_disconnected;
1590
1591 return connector_status_connected;
1592}
1593
1594static void
1595nv50_dac_destroy(struct drm_encoder *encoder)
1596{
1597 drm_encoder_cleanup(encoder);
1598 kfree(encoder);
1599}
1600
1601static const struct drm_encoder_helper_funcs nv50_dac_hfunc = {
1602 .dpms = nv50_dac_dpms,
1603 .mode_fixup = nv50_dac_mode_fixup,
1604 .prepare = nv50_dac_disconnect,
1605 .commit = nv50_dac_commit,
1606 .mode_set = nv50_dac_mode_set,
1607 .disable = nv50_dac_disconnect,
1608 .get_crtc = nv50_display_crtc_get,
1609 .detect = nv50_dac_detect
1610};
1611
1612static const struct drm_encoder_funcs nv50_dac_func = {
1613 .destroy = nv50_dac_destroy,
1614};
1615
1616static int
1617nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
1618{
1619 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1620 struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
1621 struct nouveau_encoder *nv_encoder;
1622 struct drm_encoder *encoder;
1623 int type = DRM_MODE_ENCODER_DAC;
1624
1625 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1626 if (!nv_encoder)
1627 return -ENOMEM;
1628 nv_encoder->dcb = dcbe;
1629 nv_encoder->or = ffs(dcbe->or) - 1;
1630 nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index);
1631
1632 encoder = to_drm_encoder(nv_encoder);
1633 encoder->possible_crtcs = dcbe->heads;
1634 encoder->possible_clones = 0;
1635 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type);
1636 drm_encoder_helper_add(encoder, &nv50_dac_hfunc);
1637
1638 drm_mode_connector_attach_encoder(connector, encoder);
1639 return 0;
1640}
1641
1642
1643
1644
1645static void
1646nv50_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1647{
1648 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1649 struct nouveau_connector *nv_connector;
1650 struct nv50_disp *disp = nv50_disp(encoder->dev);
1651
1652 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1653 if (!drm_detect_monitor_audio(nv_connector->edid))
1654 return;
1655
1656 drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
1657
1658 nv_exec(disp->core, NVA3_DISP_SOR_HDA_ELD + nv_encoder->or,
1659 nv_connector->base.eld,
1660 nv_connector->base.eld[2] * 4);
1661}
1662
1663static void
1664nv50_audio_disconnect(struct drm_encoder *encoder)
1665{
1666 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1667 struct nv50_disp *disp = nv50_disp(encoder->dev);
1668
1669 nv_exec(disp->core, NVA3_DISP_SOR_HDA_ELD + nv_encoder->or, NULL, 0);
1670}
1671
1672
1673
1674
1675static void
1676nv50_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1677{
1678 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1679 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1680 struct nouveau_connector *nv_connector;
1681 struct nv50_disp *disp = nv50_disp(encoder->dev);
1682 const u32 moff = (nv_crtc->index << 3) | nv_encoder->or;
1683 u32 rekey = 56;
1684 u32 max_ac_packet;
1685
1686 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1687 if (!drm_detect_hdmi_monitor(nv_connector->edid))
1688 return;
1689
1690 max_ac_packet = mode->htotal - mode->hdisplay;
1691 max_ac_packet -= rekey;
1692 max_ac_packet -= 18;
1693 max_ac_packet /= 32;
1694
1695 nv_call(disp->core, NV84_DISP_SOR_HDMI_PWR + moff,
1696 NV84_DISP_SOR_HDMI_PWR_STATE_ON |
1697 (max_ac_packet << 16) | rekey);
1698
1699 nv50_audio_mode_set(encoder, mode);
1700}
1701
1702static void
1703nv50_hdmi_disconnect(struct drm_encoder *encoder)
1704{
1705 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1706 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1707 struct nv50_disp *disp = nv50_disp(encoder->dev);
1708 const u32 moff = (nv_crtc->index << 3) | nv_encoder->or;
1709
1710 nv50_audio_disconnect(encoder);
1711
1712 nv_call(disp->core, NV84_DISP_SOR_HDMI_PWR + moff, 0x00000000);
1713}
1714
1715
1716
1717
1718static void
1719nv50_sor_dpms(struct drm_encoder *encoder, int mode)
1720{
1721 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1722 struct drm_device *dev = encoder->dev;
1723 struct nv50_disp *disp = nv50_disp(dev);
1724 struct drm_encoder *partner;
1725 int or = nv_encoder->or;
1726
1727 nv_encoder->last_dpms = mode;
1728
1729 list_for_each_entry(partner, &dev->mode_config.encoder_list, head) {
1730 struct nouveau_encoder *nv_partner = nouveau_encoder(partner);
1731
1732 if (partner->encoder_type != DRM_MODE_ENCODER_TMDS)
1733 continue;
1734
1735 if (nv_partner != nv_encoder &&
1736 nv_partner->dcb->or == nv_encoder->dcb->or) {
1737 if (nv_partner->last_dpms == DRM_MODE_DPMS_ON)
1738 return;
1739 break;
1740 }
1741 }
1742
1743 nv_call(disp->core, NV50_DISP_SOR_PWR + or, (mode == DRM_MODE_DPMS_ON));
1744}
1745
1746static bool
1747nv50_sor_mode_fixup(struct drm_encoder *encoder,
1748 const struct drm_display_mode *mode,
1749 struct drm_display_mode *adjusted_mode)
1750{
1751 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1752 struct nouveau_connector *nv_connector;
1753
1754 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1755 if (nv_connector && nv_connector->native_mode) {
1756 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
1757 int id = adjusted_mode->base.id;
1758 *adjusted_mode = *nv_connector->native_mode;
1759 adjusted_mode->base.id = id;
1760 }
1761 }
1762
1763 return true;
1764}
1765
1766static void
1767nv50_sor_disconnect(struct drm_encoder *encoder)
1768{
1769 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1770 struct nv50_mast *mast = nv50_mast(encoder->dev);
1771 const int or = nv_encoder->or;
1772 u32 *push;
1773
1774 if (nv_encoder->crtc) {
1775 nv50_crtc_prepare(nv_encoder->crtc);
1776
1777 push = evo_wait(mast, 4);
1778 if (push) {
1779 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
1780 evo_mthd(push, 0x0600 + (or * 0x40), 1);
1781 evo_data(push, 0x00000000);
1782 } else {
1783 evo_mthd(push, 0x0200 + (or * 0x20), 1);
1784 evo_data(push, 0x00000000);
1785 }
1786 evo_kick(push, mast);
1787 }
1788
1789 nv50_hdmi_disconnect(encoder);
1790 }
1791
1792 nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
1793 nv_encoder->crtc = NULL;
1794}
1795
1796static void
1797nv50_sor_commit(struct drm_encoder *encoder)
1798{
1799}
1800
1801static void
1802nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
1803 struct drm_display_mode *mode)
1804{
1805 struct nv50_disp *disp = nv50_disp(encoder->dev);
1806 struct nv50_mast *mast = nv50_mast(encoder->dev);
1807 struct drm_device *dev = encoder->dev;
1808 struct nouveau_drm *drm = nouveau_drm(dev);
1809 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1810 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1811 struct nouveau_connector *nv_connector;
1812 struct nvbios *bios = &drm->vbios;
1813 u32 *push, lvds = 0;
1814 u8 owner = 1 << nv_crtc->index;
1815 u8 proto = 0xf;
1816 u8 depth = 0x0;
1817
1818 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1819 switch (nv_encoder->dcb->type) {
1820 case DCB_OUTPUT_TMDS:
1821 if (nv_encoder->dcb->sorconf.link & 1) {
1822 if (mode->clock < 165000)
1823 proto = 0x1;
1824 else
1825 proto = 0x5;
1826 } else {
1827 proto = 0x2;
1828 }
1829
1830 nv50_hdmi_mode_set(encoder, mode);
1831 break;
1832 case DCB_OUTPUT_LVDS:
1833 proto = 0x0;
1834
1835 if (bios->fp_no_ddc) {
1836 if (bios->fp.dual_link)
1837 lvds |= 0x0100;
1838 if (bios->fp.if_is_24bit)
1839 lvds |= 0x0200;
1840 } else {
1841 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1842 if (((u8 *)nv_connector->edid)[121] == 2)
1843 lvds |= 0x0100;
1844 } else
1845 if (mode->clock >= bios->fp.duallink_transition_clk) {
1846 lvds |= 0x0100;
1847 }
1848
1849 if (lvds & 0x0100) {
1850 if (bios->fp.strapless_is_24bit & 2)
1851 lvds |= 0x0200;
1852 } else {
1853 if (bios->fp.strapless_is_24bit & 1)
1854 lvds |= 0x0200;
1855 }
1856
1857 if (nv_connector->base.display_info.bpc == 8)
1858 lvds |= 0x0200;
1859 }
1860
1861 nv_call(disp->core, NV50_DISP_SOR_LVDS_SCRIPT + nv_encoder->or, lvds);
1862 break;
1863 case DCB_OUTPUT_DP:
1864 if (nv_connector->base.display_info.bpc == 6) {
1865 nv_encoder->dp.datarate = mode->clock * 18 / 8;
1866 depth = 0x2;
1867 } else
1868 if (nv_connector->base.display_info.bpc == 8) {
1869 nv_encoder->dp.datarate = mode->clock * 24 / 8;
1870 depth = 0x5;
1871 } else {
1872 nv_encoder->dp.datarate = mode->clock * 30 / 8;
1873 depth = 0x6;
1874 }
1875
1876 if (nv_encoder->dcb->sorconf.link & 1)
1877 proto = 0x8;
1878 else
1879 proto = 0x9;
1880 break;
1881 default:
1882 BUG_ON(1);
1883 break;
1884 }
1885
1886 nv50_sor_dpms(encoder, DRM_MODE_DPMS_ON);
1887
1888 push = evo_wait(nv50_mast(dev), 8);
1889 if (push) {
1890 if (nv50_vers(mast) < NVD0_DISP_CLASS) {
1891 u32 ctrl = (depth << 16) | (proto << 8) | owner;
1892 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1893 ctrl |= 0x00001000;
1894 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1895 ctrl |= 0x00002000;
1896 evo_mthd(push, 0x0600 + (nv_encoder->or * 0x040), 1);
1897 evo_data(push, ctrl);
1898 } else {
1899 u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
1900 u32 syncs = 0x00000001;
1901
1902 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1903 syncs |= 0x00000008;
1904 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1905 syncs |= 0x00000010;
1906
1907 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1908 magic |= 0x00000001;
1909
1910 evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
1911 evo_data(push, syncs | (depth << 6));
1912 evo_data(push, magic);
1913 evo_mthd(push, 0x0200 + (nv_encoder->or * 0x020), 1);
1914 evo_data(push, owner | (proto << 8));
1915 }
1916
1917 evo_kick(push, mast);
1918 }
1919
1920 nv_encoder->crtc = encoder->crtc;
1921}
1922
1923static void
1924nv50_sor_destroy(struct drm_encoder *encoder)
1925{
1926 drm_encoder_cleanup(encoder);
1927 kfree(encoder);
1928}
1929
1930static const struct drm_encoder_helper_funcs nv50_sor_hfunc = {
1931 .dpms = nv50_sor_dpms,
1932 .mode_fixup = nv50_sor_mode_fixup,
1933 .prepare = nv50_sor_disconnect,
1934 .commit = nv50_sor_commit,
1935 .mode_set = nv50_sor_mode_set,
1936 .disable = nv50_sor_disconnect,
1937 .get_crtc = nv50_display_crtc_get,
1938};
1939
1940static const struct drm_encoder_funcs nv50_sor_func = {
1941 .destroy = nv50_sor_destroy,
1942};
1943
1944static int
1945nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1946{
1947 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1948 struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
1949 struct nouveau_encoder *nv_encoder;
1950 struct drm_encoder *encoder;
1951 int type;
1952
1953 switch (dcbe->type) {
1954 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
1955 case DCB_OUTPUT_TMDS:
1956 case DCB_OUTPUT_DP:
1957 default:
1958 type = DRM_MODE_ENCODER_TMDS;
1959 break;
1960 }
1961
1962 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1963 if (!nv_encoder)
1964 return -ENOMEM;
1965 nv_encoder->dcb = dcbe;
1966 nv_encoder->or = ffs(dcbe->or) - 1;
1967 nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index);
1968 nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
1969
1970 encoder = to_drm_encoder(nv_encoder);
1971 encoder->possible_crtcs = dcbe->heads;
1972 encoder->possible_clones = 0;
1973 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type);
1974 drm_encoder_helper_add(encoder, &nv50_sor_hfunc);
1975
1976 drm_mode_connector_attach_encoder(connector, encoder);
1977 return 0;
1978}
1979
1980
1981
1982
1983
1984static void
1985nv50_pior_dpms(struct drm_encoder *encoder, int mode)
1986{
1987 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1988 struct nv50_disp *disp = nv50_disp(encoder->dev);
1989 u32 mthd = (nv_encoder->dcb->type << 12) | nv_encoder->or;
1990 u32 ctrl = (mode == DRM_MODE_DPMS_ON);
1991 nv_call(disp->core, NV50_DISP_PIOR_PWR + mthd, ctrl);
1992}
1993
1994static bool
1995nv50_pior_mode_fixup(struct drm_encoder *encoder,
1996 const struct drm_display_mode *mode,
1997 struct drm_display_mode *adjusted_mode)
1998{
1999 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2000 struct nouveau_connector *nv_connector;
2001
2002 nv_connector = nouveau_encoder_connector_get(nv_encoder);
2003 if (nv_connector && nv_connector->native_mode) {
2004 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
2005 int id = adjusted_mode->base.id;
2006 *adjusted_mode = *nv_connector->native_mode;
2007 adjusted_mode->base.id = id;
2008 }
2009 }
2010
2011 adjusted_mode->clock *= 2;
2012 return true;
2013}
2014
2015static void
2016nv50_pior_commit(struct drm_encoder *encoder)
2017{
2018}
2019
2020static void
2021nv50_pior_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
2022 struct drm_display_mode *adjusted_mode)
2023{
2024 struct nv50_mast *mast = nv50_mast(encoder->dev);
2025 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2026 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2027 struct nouveau_connector *nv_connector;
2028 u8 owner = 1 << nv_crtc->index;
2029 u8 proto, depth;
2030 u32 *push;
2031
2032 nv_connector = nouveau_encoder_connector_get(nv_encoder);
2033 switch (nv_connector->base.display_info.bpc) {
2034 case 10: depth = 0x6; break;
2035 case 8: depth = 0x5; break;
2036 case 6: depth = 0x2; break;
2037 default: depth = 0x0; break;
2038 }
2039
2040 switch (nv_encoder->dcb->type) {
2041 case DCB_OUTPUT_TMDS:
2042 case DCB_OUTPUT_DP:
2043 proto = 0x0;
2044 break;
2045 default:
2046 BUG_ON(1);
2047 break;
2048 }
2049
2050 nv50_pior_dpms(encoder, DRM_MODE_DPMS_ON);
2051
2052 push = evo_wait(mast, 8);
2053 if (push) {
2054 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
2055 u32 ctrl = (depth << 16) | (proto << 8) | owner;
2056 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2057 ctrl |= 0x00001000;
2058 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2059 ctrl |= 0x00002000;
2060 evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1);
2061 evo_data(push, ctrl);
2062 }
2063
2064 evo_kick(push, mast);
2065 }
2066
2067 nv_encoder->crtc = encoder->crtc;
2068}
2069
2070static void
2071nv50_pior_disconnect(struct drm_encoder *encoder)
2072{
2073 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2074 struct nv50_mast *mast = nv50_mast(encoder->dev);
2075 const int or = nv_encoder->or;
2076 u32 *push;
2077
2078 if (nv_encoder->crtc) {
2079 nv50_crtc_prepare(nv_encoder->crtc);
2080
2081 push = evo_wait(mast, 4);
2082 if (push) {
2083 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
2084 evo_mthd(push, 0x0700 + (or * 0x040), 1);
2085 evo_data(push, 0x00000000);
2086 }
2087 evo_kick(push, mast);
2088 }
2089 }
2090
2091 nv_encoder->crtc = NULL;
2092}
2093
2094static void
2095nv50_pior_destroy(struct drm_encoder *encoder)
2096{
2097 drm_encoder_cleanup(encoder);
2098 kfree(encoder);
2099}
2100
2101static const struct drm_encoder_helper_funcs nv50_pior_hfunc = {
2102 .dpms = nv50_pior_dpms,
2103 .mode_fixup = nv50_pior_mode_fixup,
2104 .prepare = nv50_pior_disconnect,
2105 .commit = nv50_pior_commit,
2106 .mode_set = nv50_pior_mode_set,
2107 .disable = nv50_pior_disconnect,
2108 .get_crtc = nv50_display_crtc_get,
2109};
2110
2111static const struct drm_encoder_funcs nv50_pior_func = {
2112 .destroy = nv50_pior_destroy,
2113};
2114
2115static int
2116nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
2117{
2118 struct nouveau_drm *drm = nouveau_drm(connector->dev);
2119 struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
2120 struct nouveau_i2c_port *ddc = NULL;
2121 struct nouveau_encoder *nv_encoder;
2122 struct drm_encoder *encoder;
2123 int type;
2124
2125 switch (dcbe->type) {
2126 case DCB_OUTPUT_TMDS:
2127 ddc = i2c->find_type(i2c, NV_I2C_TYPE_EXTDDC(dcbe->extdev));
2128 type = DRM_MODE_ENCODER_TMDS;
2129 break;
2130 case DCB_OUTPUT_DP:
2131 ddc = i2c->find_type(i2c, NV_I2C_TYPE_EXTAUX(dcbe->extdev));
2132 type = DRM_MODE_ENCODER_TMDS;
2133 break;
2134 default:
2135 return -ENODEV;
2136 }
2137
2138 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2139 if (!nv_encoder)
2140 return -ENOMEM;
2141 nv_encoder->dcb = dcbe;
2142 nv_encoder->or = ffs(dcbe->or) - 1;
2143 nv_encoder->i2c = ddc;
2144
2145 encoder = to_drm_encoder(nv_encoder);
2146 encoder->possible_crtcs = dcbe->heads;
2147 encoder->possible_clones = 0;
2148 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type);
2149 drm_encoder_helper_add(encoder, &nv50_pior_hfunc);
2150
2151 drm_mode_connector_attach_encoder(connector, encoder);
2152 return 0;
2153}
2154
2155
2156
2157
2158void
2159nv50_display_fini(struct drm_device *dev)
2160{
2161}
2162
2163int
2164nv50_display_init(struct drm_device *dev)
2165{
2166 struct nv50_disp *disp = nv50_disp(dev);
2167 struct drm_crtc *crtc;
2168 u32 *push;
2169
2170 push = evo_wait(nv50_mast(dev), 32);
2171 if (!push)
2172 return -EBUSY;
2173
2174 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2175 struct nv50_sync *sync = nv50_sync(crtc);
2176 nouveau_bo_wr32(disp->sync, sync->addr / 4, sync->data);
2177 }
2178
2179 evo_mthd(push, 0x0088, 1);
2180 evo_data(push, NvEvoSync);
2181 evo_kick(push, nv50_mast(dev));
2182 return 0;
2183}
2184
2185void
2186nv50_display_destroy(struct drm_device *dev)
2187{
2188 struct nv50_disp *disp = nv50_disp(dev);
2189
2190 nv50_dmac_destroy(disp->core, &disp->mast.base);
2191
2192 nouveau_bo_unmap(disp->sync);
2193 if (disp->sync)
2194 nouveau_bo_unpin(disp->sync);
2195 nouveau_bo_ref(NULL, &disp->sync);
2196
2197 nouveau_display(dev)->priv = NULL;
2198 kfree(disp);
2199}
2200
2201int
2202nv50_display_create(struct drm_device *dev)
2203{
2204 struct nouveau_device *device = nouveau_dev(dev);
2205 struct nouveau_drm *drm = nouveau_drm(dev);
2206 struct dcb_table *dcb = &drm->vbios.dcb;
2207 struct drm_connector *connector, *tmp;
2208 struct nv50_disp *disp;
2209 struct dcb_output *dcbe;
2210 int crtcs, ret, i;
2211
2212 disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2213 if (!disp)
2214 return -ENOMEM;
2215
2216 nouveau_display(dev)->priv = disp;
2217 nouveau_display(dev)->dtor = nv50_display_destroy;
2218 nouveau_display(dev)->init = nv50_display_init;
2219 nouveau_display(dev)->fini = nv50_display_fini;
2220 disp->core = nouveau_display(dev)->core;
2221
2222
2223 ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2224 0, 0x0000, NULL, &disp->sync);
2225 if (!ret) {
2226 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM);
2227 if (!ret) {
2228 ret = nouveau_bo_map(disp->sync);
2229 if (ret)
2230 nouveau_bo_unpin(disp->sync);
2231 }
2232 if (ret)
2233 nouveau_bo_ref(NULL, &disp->sync);
2234 }
2235
2236 if (ret)
2237 goto out;
2238
2239
2240 ret = nv50_dmac_create(disp->core, NV50_DISP_MAST_CLASS, 0,
2241 &(struct nv50_display_mast_class) {
2242 .pushbuf = EVO_PUSH_HANDLE(MAST, 0),
2243 }, sizeof(struct nv50_display_mast_class),
2244 disp->sync->bo.offset, &disp->mast.base);
2245 if (ret)
2246 goto out;
2247
2248
2249 if (nv_mclass(disp->core) >= NVD0_DISP_CLASS)
2250 crtcs = nv_rd32(device, 0x022448);
2251 else
2252 crtcs = 2;
2253
2254 for (i = 0; i < crtcs; i++) {
2255 ret = nv50_crtc_create(dev, disp->core, i);
2256 if (ret)
2257 goto out;
2258 }
2259
2260
2261 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2262 connector = nouveau_connector_create(dev, dcbe->connector);
2263 if (IS_ERR(connector))
2264 continue;
2265
2266 if (dcbe->location == DCB_LOC_ON_CHIP) {
2267 switch (dcbe->type) {
2268 case DCB_OUTPUT_TMDS:
2269 case DCB_OUTPUT_LVDS:
2270 case DCB_OUTPUT_DP:
2271 ret = nv50_sor_create(connector, dcbe);
2272 break;
2273 case DCB_OUTPUT_ANALOG:
2274 ret = nv50_dac_create(connector, dcbe);
2275 break;
2276 default:
2277 ret = -ENODEV;
2278 break;
2279 }
2280 } else {
2281 ret = nv50_pior_create(connector, dcbe);
2282 }
2283
2284 if (ret) {
2285 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2286 dcbe->location, dcbe->type,
2287 ffs(dcbe->or) - 1, ret);
2288 ret = 0;
2289 }
2290 }
2291
2292
2293 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2294 if (connector->encoder_ids[0])
2295 continue;
2296
2297 NV_WARN(drm, "%s has no encoders, removing\n",
2298 drm_get_connector_name(connector));
2299 connector->funcs->destroy(connector);
2300 }
2301
2302out:
2303 if (ret)
2304 nv50_display_destroy(dev);
2305 return ret;
2306}
2307
