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27#include <linux/module.h>
28
29#include <drm/drmP.h>
30#include "vmwgfx_drv.h"
31#include <drm/ttm/ttm_placement.h>
32#include <drm/ttm/ttm_bo_driver.h>
33#include <drm/ttm/ttm_object.h>
34#include <drm/ttm/ttm_module.h>
35#include <linux/dma_remapping.h>
36
37#define VMWGFX_DRIVER_NAME "vmwgfx"
38#define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
39#define VMWGFX_CHIP_SVGAII 0
40#define VMW_FB_RESERVATION 0
41
42#define VMW_MIN_INITIAL_WIDTH 800
43#define VMW_MIN_INITIAL_HEIGHT 600
44
45
46
47
48
49
50#define DRM_IOCTL_VMW_GET_PARAM \
51 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \
52 struct drm_vmw_getparam_arg)
53#define DRM_IOCTL_VMW_ALLOC_DMABUF \
54 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \
55 union drm_vmw_alloc_dmabuf_arg)
56#define DRM_IOCTL_VMW_UNREF_DMABUF \
57 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \
58 struct drm_vmw_unref_dmabuf_arg)
59#define DRM_IOCTL_VMW_CURSOR_BYPASS \
60 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \
61 struct drm_vmw_cursor_bypass_arg)
62
63#define DRM_IOCTL_VMW_CONTROL_STREAM \
64 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \
65 struct drm_vmw_control_stream_arg)
66#define DRM_IOCTL_VMW_CLAIM_STREAM \
67 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \
68 struct drm_vmw_stream_arg)
69#define DRM_IOCTL_VMW_UNREF_STREAM \
70 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \
71 struct drm_vmw_stream_arg)
72
73#define DRM_IOCTL_VMW_CREATE_CONTEXT \
74 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \
75 struct drm_vmw_context_arg)
76#define DRM_IOCTL_VMW_UNREF_CONTEXT \
77 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \
78 struct drm_vmw_context_arg)
79#define DRM_IOCTL_VMW_CREATE_SURFACE \
80 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \
81 union drm_vmw_surface_create_arg)
82#define DRM_IOCTL_VMW_UNREF_SURFACE \
83 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \
84 struct drm_vmw_surface_arg)
85#define DRM_IOCTL_VMW_REF_SURFACE \
86 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \
87 union drm_vmw_surface_reference_arg)
88#define DRM_IOCTL_VMW_EXECBUF \
89 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \
90 struct drm_vmw_execbuf_arg)
91#define DRM_IOCTL_VMW_GET_3D_CAP \
92 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \
93 struct drm_vmw_get_3d_cap_arg)
94#define DRM_IOCTL_VMW_FENCE_WAIT \
95 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \
96 struct drm_vmw_fence_wait_arg)
97#define DRM_IOCTL_VMW_FENCE_SIGNALED \
98 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \
99 struct drm_vmw_fence_signaled_arg)
100#define DRM_IOCTL_VMW_FENCE_UNREF \
101 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \
102 struct drm_vmw_fence_arg)
103#define DRM_IOCTL_VMW_FENCE_EVENT \
104 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \
105 struct drm_vmw_fence_event_arg)
106#define DRM_IOCTL_VMW_PRESENT \
107 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \
108 struct drm_vmw_present_arg)
109#define DRM_IOCTL_VMW_PRESENT_READBACK \
110 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \
111 struct drm_vmw_present_readback_arg)
112#define DRM_IOCTL_VMW_UPDATE_LAYOUT \
113 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \
114 struct drm_vmw_update_layout_arg)
115#define DRM_IOCTL_VMW_CREATE_SHADER \
116 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \
117 struct drm_vmw_shader_create_arg)
118#define DRM_IOCTL_VMW_UNREF_SHADER \
119 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \
120 struct drm_vmw_shader_arg)
121#define DRM_IOCTL_VMW_GB_SURFACE_CREATE \
122 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \
123 union drm_vmw_gb_surface_create_arg)
124#define DRM_IOCTL_VMW_GB_SURFACE_REF \
125 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \
126 union drm_vmw_gb_surface_reference_arg)
127#define DRM_IOCTL_VMW_SYNCCPU \
128 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \
129 struct drm_vmw_synccpu_arg)
130
131
132
133
134
135
136#define VMW_IOCTL_DEF(ioctl, func, flags) \
137 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_##ioctl, flags, func, DRM_IOCTL_##ioctl}
138
139
140
141
142
143static const struct drm_ioctl_desc vmw_ioctls[] = {
144 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
145 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
146 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,
147 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
148 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,
149 DRM_UNLOCKED | DRM_RENDER_ALLOW),
150 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
151 vmw_kms_cursor_bypass_ioctl,
152 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
153
154 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
155 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
156 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
157 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
158 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
159 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
160
161 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
162 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
163 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
164 DRM_UNLOCKED | DRM_RENDER_ALLOW),
165 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
166 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
167 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
168 DRM_UNLOCKED | DRM_RENDER_ALLOW),
169 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
170 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
171 VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl,
172 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
173 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
174 DRM_UNLOCKED | DRM_RENDER_ALLOW),
175 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
176 vmw_fence_obj_signaled_ioctl,
177 DRM_UNLOCKED | DRM_RENDER_ALLOW),
178 VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
179 DRM_UNLOCKED | DRM_RENDER_ALLOW),
180 VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl,
181 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
182 VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
183 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
184
185
186 VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,
187 DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
188 VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
189 vmw_present_readback_ioctl,
190 DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
191 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT,
192 vmw_kms_update_layout_ioctl,
193 DRM_MASTER | DRM_UNLOCKED),
194 VMW_IOCTL_DEF(VMW_CREATE_SHADER,
195 vmw_shader_define_ioctl,
196 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
197 VMW_IOCTL_DEF(VMW_UNREF_SHADER,
198 vmw_shader_destroy_ioctl,
199 DRM_UNLOCKED | DRM_RENDER_ALLOW),
200 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE,
201 vmw_gb_surface_define_ioctl,
202 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
203 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF,
204 vmw_gb_surface_reference_ioctl,
205 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
206 VMW_IOCTL_DEF(VMW_SYNCCPU,
207 vmw_user_dmabuf_synccpu_ioctl,
208 DRM_UNLOCKED | DRM_RENDER_ALLOW),
209};
210
211static struct pci_device_id vmw_pci_id_list[] = {
212 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
213 {0, 0, 0}
214};
215MODULE_DEVICE_TABLE(pci, vmw_pci_id_list);
216
217static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON);
218static int vmw_force_iommu;
219static int vmw_restrict_iommu;
220static int vmw_force_coherent;
221static int vmw_restrict_dma_mask;
222
223static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
224static void vmw_master_init(struct vmw_master *);
225static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
226 void *ptr);
227
228MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
229module_param_named(enable_fbdev, enable_fbdev, int, 0600);
230MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages");
231module_param_named(force_dma_api, vmw_force_iommu, int, 0600);
232MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
233module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600);
234MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
235module_param_named(force_coherent, vmw_force_coherent, int, 0600);
236MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
237module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600);
238
239
240static void vmw_print_capabilities(uint32_t capabilities)
241{
242 DRM_INFO("Capabilities:\n");
243 if (capabilities & SVGA_CAP_RECT_COPY)
244 DRM_INFO(" Rect copy.\n");
245 if (capabilities & SVGA_CAP_CURSOR)
246 DRM_INFO(" Cursor.\n");
247 if (capabilities & SVGA_CAP_CURSOR_BYPASS)
248 DRM_INFO(" Cursor bypass.\n");
249 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
250 DRM_INFO(" Cursor bypass 2.\n");
251 if (capabilities & SVGA_CAP_8BIT_EMULATION)
252 DRM_INFO(" 8bit emulation.\n");
253 if (capabilities & SVGA_CAP_ALPHA_CURSOR)
254 DRM_INFO(" Alpha cursor.\n");
255 if (capabilities & SVGA_CAP_3D)
256 DRM_INFO(" 3D.\n");
257 if (capabilities & SVGA_CAP_EXTENDED_FIFO)
258 DRM_INFO(" Extended Fifo.\n");
259 if (capabilities & SVGA_CAP_MULTIMON)
260 DRM_INFO(" Multimon.\n");
261 if (capabilities & SVGA_CAP_PITCHLOCK)
262 DRM_INFO(" Pitchlock.\n");
263 if (capabilities & SVGA_CAP_IRQMASK)
264 DRM_INFO(" Irq mask.\n");
265 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
266 DRM_INFO(" Display Topology.\n");
267 if (capabilities & SVGA_CAP_GMR)
268 DRM_INFO(" GMR.\n");
269 if (capabilities & SVGA_CAP_TRACES)
270 DRM_INFO(" Traces.\n");
271 if (capabilities & SVGA_CAP_GMR2)
272 DRM_INFO(" GMR2.\n");
273 if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
274 DRM_INFO(" Screen Object 2.\n");
275 if (capabilities & SVGA_CAP_COMMAND_BUFFERS)
276 DRM_INFO(" Command Buffers.\n");
277 if (capabilities & SVGA_CAP_CMD_BUFFERS_2)
278 DRM_INFO(" Command Buffers 2.\n");
279 if (capabilities & SVGA_CAP_GBOBJECTS)
280 DRM_INFO(" Guest Backed Resources.\n");
281}
282
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294
295
296static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
297{
298 int ret;
299 struct ttm_buffer_object *bo;
300 struct ttm_bo_kmap_obj map;
301 volatile SVGA3dQueryResult *result;
302 bool dummy;
303
304
305
306
307
308
309 ret = ttm_bo_create(&dev_priv->bdev,
310 PAGE_SIZE,
311 ttm_bo_type_device,
312 &vmw_sys_ne_placement,
313 0, false, NULL,
314 &bo);
315
316 if (unlikely(ret != 0))
317 return ret;
318
319 ret = ttm_bo_reserve(bo, false, true, false, 0);
320 BUG_ON(ret != 0);
321
322 ret = ttm_bo_kmap(bo, 0, 1, &map);
323 if (likely(ret == 0)) {
324 result = ttm_kmap_obj_virtual(&map, &dummy);
325 result->totalSize = sizeof(*result);
326 result->state = SVGA3D_QUERYSTATE_PENDING;
327 result->result32 = 0xff;
328 ttm_bo_kunmap(&map);
329 }
330 vmw_bo_pin(bo, false);
331 ttm_bo_unreserve(bo);
332
333 if (unlikely(ret != 0)) {
334 DRM_ERROR("Dummy query buffer map failed.\n");
335 ttm_bo_unref(&bo);
336 } else
337 dev_priv->dummy_query_bo = bo;
338
339 return ret;
340}
341
342static int vmw_request_device(struct vmw_private *dev_priv)
343{
344 int ret;
345
346 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
347 if (unlikely(ret != 0)) {
348 DRM_ERROR("Unable to initialize FIFO.\n");
349 return ret;
350 }
351 vmw_fence_fifo_up(dev_priv->fman);
352 if (dev_priv->has_mob) {
353 ret = vmw_otables_setup(dev_priv);
354 if (unlikely(ret != 0)) {
355 DRM_ERROR("Unable to initialize "
356 "guest Memory OBjects.\n");
357 goto out_no_mob;
358 }
359 }
360 ret = vmw_dummy_query_bo_create(dev_priv);
361 if (unlikely(ret != 0))
362 goto out_no_query_bo;
363
364 return 0;
365
366out_no_query_bo:
367 if (dev_priv->has_mob)
368 vmw_otables_takedown(dev_priv);
369out_no_mob:
370 vmw_fence_fifo_down(dev_priv->fman);
371 vmw_fifo_release(dev_priv, &dev_priv->fifo);
372 return ret;
373}
374
375static void vmw_release_device(struct vmw_private *dev_priv)
376{
377
378
379
380
381
382 BUG_ON(dev_priv->pinned_bo != NULL);
383
384 ttm_bo_unref(&dev_priv->dummy_query_bo);
385 if (dev_priv->has_mob)
386 vmw_otables_takedown(dev_priv);
387 vmw_fence_fifo_down(dev_priv->fman);
388 vmw_fifo_release(dev_priv, &dev_priv->fifo);
389}
390
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393
394
395
396
397
398int vmw_3d_resource_inc(struct vmw_private *dev_priv,
399 bool unhide_svga)
400{
401 int ret = 0;
402
403 mutex_lock(&dev_priv->release_mutex);
404 if (unlikely(dev_priv->num_3d_resources++ == 0)) {
405 ret = vmw_request_device(dev_priv);
406 if (unlikely(ret != 0))
407 --dev_priv->num_3d_resources;
408 } else if (unhide_svga) {
409 mutex_lock(&dev_priv->hw_mutex);
410 vmw_write(dev_priv, SVGA_REG_ENABLE,
411 vmw_read(dev_priv, SVGA_REG_ENABLE) &
412 ~SVGA_REG_ENABLE_HIDE);
413 mutex_unlock(&dev_priv->hw_mutex);
414 }
415
416 mutex_unlock(&dev_priv->release_mutex);
417 return ret;
418}
419
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421
422
423
424
425
426
427
428void vmw_3d_resource_dec(struct vmw_private *dev_priv,
429 bool hide_svga)
430{
431 int32_t n3d;
432
433 mutex_lock(&dev_priv->release_mutex);
434 if (unlikely(--dev_priv->num_3d_resources == 0))
435 vmw_release_device(dev_priv);
436 else if (hide_svga) {
437 mutex_lock(&dev_priv->hw_mutex);
438 vmw_write(dev_priv, SVGA_REG_ENABLE,
439 vmw_read(dev_priv, SVGA_REG_ENABLE) |
440 SVGA_REG_ENABLE_HIDE);
441 mutex_unlock(&dev_priv->hw_mutex);
442 }
443
444 n3d = (int32_t) dev_priv->num_3d_resources;
445 mutex_unlock(&dev_priv->release_mutex);
446
447 BUG_ON(n3d < 0);
448}
449
450
451
452
453
454
455
456
457
458
459static void vmw_get_initial_size(struct vmw_private *dev_priv)
460{
461 uint32_t width;
462 uint32_t height;
463
464 width = vmw_read(dev_priv, SVGA_REG_WIDTH);
465 height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
466
467 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH);
468 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT);
469
470 if (width > dev_priv->fb_max_width ||
471 height > dev_priv->fb_max_height) {
472
473
474
475
476
477 width = VMW_MIN_INITIAL_WIDTH;
478 height = VMW_MIN_INITIAL_HEIGHT;
479 }
480
481 dev_priv->initial_width = width;
482 dev_priv->initial_height = height;
483}
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498static int vmw_dma_select_mode(struct vmw_private *dev_priv)
499{
500 static const char *names[vmw_dma_map_max] = {
501 [vmw_dma_phys] = "Using physical TTM page addresses.",
502 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.",
503 [vmw_dma_map_populate] = "Keeping DMA mappings.",
504 [vmw_dma_map_bind] = "Giving up DMA mappings early."};
505#ifdef CONFIG_X86
506 const struct dma_map_ops *dma_ops = get_dma_ops(dev_priv->dev->dev);
507
508#ifdef CONFIG_INTEL_IOMMU
509 if (intel_iommu_enabled) {
510 dev_priv->map_mode = vmw_dma_map_populate;
511 goto out_fixup;
512 }
513#endif
514
515 if (!(vmw_force_iommu || vmw_force_coherent)) {
516 dev_priv->map_mode = vmw_dma_phys;
517 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
518 return 0;
519 }
520
521 dev_priv->map_mode = vmw_dma_map_populate;
522
523 if (dma_ops->sync_single_for_cpu)
524 dev_priv->map_mode = vmw_dma_alloc_coherent;
525#ifdef CONFIG_SWIOTLB
526 if (swiotlb_nr_tbl() == 0)
527 dev_priv->map_mode = vmw_dma_map_populate;
528#endif
529
530#ifdef CONFIG_INTEL_IOMMU
531out_fixup:
532#endif
533 if (dev_priv->map_mode == vmw_dma_map_populate &&
534 vmw_restrict_iommu)
535 dev_priv->map_mode = vmw_dma_map_bind;
536
537 if (vmw_force_coherent)
538 dev_priv->map_mode = vmw_dma_alloc_coherent;
539
540#if !defined(CONFIG_SWIOTLB) && !defined(CONFIG_INTEL_IOMMU)
541
542
543
544 if (dev_priv->map_mode == vmw_dma_alloc_coherent)
545 return -EINVAL;
546#endif
547
548#else
549 dev_priv->map_mode = vmw_dma_map_populate;
550#endif
551
552 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
553
554 return 0;
555}
556
557
558
559
560
561
562
563
564
565#ifdef CONFIG_INTEL_IOMMU
566static int vmw_dma_masks(struct vmw_private *dev_priv)
567{
568 struct drm_device *dev = dev_priv->dev;
569
570 if (intel_iommu_enabled &&
571 (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) {
572 DRM_INFO("Restricting DMA addresses to 44 bits.\n");
573 return dma_set_mask(dev->dev, DMA_BIT_MASK(44));
574 }
575 return 0;
576}
577#else
578static int vmw_dma_masks(struct vmw_private *dev_priv)
579{
580 return 0;
581}
582#endif
583
584static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
585{
586 struct vmw_private *dev_priv;
587 int ret;
588 uint32_t svga_id;
589 enum vmw_res_type i;
590 bool refuse_dma = false;
591
592 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
593 if (unlikely(dev_priv == NULL)) {
594 DRM_ERROR("Failed allocating a device private struct.\n");
595 return -ENOMEM;
596 }
597
598 pci_set_master(dev->pdev);
599
600 dev_priv->dev = dev;
601 dev_priv->vmw_chipset = chipset;
602 dev_priv->last_read_seqno = (uint32_t) -100;
603 mutex_init(&dev_priv->hw_mutex);
604 mutex_init(&dev_priv->cmdbuf_mutex);
605 mutex_init(&dev_priv->release_mutex);
606 mutex_init(&dev_priv->binding_mutex);
607 rwlock_init(&dev_priv->resource_lock);
608 ttm_lock_init(&dev_priv->reservation_sem);
609
610 for (i = vmw_res_context; i < vmw_res_max; ++i) {
611 idr_init(&dev_priv->res_idr[i]);
612 INIT_LIST_HEAD(&dev_priv->res_lru[i]);
613 }
614
615 mutex_init(&dev_priv->init_mutex);
616 init_waitqueue_head(&dev_priv->fence_queue);
617 init_waitqueue_head(&dev_priv->fifo_queue);
618 dev_priv->fence_queue_waiters = 0;
619 atomic_set(&dev_priv->fifo_queue_waiters, 0);
620
621 dev_priv->used_memory_size = 0;
622
623 dev_priv->io_start = pci_resource_start(dev->pdev, 0);
624 dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
625 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
626
627 dev_priv->enable_fb = enable_fbdev;
628
629 mutex_lock(&dev_priv->hw_mutex);
630
631 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
632 svga_id = vmw_read(dev_priv, SVGA_REG_ID);
633 if (svga_id != SVGA_ID_2) {
634 ret = -ENOSYS;
635 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id);
636 mutex_unlock(&dev_priv->hw_mutex);
637 goto out_err0;
638 }
639
640 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
641 ret = vmw_dma_select_mode(dev_priv);
642 if (unlikely(ret != 0)) {
643 DRM_INFO("Restricting capabilities due to IOMMU setup.\n");
644 refuse_dma = true;
645 }
646
647 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
648 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
649 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
650 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
651
652 vmw_get_initial_size(dev_priv);
653
654 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
655 dev_priv->max_gmr_ids =
656 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
657 dev_priv->max_gmr_pages =
658 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
659 dev_priv->memory_size =
660 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
661 dev_priv->memory_size -= dev_priv->vram_size;
662 } else {
663
664
665
666
667 dev_priv->memory_size = 512*1024*1024;
668 }
669 dev_priv->max_mob_pages = 0;
670 dev_priv->max_mob_size = 0;
671 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
672 uint64_t mem_size =
673 vmw_read(dev_priv,
674 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB);
675
676 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
677 dev_priv->prim_bb_mem =
678 vmw_read(dev_priv,
679 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM);
680 dev_priv->max_mob_size =
681 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);
682 } else
683 dev_priv->prim_bb_mem = dev_priv->vram_size;
684
685 ret = vmw_dma_masks(dev_priv);
686 if (unlikely(ret != 0)) {
687 mutex_unlock(&dev_priv->hw_mutex);
688 goto out_err0;
689 }
690
691 if (unlikely(dev_priv->prim_bb_mem < dev_priv->vram_size))
692 dev_priv->prim_bb_mem = dev_priv->vram_size;
693
694 mutex_unlock(&dev_priv->hw_mutex);
695
696 vmw_print_capabilities(dev_priv->capabilities);
697
698 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
699 DRM_INFO("Max GMR ids is %u\n",
700 (unsigned)dev_priv->max_gmr_ids);
701 DRM_INFO("Max number of GMR pages is %u\n",
702 (unsigned)dev_priv->max_gmr_pages);
703 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
704 (unsigned)dev_priv->memory_size / 1024);
705 }
706 DRM_INFO("Maximum display memory size is %u kiB\n",
707 dev_priv->prim_bb_mem / 1024);
708 DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
709 dev_priv->vram_start, dev_priv->vram_size / 1024);
710 DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
711 dev_priv->mmio_start, dev_priv->mmio_size / 1024);
712
713 ret = vmw_ttm_global_init(dev_priv);
714 if (unlikely(ret != 0))
715 goto out_err0;
716
717
718 vmw_master_init(&dev_priv->fbdev_master);
719 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
720 dev_priv->active_master = &dev_priv->fbdev_master;
721
722
723 ret = ttm_bo_device_init(&dev_priv->bdev,
724 dev_priv->bo_global_ref.ref.object,
725 &vmw_bo_driver,
726 dev->anon_inode->i_mapping,
727 VMWGFX_FILE_PAGE_OFFSET,
728 false);
729 if (unlikely(ret != 0)) {
730 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
731 goto out_err1;
732 }
733
734 ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
735 (dev_priv->vram_size >> PAGE_SHIFT));
736 if (unlikely(ret != 0)) {
737 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
738 goto out_err2;
739 }
740
741 dev_priv->has_gmr = true;
742 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||
743 refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR,
744 VMW_PL_GMR) != 0) {
745 DRM_INFO("No GMR memory available. "
746 "Graphics memory resources are very limited.\n");
747 dev_priv->has_gmr = false;
748 }
749
750 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
751 dev_priv->has_mob = true;
752 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB,
753 VMW_PL_MOB) != 0) {
754 DRM_INFO("No MOB memory available. "
755 "3D will be disabled.\n");
756 dev_priv->has_mob = false;
757 }
758 }
759
760 dev_priv->mmio_mtrr = arch_phys_wc_add(dev_priv->mmio_start,
761 dev_priv->mmio_size);
762
763 dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start,
764 dev_priv->mmio_size);
765
766 if (unlikely(dev_priv->mmio_virt == NULL)) {
767 ret = -ENOMEM;
768 DRM_ERROR("Failed mapping MMIO.\n");
769 goto out_err3;
770 }
771
772
773 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
774 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
775 !vmw_fifo_have_pitchlock(dev_priv)) {
776 ret = -ENOSYS;
777 DRM_ERROR("Hardware has no pitchlock\n");
778 goto out_err4;
779 }
780
781 dev_priv->tdev = ttm_object_device_init
782 (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops);
783
784 if (unlikely(dev_priv->tdev == NULL)) {
785 DRM_ERROR("Unable to initialize TTM object management.\n");
786 ret = -ENOMEM;
787 goto out_err4;
788 }
789
790 dev->dev_private = dev_priv;
791
792 ret = pci_request_regions(dev->pdev, "vmwgfx probe");
793 dev_priv->stealth = (ret != 0);
794 if (dev_priv->stealth) {
795
796
797
798
799 DRM_INFO("It appears like vesafb is loaded. "
800 "Ignore above error if any.\n");
801 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
802 if (unlikely(ret != 0)) {
803 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
804 goto out_no_device;
805 }
806 }
807
808 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
809 ret = drm_irq_install(dev);
810 if (ret != 0) {
811 DRM_ERROR("Failed installing irq: %d\n", ret);
812 goto out_no_irq;
813 }
814 }
815
816 dev_priv->fman = vmw_fence_manager_init(dev_priv);
817 if (unlikely(dev_priv->fman == NULL)) {
818 ret = -ENOMEM;
819 goto out_no_fman;
820 }
821
822 vmw_kms_save_vga(dev_priv);
823
824
825 ret = vmw_kms_init(dev_priv);
826 if (unlikely(ret != 0))
827 goto out_no_kms;
828 vmw_overlay_init(dev_priv);
829
830 if (dev_priv->enable_fb) {
831 ret = vmw_3d_resource_inc(dev_priv, true);
832 if (unlikely(ret != 0))
833 goto out_no_fifo;
834 vmw_fb_init(dev_priv);
835 }
836
837 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
838 register_pm_notifier(&dev_priv->pm_nb);
839
840 return 0;
841
842out_no_fifo:
843 vmw_overlay_close(dev_priv);
844 vmw_kms_close(dev_priv);
845out_no_kms:
846 vmw_kms_restore_vga(dev_priv);
847 vmw_fence_manager_takedown(dev_priv->fman);
848out_no_fman:
849 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
850 drm_irq_uninstall(dev_priv->dev);
851out_no_irq:
852 if (dev_priv->stealth)
853 pci_release_region(dev->pdev, 2);
854 else
855 pci_release_regions(dev->pdev);
856out_no_device:
857 ttm_object_device_release(&dev_priv->tdev);
858out_err4:
859 iounmap(dev_priv->mmio_virt);
860out_err3:
861 arch_phys_wc_del(dev_priv->mmio_mtrr);
862 if (dev_priv->has_mob)
863 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
864 if (dev_priv->has_gmr)
865 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
866 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
867out_err2:
868 (void)ttm_bo_device_release(&dev_priv->bdev);
869out_err1:
870 vmw_ttm_global_release(dev_priv);
871out_err0:
872 for (i = vmw_res_context; i < vmw_res_max; ++i)
873 idr_destroy(&dev_priv->res_idr[i]);
874
875 kfree(dev_priv);
876 return ret;
877}
878
879static int vmw_driver_unload(struct drm_device *dev)
880{
881 struct vmw_private *dev_priv = vmw_priv(dev);
882 enum vmw_res_type i;
883
884 unregister_pm_notifier(&dev_priv->pm_nb);
885
886 if (dev_priv->ctx.res_ht_initialized)
887 drm_ht_remove(&dev_priv->ctx.res_ht);
888 if (dev_priv->ctx.cmd_bounce)
889 vfree(dev_priv->ctx.cmd_bounce);
890 if (dev_priv->enable_fb) {
891 vmw_fb_close(dev_priv);
892 vmw_kms_restore_vga(dev_priv);
893 vmw_3d_resource_dec(dev_priv, false);
894 }
895 vmw_kms_close(dev_priv);
896 vmw_overlay_close(dev_priv);
897 vmw_fence_manager_takedown(dev_priv->fman);
898 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
899 drm_irq_uninstall(dev_priv->dev);
900 if (dev_priv->stealth)
901 pci_release_region(dev->pdev, 2);
902 else
903 pci_release_regions(dev->pdev);
904
905 ttm_object_device_release(&dev_priv->tdev);
906 iounmap(dev_priv->mmio_virt);
907 arch_phys_wc_del(dev_priv->mmio_mtrr);
908 if (dev_priv->has_mob)
909 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
910 if (dev_priv->has_gmr)
911 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
912 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
913 (void)ttm_bo_device_release(&dev_priv->bdev);
914 vmw_ttm_global_release(dev_priv);
915
916 for (i = vmw_res_context; i < vmw_res_max; ++i)
917 idr_destroy(&dev_priv->res_idr[i]);
918
919 kfree(dev_priv);
920
921 return 0;
922}
923
924static void vmw_preclose(struct drm_device *dev,
925 struct drm_file *file_priv)
926{
927 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
928 struct vmw_private *dev_priv = vmw_priv(dev);
929
930 vmw_event_fence_fpriv_gone(dev_priv->fman, &vmw_fp->fence_events);
931}
932
933static void vmw_postclose(struct drm_device *dev,
934 struct drm_file *file_priv)
935{
936 struct vmw_fpriv *vmw_fp;
937
938 vmw_fp = vmw_fpriv(file_priv);
939
940 if (vmw_fp->locked_master) {
941 struct vmw_master *vmaster =
942 vmw_master(vmw_fp->locked_master);
943
944 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
945 ttm_vt_unlock(&vmaster->lock);
946 drm_master_put(&vmw_fp->locked_master);
947 }
948
949 vmw_compat_shader_man_destroy(vmw_fp->shman);
950 ttm_object_file_release(&vmw_fp->tfile);
951 kfree(vmw_fp);
952}
953
954static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
955{
956 struct vmw_private *dev_priv = vmw_priv(dev);
957 struct vmw_fpriv *vmw_fp;
958 int ret = -ENOMEM;
959
960 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
961 if (unlikely(vmw_fp == NULL))
962 return ret;
963
964 INIT_LIST_HEAD(&vmw_fp->fence_events);
965 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
966 if (unlikely(vmw_fp->tfile == NULL))
967 goto out_no_tfile;
968
969 vmw_fp->shman = vmw_compat_shader_man_create(dev_priv);
970 if (IS_ERR(vmw_fp->shman))
971 goto out_no_shman;
972
973 file_priv->driver_priv = vmw_fp;
974
975 return 0;
976
977out_no_shman:
978 ttm_object_file_release(&vmw_fp->tfile);
979out_no_tfile:
980 kfree(vmw_fp);
981 return ret;
982}
983
984static struct vmw_master *vmw_master_check(struct drm_device *dev,
985 struct drm_file *file_priv,
986 unsigned int flags)
987{
988 int ret;
989 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
990 struct vmw_master *vmaster;
991
992 if (file_priv->minor->type != DRM_MINOR_LEGACY ||
993 !(flags & DRM_AUTH))
994 return NULL;
995
996 ret = mutex_lock_interruptible(&dev->master_mutex);
997 if (unlikely(ret != 0))
998 return ERR_PTR(-ERESTARTSYS);
999
1000 if (file_priv->is_master) {
1001 mutex_unlock(&dev->master_mutex);
1002 return NULL;
1003 }
1004
1005
1006
1007
1008 if (vmw_fp->locked_master) {
1009 mutex_unlock(&dev->master_mutex);
1010 DRM_ERROR("Dropped master trying to access ioctl that "
1011 "requires authentication.\n");
1012 return ERR_PTR(-EACCES);
1013 }
1014 mutex_unlock(&dev->master_mutex);
1015
1016
1017
1018
1019 if (!(flags & DRM_UNLOCKED)) {
1020 DRM_ERROR("Refusing locked ioctl access.\n");
1021 return ERR_PTR(-EDEADLK);
1022 }
1023
1024
1025
1026
1027
1028
1029 vmaster = vmw_master(file_priv->master);
1030 ret = ttm_read_lock(&vmaster->lock, true);
1031 if (unlikely(ret != 0))
1032 vmaster = ERR_PTR(ret);
1033
1034 return vmaster;
1035}
1036
1037static long vmw_generic_ioctl(struct file *filp, unsigned int cmd,
1038 unsigned long arg,
1039 long (*ioctl_func)(struct file *, unsigned int,
1040 unsigned long))
1041{
1042 struct drm_file *file_priv = filp->private_data;
1043 struct drm_device *dev = file_priv->minor->dev;
1044 unsigned int nr = DRM_IOCTL_NR(cmd);
1045 struct vmw_master *vmaster;
1046 unsigned int flags;
1047 long ret;
1048
1049
1050
1051
1052
1053 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
1054 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
1055 const struct drm_ioctl_desc *ioctl =
1056 &vmw_ioctls[nr - DRM_COMMAND_BASE];
1057
1058 if (unlikely(ioctl->cmd_drv != cmd)) {
1059 DRM_ERROR("Invalid command format, ioctl %d\n",
1060 nr - DRM_COMMAND_BASE);
1061 return -EINVAL;
1062 }
1063 flags = ioctl->flags;
1064 } else if (!drm_ioctl_flags(nr, &flags))
1065 return -EINVAL;
1066
1067 vmaster = vmw_master_check(dev, file_priv, flags);
1068 if (unlikely(IS_ERR(vmaster))) {
1069 DRM_INFO("IOCTL ERROR %d\n", nr);
1070 return PTR_ERR(vmaster);
1071 }
1072
1073 ret = ioctl_func(filp, cmd, arg);
1074 if (vmaster)
1075 ttm_read_unlock(&vmaster->lock);
1076
1077 return ret;
1078}
1079
1080static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
1081 unsigned long arg)
1082{
1083 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl);
1084}
1085
1086#ifdef CONFIG_COMPAT
1087static long vmw_compat_ioctl(struct file *filp, unsigned int cmd,
1088 unsigned long arg)
1089{
1090 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl);
1091}
1092#endif
1093
1094static void vmw_lastclose(struct drm_device *dev)
1095{
1096 struct drm_crtc *crtc;
1097 struct drm_mode_set set;
1098 int ret;
1099
1100 set.x = 0;
1101 set.y = 0;
1102 set.fb = NULL;
1103 set.mode = NULL;
1104 set.connectors = NULL;
1105 set.num_connectors = 0;
1106
1107 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1108 set.crtc = crtc;
1109 ret = drm_mode_set_config_internal(&set);
1110 WARN_ON(ret != 0);
1111 }
1112
1113}
1114
1115static void vmw_master_init(struct vmw_master *vmaster)
1116{
1117 ttm_lock_init(&vmaster->lock);
1118 INIT_LIST_HEAD(&vmaster->fb_surf);
1119 mutex_init(&vmaster->fb_surf_mutex);
1120}
1121
1122static int vmw_master_create(struct drm_device *dev,
1123 struct drm_master *master)
1124{
1125 struct vmw_master *vmaster;
1126
1127 vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL);
1128 if (unlikely(vmaster == NULL))
1129 return -ENOMEM;
1130
1131 vmw_master_init(vmaster);
1132 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
1133 master->driver_priv = vmaster;
1134
1135 return 0;
1136}
1137
1138static void vmw_master_destroy(struct drm_device *dev,
1139 struct drm_master *master)
1140{
1141 struct vmw_master *vmaster = vmw_master(master);
1142
1143 master->driver_priv = NULL;
1144 kfree(vmaster);
1145}
1146
1147
1148static int vmw_master_set(struct drm_device *dev,
1149 struct drm_file *file_priv,
1150 bool from_open)
1151{
1152 struct vmw_private *dev_priv = vmw_priv(dev);
1153 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1154 struct vmw_master *active = dev_priv->active_master;
1155 struct vmw_master *vmaster = vmw_master(file_priv->master);
1156 int ret = 0;
1157
1158 if (!dev_priv->enable_fb) {
1159 ret = vmw_3d_resource_inc(dev_priv, true);
1160 if (unlikely(ret != 0))
1161 return ret;
1162 vmw_kms_save_vga(dev_priv);
1163 mutex_lock(&dev_priv->hw_mutex);
1164 vmw_write(dev_priv, SVGA_REG_TRACES, 0);
1165 mutex_unlock(&dev_priv->hw_mutex);
1166 }
1167
1168 if (active) {
1169 BUG_ON(active != &dev_priv->fbdev_master);
1170 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
1171 if (unlikely(ret != 0))
1172 goto out_no_active_lock;
1173
1174 ttm_lock_set_kill(&active->lock, true, SIGTERM);
1175 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
1176 if (unlikely(ret != 0)) {
1177 DRM_ERROR("Unable to clean VRAM on "
1178 "master drop.\n");
1179 }
1180
1181 dev_priv->active_master = NULL;
1182 }
1183
1184 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1185 if (!from_open) {
1186 ttm_vt_unlock(&vmaster->lock);
1187 BUG_ON(vmw_fp->locked_master != file_priv->master);
1188 drm_master_put(&vmw_fp->locked_master);
1189 }
1190
1191 dev_priv->active_master = vmaster;
1192
1193 return 0;
1194
1195out_no_active_lock:
1196 if (!dev_priv->enable_fb) {
1197 vmw_kms_restore_vga(dev_priv);
1198 vmw_3d_resource_dec(dev_priv, true);
1199 mutex_lock(&dev_priv->hw_mutex);
1200 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
1201 mutex_unlock(&dev_priv->hw_mutex);
1202 }
1203 return ret;
1204}
1205
1206static void vmw_master_drop(struct drm_device *dev,
1207 struct drm_file *file_priv,
1208 bool from_release)
1209{
1210 struct vmw_private *dev_priv = vmw_priv(dev);
1211 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1212 struct vmw_master *vmaster = vmw_master(file_priv->master);
1213 int ret;
1214
1215
1216
1217
1218
1219
1220 vmw_fp->locked_master = drm_master_get(file_priv->master);
1221 ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
1222 if (unlikely((ret != 0))) {
1223 DRM_ERROR("Unable to lock TTM at VT switch.\n");
1224 drm_master_put(&vmw_fp->locked_master);
1225 }
1226
1227 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1228 vmw_execbuf_release_pinned_bo(dev_priv);
1229
1230 if (!dev_priv->enable_fb) {
1231 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
1232 if (unlikely(ret != 0))
1233 DRM_ERROR("Unable to clean VRAM on master drop.\n");
1234 vmw_kms_restore_vga(dev_priv);
1235 vmw_3d_resource_dec(dev_priv, true);
1236 mutex_lock(&dev_priv->hw_mutex);
1237 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
1238 mutex_unlock(&dev_priv->hw_mutex);
1239 }
1240
1241 dev_priv->active_master = &dev_priv->fbdev_master;
1242 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
1243 ttm_vt_unlock(&dev_priv->fbdev_master.lock);
1244
1245 if (dev_priv->enable_fb)
1246 vmw_fb_on(dev_priv);
1247}
1248
1249
1250static void vmw_remove(struct pci_dev *pdev)
1251{
1252 struct drm_device *dev = pci_get_drvdata(pdev);
1253
1254 drm_put_dev(dev);
1255}
1256
1257static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
1258 void *ptr)
1259{
1260 struct vmw_private *dev_priv =
1261 container_of(nb, struct vmw_private, pm_nb);
1262
1263 switch (val) {
1264 case PM_HIBERNATION_PREPARE:
1265 case PM_SUSPEND_PREPARE:
1266 ttm_suspend_lock(&dev_priv->reservation_sem);
1267
1268
1269
1270
1271
1272 vmw_execbuf_release_pinned_bo(dev_priv);
1273 vmw_resource_evict_all(dev_priv);
1274 ttm_bo_swapout_all(&dev_priv->bdev);
1275
1276 break;
1277 case PM_POST_HIBERNATION:
1278 case PM_POST_SUSPEND:
1279 case PM_POST_RESTORE:
1280 ttm_suspend_unlock(&dev_priv->reservation_sem);
1281
1282 break;
1283 case PM_RESTORE_PREPARE:
1284 break;
1285 default:
1286 break;
1287 }
1288 return 0;
1289}
1290
1291
1292
1293
1294
1295static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1296{
1297 struct drm_device *dev = pci_get_drvdata(pdev);
1298 struct vmw_private *dev_priv = vmw_priv(dev);
1299
1300 if (dev_priv->num_3d_resources != 0) {
1301 DRM_INFO("Can't suspend or hibernate "
1302 "while 3D resources are active.\n");
1303 return -EBUSY;
1304 }
1305
1306 pci_save_state(pdev);
1307 pci_disable_device(pdev);
1308 pci_set_power_state(pdev, PCI_D3hot);
1309 return 0;
1310}
1311
1312static int vmw_pci_resume(struct pci_dev *pdev)
1313{
1314 pci_set_power_state(pdev, PCI_D0);
1315 pci_restore_state(pdev);
1316 return pci_enable_device(pdev);
1317}
1318
1319static int vmw_pm_suspend(struct device *kdev)
1320{
1321 struct pci_dev *pdev = to_pci_dev(kdev);
1322 struct pm_message dummy;
1323
1324 dummy.event = 0;
1325
1326 return vmw_pci_suspend(pdev, dummy);
1327}
1328
1329static int vmw_pm_resume(struct device *kdev)
1330{
1331 struct pci_dev *pdev = to_pci_dev(kdev);
1332
1333 return vmw_pci_resume(pdev);
1334}
1335
1336static int vmw_pm_prepare(struct device *kdev)
1337{
1338 struct pci_dev *pdev = to_pci_dev(kdev);
1339 struct drm_device *dev = pci_get_drvdata(pdev);
1340 struct vmw_private *dev_priv = vmw_priv(dev);
1341
1342
1343
1344
1345
1346 dev_priv->suspended = true;
1347 if (dev_priv->enable_fb)
1348 vmw_3d_resource_dec(dev_priv, true);
1349
1350 if (dev_priv->num_3d_resources != 0) {
1351
1352 DRM_INFO("Can't suspend or hibernate "
1353 "while 3D resources are active.\n");
1354
1355 if (dev_priv->enable_fb)
1356 vmw_3d_resource_inc(dev_priv, true);
1357 dev_priv->suspended = false;
1358 return -EBUSY;
1359 }
1360
1361 return 0;
1362}
1363
1364static void vmw_pm_complete(struct device *kdev)
1365{
1366 struct pci_dev *pdev = to_pci_dev(kdev);
1367 struct drm_device *dev = pci_get_drvdata(pdev);
1368 struct vmw_private *dev_priv = vmw_priv(dev);
1369
1370 mutex_lock(&dev_priv->hw_mutex);
1371 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
1372 (void) vmw_read(dev_priv, SVGA_REG_ID);
1373 mutex_unlock(&dev_priv->hw_mutex);
1374
1375
1376
1377
1378
1379 if (dev_priv->enable_fb)
1380 vmw_3d_resource_inc(dev_priv, false);
1381
1382 dev_priv->suspended = false;
1383}
1384
1385static const struct dev_pm_ops vmw_pm_ops = {
1386 .prepare = vmw_pm_prepare,
1387 .complete = vmw_pm_complete,
1388 .suspend = vmw_pm_suspend,
1389 .resume = vmw_pm_resume,
1390};
1391
1392static const struct file_operations vmwgfx_driver_fops = {
1393 .owner = THIS_MODULE,
1394 .open = drm_open,
1395 .release = drm_release,
1396 .unlocked_ioctl = vmw_unlocked_ioctl,
1397 .mmap = vmw_mmap,
1398 .poll = vmw_fops_poll,
1399 .read = vmw_fops_read,
1400#if defined(CONFIG_COMPAT)
1401 .compat_ioctl = vmw_compat_ioctl,
1402#endif
1403 .llseek = noop_llseek,
1404};
1405
1406static struct drm_driver driver = {
1407 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
1408 DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER,
1409 .load = vmw_driver_load,
1410 .unload = vmw_driver_unload,
1411 .lastclose = vmw_lastclose,
1412 .irq_preinstall = vmw_irq_preinstall,
1413 .irq_postinstall = vmw_irq_postinstall,
1414 .irq_uninstall = vmw_irq_uninstall,
1415 .irq_handler = vmw_irq_handler,
1416 .get_vblank_counter = vmw_get_vblank_counter,
1417 .enable_vblank = vmw_enable_vblank,
1418 .disable_vblank = vmw_disable_vblank,
1419 .ioctls = vmw_ioctls,
1420 .num_ioctls = DRM_ARRAY_SIZE(vmw_ioctls),
1421 .master_create = vmw_master_create,
1422 .master_destroy = vmw_master_destroy,
1423 .master_set = vmw_master_set,
1424 .master_drop = vmw_master_drop,
1425 .open = vmw_driver_open,
1426 .preclose = vmw_preclose,
1427 .postclose = vmw_postclose,
1428
1429 .dumb_create = vmw_dumb_create,
1430 .dumb_map_offset = vmw_dumb_map_offset,
1431 .dumb_destroy = vmw_dumb_destroy,
1432
1433 .prime_fd_to_handle = vmw_prime_fd_to_handle,
1434 .prime_handle_to_fd = vmw_prime_handle_to_fd,
1435
1436 .fops = &vmwgfx_driver_fops,
1437 .name = VMWGFX_DRIVER_NAME,
1438 .desc = VMWGFX_DRIVER_DESC,
1439 .date = VMWGFX_DRIVER_DATE,
1440 .major = VMWGFX_DRIVER_MAJOR,
1441 .minor = VMWGFX_DRIVER_MINOR,
1442 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
1443};
1444
1445static struct pci_driver vmw_pci_driver = {
1446 .name = VMWGFX_DRIVER_NAME,
1447 .id_table = vmw_pci_id_list,
1448 .probe = vmw_probe,
1449 .remove = vmw_remove,
1450 .driver = {
1451 .pm = &vmw_pm_ops
1452 }
1453};
1454
1455static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1456{
1457 return drm_get_pci_dev(pdev, ent, &driver);
1458}
1459
1460static int __init vmwgfx_init(void)
1461{
1462 int ret;
1463 ret = drm_pci_init(&driver, &vmw_pci_driver);
1464 if (ret)
1465 DRM_ERROR("Failed initializing DRM.\n");
1466 return ret;
1467}
1468
1469static void __exit vmwgfx_exit(void)
1470{
1471 drm_pci_exit(&driver, &vmw_pci_driver);
1472}
1473
1474module_init(vmwgfx_init);
1475module_exit(vmwgfx_exit);
1476
1477MODULE_AUTHOR("VMware Inc. and others");
1478MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1479MODULE_LICENSE("GPL and additional rights");
1480MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
1481 __stringify(VMWGFX_DRIVER_MINOR) "."
1482 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
1483 "0");
1484
