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24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/init.h>
27#include <linux/delay.h>
28#include <linux/string.h>
29#include <linux/slab.h>
30
31#include "dvb_frontend.h"
32
33#include "dib3000.h"
34#include "dib3000mb_priv.h"
35
36
37#define DRIVER_VERSION "0.1"
38#define DRIVER_DESC "DiBcom 3000M-B DVB-T demodulator"
39#define DRIVER_AUTHOR "Patrick Boettcher, patrick.boettcher@desy.de"
40
41static int debug;
42module_param(debug, int, 0644);
43MODULE_PARM_DESC(debug, "set debugging level (1=info,2=xfer,4=setfe,8=getfe (|-able)).");
44
45#define deb_info(args...) dprintk(0x01,args)
46#define deb_i2c(args...) dprintk(0x02,args)
47#define deb_srch(args...) dprintk(0x04,args)
48#define deb_info(args...) dprintk(0x01,args)
49#define deb_xfer(args...) dprintk(0x02,args)
50#define deb_setf(args...) dprintk(0x04,args)
51#define deb_getf(args...) dprintk(0x08,args)
52
53static int dib3000_read_reg(struct dib3000_state *state, u16 reg)
54{
55 u8 wb[] = { ((reg >> 8) | 0x80) & 0xff, reg & 0xff };
56 u8 rb[2];
57 struct i2c_msg msg[] = {
58 { .addr = state->config.demod_address, .flags = 0, .buf = wb, .len = 2 },
59 { .addr = state->config.demod_address, .flags = I2C_M_RD, .buf = rb, .len = 2 },
60 };
61
62 if (i2c_transfer(state->i2c, msg, 2) != 2)
63 deb_i2c("i2c read error\n");
64
65 deb_i2c("reading i2c bus (reg: %5d 0x%04x, val: %5d 0x%04x)\n",reg,reg,
66 (rb[0] << 8) | rb[1],(rb[0] << 8) | rb[1]);
67
68 return (rb[0] << 8) | rb[1];
69}
70
71static int dib3000_write_reg(struct dib3000_state *state, u16 reg, u16 val)
72{
73 u8 b[] = {
74 (reg >> 8) & 0xff, reg & 0xff,
75 (val >> 8) & 0xff, val & 0xff,
76 };
77 struct i2c_msg msg[] = {
78 { .addr = state->config.demod_address, .flags = 0, .buf = b, .len = 4 }
79 };
80 deb_i2c("writing i2c bus (reg: %5d 0x%04x, val: %5d 0x%04x)\n",reg,reg,val,val);
81
82 return i2c_transfer(state->i2c,msg, 1) != 1 ? -EREMOTEIO : 0;
83}
84
85static int dib3000_search_status(u16 irq,u16 lock)
86{
87 if (irq & 0x02) {
88 if (lock & 0x01) {
89 deb_srch("auto search succeeded\n");
90 return 1;
91 } else {
92 deb_srch("auto search not successful\n");
93 return 0;
94 }
95 } else if (irq & 0x01) {
96 deb_srch("auto search failed\n");
97 return 0;
98 }
99 return -1;
100}
101
102
103static u16 dib3000_seq[2][2][2] =
104 {
105 {
106 { 0, 1 },
107 { 3, 9 },
108 },
109 {
110 { 2, 5 },
111 { 6, 11 },
112 }
113 };
114
115static int dib3000mb_get_frontend(struct dvb_frontend* fe);
116
117static int dib3000mb_set_frontend(struct dvb_frontend *fe, int tuner)
118{
119 struct dib3000_state* state = fe->demodulator_priv;
120 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
121 fe_code_rate_t fe_cr = FEC_NONE;
122 int search_state, seq;
123
124 if (tuner && fe->ops.tuner_ops.set_params) {
125 fe->ops.tuner_ops.set_params(fe);
126 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
127
128 deb_setf("bandwidth: ");
129 switch (c->bandwidth_hz) {
130 case 8000000:
131 deb_setf("8 MHz\n");
132 wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[2]);
133 wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_8mhz);
134 break;
135 case 7000000:
136 deb_setf("7 MHz\n");
137 wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[1]);
138 wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_7mhz);
139 break;
140 case 6000000:
141 deb_setf("6 MHz\n");
142 wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[0]);
143 wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_6mhz);
144 break;
145 case 0:
146 return -EOPNOTSUPP;
147 default:
148 err("unknown bandwidth value.");
149 return -EINVAL;
150 }
151 }
152 wr(DIB3000MB_REG_LOCK1_MASK, DIB3000MB_LOCK1_SEARCH_4);
153
154 deb_setf("transmission mode: ");
155 switch (c->transmission_mode) {
156 case TRANSMISSION_MODE_2K:
157 deb_setf("2k\n");
158 wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_2K);
159 break;
160 case TRANSMISSION_MODE_8K:
161 deb_setf("8k\n");
162 wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_8K);
163 break;
164 case TRANSMISSION_MODE_AUTO:
165 deb_setf("auto\n");
166 break;
167 default:
168 return -EINVAL;
169 }
170
171 deb_setf("guard: ");
172 switch (c->guard_interval) {
173 case GUARD_INTERVAL_1_32:
174 deb_setf("1_32\n");
175 wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_32);
176 break;
177 case GUARD_INTERVAL_1_16:
178 deb_setf("1_16\n");
179 wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_16);
180 break;
181 case GUARD_INTERVAL_1_8:
182 deb_setf("1_8\n");
183 wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_8);
184 break;
185 case GUARD_INTERVAL_1_4:
186 deb_setf("1_4\n");
187 wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_4);
188 break;
189 case GUARD_INTERVAL_AUTO:
190 deb_setf("auto\n");
191 break;
192 default:
193 return -EINVAL;
194 }
195
196 deb_setf("inversion: ");
197 switch (c->inversion) {
198 case INVERSION_OFF:
199 deb_setf("off\n");
200 wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_OFF);
201 break;
202 case INVERSION_AUTO:
203 deb_setf("auto ");
204 break;
205 case INVERSION_ON:
206 deb_setf("on\n");
207 wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_ON);
208 break;
209 default:
210 return -EINVAL;
211 }
212
213 deb_setf("modulation: ");
214 switch (c->modulation) {
215 case QPSK:
216 deb_setf("qpsk\n");
217 wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_QPSK);
218 break;
219 case QAM_16:
220 deb_setf("qam16\n");
221 wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_16QAM);
222 break;
223 case QAM_64:
224 deb_setf("qam64\n");
225 wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_64QAM);
226 break;
227 case QAM_AUTO:
228 break;
229 default:
230 return -EINVAL;
231 }
232 deb_setf("hierarchy: ");
233 switch (c->hierarchy) {
234 case HIERARCHY_NONE:
235 deb_setf("none ");
236
237 case HIERARCHY_1:
238 deb_setf("alpha=1\n");
239 wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_1);
240 break;
241 case HIERARCHY_2:
242 deb_setf("alpha=2\n");
243 wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_2);
244 break;
245 case HIERARCHY_4:
246 deb_setf("alpha=4\n");
247 wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_4);
248 break;
249 case HIERARCHY_AUTO:
250 deb_setf("alpha=auto\n");
251 break;
252 default:
253 return -EINVAL;
254 }
255
256 deb_setf("hierarchy: ");
257 if (c->hierarchy == HIERARCHY_NONE) {
258 deb_setf("none\n");
259 wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_OFF);
260 wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_HP);
261 fe_cr = c->code_rate_HP;
262 } else if (c->hierarchy != HIERARCHY_AUTO) {
263 deb_setf("on\n");
264 wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_ON);
265 wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_LP);
266 fe_cr = c->code_rate_LP;
267 }
268 deb_setf("fec: ");
269 switch (fe_cr) {
270 case FEC_1_2:
271 deb_setf("1_2\n");
272 wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_1_2);
273 break;
274 case FEC_2_3:
275 deb_setf("2_3\n");
276 wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_2_3);
277 break;
278 case FEC_3_4:
279 deb_setf("3_4\n");
280 wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_3_4);
281 break;
282 case FEC_5_6:
283 deb_setf("5_6\n");
284 wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_5_6);
285 break;
286 case FEC_7_8:
287 deb_setf("7_8\n");
288 wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_7_8);
289 break;
290 case FEC_NONE:
291 deb_setf("none ");
292 break;
293 case FEC_AUTO:
294 deb_setf("auto\n");
295 break;
296 default:
297 return -EINVAL;
298 }
299
300 seq = dib3000_seq
301 [c->transmission_mode == TRANSMISSION_MODE_AUTO]
302 [c->guard_interval == GUARD_INTERVAL_AUTO]
303 [c->inversion == INVERSION_AUTO];
304
305 deb_setf("seq? %d\n", seq);
306
307 wr(DIB3000MB_REG_SEQ, seq);
308
309 wr(DIB3000MB_REG_ISI, seq ? DIB3000MB_ISI_INHIBIT : DIB3000MB_ISI_ACTIVATE);
310
311 if (c->transmission_mode == TRANSMISSION_MODE_2K) {
312 if (c->guard_interval == GUARD_INTERVAL_1_8) {
313 wr(DIB3000MB_REG_SYNC_IMPROVEMENT, DIB3000MB_SYNC_IMPROVE_2K_1_8);
314 } else {
315 wr(DIB3000MB_REG_SYNC_IMPROVEMENT, DIB3000MB_SYNC_IMPROVE_DEFAULT);
316 }
317
318 wr(DIB3000MB_REG_UNK_121, DIB3000MB_UNK_121_2K);
319 } else {
320 wr(DIB3000MB_REG_UNK_121, DIB3000MB_UNK_121_DEFAULT);
321 }
322
323 wr(DIB3000MB_REG_MOBILE_ALGO, DIB3000MB_MOBILE_ALGO_OFF);
324 wr(DIB3000MB_REG_MOBILE_MODE_QAM, DIB3000MB_MOBILE_MODE_QAM_OFF);
325 wr(DIB3000MB_REG_MOBILE_MODE, DIB3000MB_MOBILE_MODE_OFF);
326
327 wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_high);
328
329 wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_ACTIVATE);
330
331 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AGC + DIB3000MB_RESTART_CTRL);
332 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF);
333
334
335 msleep(70);
336
337 wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_low);
338
339
340 if (c->modulation == QAM_AUTO ||
341 c->hierarchy == HIERARCHY_AUTO ||
342 fe_cr == FEC_AUTO ||
343 c->inversion == INVERSION_AUTO) {
344 int as_count=0;
345
346 deb_setf("autosearch enabled.\n");
347
348 wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_INHIBIT);
349
350 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AUTO_SEARCH);
351 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF);
352
353 while ((search_state =
354 dib3000_search_status(
355 rd(DIB3000MB_REG_AS_IRQ_PENDING),
356 rd(DIB3000MB_REG_LOCK2_VALUE))) < 0 && as_count++ < 100)
357 msleep(1);
358
359 deb_setf("search_state after autosearch %d after %d checks\n",search_state,as_count);
360
361 if (search_state == 1) {
362 if (dib3000mb_get_frontend(fe) == 0) {
363 deb_setf("reading tuning data from frontend succeeded.\n");
364 return dib3000mb_set_frontend(fe, 0);
365 }
366 }
367
368 } else {
369 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_CTRL);
370 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF);
371 }
372
373 return 0;
374}
375
376static int dib3000mb_fe_init(struct dvb_frontend* fe, int mobile_mode)
377{
378 struct dib3000_state* state = fe->demodulator_priv;
379
380 deb_info("dib3000mb is getting up.\n");
381 wr(DIB3000MB_REG_POWER_CONTROL, DIB3000MB_POWER_UP);
382
383 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AGC);
384
385 wr(DIB3000MB_REG_RESET_DEVICE, DIB3000MB_RESET_DEVICE);
386 wr(DIB3000MB_REG_RESET_DEVICE, DIB3000MB_RESET_DEVICE_RST);
387
388 wr(DIB3000MB_REG_CLOCK, DIB3000MB_CLOCK_DEFAULT);
389
390 wr(DIB3000MB_REG_ELECT_OUT_MODE, DIB3000MB_ELECT_OUT_MODE_ON);
391
392 wr(DIB3000MB_REG_DDS_FREQ_MSB, DIB3000MB_DDS_FREQ_MSB);
393 wr(DIB3000MB_REG_DDS_FREQ_LSB, DIB3000MB_DDS_FREQ_LSB);
394
395 wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[2]);
396
397 wr_foreach(dib3000mb_reg_impulse_noise,
398 dib3000mb_impulse_noise_values[DIB3000MB_IMPNOISE_OFF]);
399
400 wr_foreach(dib3000mb_reg_agc_gain, dib3000mb_default_agc_gain);
401
402 wr(DIB3000MB_REG_PHASE_NOISE, DIB3000MB_PHASE_NOISE_DEFAULT);
403
404 wr_foreach(dib3000mb_reg_phase_noise, dib3000mb_default_noise_phase);
405
406 wr_foreach(dib3000mb_reg_lock_duration, dib3000mb_default_lock_duration);
407
408 wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_low);
409
410 wr(DIB3000MB_REG_LOCK0_MASK, DIB3000MB_LOCK0_DEFAULT);
411 wr(DIB3000MB_REG_LOCK1_MASK, DIB3000MB_LOCK1_SEARCH_4);
412 wr(DIB3000MB_REG_LOCK2_MASK, DIB3000MB_LOCK2_DEFAULT);
413 wr(DIB3000MB_REG_SEQ, dib3000_seq[1][1][1]);
414
415 wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_8mhz);
416
417 wr(DIB3000MB_REG_UNK_68, DIB3000MB_UNK_68);
418 wr(DIB3000MB_REG_UNK_69, DIB3000MB_UNK_69);
419 wr(DIB3000MB_REG_UNK_71, DIB3000MB_UNK_71);
420 wr(DIB3000MB_REG_UNK_77, DIB3000MB_UNK_77);
421 wr(DIB3000MB_REG_UNK_78, DIB3000MB_UNK_78);
422 wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_INHIBIT);
423 wr(DIB3000MB_REG_UNK_92, DIB3000MB_UNK_92);
424 wr(DIB3000MB_REG_UNK_96, DIB3000MB_UNK_96);
425 wr(DIB3000MB_REG_UNK_97, DIB3000MB_UNK_97);
426 wr(DIB3000MB_REG_UNK_106, DIB3000MB_UNK_106);
427 wr(DIB3000MB_REG_UNK_107, DIB3000MB_UNK_107);
428 wr(DIB3000MB_REG_UNK_108, DIB3000MB_UNK_108);
429 wr(DIB3000MB_REG_UNK_122, DIB3000MB_UNK_122);
430 wr(DIB3000MB_REG_MOBILE_MODE_QAM, DIB3000MB_MOBILE_MODE_QAM_OFF);
431 wr(DIB3000MB_REG_BERLEN, DIB3000MB_BERLEN_DEFAULT);
432
433 wr_foreach(dib3000mb_reg_filter_coeffs, dib3000mb_filter_coeffs);
434
435 wr(DIB3000MB_REG_MOBILE_ALGO, DIB3000MB_MOBILE_ALGO_ON);
436 wr(DIB3000MB_REG_MULTI_DEMOD_MSB, DIB3000MB_MULTI_DEMOD_MSB);
437 wr(DIB3000MB_REG_MULTI_DEMOD_LSB, DIB3000MB_MULTI_DEMOD_LSB);
438
439 wr(DIB3000MB_REG_OUTPUT_MODE, DIB3000MB_OUTPUT_MODE_SLAVE);
440
441 wr(DIB3000MB_REG_FIFO_142, DIB3000MB_FIFO_142);
442 wr(DIB3000MB_REG_MPEG2_OUT_MODE, DIB3000MB_MPEG2_OUT_MODE_188);
443 wr(DIB3000MB_REG_PID_PARSE, DIB3000MB_PID_PARSE_ACTIVATE);
444 wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_INHIBIT);
445 wr(DIB3000MB_REG_FIFO_146, DIB3000MB_FIFO_146);
446 wr(DIB3000MB_REG_FIFO_147, DIB3000MB_FIFO_147);
447
448 wr(DIB3000MB_REG_DATA_IN_DIVERSITY, DIB3000MB_DATA_DIVERSITY_IN_OFF);
449
450 return 0;
451}
452
453static int dib3000mb_get_frontend(struct dvb_frontend* fe)
454{
455 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
456 struct dib3000_state* state = fe->demodulator_priv;
457 fe_code_rate_t *cr;
458 u16 tps_val;
459 int inv_test1,inv_test2;
460 u32 dds_val, threshold = 0x800000;
461
462 if (!rd(DIB3000MB_REG_TPS_LOCK))
463 return 0;
464
465 dds_val = ((rd(DIB3000MB_REG_DDS_VALUE_MSB) & 0xff) << 16) + rd(DIB3000MB_REG_DDS_VALUE_LSB);
466 deb_getf("DDS_VAL: %x %x %x",dds_val, rd(DIB3000MB_REG_DDS_VALUE_MSB), rd(DIB3000MB_REG_DDS_VALUE_LSB));
467 if (dds_val < threshold)
468 inv_test1 = 0;
469 else if (dds_val == threshold)
470 inv_test1 = 1;
471 else
472 inv_test1 = 2;
473
474 dds_val = ((rd(DIB3000MB_REG_DDS_FREQ_MSB) & 0xff) << 16) + rd(DIB3000MB_REG_DDS_FREQ_LSB);
475 deb_getf("DDS_FREQ: %x %x %x",dds_val, rd(DIB3000MB_REG_DDS_FREQ_MSB), rd(DIB3000MB_REG_DDS_FREQ_LSB));
476 if (dds_val < threshold)
477 inv_test2 = 0;
478 else if (dds_val == threshold)
479 inv_test2 = 1;
480 else
481 inv_test2 = 2;
482
483 c->inversion =
484 ((inv_test2 == 2) && (inv_test1==1 || inv_test1==0)) ||
485 ((inv_test2 == 0) && (inv_test1==1 || inv_test1==2)) ?
486 INVERSION_ON : INVERSION_OFF;
487
488 deb_getf("inversion %d %d, %d\n", inv_test2, inv_test1, c->inversion);
489
490 switch ((tps_val = rd(DIB3000MB_REG_TPS_QAM))) {
491 case DIB3000_CONSTELLATION_QPSK:
492 deb_getf("QPSK ");
493 c->modulation = QPSK;
494 break;
495 case DIB3000_CONSTELLATION_16QAM:
496 deb_getf("QAM16 ");
497 c->modulation = QAM_16;
498 break;
499 case DIB3000_CONSTELLATION_64QAM:
500 deb_getf("QAM64 ");
501 c->modulation = QAM_64;
502 break;
503 default:
504 err("Unexpected constellation returned by TPS (%d)", tps_val);
505 break;
506 }
507 deb_getf("TPS: %d\n", tps_val);
508
509 if (rd(DIB3000MB_REG_TPS_HRCH)) {
510 deb_getf("HRCH ON\n");
511 cr = &c->code_rate_LP;
512 c->code_rate_HP = FEC_NONE;
513 switch ((tps_val = rd(DIB3000MB_REG_TPS_VIT_ALPHA))) {
514 case DIB3000_ALPHA_0:
515 deb_getf("HIERARCHY_NONE ");
516 c->hierarchy = HIERARCHY_NONE;
517 break;
518 case DIB3000_ALPHA_1:
519 deb_getf("HIERARCHY_1 ");
520 c->hierarchy = HIERARCHY_1;
521 break;
522 case DIB3000_ALPHA_2:
523 deb_getf("HIERARCHY_2 ");
524 c->hierarchy = HIERARCHY_2;
525 break;
526 case DIB3000_ALPHA_4:
527 deb_getf("HIERARCHY_4 ");
528 c->hierarchy = HIERARCHY_4;
529 break;
530 default:
531 err("Unexpected ALPHA value returned by TPS (%d)", tps_val);
532 break;
533 }
534 deb_getf("TPS: %d\n", tps_val);
535
536 tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_LP);
537 } else {
538 deb_getf("HRCH OFF\n");
539 cr = &c->code_rate_HP;
540 c->code_rate_LP = FEC_NONE;
541 c->hierarchy = HIERARCHY_NONE;
542
543 tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_HP);
544 }
545
546 switch (tps_val) {
547 case DIB3000_FEC_1_2:
548 deb_getf("FEC_1_2 ");
549 *cr = FEC_1_2;
550 break;
551 case DIB3000_FEC_2_3:
552 deb_getf("FEC_2_3 ");
553 *cr = FEC_2_3;
554 break;
555 case DIB3000_FEC_3_4:
556 deb_getf("FEC_3_4 ");
557 *cr = FEC_3_4;
558 break;
559 case DIB3000_FEC_5_6:
560 deb_getf("FEC_5_6 ");
561 *cr = FEC_4_5;
562 break;
563 case DIB3000_FEC_7_8:
564 deb_getf("FEC_7_8 ");
565 *cr = FEC_7_8;
566 break;
567 default:
568 err("Unexpected FEC returned by TPS (%d)", tps_val);
569 break;
570 }
571 deb_getf("TPS: %d\n",tps_val);
572
573 switch ((tps_val = rd(DIB3000MB_REG_TPS_GUARD_TIME))) {
574 case DIB3000_GUARD_TIME_1_32:
575 deb_getf("GUARD_INTERVAL_1_32 ");
576 c->guard_interval = GUARD_INTERVAL_1_32;
577 break;
578 case DIB3000_GUARD_TIME_1_16:
579 deb_getf("GUARD_INTERVAL_1_16 ");
580 c->guard_interval = GUARD_INTERVAL_1_16;
581 break;
582 case DIB3000_GUARD_TIME_1_8:
583 deb_getf("GUARD_INTERVAL_1_8 ");
584 c->guard_interval = GUARD_INTERVAL_1_8;
585 break;
586 case DIB3000_GUARD_TIME_1_4:
587 deb_getf("GUARD_INTERVAL_1_4 ");
588 c->guard_interval = GUARD_INTERVAL_1_4;
589 break;
590 default:
591 err("Unexpected Guard Time returned by TPS (%d)", tps_val);
592 break;
593 }
594 deb_getf("TPS: %d\n", tps_val);
595
596 switch ((tps_val = rd(DIB3000MB_REG_TPS_FFT))) {
597 case DIB3000_TRANSMISSION_MODE_2K:
598 deb_getf("TRANSMISSION_MODE_2K ");
599 c->transmission_mode = TRANSMISSION_MODE_2K;
600 break;
601 case DIB3000_TRANSMISSION_MODE_8K:
602 deb_getf("TRANSMISSION_MODE_8K ");
603 c->transmission_mode = TRANSMISSION_MODE_8K;
604 break;
605 default:
606 err("unexpected transmission mode return by TPS (%d)", tps_val);
607 break;
608 }
609 deb_getf("TPS: %d\n", tps_val);
610
611 return 0;
612}
613
614static int dib3000mb_read_status(struct dvb_frontend* fe, fe_status_t *stat)
615{
616 struct dib3000_state* state = fe->demodulator_priv;
617
618 *stat = 0;
619
620 if (rd(DIB3000MB_REG_AGC_LOCK))
621 *stat |= FE_HAS_SIGNAL;
622 if (rd(DIB3000MB_REG_CARRIER_LOCK))
623 *stat |= FE_HAS_CARRIER;
624 if (rd(DIB3000MB_REG_VIT_LCK))
625 *stat |= FE_HAS_VITERBI;
626 if (rd(DIB3000MB_REG_TS_SYNC_LOCK))
627 *stat |= (FE_HAS_SYNC | FE_HAS_LOCK);
628
629 deb_getf("actual status is %2x\n",*stat);
630
631 deb_getf("autoval: tps: %d, qam: %d, hrch: %d, alpha: %d, hp: %d, lp: %d, guard: %d, fft: %d cell: %d\n",
632 rd(DIB3000MB_REG_TPS_LOCK),
633 rd(DIB3000MB_REG_TPS_QAM),
634 rd(DIB3000MB_REG_TPS_HRCH),
635 rd(DIB3000MB_REG_TPS_VIT_ALPHA),
636 rd(DIB3000MB_REG_TPS_CODE_RATE_HP),
637 rd(DIB3000MB_REG_TPS_CODE_RATE_LP),
638 rd(DIB3000MB_REG_TPS_GUARD_TIME),
639 rd(DIB3000MB_REG_TPS_FFT),
640 rd(DIB3000MB_REG_TPS_CELL_ID));
641
642
643 return 0;
644}
645
646static int dib3000mb_read_ber(struct dvb_frontend* fe, u32 *ber)
647{
648 struct dib3000_state* state = fe->demodulator_priv;
649
650 *ber = ((rd(DIB3000MB_REG_BER_MSB) << 16) | rd(DIB3000MB_REG_BER_LSB));
651 return 0;
652}
653
654
655static int dib3000mb_read_signal_strength(struct dvb_frontend* fe, u16 *strength)
656{
657 struct dib3000_state* state = fe->demodulator_priv;
658
659 *strength = rd(DIB3000MB_REG_SIGNAL_POWER) * 0xffff / 0x170;
660 return 0;
661}
662
663static int dib3000mb_read_snr(struct dvb_frontend* fe, u16 *snr)
664{
665 struct dib3000_state* state = fe->demodulator_priv;
666 short sigpow = rd(DIB3000MB_REG_SIGNAL_POWER);
667 int icipow = ((rd(DIB3000MB_REG_NOISE_POWER_MSB) & 0xff) << 16) |
668 rd(DIB3000MB_REG_NOISE_POWER_LSB);
669 *snr = (sigpow << 8) / ((icipow > 0) ? icipow : 1);
670 return 0;
671}
672
673static int dib3000mb_read_unc_blocks(struct dvb_frontend* fe, u32 *unc)
674{
675 struct dib3000_state* state = fe->demodulator_priv;
676
677 *unc = rd(DIB3000MB_REG_PACKET_ERROR_RATE);
678 return 0;
679}
680
681static int dib3000mb_sleep(struct dvb_frontend* fe)
682{
683 struct dib3000_state* state = fe->demodulator_priv;
684 deb_info("dib3000mb is going to bed.\n");
685 wr(DIB3000MB_REG_POWER_CONTROL, DIB3000MB_POWER_DOWN);
686 return 0;
687}
688
689static int dib3000mb_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune)
690{
691 tune->min_delay_ms = 800;
692 return 0;
693}
694
695static int dib3000mb_fe_init_nonmobile(struct dvb_frontend* fe)
696{
697 return dib3000mb_fe_init(fe, 0);
698}
699
700static int dib3000mb_set_frontend_and_tuner(struct dvb_frontend *fe)
701{
702 return dib3000mb_set_frontend(fe, 1);
703}
704
705static void dib3000mb_release(struct dvb_frontend* fe)
706{
707 struct dib3000_state *state = fe->demodulator_priv;
708 kfree(state);
709}
710
711
712static int dib3000mb_pid_control(struct dvb_frontend *fe,int index, int pid,int onoff)
713{
714 struct dib3000_state *state = fe->demodulator_priv;
715 pid = (onoff ? pid | DIB3000_ACTIVATE_PID_FILTERING : 0);
716 wr(index+DIB3000MB_REG_FIRST_PID,pid);
717 return 0;
718}
719
720static int dib3000mb_fifo_control(struct dvb_frontend *fe, int onoff)
721{
722 struct dib3000_state *state = fe->demodulator_priv;
723
724 deb_xfer("%s fifo\n",onoff ? "enabling" : "disabling");
725 if (onoff) {
726 wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_ACTIVATE);
727 } else {
728 wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_INHIBIT);
729 }
730 return 0;
731}
732
733static int dib3000mb_pid_parse(struct dvb_frontend *fe, int onoff)
734{
735 struct dib3000_state *state = fe->demodulator_priv;
736 deb_xfer("%s pid parsing\n",onoff ? "enabling" : "disabling");
737 wr(DIB3000MB_REG_PID_PARSE,onoff);
738 return 0;
739}
740
741static int dib3000mb_tuner_pass_ctrl(struct dvb_frontend *fe, int onoff, u8 pll_addr)
742{
743 struct dib3000_state *state = fe->demodulator_priv;
744 if (onoff) {
745 wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_ENABLE(pll_addr));
746 } else {
747 wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_DISABLE(pll_addr));
748 }
749 return 0;
750}
751
752static struct dvb_frontend_ops dib3000mb_ops;
753
754struct dvb_frontend* dib3000mb_attach(const struct dib3000_config* config,
755 struct i2c_adapter* i2c, struct dib_fe_xfer_ops *xfer_ops)
756{
757 struct dib3000_state* state = NULL;
758
759
760 state = kzalloc(sizeof(struct dib3000_state), GFP_KERNEL);
761 if (state == NULL)
762 goto error;
763
764
765 state->i2c = i2c;
766 memcpy(&state->config,config,sizeof(struct dib3000_config));
767
768
769 if (rd(DIB3000_REG_MANUFACTOR_ID) != DIB3000_I2C_ID_DIBCOM)
770 goto error;
771
772 if (rd(DIB3000_REG_DEVICE_ID) != DIB3000MB_DEVICE_ID)
773 goto error;
774
775
776 memcpy(&state->frontend.ops, &dib3000mb_ops, sizeof(struct dvb_frontend_ops));
777 state->frontend.demodulator_priv = state;
778
779
780 xfer_ops->pid_parse = dib3000mb_pid_parse;
781 xfer_ops->fifo_ctrl = dib3000mb_fifo_control;
782 xfer_ops->pid_ctrl = dib3000mb_pid_control;
783 xfer_ops->tuner_pass_ctrl = dib3000mb_tuner_pass_ctrl;
784
785 return &state->frontend;
786
787error:
788 kfree(state);
789 return NULL;
790}
791
792static struct dvb_frontend_ops dib3000mb_ops = {
793 .delsys = { SYS_DVBT },
794 .info = {
795 .name = "DiBcom 3000M-B DVB-T",
796 .frequency_min = 44250000,
797 .frequency_max = 867250000,
798 .frequency_stepsize = 62500,
799 .caps = FE_CAN_INVERSION_AUTO |
800 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
801 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
802 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
803 FE_CAN_TRANSMISSION_MODE_AUTO |
804 FE_CAN_GUARD_INTERVAL_AUTO |
805 FE_CAN_RECOVER |
806 FE_CAN_HIERARCHY_AUTO,
807 },
808
809 .release = dib3000mb_release,
810
811 .init = dib3000mb_fe_init_nonmobile,
812 .sleep = dib3000mb_sleep,
813
814 .set_frontend = dib3000mb_set_frontend_and_tuner,
815 .get_frontend = dib3000mb_get_frontend,
816 .get_tune_settings = dib3000mb_fe_get_tune_settings,
817
818 .read_status = dib3000mb_read_status,
819 .read_ber = dib3000mb_read_ber,
820 .read_signal_strength = dib3000mb_read_signal_strength,
821 .read_snr = dib3000mb_read_snr,
822 .read_ucblocks = dib3000mb_read_unc_blocks,
823};
824
825MODULE_AUTHOR(DRIVER_AUTHOR);
826MODULE_DESCRIPTION(DRIVER_DESC);
827MODULE_LICENSE("GPL");
828
829EXPORT_SYMBOL(dib3000mb_attach);
830
