1
2#ifndef _VSC7321_REG_H_
3#define _VSC7321_REG_H_
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12
13#define CRA(blk,sub,adr) ((((blk) & 0x7) << 13) | (((sub) & 0xf) << 9) | (((adr) & 0xff) << 1))
14
15
16#define REG_CHIP_ID CRA(0x7,0xf,0x00)
17#define REG_BLADE_ID CRA(0x7,0xf,0x01)
18#define REG_SW_RESET CRA(0x7,0xf,0x02)
19#define REG_MEM_BIST CRA(0x7,0xf,0x04)
20#define REG_IFACE_MODE CRA(0x7,0xf,0x07)
21#define REG_MSCH CRA(0x7,0x2,0x06)
22#define REG_CRC_CNT CRA(0x7,0x2,0x0a)
23#define REG_CRC_CFG CRA(0x7,0x2,0x0b)
24#define REG_SI_TRANSFER_SEL CRA(0x7,0xf,0x18)
25#define REG_PLL_CLK_SPEED CRA(0x7,0xf,0x19)
26#define REG_SYS_CLK_SELECT CRA(0x7,0xf,0x1c)
27#define REG_GPIO_CTRL CRA(0x7,0xf,0x1d)
28#define REG_GPIO_OUT CRA(0x7,0xf,0x1e)
29#define REG_GPIO_IN CRA(0x7,0xf,0x1f)
30#define REG_CPU_TRANSFER_SEL CRA(0x7,0xf,0x20)
31#define REG_LOCAL_DATA CRA(0x7,0xf,0xfe)
32#define REG_LOCAL_STATUS CRA(0x7,0xf,0xff)
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34
35#define REG_AGGR_SETUP CRA(0x7,0x1,0x00)
36#define REG_PMAP_TABLE CRA(0x7,0x1,0x01)
37#define REG_MPLS_BIT0 CRA(0x7,0x1,0x08)
38#define REG_MPLS_BIT1 CRA(0x7,0x1,0x09)
39#define REG_MPLS_BIT2 CRA(0x7,0x1,0x0a)
40#define REG_MPLS_BIT3 CRA(0x7,0x1,0x0b)
41#define REG_MPLS_BITMASK CRA(0x7,0x1,0x0c)
42#define REG_PRE_BIT0POS CRA(0x7,0x1,0x10)
43#define REG_PRE_BIT1POS CRA(0x7,0x1,0x11)
44#define REG_PRE_BIT2POS CRA(0x7,0x1,0x12)
45#define REG_PRE_BIT3POS CRA(0x7,0x1,0x13)
46#define REG_PRE_ERR_CNT CRA(0x7,0x1,0x14)
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50
51#define REG_RAM_BIST_CMD CRA(0x7,0x1,0x00)
52#define REG_RAM_BIST_RESULT CRA(0x7,0x1,0x01)
53#define BIST_PORT_SELECT 0x00
54#define BIST_COMMAND 0x01
55#define BIST_STATUS 0x02
56#define BIST_ERR_CNT_LSB 0x03
57#define BIST_ERR_CNT_MSB 0x04
58#define BIST_ERR_SEL_LSB 0x05
59#define BIST_ERR_SEL_MSB 0x06
60#define BIST_ERROR_STATE 0x07
61#define BIST_ERR_ADR0 0x08
62#define BIST_ERR_ADR1 0x09
63#define BIST_ERR_ADR2 0x0a
64#define BIST_ERR_ADR3 0x0b
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69
70#define REG_TEST(ie,fn) CRA(0x2,ie&1,0x00+fn)
71#define REG_TOP_BOTTOM(ie,fn) CRA(0x2,ie&1,0x10+fn)
72#define REG_TAIL(ie,fn) CRA(0x2,ie&1,0x20+fn)
73#define REG_HEAD(ie,fn) CRA(0x2,ie&1,0x30+fn)
74#define REG_HIGH_LOW_WM(ie,fn) CRA(0x2,ie&1,0x40+fn)
75#define REG_CT_THRHLD(ie,fn) CRA(0x2,ie&1,0x50+fn)
76#define REG_FIFO_DROP_CNT(ie,fn) CRA(0x2,ie&1,0x60+fn)
77#define REG_DEBUG_BUF_CNT(ie,fn) CRA(0x2,ie&1,0x70+fn)
78#define REG_BUCKI(fn) CRA(0x2,2,0x20+fn)
79#define REG_BUCKE(fn) CRA(0x2,3,0x20+fn)
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85
86#define REG_TRAFFIC_SHAPER_BUCKET(ie,bn) CRA(0x2,ie&1,0x0a + (bn>7) | ((bn&7)<<4))
87#define REG_TRAFFIC_SHAPER_CONTROL(ie) CRA(0x2,ie&1,0x3b)
88
89#define REG_SRAM_ADR(ie) CRA(0x2,ie&1,0x0e)
90#define REG_SRAM_WR_STRB(ie) CRA(0x2,ie&1,0x1e)
91#define REG_SRAM_RD_STRB(ie) CRA(0x2,ie&1,0x2e)
92#define REG_SRAM_DATA_0(ie) CRA(0x2,ie&1,0x3e)
93#define REG_SRAM_DATA_1(ie) CRA(0x2,ie&1,0x4e)
94#define REG_SRAM_DATA_2(ie) CRA(0x2,ie&1,0x5e)
95#define REG_SRAM_DATA_3(ie) CRA(0x2,ie&1,0x6e)
96#define REG_SRAM_DATA_BLK_TYPE(ie) CRA(0x2,ie&1,0x7e)
97
98#define REG_CONTROL(ie) CRA(0x2,ie&1,0x0f)
99#define REG_ING_CONTROL CRA(0x2,0x0,0x0f)
100#define REG_EGR_CONTROL CRA(0x2,0x1,0x0f)
101#define REG_AGE_TIMER(ie) CRA(0x2,ie&1,0x1f)
102#define REG_AGE_INC(ie) CRA(0x2,ie&1,0x2f)
103#define DEBUG_OUT(ie) CRA(0x2,ie&1,0x3f)
104#define DEBUG_CNT(ie) CRA(0x2,ie&1,0x4f)
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106
107#define REG_SPI4_MISC CRA(0x5,0x0,0x00)
108#define REG_SPI4_STATUS CRA(0x5,0x0,0x01)
109#define REG_SPI4_ING_SETUP0 CRA(0x5,0x0,0x02)
110#define REG_SPI4_ING_SETUP1 CRA(0x5,0x0,0x03)
111#define REG_SPI4_ING_SETUP2 CRA(0x5,0x0,0x04)
112#define REG_SPI4_EGR_SETUP0 CRA(0x5,0x0,0x05)
113#define REG_SPI4_DBG_CNT(n) CRA(0x5,0x0,0x10+n)
114#define REG_SPI4_DBG_SETUP CRA(0x5,0x0,0x1A)
115#define REG_SPI4_TEST CRA(0x5,0x0,0x20)
116#define REG_TPGEN_UP0 CRA(0x5,0x0,0x21)
117#define REG_TPGEN_UP1 CRA(0x5,0x0,0x22)
118#define REG_TPCHK_UP0 CRA(0x5,0x0,0x23)
119#define REG_TPCHK_UP1 CRA(0x5,0x0,0x24)
120#define REG_TPSAM_P0 CRA(0x5,0x0,0x25)
121#define REG_TPSAM_P1 CRA(0x5,0x0,0x26)
122#define REG_TPERR_CNT CRA(0x5,0x0,0x27)
123#define REG_SPI4_STICKY CRA(0x5,0x0,0x30)
124#define REG_SPI4_DBG_INH CRA(0x5,0x0,0x31)
125#define REG_SPI4_DBG_STATUS CRA(0x5,0x0,0x32)
126#define REG_SPI4_DBG_GRANT CRA(0x5,0x0,0x33)
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128#define REG_SPI4_DESKEW CRA(0x5,0x0,0x43)
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140#define REG_MISC_10G CRA(0x1,0xa,0x00)
141#define REG_PAUSE_10G CRA(0x1,0xa,0x01)
142#define REG_NORMALIZER_10G CRA(0x1,0xa,0x05)
143#define REG_STICKY_RX CRA(0x1,0xa,0x06)
144#define REG_DENORM_10G CRA(0x1,0xa,0x07)
145#define REG_STICKY_TX CRA(0x1,0xa,0x08)
146#define REG_MAX_RXHIGH CRA(0x1,0xa,0x0a)
147#define REG_MAX_RXLOW CRA(0x1,0xa,0x0b)
148#define REG_MAC_TX_STICKY CRA(0x1,0xa,0x0c)
149#define REG_MAC_TX_RUNNING CRA(0x1,0xa,0x0d)
150#define REG_TX_ABORT_AGE CRA(0x1,0xa,0x14)
151#define REG_TX_ABORT_SHORT CRA(0x1,0xa,0x15)
152#define REG_TX_ABORT_TAXI CRA(0x1,0xa,0x16)
153#define REG_TX_ABORT_UNDERRUN CRA(0x1,0xa,0x17)
154#define REG_TX_DENORM_DISCARD CRA(0x1,0xa,0x18)
155#define REG_XAUI_STAT_A CRA(0x1,0xa,0x20)
156#define REG_XAUI_STAT_B CRA(0x1,0xa,0x21)
157#define REG_XAUI_STAT_C CRA(0x1,0xa,0x22)
158#define REG_XAUI_CONF_A CRA(0x1,0xa,0x23)
159#define REG_XAUI_CONF_B CRA(0x1,0xa,0x24)
160#define REG_XAUI_CODE_GRP_CNT CRA(0x1,0xa,0x25)
161#define REG_XAUI_CONF_TEST_A CRA(0x1,0xa,0x26)
162#define REG_PDERRCNT CRA(0x1,0xa,0x27)
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165
166#define REG_MAX_LEN(pn) CRA(0x1,pn,0x02)
167#define REG_MAC_HIGH_ADDR(pn) CRA(0x1,pn,0x03)
168#define REG_MAC_LOW_ADDR(pn) CRA(0x1,pn,0x04)
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173#define REG_MODE_CFG(pn) CRA(0x1,pn,0x00)
174#define REG_PAUSE_CFG(pn) CRA(0x1,pn,0x01)
175#define REG_NORMALIZER(pn) CRA(0x1,pn,0x05)
176#define REG_TBI_STATUS(pn) CRA(0x1,pn,0x06)
177#define REG_PCS_STATUS_DBG(pn) CRA(0x1,pn,0x07)
178#define REG_PCS_CTRL(pn) CRA(0x1,pn,0x08)
179#define REG_TBI_CONFIG(pn) CRA(0x1,pn,0x09)
180#define REG_STICK_BIT(pn) CRA(0x1,pn,0x0a)
181#define REG_DEV_SETUP(pn) CRA(0x1,pn,0x0b)
182#define REG_DROP_CNT(pn) CRA(0x1,pn,0x0c)
183#define REG_PORT_POS(pn) CRA(0x1,pn,0x0d)
184#define REG_PORT_FAIL(pn) CRA(0x1,pn,0x0e)
185#define REG_SERDES_CONF(pn) CRA(0x1,pn,0x0f)
186#define REG_SERDES_TEST(pn) CRA(0x1,pn,0x10)
187#define REG_SERDES_STAT(pn) CRA(0x1,pn,0x11)
188#define REG_SERDES_COM_CNT(pn) CRA(0x1,pn,0x12)
189#define REG_DENORM(pn) CRA(0x1,pn,0x15)
190#define REG_DBG(pn) CRA(0x1,pn,0x16)
191#define REG_TX_IFG(pn) CRA(0x1,pn,0x18)
192#define REG_HDX(pn) CRA(0x1,pn,0x19)
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199enum {
200 RxInBytes = 0x00,
201 RxSymbolCarrier = 0x01,
202 RxPause = 0x02,
203 RxUnsupOpcode = 0x03,
204 RxOkBytes = 0x04,
205 RxBadBytes = 0x05,
206 RxUnicast = 0x06,
207 RxMulticast = 0x07,
208 RxBroadcast = 0x08,
209 Crc = 0x09,
210 RxAlignment = 0x0a,
211 RxUndersize = 0x0b,
212 RxFragments = 0x0c,
213 RxInRangeLengthError = 0x0d,
214 RxOutOfRangeError = 0x0e,
215 RxOversize = 0x0f,
216 RxJabbers = 0x10,
217 RxSize64 = 0x11,
218 RxSize65To127 = 0x12,
219 RxSize128To255 = 0x13,
220 RxSize256To511 = 0x14,
221 RxSize512To1023 = 0x15,
222 RxSize1024To1518 = 0x16,
223 RxSize1519ToMax = 0x17,
224
225 TxOutBytes = 0x18,
226 TxPause = 0x19,
227 TxOkBytes = 0x1a,
228 TxUnicast = 0x1b,
229 TxMulticast = 0x1c,
230 TxBroadcast = 0x1d,
231 TxMultipleColl = 0x1e,
232 TxLateColl = 0x1f,
233 TxXcoll = 0x20,
234 TxDefer = 0x21,
235 TxXdefer = 0x22,
236 TxCsense = 0x23,
237 TxSize64 = 0x24,
238 TxSize65To127 = 0x25,
239 TxSize128To255 = 0x26,
240 TxSize256To511 = 0x27,
241 TxSize512To1023 = 0x28,
242 TxSize1024To1518 = 0x29,
243 TxSize1519ToMax = 0x2a,
244 TxSingleColl = 0x2b,
245 TxBackoff2 = 0x2c,
246 TxBackoff3 = 0x2d,
247 TxBackoff4 = 0x2e,
248 TxBackoff5 = 0x2f,
249 TxBackoff6 = 0x30,
250 TxBackoff7 = 0x31,
251 TxBackoff8 = 0x32,
252 TxBackoff9 = 0x33,
253 TxBackoff10 = 0x34,
254 TxBackoff11 = 0x35,
255 TxBackoff12 = 0x36,
256 TxBackoff13 = 0x37,
257 TxBackoff14 = 0x38,
258 TxBackoff15 = 0x39,
259 TxUnderrun = 0x3a,
260
261 RxIpgShrink = 0x3c,
262
263 StatSticky1G = 0x3e,
264 StatInit = 0x3f
265};
266
267#define REG_RX_XGMII_PROT_ERR CRA(0x4,0xa,0x3b)
268#define REG_STAT_STICKY10G CRA(0x4,0xa,StatSticky1G)
269
270#define REG_RX_OK_BYTES(pn) CRA(0x4,pn,RxOkBytes)
271#define REG_RX_BAD_BYTES(pn) CRA(0x4,pn,RxBadBytes)
272#define REG_TX_OK_BYTES(pn) CRA(0x4,pn,TxOkBytes)
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279
280#define REG_MIIM_STATUS CRA(0x3,0x0,0x00)
281#define REG_MIIM_CMD CRA(0x3,0x0,0x01)
282#define REG_MIIM_DATA CRA(0x3,0x0,0x02)
283#define REG_MIIM_PRESCALE CRA(0x3,0x0,0x03)
284
285#define REG_ING_FFILT_UM_EN CRA(0x2, 0, 0xd)
286#define REG_ING_FFILT_BE_EN CRA(0x2, 0, 0x1d)
287#define REG_ING_FFILT_VAL0 CRA(0x2, 0, 0x2d)
288#define REG_ING_FFILT_VAL1 CRA(0x2, 0, 0x3d)
289#define REG_ING_FFILT_MASK0 CRA(0x2, 0, 0x4d)
290#define REG_ING_FFILT_MASK1 CRA(0x2, 0, 0x5d)
291#define REG_ING_FFILT_MASK2 CRA(0x2, 0, 0x6d)
292#define REG_ING_FFILT_ETYPE CRA(0x2, 0, 0x7d)
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296
297#endif
298