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8#include "qlcnic.h"
9#include "qlcnic_hdr.h"
10
11#include <linux/slab.h>
12#include <net/ip.h>
13#include <linux/bitops.h>
14
15#define MASK(n) ((1ULL<<(n))-1)
16#define OCM_WIN_P3P(addr) (addr & 0xffc0000)
17
18#define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
19
20#define CRB_BLK(off) ((off >> 20) & 0x3f)
21#define CRB_SUBBLK(off) ((off >> 16) & 0xf)
22#define CRB_WINDOW_2M (0x130060)
23#define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
24#define CRB_INDIRECT_2M (0x1e0000UL)
25
26struct qlcnic_ms_reg_ctrl {
27 u32 ocm_window;
28 u32 control;
29 u32 hi;
30 u32 low;
31 u32 rd[4];
32 u32 wd[4];
33 u64 off;
34};
35
36#ifndef readq
37static inline u64 readq(void __iomem *addr)
38{
39 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
40}
41#endif
42
43#ifndef writeq
44static inline void writeq(u64 val, void __iomem *addr)
45{
46 writel(((u32) (val)), (addr));
47 writel(((u32) (val >> 32)), (addr + 4));
48}
49#endif
50
51static struct crb_128M_2M_block_map
52crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
53 {{{0, 0, 0, 0} } },
54 {{{1, 0x0100000, 0x0102000, 0x120000},
55 {1, 0x0110000, 0x0120000, 0x130000},
56 {1, 0x0120000, 0x0122000, 0x124000},
57 {1, 0x0130000, 0x0132000, 0x126000},
58 {1, 0x0140000, 0x0142000, 0x128000},
59 {1, 0x0150000, 0x0152000, 0x12a000},
60 {1, 0x0160000, 0x0170000, 0x110000},
61 {1, 0x0170000, 0x0172000, 0x12e000},
62 {0, 0x0000000, 0x0000000, 0x000000},
63 {0, 0x0000000, 0x0000000, 0x000000},
64 {0, 0x0000000, 0x0000000, 0x000000},
65 {0, 0x0000000, 0x0000000, 0x000000},
66 {0, 0x0000000, 0x0000000, 0x000000},
67 {0, 0x0000000, 0x0000000, 0x000000},
68 {1, 0x01e0000, 0x01e0800, 0x122000},
69 {0, 0x0000000, 0x0000000, 0x000000} } },
70 {{{1, 0x0200000, 0x0210000, 0x180000} } },
71 {{{0, 0, 0, 0} } },
72 {{{1, 0x0400000, 0x0401000, 0x169000} } },
73 {{{1, 0x0500000, 0x0510000, 0x140000} } },
74 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },
75 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },
76 {{{1, 0x0800000, 0x0802000, 0x170000},
77 {0, 0x0000000, 0x0000000, 0x000000},
78 {0, 0x0000000, 0x0000000, 0x000000},
79 {0, 0x0000000, 0x0000000, 0x000000},
80 {0, 0x0000000, 0x0000000, 0x000000},
81 {0, 0x0000000, 0x0000000, 0x000000},
82 {0, 0x0000000, 0x0000000, 0x000000},
83 {0, 0x0000000, 0x0000000, 0x000000},
84 {0, 0x0000000, 0x0000000, 0x000000},
85 {0, 0x0000000, 0x0000000, 0x000000},
86 {0, 0x0000000, 0x0000000, 0x000000},
87 {0, 0x0000000, 0x0000000, 0x000000},
88 {0, 0x0000000, 0x0000000, 0x000000},
89 {0, 0x0000000, 0x0000000, 0x000000},
90 {0, 0x0000000, 0x0000000, 0x000000},
91 {1, 0x08f0000, 0x08f2000, 0x172000} } },
92 {{{1, 0x0900000, 0x0902000, 0x174000},
93 {0, 0x0000000, 0x0000000, 0x000000},
94 {0, 0x0000000, 0x0000000, 0x000000},
95 {0, 0x0000000, 0x0000000, 0x000000},
96 {0, 0x0000000, 0x0000000, 0x000000},
97 {0, 0x0000000, 0x0000000, 0x000000},
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {1, 0x09f0000, 0x09f2000, 0x176000} } },
108 {{{0, 0x0a00000, 0x0a02000, 0x178000},
109 {0, 0x0000000, 0x0000000, 0x000000},
110 {0, 0x0000000, 0x0000000, 0x000000},
111 {0, 0x0000000, 0x0000000, 0x000000},
112 {0, 0x0000000, 0x0000000, 0x000000},
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
124 {{{0, 0x0b00000, 0x0b02000, 0x17c000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
140 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },
141 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },
142 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },
143 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },
144 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },
145 {{{1, 0x1100000, 0x1101000, 0x160000} } },
146 {{{1, 0x1200000, 0x1201000, 0x161000} } },
147 {{{1, 0x1300000, 0x1301000, 0x162000} } },
148 {{{1, 0x1400000, 0x1401000, 0x163000} } },
149 {{{1, 0x1500000, 0x1501000, 0x165000} } },
150 {{{1, 0x1600000, 0x1601000, 0x166000} } },
151 {{{0, 0, 0, 0} } },
152 {{{0, 0, 0, 0} } },
153 {{{0, 0, 0, 0} } },
154 {{{0, 0, 0, 0} } },
155 {{{0, 0, 0, 0} } },
156 {{{0, 0, 0, 0} } },
157 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },
158 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },
159 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },
160 {{{0} } },
161 {{{1, 0x2100000, 0x2102000, 0x120000},
162 {1, 0x2110000, 0x2120000, 0x130000},
163 {1, 0x2120000, 0x2122000, 0x124000},
164 {1, 0x2130000, 0x2132000, 0x126000},
165 {1, 0x2140000, 0x2142000, 0x128000},
166 {1, 0x2150000, 0x2152000, 0x12a000},
167 {1, 0x2160000, 0x2170000, 0x110000},
168 {1, 0x2170000, 0x2172000, 0x12e000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000} } },
177 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },
178 {{{0} } },
179 {{{0} } },
180 {{{0} } },
181 {{{0} } },
182 {{{0} } },
183 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },
184 {{{1, 0x2900000, 0x2901000, 0x16b000} } },
185 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },
186 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },
187 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },
188 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },
189 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },
190 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },
191 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },
192 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },
193 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },
194 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },
195 {{{0} } },
196 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },
197 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },
198 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },
199 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },
200 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },
201 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },
202 {{{0} } },
203 {{{0} } },
204 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },
205 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },
206 {{{1, 0x3f00000, 0x3f01000, 0x168000} } }
207};
208
209
210
211
212static const unsigned crb_hub_agt[64] = {
213 0,
214 QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
215 QLCNIC_HW_CRB_HUB_AGT_ADR_MN,
216 QLCNIC_HW_CRB_HUB_AGT_ADR_MS,
217 0,
218 QLCNIC_HW_CRB_HUB_AGT_ADR_SRE,
219 QLCNIC_HW_CRB_HUB_AGT_ADR_NIU,
220 QLCNIC_HW_CRB_HUB_AGT_ADR_QMN,
221 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0,
222 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1,
223 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2,
224 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3,
225 QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
226 QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
227 QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
228 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4,
229 QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
230 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0,
231 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1,
232 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2,
233 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3,
234 QLCNIC_HW_CRB_HUB_AGT_ADR_PGND,
235 QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI,
236 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0,
237 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1,
238 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2,
239 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3,
240 0,
241 QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI,
242 QLCNIC_HW_CRB_HUB_AGT_ADR_SN,
243 0,
244 QLCNIC_HW_CRB_HUB_AGT_ADR_EG,
245 0,
246 QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
247 QLCNIC_HW_CRB_HUB_AGT_ADR_CAM,
248 0,
249 0,
250 0,
251 0,
252 0,
253 QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
254 0,
255 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1,
256 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2,
257 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3,
258 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4,
259 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5,
260 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6,
261 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7,
262 QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
263 QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
264 QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
265 0,
266 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0,
267 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8,
268 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9,
269 QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0,
270 0,
271 QLCNIC_HW_CRB_HUB_AGT_ADR_SMB,
272 QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0,
273 QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1,
274 0,
275 QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC,
276 0,
277};
278
279static const u32 msi_tgt_status[8] = {
280 ISR_INT_TARGET_STATUS, ISR_INT_TARGET_STATUS_F1,
281 ISR_INT_TARGET_STATUS_F2, ISR_INT_TARGET_STATUS_F3,
282 ISR_INT_TARGET_STATUS_F4, ISR_INT_TARGET_STATUS_F5,
283 ISR_INT_TARGET_STATUS_F6, ISR_INT_TARGET_STATUS_F7
284};
285
286
287
288#define QLCNIC_PCIE_SEM_TIMEOUT 10000
289
290static void qlcnic_read_window_reg(u32 addr, void __iomem *bar0, u32 *data)
291{
292 u32 dest;
293 void __iomem *val;
294
295 dest = addr & 0xFFFF0000;
296 val = bar0 + QLCNIC_FW_DUMP_REG1;
297 writel(dest, val);
298 readl(val);
299 val = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr);
300 *data = readl(val);
301}
302
303static void qlcnic_write_window_reg(u32 addr, void __iomem *bar0, u32 data)
304{
305 u32 dest;
306 void __iomem *val;
307
308 dest = addr & 0xFFFF0000;
309 val = bar0 + QLCNIC_FW_DUMP_REG1;
310 writel(dest, val);
311 readl(val);
312 val = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr);
313 writel(data, val);
314 readl(val);
315}
316
317int
318qlcnic_pcie_sem_lock(struct qlcnic_adapter *adapter, int sem, u32 id_reg)
319{
320 int timeout = 0, err = 0, done = 0;
321
322 while (!done) {
323 done = QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem)),
324 &err);
325 if (done == 1)
326 break;
327 if (++timeout >= QLCNIC_PCIE_SEM_TIMEOUT) {
328 if (id_reg) {
329 done = QLCRD32(adapter, id_reg, &err);
330 if (done != -1)
331 dev_err(&adapter->pdev->dev,
332 "Failed to acquire sem=%d lock held by=%d\n",
333 sem, done);
334 else
335 dev_err(&adapter->pdev->dev,
336 "Failed to acquire sem=%d lock",
337 sem);
338 } else {
339 dev_err(&adapter->pdev->dev,
340 "Failed to acquire sem=%d lock", sem);
341 }
342 return -EIO;
343 }
344 msleep(1);
345 }
346
347 if (id_reg)
348 QLCWR32(adapter, id_reg, adapter->portnum);
349
350 return 0;
351}
352
353void
354qlcnic_pcie_sem_unlock(struct qlcnic_adapter *adapter, int sem)
355{
356 int err = 0;
357
358 QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem)), &err);
359}
360
361int qlcnic_ind_rd(struct qlcnic_adapter *adapter, u32 addr)
362{
363 int err = 0;
364 u32 data;
365
366 if (qlcnic_82xx_check(adapter))
367 qlcnic_read_window_reg(addr, adapter->ahw->pci_base0, &data);
368 else {
369 data = QLCRD32(adapter, addr, &err);
370 if (err == -EIO)
371 return err;
372 }
373 return data;
374}
375
376void qlcnic_ind_wr(struct qlcnic_adapter *adapter, u32 addr, u32 data)
377{
378 if (qlcnic_82xx_check(adapter))
379 qlcnic_write_window_reg(addr, adapter->ahw->pci_base0, data);
380 else
381 qlcnic_83xx_wrt_reg_indirect(adapter, addr, data);
382}
383
384static int
385qlcnic_send_cmd_descs(struct qlcnic_adapter *adapter,
386 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
387{
388 u32 i, producer;
389 struct qlcnic_cmd_buffer *pbuf;
390 struct cmd_desc_type0 *cmd_desc;
391 struct qlcnic_host_tx_ring *tx_ring;
392
393 i = 0;
394
395 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
396 return -EIO;
397
398 tx_ring = &adapter->tx_ring[0];
399 __netif_tx_lock_bh(tx_ring->txq);
400
401 producer = tx_ring->producer;
402
403 if (nr_desc >= qlcnic_tx_avail(tx_ring)) {
404 netif_tx_stop_queue(tx_ring->txq);
405 smp_mb();
406 if (qlcnic_tx_avail(tx_ring) > nr_desc) {
407 if (qlcnic_tx_avail(tx_ring) > TX_STOP_THRESH)
408 netif_tx_wake_queue(tx_ring->txq);
409 } else {
410 adapter->stats.xmit_off++;
411 __netif_tx_unlock_bh(tx_ring->txq);
412 return -EBUSY;
413 }
414 }
415
416 do {
417 cmd_desc = &cmd_desc_arr[i];
418
419 pbuf = &tx_ring->cmd_buf_arr[producer];
420 pbuf->skb = NULL;
421 pbuf->frag_count = 0;
422
423 memcpy(&tx_ring->desc_head[producer],
424 cmd_desc, sizeof(struct cmd_desc_type0));
425
426 producer = get_next_index(producer, tx_ring->num_desc);
427 i++;
428
429 } while (i != nr_desc);
430
431 tx_ring->producer = producer;
432
433 qlcnic_update_cmd_producer(tx_ring);
434
435 __netif_tx_unlock_bh(tx_ring->txq);
436
437 return 0;
438}
439
440int qlcnic_82xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
441 u16 vlan_id, u8 op)
442{
443 struct qlcnic_nic_req req;
444 struct qlcnic_mac_req *mac_req;
445 struct qlcnic_vlan_req *vlan_req;
446 u64 word;
447
448 memset(&req, 0, sizeof(struct qlcnic_nic_req));
449 req.qhdr = cpu_to_le64(QLCNIC_REQUEST << 23);
450
451 word = QLCNIC_MAC_EVENT | ((u64)adapter->portnum << 16);
452 req.req_hdr = cpu_to_le64(word);
453
454 mac_req = (struct qlcnic_mac_req *)&req.words[0];
455 mac_req->op = op;
456 memcpy(mac_req->mac_addr, addr, ETH_ALEN);
457
458 vlan_req = (struct qlcnic_vlan_req *)&req.words[1];
459 vlan_req->vlan_id = cpu_to_le16(vlan_id);
460
461 return qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
462}
463
464int qlcnic_nic_del_mac(struct qlcnic_adapter *adapter, const u8 *addr)
465{
466 struct qlcnic_mac_vlan_list *cur;
467 struct list_head *head;
468 int err = -EINVAL;
469
470
471 list_for_each(head, &adapter->mac_list) {
472 cur = list_entry(head, struct qlcnic_mac_vlan_list, list);
473 if (ether_addr_equal(addr, cur->mac_addr)) {
474 err = qlcnic_sre_macaddr_change(adapter, cur->mac_addr,
475 0, QLCNIC_MAC_DEL);
476 if (err)
477 return err;
478 list_del(&cur->list);
479 kfree(cur);
480 return err;
481 }
482 }
483 return err;
484}
485
486int qlcnic_nic_add_mac(struct qlcnic_adapter *adapter, const u8 *addr, u16 vlan)
487{
488 struct qlcnic_mac_vlan_list *cur;
489 struct list_head *head;
490
491
492 list_for_each(head, &adapter->mac_list) {
493 cur = list_entry(head, struct qlcnic_mac_vlan_list, list);
494 if (ether_addr_equal(addr, cur->mac_addr) &&
495 cur->vlan_id == vlan)
496 return 0;
497 }
498
499 cur = kzalloc(sizeof(*cur), GFP_ATOMIC);
500 if (cur == NULL)
501 return -ENOMEM;
502
503 memcpy(cur->mac_addr, addr, ETH_ALEN);
504
505 if (qlcnic_sre_macaddr_change(adapter,
506 cur->mac_addr, vlan, QLCNIC_MAC_ADD)) {
507 kfree(cur);
508 return -EIO;
509 }
510
511 cur->vlan_id = vlan;
512 list_add_tail(&cur->list, &adapter->mac_list);
513 return 0;
514}
515
516static void __qlcnic_set_multi(struct net_device *netdev, u16 vlan)
517{
518 struct qlcnic_adapter *adapter = netdev_priv(netdev);
519 struct qlcnic_hardware_context *ahw = adapter->ahw;
520 struct netdev_hw_addr *ha;
521 static const u8 bcast_addr[ETH_ALEN] = {
522 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
523 };
524 u32 mode = VPORT_MISS_MODE_DROP;
525
526 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
527 return;
528
529 qlcnic_nic_add_mac(adapter, adapter->mac_addr, vlan);
530 qlcnic_nic_add_mac(adapter, bcast_addr, vlan);
531
532 if (netdev->flags & IFF_PROMISC) {
533 if (!(adapter->flags & QLCNIC_PROMISC_DISABLED))
534 mode = VPORT_MISS_MODE_ACCEPT_ALL;
535 } else if ((netdev->flags & IFF_ALLMULTI) ||
536 (netdev_mc_count(netdev) > ahw->max_mc_count)) {
537 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
538 } else if (!netdev_mc_empty(netdev)) {
539 netdev_for_each_mc_addr(ha, netdev)
540 qlcnic_nic_add_mac(adapter, ha->addr, vlan);
541 }
542
543
544
545
546 if (netdev_uc_count(netdev) > ahw->max_uc_count) {
547 mode = VPORT_MISS_MODE_ACCEPT_ALL;
548 } else if (!netdev_uc_empty(netdev)) {
549 netdev_for_each_uc_addr(ha, netdev)
550 qlcnic_nic_add_mac(adapter, ha->addr, vlan);
551 }
552
553 if (mode == VPORT_MISS_MODE_ACCEPT_ALL &&
554 !adapter->fdb_mac_learn) {
555 qlcnic_alloc_lb_filters_mem(adapter);
556 adapter->drv_mac_learn = 1;
557 if (adapter->flags & QLCNIC_ESWITCH_ENABLED)
558 adapter->rx_mac_learn = true;
559 } else {
560 adapter->drv_mac_learn = 0;
561 adapter->rx_mac_learn = false;
562 }
563
564 qlcnic_nic_set_promisc(adapter, mode);
565}
566
567void qlcnic_set_multi(struct net_device *netdev)
568{
569 struct qlcnic_adapter *adapter = netdev_priv(netdev);
570 struct qlcnic_mac_vlan_list *cur;
571 struct netdev_hw_addr *ha;
572 size_t temp;
573
574 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
575 return;
576 if (qlcnic_sriov_vf_check(adapter)) {
577 if (!netdev_mc_empty(netdev)) {
578 netdev_for_each_mc_addr(ha, netdev) {
579 temp = sizeof(struct qlcnic_mac_vlan_list);
580 cur = kzalloc(temp, GFP_ATOMIC);
581 if (cur == NULL)
582 break;
583 memcpy(cur->mac_addr,
584 ha->addr, ETH_ALEN);
585 list_add_tail(&cur->list, &adapter->vf_mc_list);
586 }
587 }
588 qlcnic_sriov_vf_schedule_multi(adapter->netdev);
589 return;
590 }
591 __qlcnic_set_multi(netdev, 0);
592}
593
594int qlcnic_82xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
595{
596 struct qlcnic_nic_req req;
597 u64 word;
598
599 memset(&req, 0, sizeof(struct qlcnic_nic_req));
600
601 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
602
603 word = QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE |
604 ((u64)adapter->portnum << 16);
605 req.req_hdr = cpu_to_le64(word);
606
607 req.words[0] = cpu_to_le64(mode);
608
609 return qlcnic_send_cmd_descs(adapter,
610 (struct cmd_desc_type0 *)&req, 1);
611}
612
613void qlcnic_82xx_free_mac_list(struct qlcnic_adapter *adapter)
614{
615 struct list_head *head = &adapter->mac_list;
616 struct qlcnic_mac_vlan_list *cur;
617
618 while (!list_empty(head)) {
619 cur = list_entry(head->next, struct qlcnic_mac_vlan_list, list);
620 qlcnic_sre_macaddr_change(adapter,
621 cur->mac_addr, 0, QLCNIC_MAC_DEL);
622 list_del(&cur->list);
623 kfree(cur);
624 }
625}
626
627void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter)
628{
629 struct qlcnic_filter *tmp_fil;
630 struct hlist_node *n;
631 struct hlist_head *head;
632 int i;
633 unsigned long time;
634 u8 cmd;
635
636 for (i = 0; i < adapter->fhash.fbucket_size; i++) {
637 head = &(adapter->fhash.fhead[i]);
638 hlist_for_each_entry_safe(tmp_fil, n, head, fnode) {
639 cmd = tmp_fil->vlan_id ? QLCNIC_MAC_VLAN_DEL :
640 QLCNIC_MAC_DEL;
641 time = tmp_fil->ftime;
642 if (jiffies > (QLCNIC_FILTER_AGE * HZ + time)) {
643 qlcnic_sre_macaddr_change(adapter,
644 tmp_fil->faddr,
645 tmp_fil->vlan_id,
646 cmd);
647 spin_lock_bh(&adapter->mac_learn_lock);
648 adapter->fhash.fnum--;
649 hlist_del(&tmp_fil->fnode);
650 spin_unlock_bh(&adapter->mac_learn_lock);
651 kfree(tmp_fil);
652 }
653 }
654 }
655 for (i = 0; i < adapter->rx_fhash.fbucket_size; i++) {
656 head = &(adapter->rx_fhash.fhead[i]);
657
658 hlist_for_each_entry_safe(tmp_fil, n, head, fnode)
659 {
660 time = tmp_fil->ftime;
661 if (jiffies > (QLCNIC_FILTER_AGE * HZ + time)) {
662 spin_lock_bh(&adapter->rx_mac_learn_lock);
663 adapter->rx_fhash.fnum--;
664 hlist_del(&tmp_fil->fnode);
665 spin_unlock_bh(&adapter->rx_mac_learn_lock);
666 kfree(tmp_fil);
667 }
668 }
669 }
670}
671
672void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter)
673{
674 struct qlcnic_filter *tmp_fil;
675 struct hlist_node *n;
676 struct hlist_head *head;
677 int i;
678 u8 cmd;
679
680 for (i = 0; i < adapter->fhash.fbucket_size; i++) {
681 head = &(adapter->fhash.fhead[i]);
682 hlist_for_each_entry_safe(tmp_fil, n, head, fnode) {
683 cmd = tmp_fil->vlan_id ? QLCNIC_MAC_VLAN_DEL :
684 QLCNIC_MAC_DEL;
685 qlcnic_sre_macaddr_change(adapter,
686 tmp_fil->faddr,
687 tmp_fil->vlan_id,
688 cmd);
689 spin_lock_bh(&adapter->mac_learn_lock);
690 adapter->fhash.fnum--;
691 hlist_del(&tmp_fil->fnode);
692 spin_unlock_bh(&adapter->mac_learn_lock);
693 kfree(tmp_fil);
694 }
695 }
696}
697
698static int qlcnic_set_fw_loopback(struct qlcnic_adapter *adapter, u8 flag)
699{
700 struct qlcnic_nic_req req;
701 int rv;
702
703 memset(&req, 0, sizeof(struct qlcnic_nic_req));
704
705 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
706 req.req_hdr = cpu_to_le64(QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK |
707 ((u64) adapter->portnum << 16) | ((u64) 0x1 << 32));
708
709 req.words[0] = cpu_to_le64(flag);
710
711 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
712 if (rv != 0)
713 dev_err(&adapter->pdev->dev, "%sting loopback mode failed\n",
714 flag ? "Set" : "Reset");
715 return rv;
716}
717
718int qlcnic_82xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
719{
720 if (qlcnic_set_fw_loopback(adapter, mode))
721 return -EIO;
722
723 if (qlcnic_nic_set_promisc(adapter,
724 VPORT_MISS_MODE_ACCEPT_ALL)) {
725 qlcnic_set_fw_loopback(adapter, 0);
726 return -EIO;
727 }
728
729 msleep(1000);
730 return 0;
731}
732
733int qlcnic_82xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
734{
735 struct net_device *netdev = adapter->netdev;
736
737 mode = VPORT_MISS_MODE_DROP;
738 qlcnic_set_fw_loopback(adapter, 0);
739
740 if (netdev->flags & IFF_PROMISC)
741 mode = VPORT_MISS_MODE_ACCEPT_ALL;
742 else if (netdev->flags & IFF_ALLMULTI)
743 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
744
745 qlcnic_nic_set_promisc(adapter, mode);
746 msleep(1000);
747 return 0;
748}
749
750int qlcnic_82xx_read_phys_port_id(struct qlcnic_adapter *adapter)
751{
752 u8 mac[ETH_ALEN];
753 int ret;
754
755 ret = qlcnic_get_mac_address(adapter, mac,
756 adapter->ahw->physical_port);
757 if (ret)
758 return ret;
759
760 memcpy(adapter->ahw->phys_port_id, mac, ETH_ALEN);
761 adapter->flags |= QLCNIC_HAS_PHYS_PORT_ID;
762
763 return 0;
764}
765
766int qlcnic_82xx_set_rx_coalesce(struct qlcnic_adapter *adapter)
767{
768 struct qlcnic_nic_req req;
769 int rv;
770
771 memset(&req, 0, sizeof(struct qlcnic_nic_req));
772
773 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
774
775 req.req_hdr = cpu_to_le64(QLCNIC_CONFIG_INTR_COALESCE |
776 ((u64) adapter->portnum << 16));
777
778 req.words[0] = cpu_to_le64(((u64) adapter->ahw->coal.flag) << 32);
779 req.words[2] = cpu_to_le64(adapter->ahw->coal.rx_packets |
780 ((u64) adapter->ahw->coal.rx_time_us) << 16);
781 req.words[5] = cpu_to_le64(adapter->ahw->coal.timer_out |
782 ((u64) adapter->ahw->coal.type) << 32 |
783 ((u64) adapter->ahw->coal.sts_ring_mask) << 40);
784 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
785 if (rv != 0)
786 dev_err(&adapter->netdev->dev,
787 "Could not send interrupt coalescing parameters\n");
788
789 return rv;
790}
791
792
793int qlcnic_82xx_config_intr_coalesce(struct qlcnic_adapter *adapter,
794 struct ethtool_coalesce *ethcoal)
795{
796 struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
797 int rv;
798
799 coal->flag = QLCNIC_INTR_DEFAULT;
800 coal->rx_time_us = ethcoal->rx_coalesce_usecs;
801 coal->rx_packets = ethcoal->rx_max_coalesced_frames;
802
803 rv = qlcnic_82xx_set_rx_coalesce(adapter);
804
805 if (rv)
806 netdev_err(adapter->netdev,
807 "Failed to set Rx coalescing parametrs\n");
808
809 return rv;
810}
811
812#define QLCNIC_ENABLE_IPV4_LRO BIT_0
813#define QLCNIC_ENABLE_IPV6_LRO (BIT_1 | BIT_9)
814
815int qlcnic_82xx_config_hw_lro(struct qlcnic_adapter *adapter, int enable)
816{
817 struct qlcnic_nic_req req;
818 u64 word;
819 int rv;
820
821 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
822 return 0;
823
824 memset(&req, 0, sizeof(struct qlcnic_nic_req));
825
826 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
827
828 word = QLCNIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
829 req.req_hdr = cpu_to_le64(word);
830
831 word = 0;
832 if (enable) {
833 word = QLCNIC_ENABLE_IPV4_LRO;
834 if (adapter->ahw->extra_capability[0] &
835 QLCNIC_FW_CAP2_HW_LRO_IPV6)
836 word |= QLCNIC_ENABLE_IPV6_LRO;
837 }
838
839 req.words[0] = cpu_to_le64(word);
840
841 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
842 if (rv != 0)
843 dev_err(&adapter->netdev->dev,
844 "Could not send configure hw lro request\n");
845
846 return rv;
847}
848
849int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable)
850{
851 struct qlcnic_nic_req req;
852 u64 word;
853 int rv;
854
855 if (!!(adapter->flags & QLCNIC_BRIDGE_ENABLED) == enable)
856 return 0;
857
858 memset(&req, 0, sizeof(struct qlcnic_nic_req));
859
860 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
861
862 word = QLCNIC_H2C_OPCODE_CONFIG_BRIDGING |
863 ((u64)adapter->portnum << 16);
864 req.req_hdr = cpu_to_le64(word);
865
866 req.words[0] = cpu_to_le64(enable);
867
868 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
869 if (rv != 0)
870 dev_err(&adapter->netdev->dev,
871 "Could not send configure bridge mode request\n");
872
873 adapter->flags ^= QLCNIC_BRIDGE_ENABLED;
874
875 return rv;
876}
877
878
879#define QLCNIC_RSS_HASHTYPE_IP_TCP 0x3
880#define QLCNIC_ENABLE_TYPE_C_RSS BIT_10
881#define QLCNIC_RSS_FEATURE_FLAG (1ULL << 63)
882#define QLCNIC_RSS_IND_TABLE_MASK 0x7ULL
883
884int qlcnic_82xx_config_rss(struct qlcnic_adapter *adapter, int enable)
885{
886 struct qlcnic_nic_req req;
887 u64 word;
888 int i, rv;
889
890 static const u64 key[] = {
891 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
892 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
893 0x255b0ec26d5a56daULL
894 };
895
896 memset(&req, 0, sizeof(struct qlcnic_nic_req));
897 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
898
899 word = QLCNIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
900 req.req_hdr = cpu_to_le64(word);
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915 word = ((u64)(QLCNIC_RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
916 ((u64)(QLCNIC_RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
917 ((u64)(enable & 0x1) << 8) |
918 ((u64)QLCNIC_RSS_IND_TABLE_MASK << 48) |
919 (u64)QLCNIC_ENABLE_TYPE_C_RSS |
920 (u64)QLCNIC_RSS_FEATURE_FLAG;
921
922 req.words[0] = cpu_to_le64(word);
923 for (i = 0; i < 5; i++)
924 req.words[i+1] = cpu_to_le64(key[i]);
925
926 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
927 if (rv != 0)
928 dev_err(&adapter->netdev->dev, "could not configure RSS\n");
929
930 return rv;
931}
932
933void qlcnic_82xx_config_ipaddr(struct qlcnic_adapter *adapter,
934 __be32 ip, int cmd)
935{
936 struct qlcnic_nic_req req;
937 struct qlcnic_ipaddr *ipa;
938 u64 word;
939 int rv;
940
941 memset(&req, 0, sizeof(struct qlcnic_nic_req));
942 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
943
944 word = QLCNIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
945 req.req_hdr = cpu_to_le64(word);
946
947 req.words[0] = cpu_to_le64(cmd);
948 ipa = (struct qlcnic_ipaddr *)&req.words[1];
949 ipa->ipv4 = ip;
950
951 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
952 if (rv != 0)
953 dev_err(&adapter->netdev->dev,
954 "could not notify %s IP 0x%x reuqest\n",
955 (cmd == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
956}
957
958int qlcnic_82xx_linkevent_request(struct qlcnic_adapter *adapter, int enable)
959{
960 struct qlcnic_nic_req req;
961 u64 word;
962 int rv;
963 memset(&req, 0, sizeof(struct qlcnic_nic_req));
964 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
965
966 word = QLCNIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
967 req.req_hdr = cpu_to_le64(word);
968 req.words[0] = cpu_to_le64(enable | (enable << 8));
969 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
970 if (rv != 0)
971 dev_err(&adapter->netdev->dev,
972 "could not configure link notification\n");
973
974 return rv;
975}
976
977static int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter)
978{
979 struct qlcnic_nic_req req;
980 u64 word;
981 int rv;
982
983 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
984 return 0;
985
986 memset(&req, 0, sizeof(struct qlcnic_nic_req));
987 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
988
989 word = QLCNIC_H2C_OPCODE_LRO_REQUEST |
990 ((u64)adapter->portnum << 16) |
991 ((u64)QLCNIC_LRO_REQUEST_CLEANUP << 56) ;
992
993 req.req_hdr = cpu_to_le64(word);
994
995 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
996 if (rv != 0)
997 dev_err(&adapter->netdev->dev,
998 "could not cleanup lro flows\n");
999
1000 return rv;
1001}
1002
1003
1004
1005
1006
1007
1008int qlcnic_change_mtu(struct net_device *netdev, int mtu)
1009{
1010 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1011 int rc = 0;
1012
1013 if (mtu < P3P_MIN_MTU || mtu > P3P_MAX_MTU) {
1014 dev_err(&adapter->netdev->dev, "%d bytes < mtu < %d bytes"
1015 " not supported\n", P3P_MAX_MTU, P3P_MIN_MTU);
1016 return -EINVAL;
1017 }
1018
1019 rc = qlcnic_fw_cmd_set_mtu(adapter, mtu);
1020
1021 if (!rc)
1022 netdev->mtu = mtu;
1023
1024 return rc;
1025}
1026
1027static netdev_features_t qlcnic_process_flags(struct qlcnic_adapter *adapter,
1028 netdev_features_t features)
1029{
1030 u32 offload_flags = adapter->offload_flags;
1031
1032 if (offload_flags & BIT_0) {
1033 features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM |
1034 NETIF_F_IPV6_CSUM;
1035 adapter->rx_csum = 1;
1036 if (QLCNIC_IS_TSO_CAPABLE(adapter)) {
1037 if (!(offload_flags & BIT_1))
1038 features &= ~NETIF_F_TSO;
1039 else
1040 features |= NETIF_F_TSO;
1041
1042 if (!(offload_flags & BIT_2))
1043 features &= ~NETIF_F_TSO6;
1044 else
1045 features |= NETIF_F_TSO6;
1046 }
1047 } else {
1048 features &= ~(NETIF_F_RXCSUM |
1049 NETIF_F_IP_CSUM |
1050 NETIF_F_IPV6_CSUM);
1051
1052 if (QLCNIC_IS_TSO_CAPABLE(adapter))
1053 features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
1054 adapter->rx_csum = 0;
1055 }
1056
1057 return features;
1058}
1059
1060netdev_features_t qlcnic_fix_features(struct net_device *netdev,
1061 netdev_features_t features)
1062{
1063 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1064 netdev_features_t changed;
1065
1066 if (qlcnic_82xx_check(adapter) &&
1067 (adapter->flags & QLCNIC_ESWITCH_ENABLED)) {
1068 if (adapter->flags & QLCNIC_APP_CHANGED_FLAGS) {
1069 features = qlcnic_process_flags(adapter, features);
1070 } else {
1071 changed = features ^ netdev->features;
1072 features ^= changed & (NETIF_F_RXCSUM |
1073 NETIF_F_IP_CSUM |
1074 NETIF_F_IPV6_CSUM |
1075 NETIF_F_TSO |
1076 NETIF_F_TSO6);
1077 }
1078 }
1079
1080 if (!(features & NETIF_F_RXCSUM))
1081 features &= ~NETIF_F_LRO;
1082
1083 return features;
1084}
1085
1086
1087int qlcnic_set_features(struct net_device *netdev, netdev_features_t features)
1088{
1089 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1090 netdev_features_t changed = netdev->features ^ features;
1091 int hw_lro = (features & NETIF_F_LRO) ? QLCNIC_LRO_ENABLED : 0;
1092
1093 if (!(changed & NETIF_F_LRO))
1094 return 0;
1095
1096 netdev->features ^= NETIF_F_LRO;
1097
1098 if (qlcnic_config_hw_lro(adapter, hw_lro))
1099 return -EIO;
1100
1101 if (!hw_lro && qlcnic_82xx_check(adapter)) {
1102 if (qlcnic_send_lro_cleanup(adapter))
1103 return -EIO;
1104 }
1105
1106 return 0;
1107}
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118static int qlcnic_pci_get_crb_addr_2M(struct qlcnic_hardware_context *ahw,
1119 ulong off, void __iomem **addr)
1120{
1121 const struct crb_128M_2M_sub_block_map *m;
1122
1123 if ((off >= QLCNIC_CRB_MAX) || (off < QLCNIC_PCI_CRBSPACE))
1124 return -EINVAL;
1125
1126 off -= QLCNIC_PCI_CRBSPACE;
1127
1128
1129
1130
1131 m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
1132
1133 if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
1134 *addr = ahw->pci_base0 + m->start_2M +
1135 (off - m->start_128M);
1136 return 0;
1137 }
1138
1139
1140
1141
1142 *addr = ahw->pci_base0 + CRB_INDIRECT_2M + (off & MASK(16));
1143 return 1;
1144}
1145
1146
1147
1148
1149
1150
1151static int
1152qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter *adapter, ulong off)
1153{
1154 u32 window;
1155 void __iomem *addr = adapter->ahw->pci_base0 + CRB_WINDOW_2M;
1156
1157 off -= QLCNIC_PCI_CRBSPACE;
1158
1159 window = CRB_HI(off);
1160 if (window == 0) {
1161 dev_err(&adapter->pdev->dev, "Invalid offset 0x%lx\n", off);
1162 return -EIO;
1163 }
1164
1165 writel(window, addr);
1166 if (readl(addr) != window) {
1167 if (printk_ratelimit())
1168 dev_warn(&adapter->pdev->dev,
1169 "failed to set CRB window to %d off 0x%lx\n",
1170 window, off);
1171 return -EIO;
1172 }
1173 return 0;
1174}
1175
1176int qlcnic_82xx_hw_write_wx_2M(struct qlcnic_adapter *adapter, ulong off,
1177 u32 data)
1178{
1179 unsigned long flags;
1180 int rv;
1181 void __iomem *addr = NULL;
1182
1183 rv = qlcnic_pci_get_crb_addr_2M(adapter->ahw, off, &addr);
1184
1185 if (rv == 0) {
1186 writel(data, addr);
1187 return 0;
1188 }
1189
1190 if (rv > 0) {
1191
1192 write_lock_irqsave(&adapter->ahw->crb_lock, flags);
1193 crb_win_lock(adapter);
1194 rv = qlcnic_pci_set_crbwindow_2M(adapter, off);
1195 if (!rv)
1196 writel(data, addr);
1197 crb_win_unlock(adapter);
1198 write_unlock_irqrestore(&adapter->ahw->crb_lock, flags);
1199 return rv;
1200 }
1201
1202 dev_err(&adapter->pdev->dev,
1203 "%s: invalid offset: 0x%016lx\n", __func__, off);
1204 dump_stack();
1205 return -EIO;
1206}
1207
1208int qlcnic_82xx_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off,
1209 int *err)
1210{
1211 unsigned long flags;
1212 int rv;
1213 u32 data = -1;
1214 void __iomem *addr = NULL;
1215
1216 rv = qlcnic_pci_get_crb_addr_2M(adapter->ahw, off, &addr);
1217
1218 if (rv == 0)
1219 return readl(addr);
1220
1221 if (rv > 0) {
1222
1223 write_lock_irqsave(&adapter->ahw->crb_lock, flags);
1224 crb_win_lock(adapter);
1225 if (!qlcnic_pci_set_crbwindow_2M(adapter, off))
1226 data = readl(addr);
1227 crb_win_unlock(adapter);
1228 write_unlock_irqrestore(&adapter->ahw->crb_lock, flags);
1229 return data;
1230 }
1231
1232 dev_err(&adapter->pdev->dev,
1233 "%s: invalid offset: 0x%016lx\n", __func__, off);
1234 dump_stack();
1235 return -1;
1236}
1237
1238void __iomem *qlcnic_get_ioaddr(struct qlcnic_hardware_context *ahw,
1239 u32 offset)
1240{
1241 void __iomem *addr = NULL;
1242
1243 WARN_ON(qlcnic_pci_get_crb_addr_2M(ahw, offset, &addr));
1244
1245 return addr;
1246}
1247
1248static int qlcnic_pci_mem_access_direct(struct qlcnic_adapter *adapter,
1249 u32 window, u64 off, u64 *data, int op)
1250{
1251 void __iomem *addr;
1252 u32 start;
1253
1254 mutex_lock(&adapter->ahw->mem_lock);
1255
1256 writel(window, adapter->ahw->ocm_win_crb);
1257
1258 readl(adapter->ahw->ocm_win_crb);
1259 start = QLCNIC_PCI_OCM0_2M + off;
1260
1261 addr = adapter->ahw->pci_base0 + start;
1262
1263 if (op == 0)
1264 *data = readq(addr);
1265 else
1266 writeq(*data, addr);
1267
1268
1269 writel(0, adapter->ahw->ocm_win_crb);
1270 readl(adapter->ahw->ocm_win_crb);
1271
1272 mutex_unlock(&adapter->ahw->mem_lock);
1273 return 0;
1274}
1275
1276static void
1277qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
1278{
1279 void __iomem *addr = adapter->ahw->pci_base0 +
1280 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
1281
1282 mutex_lock(&adapter->ahw->mem_lock);
1283 *data = readq(addr);
1284 mutex_unlock(&adapter->ahw->mem_lock);
1285}
1286
1287static void
1288qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
1289{
1290 void __iomem *addr = adapter->ahw->pci_base0 +
1291 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
1292
1293 mutex_lock(&adapter->ahw->mem_lock);
1294 writeq(data, addr);
1295 mutex_unlock(&adapter->ahw->mem_lock);
1296}
1297
1298
1299
1300
1301static void qlcnic_set_ms_controls(struct qlcnic_adapter *adapter, u64 off,
1302 struct qlcnic_ms_reg_ctrl *ms)
1303{
1304 ms->control = QLCNIC_MS_CTRL;
1305 ms->low = QLCNIC_MS_ADDR_LO;
1306 ms->hi = QLCNIC_MS_ADDR_HI;
1307 if (off & 0xf) {
1308 ms->wd[0] = QLCNIC_MS_WRTDATA_LO;
1309 ms->rd[0] = QLCNIC_MS_RDDATA_LO;
1310 ms->wd[1] = QLCNIC_MS_WRTDATA_HI;
1311 ms->rd[1] = QLCNIC_MS_RDDATA_HI;
1312 ms->wd[2] = QLCNIC_MS_WRTDATA_ULO;
1313 ms->wd[3] = QLCNIC_MS_WRTDATA_UHI;
1314 ms->rd[2] = QLCNIC_MS_RDDATA_ULO;
1315 ms->rd[3] = QLCNIC_MS_RDDATA_UHI;
1316 } else {
1317 ms->wd[0] = QLCNIC_MS_WRTDATA_ULO;
1318 ms->rd[0] = QLCNIC_MS_RDDATA_ULO;
1319 ms->wd[1] = QLCNIC_MS_WRTDATA_UHI;
1320 ms->rd[1] = QLCNIC_MS_RDDATA_UHI;
1321 ms->wd[2] = QLCNIC_MS_WRTDATA_LO;
1322 ms->wd[3] = QLCNIC_MS_WRTDATA_HI;
1323 ms->rd[2] = QLCNIC_MS_RDDATA_LO;
1324 ms->rd[3] = QLCNIC_MS_RDDATA_HI;
1325 }
1326
1327 ms->ocm_window = OCM_WIN_P3P(off);
1328 ms->off = GET_MEM_OFFS_2M(off);
1329}
1330
1331int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
1332{
1333 int j, ret = 0;
1334 u32 temp, off8;
1335 struct qlcnic_ms_reg_ctrl ms;
1336
1337
1338 if (off & 7)
1339 return -EIO;
1340
1341 memset(&ms, 0, sizeof(struct qlcnic_ms_reg_ctrl));
1342 if (!(ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1343 QLCNIC_ADDR_QDR_NET_MAX) ||
1344 ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET,
1345 QLCNIC_ADDR_DDR_NET_MAX)))
1346 return -EIO;
1347
1348 qlcnic_set_ms_controls(adapter, off, &ms);
1349
1350 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
1351 return qlcnic_pci_mem_access_direct(adapter, ms.ocm_window,
1352 ms.off, &data, 1);
1353
1354 off8 = off & ~0xf;
1355
1356 mutex_lock(&adapter->ahw->mem_lock);
1357
1358 qlcnic_ind_wr(adapter, ms.low, off8);
1359 qlcnic_ind_wr(adapter, ms.hi, 0);
1360
1361 qlcnic_ind_wr(adapter, ms.control, TA_CTL_ENABLE);
1362 qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_START_ENABLE);
1363
1364 for (j = 0; j < MAX_CTL_CHECK; j++) {
1365 temp = qlcnic_ind_rd(adapter, ms.control);
1366 if ((temp & TA_CTL_BUSY) == 0)
1367 break;
1368 }
1369
1370 if (j >= MAX_CTL_CHECK) {
1371 ret = -EIO;
1372 goto done;
1373 }
1374
1375
1376 qlcnic_ind_wr(adapter, ms.wd[0], qlcnic_ind_rd(adapter, ms.rd[0]));
1377 qlcnic_ind_wr(adapter, ms.wd[1], qlcnic_ind_rd(adapter, ms.rd[1]));
1378
1379 qlcnic_ind_wr(adapter, ms.wd[2], data & 0xffffffff);
1380 qlcnic_ind_wr(adapter, ms.wd[3], (data >> 32) & 0xffffffff);
1381
1382 qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_WRITE_ENABLE);
1383 qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_WRITE_START);
1384
1385 for (j = 0; j < MAX_CTL_CHECK; j++) {
1386 temp = qlcnic_ind_rd(adapter, ms.control);
1387 if ((temp & TA_CTL_BUSY) == 0)
1388 break;
1389 }
1390
1391 if (j >= MAX_CTL_CHECK) {
1392 if (printk_ratelimit())
1393 dev_err(&adapter->pdev->dev,
1394 "failed to write through agent\n");
1395 ret = -EIO;
1396 } else
1397 ret = 0;
1398
1399done:
1400 mutex_unlock(&adapter->ahw->mem_lock);
1401
1402 return ret;
1403}
1404
1405int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
1406{
1407 int j, ret;
1408 u32 temp, off8;
1409 u64 val;
1410 struct qlcnic_ms_reg_ctrl ms;
1411
1412
1413 if (off & 7)
1414 return -EIO;
1415 if (!(ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1416 QLCNIC_ADDR_QDR_NET_MAX) ||
1417 ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET,
1418 QLCNIC_ADDR_DDR_NET_MAX)))
1419 return -EIO;
1420
1421 memset(&ms, 0, sizeof(struct qlcnic_ms_reg_ctrl));
1422 qlcnic_set_ms_controls(adapter, off, &ms);
1423
1424 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
1425 return qlcnic_pci_mem_access_direct(adapter, ms.ocm_window,
1426 ms.off, data, 0);
1427
1428 mutex_lock(&adapter->ahw->mem_lock);
1429
1430 off8 = off & ~0xf;
1431
1432 qlcnic_ind_wr(adapter, ms.low, off8);
1433 qlcnic_ind_wr(adapter, ms.hi, 0);
1434
1435 qlcnic_ind_wr(adapter, ms.control, TA_CTL_ENABLE);
1436 qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_START_ENABLE);
1437
1438 for (j = 0; j < MAX_CTL_CHECK; j++) {
1439 temp = qlcnic_ind_rd(adapter, ms.control);
1440 if ((temp & TA_CTL_BUSY) == 0)
1441 break;
1442 }
1443
1444 if (j >= MAX_CTL_CHECK) {
1445 if (printk_ratelimit())
1446 dev_err(&adapter->pdev->dev,
1447 "failed to read through agent\n");
1448 ret = -EIO;
1449 } else {
1450
1451 temp = qlcnic_ind_rd(adapter, ms.rd[3]);
1452 val = (u64)temp << 32;
1453 val |= qlcnic_ind_rd(adapter, ms.rd[2]);
1454 *data = val;
1455 ret = 0;
1456 }
1457
1458 mutex_unlock(&adapter->ahw->mem_lock);
1459
1460 return ret;
1461}
1462
1463int qlcnic_82xx_get_board_info(struct qlcnic_adapter *adapter)
1464{
1465 int offset, board_type, magic, err = 0;
1466 struct pci_dev *pdev = adapter->pdev;
1467
1468 offset = QLCNIC_FW_MAGIC_OFFSET;
1469 if (qlcnic_rom_fast_read(adapter, offset, &magic))
1470 return -EIO;
1471
1472 if (magic != QLCNIC_BDINFO_MAGIC) {
1473 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1474 magic);
1475 return -EIO;
1476 }
1477
1478 offset = QLCNIC_BRDTYPE_OFFSET;
1479 if (qlcnic_rom_fast_read(adapter, offset, &board_type))
1480 return -EIO;
1481
1482 adapter->ahw->board_type = board_type;
1483
1484 if (board_type == QLCNIC_BRDTYPE_P3P_4_GB_MM) {
1485 u32 gpio = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_PAD_GPIO_I, &err);
1486 if (err == -EIO)
1487 return err;
1488 if ((gpio & 0x8000) == 0)
1489 board_type = QLCNIC_BRDTYPE_P3P_10G_TP;
1490 }
1491
1492 switch (board_type) {
1493 case QLCNIC_BRDTYPE_P3P_HMEZ:
1494 case QLCNIC_BRDTYPE_P3P_XG_LOM:
1495 case QLCNIC_BRDTYPE_P3P_10G_CX4:
1496 case QLCNIC_BRDTYPE_P3P_10G_CX4_LP:
1497 case QLCNIC_BRDTYPE_P3P_IMEZ:
1498 case QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS:
1499 case QLCNIC_BRDTYPE_P3P_10G_SFP_CT:
1500 case QLCNIC_BRDTYPE_P3P_10G_SFP_QT:
1501 case QLCNIC_BRDTYPE_P3P_10G_XFP:
1502 case QLCNIC_BRDTYPE_P3P_10000_BASE_T:
1503 adapter->ahw->port_type = QLCNIC_XGBE;
1504 break;
1505 case QLCNIC_BRDTYPE_P3P_REF_QG:
1506 case QLCNIC_BRDTYPE_P3P_4_GB:
1507 case QLCNIC_BRDTYPE_P3P_4_GB_MM:
1508 adapter->ahw->port_type = QLCNIC_GBE;
1509 break;
1510 case QLCNIC_BRDTYPE_P3P_10G_TP:
1511 adapter->ahw->port_type = (adapter->portnum < 2) ?
1512 QLCNIC_XGBE : QLCNIC_GBE;
1513 break;
1514 default:
1515 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1516 adapter->ahw->port_type = QLCNIC_XGBE;
1517 break;
1518 }
1519
1520 return 0;
1521}
1522
1523static int
1524qlcnic_wol_supported(struct qlcnic_adapter *adapter)
1525{
1526 u32 wol_cfg;
1527 int err = 0;
1528
1529 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV, &err);
1530 if (wol_cfg & (1UL << adapter->portnum)) {
1531 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG, &err);
1532 if (err == -EIO)
1533 return err;
1534 if (wol_cfg & (1 << adapter->portnum))
1535 return 1;
1536 }
1537
1538 return 0;
1539}
1540
1541int qlcnic_82xx_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate)
1542{
1543 struct qlcnic_nic_req req;
1544 int rv;
1545 u64 word;
1546
1547 memset(&req, 0, sizeof(struct qlcnic_nic_req));
1548 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1549
1550 word = QLCNIC_H2C_OPCODE_CONFIG_LED | ((u64)adapter->portnum << 16);
1551 req.req_hdr = cpu_to_le64(word);
1552
1553 req.words[0] = cpu_to_le64(((u64)rate << 32) | adapter->portnum);
1554 req.words[1] = cpu_to_le64(state);
1555
1556 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1557 if (rv)
1558 dev_err(&adapter->pdev->dev, "LED configuration failed.\n");
1559
1560 return rv;
1561}
1562
1563void qlcnic_82xx_get_beacon_state(struct qlcnic_adapter *adapter)
1564{
1565 struct qlcnic_hardware_context *ahw = adapter->ahw;
1566 struct qlcnic_cmd_args cmd;
1567 u8 beacon_state;
1568 int err = 0;
1569
1570 if (ahw->extra_capability[0] & QLCNIC_FW_CAPABILITY_2_BEACON) {
1571 err = qlcnic_alloc_mbx_args(&cmd, adapter,
1572 QLCNIC_CMD_GET_LED_STATUS);
1573 if (!err) {
1574 err = qlcnic_issue_cmd(adapter, &cmd);
1575 if (err) {
1576 netdev_err(adapter->netdev,
1577 "Failed to get current beacon state, err=%d\n",
1578 err);
1579 } else {
1580 beacon_state = cmd.rsp.arg[1];
1581 if (beacon_state == QLCNIC_BEACON_DISABLE)
1582 ahw->beacon_state = QLCNIC_BEACON_OFF;
1583 else if (beacon_state == QLCNIC_BEACON_EANBLE)
1584 ahw->beacon_state = QLCNIC_BEACON_ON;
1585 }
1586 }
1587 qlcnic_free_mbx_args(&cmd);
1588 }
1589
1590 return;
1591}
1592
1593void qlcnic_82xx_get_func_no(struct qlcnic_adapter *adapter)
1594{
1595 void __iomem *msix_base_addr;
1596 u32 func;
1597 u32 msix_base;
1598
1599 pci_read_config_dword(adapter->pdev, QLCNIC_MSIX_TABLE_OFFSET, &func);
1600 msix_base_addr = adapter->ahw->pci_base0 + QLCNIC_MSIX_BASE;
1601 msix_base = readl(msix_base_addr);
1602 func = (func - msix_base) / QLCNIC_MSIX_TBL_PGSIZE;
1603 adapter->ahw->pci_func = func;
1604}
1605
1606void qlcnic_82xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
1607 loff_t offset, size_t size)
1608{
1609 int err = 0;
1610 u32 data;
1611 u64 qmdata;
1612
1613 if (ADDR_IN_RANGE(offset, QLCNIC_PCI_CAMQM, QLCNIC_PCI_CAMQM_END)) {
1614 qlcnic_pci_camqm_read_2M(adapter, offset, &qmdata);
1615 memcpy(buf, &qmdata, size);
1616 } else {
1617 data = QLCRD32(adapter, offset, &err);
1618 memcpy(buf, &data, size);
1619 }
1620}
1621
1622void qlcnic_82xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
1623 loff_t offset, size_t size)
1624{
1625 u32 data;
1626 u64 qmdata;
1627
1628 if (ADDR_IN_RANGE(offset, QLCNIC_PCI_CAMQM, QLCNIC_PCI_CAMQM_END)) {
1629 memcpy(&qmdata, buf, size);
1630 qlcnic_pci_camqm_write_2M(adapter, offset, qmdata);
1631 } else {
1632 memcpy(&data, buf, size);
1633 QLCWR32(adapter, offset, data);
1634 }
1635}
1636
1637int qlcnic_82xx_api_lock(struct qlcnic_adapter *adapter)
1638{
1639 return qlcnic_pcie_sem_lock(adapter, 5, 0);
1640}
1641
1642void qlcnic_82xx_api_unlock(struct qlcnic_adapter *adapter)
1643{
1644 qlcnic_pcie_sem_unlock(adapter, 5);
1645}
1646
1647int qlcnic_82xx_shutdown(struct pci_dev *pdev)
1648{
1649 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
1650 struct net_device *netdev = adapter->netdev;
1651 int retval;
1652
1653 netif_device_detach(netdev);
1654
1655 qlcnic_cancel_idc_work(adapter);
1656
1657 if (netif_running(netdev))
1658 qlcnic_down(adapter, netdev);
1659
1660 qlcnic_clr_all_drv_state(adapter, 0);
1661
1662 clear_bit(__QLCNIC_RESETTING, &adapter->state);
1663
1664 retval = pci_save_state(pdev);
1665 if (retval)
1666 return retval;
1667
1668 if (qlcnic_wol_supported(adapter)) {
1669 pci_enable_wake(pdev, PCI_D3cold, 1);
1670 pci_enable_wake(pdev, PCI_D3hot, 1);
1671 }
1672
1673 return 0;
1674}
1675
1676int qlcnic_82xx_resume(struct qlcnic_adapter *adapter)
1677{
1678 struct net_device *netdev = adapter->netdev;
1679 int err;
1680
1681 err = qlcnic_start_firmware(adapter);
1682 if (err) {
1683 dev_err(&adapter->pdev->dev, "failed to start firmware\n");
1684 return err;
1685 }
1686
1687 if (netif_running(netdev)) {
1688 err = qlcnic_up(adapter, netdev);
1689 if (!err)
1690 qlcnic_restore_indev_addr(netdev, NETDEV_UP);
1691 }
1692
1693 netif_device_attach(netdev);
1694 qlcnic_schedule_work(adapter, qlcnic_fw_poll_work, FW_POLL_DELAY);
1695 return err;
1696}
1697
