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43#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44
45#include <linux/module.h>
46#include <linux/delay.h>
47#include <linux/dma-mapping.h>
48#include <linux/hardirq.h>
49#include <linux/if.h>
50#include <linux/io.h>
51#include <linux/netdevice.h>
52#include <linux/cache.h>
53#include <linux/ethtool.h>
54#include <linux/uaccess.h>
55#include <linux/slab.h>
56#include <linux/etherdevice.h>
57#include <linux/nl80211.h>
58
59#include <net/cfg80211.h>
60#include <net/ieee80211_radiotap.h>
61
62#include <asm/unaligned.h>
63
64#include <net/mac80211.h>
65#include "base.h"
66#include "reg.h"
67#include "debug.h"
68#include "ani.h"
69#include "ath5k.h"
70#include "../regd.h"
71
72#define CREATE_TRACE_POINTS
73#include "trace.h"
74
75bool ath5k_modparam_nohwcrypt;
76module_param_named(nohwcrypt, ath5k_modparam_nohwcrypt, bool, S_IRUGO);
77MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
78
79static bool modparam_fastchanswitch;
80module_param_named(fastchanswitch, modparam_fastchanswitch, bool, S_IRUGO);
81MODULE_PARM_DESC(fastchanswitch, "Enable fast channel switching for AR2413/AR5413 radios.");
82
83static bool ath5k_modparam_no_hw_rfkill_switch;
84module_param_named(no_hw_rfkill_switch, ath5k_modparam_no_hw_rfkill_switch,
85 bool, S_IRUGO);
86MODULE_PARM_DESC(no_hw_rfkill_switch, "Ignore the GPIO RFKill switch state");
87
88
89
90MODULE_AUTHOR("Jiri Slaby");
91MODULE_AUTHOR("Nick Kossifidis");
92MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
93MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
94MODULE_LICENSE("Dual BSD/GPL");
95
96static int ath5k_init(struct ieee80211_hw *hw);
97static int ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
98 bool skip_pcu);
99
100
101static const struct ath5k_srev_name srev_names[] = {
102#ifdef CONFIG_ATHEROS_AR231X
103 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 },
104 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 },
105 { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 },
106 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 },
107 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 },
108 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 },
109 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 },
110#else
111 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
112 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
113 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
114 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
115 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
116 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
117 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
118 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
119 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
120 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
121 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
122 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
123 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
124 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
125 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
126 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
127 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
128 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
129#endif
130 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
131 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
132 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
133 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
134 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
135 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
136 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
137 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
138 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
139 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
140 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
141 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
142 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
143 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
144 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
145#ifdef CONFIG_ATHEROS_AR231X
146 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
147 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
148#endif
149 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
150};
151
152static const struct ieee80211_rate ath5k_rates[] = {
153 { .bitrate = 10,
154 .hw_value = ATH5K_RATE_CODE_1M, },
155 { .bitrate = 20,
156 .hw_value = ATH5K_RATE_CODE_2M,
157 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
158 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
159 { .bitrate = 55,
160 .hw_value = ATH5K_RATE_CODE_5_5M,
161 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
162 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
163 { .bitrate = 110,
164 .hw_value = ATH5K_RATE_CODE_11M,
165 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
166 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
167 { .bitrate = 60,
168 .hw_value = ATH5K_RATE_CODE_6M,
169 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
170 IEEE80211_RATE_SUPPORTS_10MHZ },
171 { .bitrate = 90,
172 .hw_value = ATH5K_RATE_CODE_9M,
173 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
174 IEEE80211_RATE_SUPPORTS_10MHZ },
175 { .bitrate = 120,
176 .hw_value = ATH5K_RATE_CODE_12M,
177 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
178 IEEE80211_RATE_SUPPORTS_10MHZ },
179 { .bitrate = 180,
180 .hw_value = ATH5K_RATE_CODE_18M,
181 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
182 IEEE80211_RATE_SUPPORTS_10MHZ },
183 { .bitrate = 240,
184 .hw_value = ATH5K_RATE_CODE_24M,
185 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
186 IEEE80211_RATE_SUPPORTS_10MHZ },
187 { .bitrate = 360,
188 .hw_value = ATH5K_RATE_CODE_36M,
189 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
190 IEEE80211_RATE_SUPPORTS_10MHZ },
191 { .bitrate = 480,
192 .hw_value = ATH5K_RATE_CODE_48M,
193 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
194 IEEE80211_RATE_SUPPORTS_10MHZ },
195 { .bitrate = 540,
196 .hw_value = ATH5K_RATE_CODE_54M,
197 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
198 IEEE80211_RATE_SUPPORTS_10MHZ },
199};
200
201static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
202{
203 u64 tsf = ath5k_hw_get_tsf64(ah);
204
205 if ((tsf & 0x7fff) < rstamp)
206 tsf -= 0x8000;
207
208 return (tsf & ~0x7fff) | rstamp;
209}
210
211const char *
212ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
213{
214 const char *name = "xxxxx";
215 unsigned int i;
216
217 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
218 if (srev_names[i].sr_type != type)
219 continue;
220
221 if ((val & 0xf0) == srev_names[i].sr_val)
222 name = srev_names[i].sr_name;
223
224 if ((val & 0xff) == srev_names[i].sr_val) {
225 name = srev_names[i].sr_name;
226 break;
227 }
228 }
229
230 return name;
231}
232static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
233{
234 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
235 return ath5k_hw_reg_read(ah, reg_offset);
236}
237
238static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
239{
240 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
241 ath5k_hw_reg_write(ah, val, reg_offset);
242}
243
244static const struct ath_ops ath5k_common_ops = {
245 .read = ath5k_ioread32,
246 .write = ath5k_iowrite32,
247};
248
249
250
251
252
253static void ath5k_reg_notifier(struct wiphy *wiphy,
254 struct regulatory_request *request)
255{
256 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
257 struct ath5k_hw *ah = hw->priv;
258 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
259
260 ath_reg_notifier_apply(wiphy, request, regulatory);
261}
262
263
264
265
266
267
268
269
270#ifdef CONFIG_ATH5K_TEST_CHANNELS
271static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band)
272{
273 return true;
274}
275
276#else
277static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band)
278{
279 if (band == IEEE80211_BAND_2GHZ && chan <= 14)
280 return true;
281
282 return
283 (((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
284
285 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
286
287 ((chan & 3) == 1 && chan >= 149 && chan <= 165) ||
288
289 (chan == 8 || chan == 12 || chan == 16) ||
290
291 (chan == 184 || chan == 188 || chan == 192 || chan == 196));
292}
293#endif
294
295static unsigned int
296ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels,
297 unsigned int mode, unsigned int max)
298{
299 unsigned int count, size, freq, ch;
300 enum ieee80211_band band;
301
302 switch (mode) {
303 case AR5K_MODE_11A:
304
305 size = 220;
306 band = IEEE80211_BAND_5GHZ;
307 break;
308 case AR5K_MODE_11B:
309 case AR5K_MODE_11G:
310 size = 26;
311 band = IEEE80211_BAND_2GHZ;
312 break;
313 default:
314 ATH5K_WARN(ah, "bad mode, not copying channels\n");
315 return 0;
316 }
317
318 count = 0;
319 for (ch = 1; ch <= size && count < max; ch++) {
320 freq = ieee80211_channel_to_frequency(ch, band);
321
322 if (freq == 0)
323 continue;
324
325
326 channels[count].center_freq = freq;
327 channels[count].band = band;
328 channels[count].hw_value = mode;
329
330
331 if (!ath5k_channel_ok(ah, &channels[count]))
332 continue;
333
334 if (!ath5k_is_standard_channel(ch, band))
335 continue;
336
337 count++;
338 }
339
340 return count;
341}
342
343static void
344ath5k_setup_rate_idx(struct ath5k_hw *ah, struct ieee80211_supported_band *b)
345{
346 u8 i;
347
348 for (i = 0; i < AR5K_MAX_RATES; i++)
349 ah->rate_idx[b->band][i] = -1;
350
351 for (i = 0; i < b->n_bitrates; i++) {
352 ah->rate_idx[b->band][b->bitrates[i].hw_value] = i;
353 if (b->bitrates[i].hw_value_short)
354 ah->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
355 }
356}
357
358static int
359ath5k_setup_bands(struct ieee80211_hw *hw)
360{
361 struct ath5k_hw *ah = hw->priv;
362 struct ieee80211_supported_band *sband;
363 int max_c, count_c = 0;
364 int i;
365
366 BUILD_BUG_ON(ARRAY_SIZE(ah->sbands) < IEEE80211_NUM_BANDS);
367 max_c = ARRAY_SIZE(ah->channels);
368
369
370 sband = &ah->sbands[IEEE80211_BAND_2GHZ];
371 sband->band = IEEE80211_BAND_2GHZ;
372 sband->bitrates = &ah->rates[IEEE80211_BAND_2GHZ][0];
373
374 if (test_bit(AR5K_MODE_11G, ah->ah_capabilities.cap_mode)) {
375
376 memcpy(sband->bitrates, &ath5k_rates[0],
377 sizeof(struct ieee80211_rate) * 12);
378 sband->n_bitrates = 12;
379
380 sband->channels = ah->channels;
381 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
382 AR5K_MODE_11G, max_c);
383
384 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
385 count_c = sband->n_channels;
386 max_c -= count_c;
387 } else if (test_bit(AR5K_MODE_11B, ah->ah_capabilities.cap_mode)) {
388
389 memcpy(sband->bitrates, &ath5k_rates[0],
390 sizeof(struct ieee80211_rate) * 4);
391 sband->n_bitrates = 4;
392
393
394
395
396
397 if (ah->ah_version == AR5K_AR5211) {
398 for (i = 0; i < 4; i++) {
399 sband->bitrates[i].hw_value =
400 sband->bitrates[i].hw_value & 0xF;
401 sband->bitrates[i].hw_value_short =
402 sband->bitrates[i].hw_value_short & 0xF;
403 }
404 }
405
406 sband->channels = ah->channels;
407 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
408 AR5K_MODE_11B, max_c);
409
410 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
411 count_c = sband->n_channels;
412 max_c -= count_c;
413 }
414 ath5k_setup_rate_idx(ah, sband);
415
416
417 if (test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) {
418 sband = &ah->sbands[IEEE80211_BAND_5GHZ];
419 sband->band = IEEE80211_BAND_5GHZ;
420 sband->bitrates = &ah->rates[IEEE80211_BAND_5GHZ][0];
421
422 memcpy(sband->bitrates, &ath5k_rates[4],
423 sizeof(struct ieee80211_rate) * 8);
424 sband->n_bitrates = 8;
425
426 sband->channels = &ah->channels[count_c];
427 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
428 AR5K_MODE_11A, max_c);
429
430 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
431 }
432 ath5k_setup_rate_idx(ah, sband);
433
434 ath5k_debug_dump_bands(ah);
435
436 return 0;
437}
438
439
440
441
442
443
444
445
446int
447ath5k_chan_set(struct ath5k_hw *ah, struct cfg80211_chan_def *chandef)
448{
449 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
450 "channel set, resetting (%u -> %u MHz)\n",
451 ah->curchan->center_freq, chandef->chan->center_freq);
452
453 switch (chandef->width) {
454 case NL80211_CHAN_WIDTH_20:
455 case NL80211_CHAN_WIDTH_20_NOHT:
456 ah->ah_bwmode = AR5K_BWMODE_DEFAULT;
457 break;
458 case NL80211_CHAN_WIDTH_5:
459 ah->ah_bwmode = AR5K_BWMODE_5MHZ;
460 break;
461 case NL80211_CHAN_WIDTH_10:
462 ah->ah_bwmode = AR5K_BWMODE_10MHZ;
463 break;
464 default:
465 WARN_ON(1);
466 return -EINVAL;
467 }
468
469
470
471
472
473
474
475 return ath5k_reset(ah, chandef->chan, true);
476}
477
478void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
479{
480 struct ath5k_vif_iter_data *iter_data = data;
481 int i;
482 struct ath5k_vif *avf = (void *)vif->drv_priv;
483
484 if (iter_data->hw_macaddr)
485 for (i = 0; i < ETH_ALEN; i++)
486 iter_data->mask[i] &=
487 ~(iter_data->hw_macaddr[i] ^ mac[i]);
488
489 if (!iter_data->found_active) {
490 iter_data->found_active = true;
491 memcpy(iter_data->active_mac, mac, ETH_ALEN);
492 }
493
494 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr)
495 if (ether_addr_equal(iter_data->hw_macaddr, mac))
496 iter_data->need_set_hw_addr = false;
497
498 if (!iter_data->any_assoc) {
499 if (avf->assoc)
500 iter_data->any_assoc = true;
501 }
502
503
504
505
506
507
508 if (avf->opmode == NL80211_IFTYPE_AP)
509 iter_data->opmode = NL80211_IFTYPE_AP;
510 else {
511 if (avf->opmode == NL80211_IFTYPE_STATION)
512 iter_data->n_stas++;
513 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED)
514 iter_data->opmode = avf->opmode;
515 }
516}
517
518void
519ath5k_update_bssid_mask_and_opmode(struct ath5k_hw *ah,
520 struct ieee80211_vif *vif)
521{
522 struct ath_common *common = ath5k_hw_common(ah);
523 struct ath5k_vif_iter_data iter_data;
524 u32 rfilt;
525
526
527
528
529
530 iter_data.hw_macaddr = common->macaddr;
531 memset(&iter_data.mask, 0xff, ETH_ALEN);
532 iter_data.found_active = false;
533 iter_data.need_set_hw_addr = true;
534 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED;
535 iter_data.n_stas = 0;
536
537 if (vif)
538 ath5k_vif_iter(&iter_data, vif->addr, vif);
539
540
541 ieee80211_iterate_active_interfaces_atomic(
542 ah->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
543 ath5k_vif_iter, &iter_data);
544 memcpy(ah->bssidmask, iter_data.mask, ETH_ALEN);
545
546 ah->opmode = iter_data.opmode;
547 if (ah->opmode == NL80211_IFTYPE_UNSPECIFIED)
548
549 ah->opmode = NL80211_IFTYPE_STATION;
550
551 ath5k_hw_set_opmode(ah, ah->opmode);
552 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
553 ah->opmode, ath_opmode_to_string(ah->opmode));
554
555 if (iter_data.need_set_hw_addr && iter_data.found_active)
556 ath5k_hw_set_lladdr(ah, iter_data.active_mac);
557
558 if (ath5k_hw_hasbssidmask(ah))
559 ath5k_hw_set_bssid_mask(ah, ah->bssidmask);
560
561
562 if (iter_data.n_stas > 1) {
563
564
565
566
567 ah->filter_flags |= AR5K_RX_FILTER_PROM;
568 }
569
570 rfilt = ah->filter_flags;
571 ath5k_hw_set_rx_filter(ah, rfilt);
572 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
573}
574
575static inline int
576ath5k_hw_to_driver_rix(struct ath5k_hw *ah, int hw_rix)
577{
578 int rix;
579
580
581 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
582 "hw_rix out of bounds: %x\n", hw_rix))
583 return 0;
584
585 rix = ah->rate_idx[ah->curchan->band][hw_rix];
586 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
587 rix = 0;
588
589 return rix;
590}
591
592
593
594
595
596static
597struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_hw *ah, dma_addr_t *skb_addr)
598{
599 struct ath_common *common = ath5k_hw_common(ah);
600 struct sk_buff *skb;
601
602
603
604
605
606 skb = ath_rxbuf_alloc(common,
607 common->rx_bufsize,
608 GFP_ATOMIC);
609
610 if (!skb) {
611 ATH5K_ERR(ah, "can't alloc skbuff of size %u\n",
612 common->rx_bufsize);
613 return NULL;
614 }
615
616 *skb_addr = dma_map_single(ah->dev,
617 skb->data, common->rx_bufsize,
618 DMA_FROM_DEVICE);
619
620 if (unlikely(dma_mapping_error(ah->dev, *skb_addr))) {
621 ATH5K_ERR(ah, "%s: DMA mapping failed\n", __func__);
622 dev_kfree_skb(skb);
623 return NULL;
624 }
625 return skb;
626}
627
628static int
629ath5k_rxbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf)
630{
631 struct sk_buff *skb = bf->skb;
632 struct ath5k_desc *ds;
633 int ret;
634
635 if (!skb) {
636 skb = ath5k_rx_skb_alloc(ah, &bf->skbaddr);
637 if (!skb)
638 return -ENOMEM;
639 bf->skb = skb;
640 }
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657 ds = bf->desc;
658 ds->ds_link = bf->daddr;
659 ds->ds_data = bf->skbaddr;
660 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
661 if (ret) {
662 ATH5K_ERR(ah, "%s: could not setup RX desc\n", __func__);
663 return ret;
664 }
665
666 if (ah->rxlink != NULL)
667 *ah->rxlink = bf->daddr;
668 ah->rxlink = &ds->ds_link;
669 return 0;
670}
671
672static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
673{
674 struct ieee80211_hdr *hdr;
675 enum ath5k_pkt_type htype;
676 __le16 fc;
677
678 hdr = (struct ieee80211_hdr *)skb->data;
679 fc = hdr->frame_control;
680
681 if (ieee80211_is_beacon(fc))
682 htype = AR5K_PKT_TYPE_BEACON;
683 else if (ieee80211_is_probe_resp(fc))
684 htype = AR5K_PKT_TYPE_PROBE_RESP;
685 else if (ieee80211_is_atim(fc))
686 htype = AR5K_PKT_TYPE_ATIM;
687 else if (ieee80211_is_pspoll(fc))
688 htype = AR5K_PKT_TYPE_PSPOLL;
689 else
690 htype = AR5K_PKT_TYPE_NORMAL;
691
692 return htype;
693}
694
695static struct ieee80211_rate *
696ath5k_get_rate(const struct ieee80211_hw *hw,
697 const struct ieee80211_tx_info *info,
698 struct ath5k_buf *bf, int idx)
699{
700
701
702
703
704 if (bf->rates[idx].idx < 0) {
705 return NULL;
706 }
707
708 return &hw->wiphy->bands[info->band]->bitrates[ bf->rates[idx].idx ];
709}
710
711static u16
712ath5k_get_rate_hw_value(const struct ieee80211_hw *hw,
713 const struct ieee80211_tx_info *info,
714 struct ath5k_buf *bf, int idx)
715{
716 struct ieee80211_rate *rate;
717 u16 hw_rate;
718 u8 rc_flags;
719
720 rate = ath5k_get_rate(hw, info, bf, idx);
721 if (!rate)
722 return 0;
723
724 rc_flags = bf->rates[idx].flags;
725 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
726 rate->hw_value_short : rate->hw_value;
727
728 return hw_rate;
729}
730
731static int
732ath5k_txbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf,
733 struct ath5k_txq *txq, int padsize,
734 struct ieee80211_tx_control *control)
735{
736 struct ath5k_desc *ds = bf->desc;
737 struct sk_buff *skb = bf->skb;
738 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
739 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
740 struct ieee80211_rate *rate;
741 unsigned int mrr_rate[3], mrr_tries[3];
742 int i, ret;
743 u16 hw_rate;
744 u16 cts_rate = 0;
745 u16 duration = 0;
746 u8 rc_flags;
747
748 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
749
750
751 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len,
752 DMA_TO_DEVICE);
753
754 if (dma_mapping_error(ah->dev, bf->skbaddr))
755 return -ENOSPC;
756
757 ieee80211_get_tx_rates(info->control.vif, (control) ? control->sta : NULL, skb, bf->rates,
758 ARRAY_SIZE(bf->rates));
759
760 rate = ath5k_get_rate(ah->hw, info, bf, 0);
761
762 if (!rate) {
763 ret = -EINVAL;
764 goto err_unmap;
765 }
766
767 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
768 flags |= AR5K_TXDESC_NOACK;
769
770 rc_flags = info->control.rates[0].flags;
771
772 hw_rate = ath5k_get_rate_hw_value(ah->hw, info, bf, 0);
773
774 pktlen = skb->len;
775
776
777
778
779 if (info->control.hw_key) {
780 keyidx = info->control.hw_key->hw_key_idx;
781 pktlen += info->control.hw_key->icv_len;
782 }
783 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
784 flags |= AR5K_TXDESC_RTSENA;
785 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value;
786 duration = le16_to_cpu(ieee80211_rts_duration(ah->hw,
787 info->control.vif, pktlen, info));
788 }
789 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
790 flags |= AR5K_TXDESC_CTSENA;
791 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value;
792 duration = le16_to_cpu(ieee80211_ctstoself_duration(ah->hw,
793 info->control.vif, pktlen, info));
794 }
795
796 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
797 ieee80211_get_hdrlen_from_skb(skb), padsize,
798 get_hw_packet_type(skb),
799 (ah->ah_txpower.txp_requested * 2),
800 hw_rate,
801 bf->rates[0].count, keyidx, ah->ah_tx_ant, flags,
802 cts_rate, duration);
803 if (ret)
804 goto err_unmap;
805
806
807 if (ah->ah_capabilities.cap_has_mrr_support) {
808 memset(mrr_rate, 0, sizeof(mrr_rate));
809 memset(mrr_tries, 0, sizeof(mrr_tries));
810
811 for (i = 0; i < 3; i++) {
812
813 rate = ath5k_get_rate(ah->hw, info, bf, i);
814 if (!rate)
815 break;
816
817 mrr_rate[i] = ath5k_get_rate_hw_value(ah->hw, info, bf, i);
818 mrr_tries[i] = bf->rates[i].count;
819 }
820
821 ath5k_hw_setup_mrr_tx_desc(ah, ds,
822 mrr_rate[0], mrr_tries[0],
823 mrr_rate[1], mrr_tries[1],
824 mrr_rate[2], mrr_tries[2]);
825 }
826
827 ds->ds_link = 0;
828 ds->ds_data = bf->skbaddr;
829
830 spin_lock_bh(&txq->lock);
831 list_add_tail(&bf->list, &txq->q);
832 txq->txq_len++;
833 if (txq->link == NULL)
834 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
835 else
836 *txq->link = bf->daddr;
837
838 txq->link = &ds->ds_link;
839 ath5k_hw_start_tx_dma(ah, txq->qnum);
840 mmiowb();
841 spin_unlock_bh(&txq->lock);
842
843 return 0;
844err_unmap:
845 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
846 return ret;
847}
848
849
850
851
852
853static int
854ath5k_desc_alloc(struct ath5k_hw *ah)
855{
856 struct ath5k_desc *ds;
857 struct ath5k_buf *bf;
858 dma_addr_t da;
859 unsigned int i;
860 int ret;
861
862
863 ah->desc_len = sizeof(struct ath5k_desc) *
864 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
865
866 ah->desc = dma_alloc_coherent(ah->dev, ah->desc_len,
867 &ah->desc_daddr, GFP_KERNEL);
868 if (ah->desc == NULL) {
869 ATH5K_ERR(ah, "can't allocate descriptors\n");
870 ret = -ENOMEM;
871 goto err;
872 }
873 ds = ah->desc;
874 da = ah->desc_daddr;
875 ATH5K_DBG(ah, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
876 ds, ah->desc_len, (unsigned long long)ah->desc_daddr);
877
878 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
879 sizeof(struct ath5k_buf), GFP_KERNEL);
880 if (bf == NULL) {
881 ATH5K_ERR(ah, "can't allocate bufptr\n");
882 ret = -ENOMEM;
883 goto err_free;
884 }
885 ah->bufptr = bf;
886
887 INIT_LIST_HEAD(&ah->rxbuf);
888 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
889 bf->desc = ds;
890 bf->daddr = da;
891 list_add_tail(&bf->list, &ah->rxbuf);
892 }
893
894 INIT_LIST_HEAD(&ah->txbuf);
895 ah->txbuf_len = ATH_TXBUF;
896 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
897 bf->desc = ds;
898 bf->daddr = da;
899 list_add_tail(&bf->list, &ah->txbuf);
900 }
901
902
903 INIT_LIST_HEAD(&ah->bcbuf);
904 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) {
905 bf->desc = ds;
906 bf->daddr = da;
907 list_add_tail(&bf->list, &ah->bcbuf);
908 }
909
910 return 0;
911err_free:
912 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr);
913err:
914 ah->desc = NULL;
915 return ret;
916}
917
918void
919ath5k_txbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf)
920{
921 BUG_ON(!bf);
922 if (!bf->skb)
923 return;
924 dma_unmap_single(ah->dev, bf->skbaddr, bf->skb->len,
925 DMA_TO_DEVICE);
926 ieee80211_free_txskb(ah->hw, bf->skb);
927 bf->skb = NULL;
928 bf->skbaddr = 0;
929 bf->desc->ds_data = 0;
930}
931
932void
933ath5k_rxbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf)
934{
935 struct ath_common *common = ath5k_hw_common(ah);
936
937 BUG_ON(!bf);
938 if (!bf->skb)
939 return;
940 dma_unmap_single(ah->dev, bf->skbaddr, common->rx_bufsize,
941 DMA_FROM_DEVICE);
942 dev_kfree_skb_any(bf->skb);
943 bf->skb = NULL;
944 bf->skbaddr = 0;
945 bf->desc->ds_data = 0;
946}
947
948static void
949ath5k_desc_free(struct ath5k_hw *ah)
950{
951 struct ath5k_buf *bf;
952
953 list_for_each_entry(bf, &ah->txbuf, list)
954 ath5k_txbuf_free_skb(ah, bf);
955 list_for_each_entry(bf, &ah->rxbuf, list)
956 ath5k_rxbuf_free_skb(ah, bf);
957 list_for_each_entry(bf, &ah->bcbuf, list)
958 ath5k_txbuf_free_skb(ah, bf);
959
960
961 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr);
962 ah->desc = NULL;
963 ah->desc_daddr = 0;
964
965 kfree(ah->bufptr);
966 ah->bufptr = NULL;
967}
968
969
970
971
972
973
974static struct ath5k_txq *
975ath5k_txq_setup(struct ath5k_hw *ah,
976 int qtype, int subtype)
977{
978 struct ath5k_txq *txq;
979 struct ath5k_txq_info qi = {
980 .tqi_subtype = subtype,
981
982
983 .tqi_aifs = AR5K_TUNE_AIFS,
984 .tqi_cw_min = AR5K_TUNE_CWMIN,
985 .tqi_cw_max = AR5K_TUNE_CWMAX
986 };
987 int qnum;
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1002 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1003 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1004 if (qnum < 0) {
1005
1006
1007
1008
1009 return ERR_PTR(qnum);
1010 }
1011 txq = &ah->txqs[qnum];
1012 if (!txq->setup) {
1013 txq->qnum = qnum;
1014 txq->link = NULL;
1015 INIT_LIST_HEAD(&txq->q);
1016 spin_lock_init(&txq->lock);
1017 txq->setup = true;
1018 txq->txq_len = 0;
1019 txq->txq_max = ATH5K_TXQ_LEN_MAX;
1020 txq->txq_poll_mark = false;
1021 txq->txq_stuck = 0;
1022 }
1023 return &ah->txqs[qnum];
1024}
1025
1026static int
1027ath5k_beaconq_setup(struct ath5k_hw *ah)
1028{
1029 struct ath5k_txq_info qi = {
1030
1031
1032 .tqi_aifs = AR5K_TUNE_AIFS,
1033 .tqi_cw_min = AR5K_TUNE_CWMIN,
1034 .tqi_cw_max = AR5K_TUNE_CWMAX,
1035
1036 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1037 };
1038
1039 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1040}
1041
1042static int
1043ath5k_beaconq_config(struct ath5k_hw *ah)
1044{
1045 struct ath5k_txq_info qi;
1046 int ret;
1047
1048 ret = ath5k_hw_get_tx_queueprops(ah, ah->bhalq, &qi);
1049 if (ret)
1050 goto err;
1051
1052 if (ah->opmode == NL80211_IFTYPE_AP ||
1053 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
1054
1055
1056
1057
1058 qi.tqi_aifs = 0;
1059 qi.tqi_cw_min = 0;
1060 qi.tqi_cw_max = 0;
1061 } else if (ah->opmode == NL80211_IFTYPE_ADHOC) {
1062
1063
1064
1065 qi.tqi_aifs = 0;
1066 qi.tqi_cw_min = 0;
1067 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
1068 }
1069
1070 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1071 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1072 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1073
1074 ret = ath5k_hw_set_tx_queueprops(ah, ah->bhalq, &qi);
1075 if (ret) {
1076 ATH5K_ERR(ah, "%s: unable to update parameters for beacon "
1077 "hardware queue!\n", __func__);
1078 goto err;
1079 }
1080 ret = ath5k_hw_reset_tx_queue(ah, ah->bhalq);
1081 if (ret)
1082 goto err;
1083
1084
1085 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1086 if (ret)
1087 goto err;
1088
1089 qi.tqi_ready_time = (ah->bintval * 80) / 100;
1090 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1091 if (ret)
1092 goto err;
1093
1094 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1095err:
1096 return ret;
1097}
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110static void
1111ath5k_drain_tx_buffs(struct ath5k_hw *ah)
1112{
1113 struct ath5k_txq *txq;
1114 struct ath5k_buf *bf, *bf0;
1115 int i;
1116
1117 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
1118 if (ah->txqs[i].setup) {
1119 txq = &ah->txqs[i];
1120 spin_lock_bh(&txq->lock);
1121 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1122 ath5k_debug_printtxbuf(ah, bf);
1123
1124 ath5k_txbuf_free_skb(ah, bf);
1125
1126 spin_lock(&ah->txbuflock);
1127 list_move_tail(&bf->list, &ah->txbuf);
1128 ah->txbuf_len++;
1129 txq->txq_len--;
1130 spin_unlock(&ah->txbuflock);
1131 }
1132 txq->link = NULL;
1133 txq->txq_poll_mark = false;
1134 spin_unlock_bh(&txq->lock);
1135 }
1136 }
1137}
1138
1139static void
1140ath5k_txq_release(struct ath5k_hw *ah)
1141{
1142 struct ath5k_txq *txq = ah->txqs;
1143 unsigned int i;
1144
1145 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++, txq++)
1146 if (txq->setup) {
1147 ath5k_hw_release_tx_queue(ah, txq->qnum);
1148 txq->setup = false;
1149 }
1150}
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160static int
1161ath5k_rx_start(struct ath5k_hw *ah)
1162{
1163 struct ath_common *common = ath5k_hw_common(ah);
1164 struct ath5k_buf *bf;
1165 int ret;
1166
1167 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
1168
1169 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1170 common->cachelsz, common->rx_bufsize);
1171
1172 spin_lock_bh(&ah->rxbuflock);
1173 ah->rxlink = NULL;
1174 list_for_each_entry(bf, &ah->rxbuf, list) {
1175 ret = ath5k_rxbuf_setup(ah, bf);
1176 if (ret != 0) {
1177 spin_unlock_bh(&ah->rxbuflock);
1178 goto err;
1179 }
1180 }
1181 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list);
1182 ath5k_hw_set_rxdp(ah, bf->daddr);
1183 spin_unlock_bh(&ah->rxbuflock);
1184
1185 ath5k_hw_start_rx_dma(ah);
1186 ath5k_update_bssid_mask_and_opmode(ah, NULL);
1187 ath5k_hw_start_rx_pcu(ah);
1188
1189 return 0;
1190err:
1191 return ret;
1192}
1193
1194
1195
1196
1197
1198
1199
1200
1201static void
1202ath5k_rx_stop(struct ath5k_hw *ah)
1203{
1204
1205 ath5k_hw_set_rx_filter(ah, 0);
1206 ath5k_hw_stop_rx_pcu(ah);
1207
1208 ath5k_debug_printrxbuffs(ah);
1209}
1210
1211static unsigned int
1212ath5k_rx_decrypted(struct ath5k_hw *ah, struct sk_buff *skb,
1213 struct ath5k_rx_status *rs)
1214{
1215 struct ath_common *common = ath5k_hw_common(ah);
1216 struct ieee80211_hdr *hdr = (void *)skb->data;
1217 unsigned int keyix, hlen;
1218
1219 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1220 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1221 return RX_FLAG_DECRYPTED;
1222
1223
1224
1225
1226 hlen = ieee80211_hdrlen(hdr->frame_control);
1227 if (ieee80211_has_protected(hdr->frame_control) &&
1228 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1229 skb->len >= hlen + 4) {
1230 keyix = skb->data[hlen + 3] >> 6;
1231
1232 if (test_bit(keyix, common->keymap))
1233 return RX_FLAG_DECRYPTED;
1234 }
1235
1236 return 0;
1237}
1238
1239
1240static void
1241ath5k_check_ibss_tsf(struct ath5k_hw *ah, struct sk_buff *skb,
1242 struct ieee80211_rx_status *rxs)
1243{
1244 u64 tsf, bc_tstamp;
1245 u32 hw_tu;
1246 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1247
1248 if (le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS) {
1249
1250
1251
1252
1253
1254 tsf = ath5k_hw_get_tsf64(ah);
1255 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1256 hw_tu = TSF_TO_TU(tsf);
1257
1258 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
1259 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1260 (unsigned long long)bc_tstamp,
1261 (unsigned long long)rxs->mactime,
1262 (unsigned long long)(rxs->mactime - bc_tstamp),
1263 (unsigned long long)tsf);
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276 if (bc_tstamp > rxs->mactime) {
1277 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
1278 "fixing mactime from %llx to %llx\n",
1279 (unsigned long long)rxs->mactime,
1280 (unsigned long long)tsf);
1281 rxs->mactime = tsf;
1282 }
1283
1284
1285
1286
1287
1288
1289
1290 if (hw_tu >= ah->nexttbtt)
1291 ath5k_beacon_update_timers(ah, bc_tstamp);
1292
1293
1294
1295
1296 if (!ath5k_hw_check_beacon_timers(ah, ah->bintval)) {
1297 ath5k_beacon_update_timers(ah, bc_tstamp);
1298 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
1299 "fixed beacon timers after beacon receive\n");
1300 }
1301 }
1302}
1303
1304
1305
1306
1307static int ath5k_common_padpos(struct sk_buff *skb)
1308{
1309 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1310 __le16 frame_control = hdr->frame_control;
1311 int padpos = 24;
1312
1313 if (ieee80211_has_a4(frame_control))
1314 padpos += ETH_ALEN;
1315
1316 if (ieee80211_is_data_qos(frame_control))
1317 padpos += IEEE80211_QOS_CTL_LEN;
1318
1319 return padpos;
1320}
1321
1322
1323
1324
1325
1326static int ath5k_add_padding(struct sk_buff *skb)
1327{
1328 int padpos = ath5k_common_padpos(skb);
1329 int padsize = padpos & 3;
1330
1331 if (padsize && skb->len > padpos) {
1332
1333 if (skb_headroom(skb) < padsize)
1334 return -1;
1335
1336 skb_push(skb, padsize);
1337 memmove(skb->data, skb->data + padsize, padpos);
1338 return padsize;
1339 }
1340
1341 return 0;
1342}
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357static int ath5k_remove_padding(struct sk_buff *skb)
1358{
1359 int padpos = ath5k_common_padpos(skb);
1360 int padsize = padpos & 3;
1361
1362 if (padsize && skb->len >= padpos + padsize) {
1363 memmove(skb->data + padsize, skb->data, padpos);
1364 skb_pull(skb, padsize);
1365 return padsize;
1366 }
1367
1368 return 0;
1369}
1370
1371static void
1372ath5k_receive_frame(struct ath5k_hw *ah, struct sk_buff *skb,
1373 struct ath5k_rx_status *rs)
1374{
1375 struct ieee80211_rx_status *rxs;
1376 struct ath_common *common = ath5k_hw_common(ah);
1377
1378 ath5k_remove_padding(skb);
1379
1380 rxs = IEEE80211_SKB_RXCB(skb);
1381
1382 rxs->flag = 0;
1383 if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1384 rxs->flag |= RX_FLAG_MMIC_ERROR;
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395 rxs->mactime = ath5k_extend_tsf(ah, rs->rs_tstamp);
1396 rxs->flag |= RX_FLAG_MACTIME_END;
1397
1398 rxs->freq = ah->curchan->center_freq;
1399 rxs->band = ah->curchan->band;
1400
1401 rxs->signal = ah->ah_noise_floor + rs->rs_rssi;
1402
1403 rxs->antenna = rs->rs_antenna;
1404
1405 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
1406 ah->stats.antenna_rx[rs->rs_antenna]++;
1407 else
1408 ah->stats.antenna_rx[0]++;
1409
1410 rxs->rate_idx = ath5k_hw_to_driver_rix(ah, rs->rs_rate);
1411 rxs->flag |= ath5k_rx_decrypted(ah, skb, rs);
1412 switch (ah->ah_bwmode) {
1413 case AR5K_BWMODE_5MHZ:
1414 rxs->flag |= RX_FLAG_5MHZ;
1415 break;
1416 case AR5K_BWMODE_10MHZ:
1417 rxs->flag |= RX_FLAG_10MHZ;
1418 break;
1419 default:
1420 break;
1421 }
1422
1423 if (rxs->rate_idx >= 0 && rs->rs_rate ==
1424 ah->sbands[ah->curchan->band].bitrates[rxs->rate_idx].hw_value_short)
1425 rxs->flag |= RX_FLAG_SHORTPRE;
1426
1427 trace_ath5k_rx(ah, skb);
1428
1429 if (ath_is_mybeacon(common, (struct ieee80211_hdr *)skb->data)) {
1430 ewma_add(&ah->ah_beacon_rssi_avg, rs->rs_rssi);
1431
1432
1433 if (ah->opmode == NL80211_IFTYPE_ADHOC)
1434 ath5k_check_ibss_tsf(ah, skb, rxs);
1435 }
1436
1437 ieee80211_rx(ah->hw, skb);
1438}
1439
1440
1441
1442
1443
1444
1445static bool
1446ath5k_receive_frame_ok(struct ath5k_hw *ah, struct ath5k_rx_status *rs)
1447{
1448 ah->stats.rx_all_count++;
1449 ah->stats.rx_bytes_count += rs->rs_datalen;
1450
1451 if (unlikely(rs->rs_status)) {
1452 if (rs->rs_status & AR5K_RXERR_CRC)
1453 ah->stats.rxerr_crc++;
1454 if (rs->rs_status & AR5K_RXERR_FIFO)
1455 ah->stats.rxerr_fifo++;
1456 if (rs->rs_status & AR5K_RXERR_PHY) {
1457 ah->stats.rxerr_phy++;
1458 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
1459 ah->stats.rxerr_phy_code[rs->rs_phyerr]++;
1460 return false;
1461 }
1462 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473 ah->stats.rxerr_decrypt++;
1474 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1475 !(rs->rs_status & AR5K_RXERR_CRC))
1476 return true;
1477 }
1478 if (rs->rs_status & AR5K_RXERR_MIC) {
1479 ah->stats.rxerr_mic++;
1480 return true;
1481 }
1482
1483
1484 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT))
1485 return false;
1486 }
1487
1488 if (unlikely(rs->rs_more)) {
1489 ah->stats.rxerr_jumbo++;
1490 return false;
1491 }
1492 return true;
1493}
1494
1495static void
1496ath5k_set_current_imask(struct ath5k_hw *ah)
1497{
1498 enum ath5k_int imask;
1499 unsigned long flags;
1500
1501 spin_lock_irqsave(&ah->irqlock, flags);
1502 imask = ah->imask;
1503 if (ah->rx_pending)
1504 imask &= ~AR5K_INT_RX_ALL;
1505 if (ah->tx_pending)
1506 imask &= ~AR5K_INT_TX_ALL;
1507 ath5k_hw_set_imr(ah, imask);
1508 spin_unlock_irqrestore(&ah->irqlock, flags);
1509}
1510
1511static void
1512ath5k_tasklet_rx(unsigned long data)
1513{
1514 struct ath5k_rx_status rs = {};
1515 struct sk_buff *skb, *next_skb;
1516 dma_addr_t next_skb_addr;
1517 struct ath5k_hw *ah = (void *)data;
1518 struct ath_common *common = ath5k_hw_common(ah);
1519 struct ath5k_buf *bf;
1520 struct ath5k_desc *ds;
1521 int ret;
1522
1523 spin_lock(&ah->rxbuflock);
1524 if (list_empty(&ah->rxbuf)) {
1525 ATH5K_WARN(ah, "empty rx buf pool\n");
1526 goto unlock;
1527 }
1528 do {
1529 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list);
1530 BUG_ON(bf->skb == NULL);
1531 skb = bf->skb;
1532 ds = bf->desc;
1533
1534
1535 if (ath5k_hw_get_rxdp(ah) == bf->daddr)
1536 break;
1537
1538 ret = ah->ah_proc_rx_desc(ah, ds, &rs);
1539 if (unlikely(ret == -EINPROGRESS))
1540 break;
1541 else if (unlikely(ret)) {
1542 ATH5K_ERR(ah, "error in processing rx descriptor\n");
1543 ah->stats.rxerr_proc++;
1544 break;
1545 }
1546
1547 if (ath5k_receive_frame_ok(ah, &rs)) {
1548 next_skb = ath5k_rx_skb_alloc(ah, &next_skb_addr);
1549
1550
1551
1552
1553
1554 if (!next_skb)
1555 goto next;
1556
1557 dma_unmap_single(ah->dev, bf->skbaddr,
1558 common->rx_bufsize,
1559 DMA_FROM_DEVICE);
1560
1561 skb_put(skb, rs.rs_datalen);
1562
1563 ath5k_receive_frame(ah, skb, &rs);
1564
1565 bf->skb = next_skb;
1566 bf->skbaddr = next_skb_addr;
1567 }
1568next:
1569 list_move_tail(&bf->list, &ah->rxbuf);
1570 } while (ath5k_rxbuf_setup(ah, bf) == 0);
1571unlock:
1572 spin_unlock(&ah->rxbuflock);
1573 ah->rx_pending = false;
1574 ath5k_set_current_imask(ah);
1575}
1576
1577
1578
1579
1580
1581
1582void
1583ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1584 struct ath5k_txq *txq, struct ieee80211_tx_control *control)
1585{
1586 struct ath5k_hw *ah = hw->priv;
1587 struct ath5k_buf *bf;
1588 unsigned long flags;
1589 int padsize;
1590
1591 trace_ath5k_tx(ah, skb, txq);
1592
1593
1594
1595
1596
1597 padsize = ath5k_add_padding(skb);
1598 if (padsize < 0) {
1599 ATH5K_ERR(ah, "tx hdrlen not %%4: not enough"
1600 " headroom to pad");
1601 goto drop_packet;
1602 }
1603
1604 if (txq->txq_len >= txq->txq_max &&
1605 txq->qnum <= AR5K_TX_QUEUE_ID_DATA_MAX)
1606 ieee80211_stop_queue(hw, txq->qnum);
1607
1608 spin_lock_irqsave(&ah->txbuflock, flags);
1609 if (list_empty(&ah->txbuf)) {
1610 ATH5K_ERR(ah, "no further txbuf available, dropping packet\n");
1611 spin_unlock_irqrestore(&ah->txbuflock, flags);
1612 ieee80211_stop_queues(hw);
1613 goto drop_packet;
1614 }
1615 bf = list_first_entry(&ah->txbuf, struct ath5k_buf, list);
1616 list_del(&bf->list);
1617 ah->txbuf_len--;
1618 if (list_empty(&ah->txbuf))
1619 ieee80211_stop_queues(hw);
1620 spin_unlock_irqrestore(&ah->txbuflock, flags);
1621
1622 bf->skb = skb;
1623
1624 if (ath5k_txbuf_setup(ah, bf, txq, padsize, control)) {
1625 bf->skb = NULL;
1626 spin_lock_irqsave(&ah->txbuflock, flags);
1627 list_add_tail(&bf->list, &ah->txbuf);
1628 ah->txbuf_len++;
1629 spin_unlock_irqrestore(&ah->txbuflock, flags);
1630 goto drop_packet;
1631 }
1632 return;
1633
1634drop_packet:
1635 ieee80211_free_txskb(hw, skb);
1636}
1637
1638static void
1639ath5k_tx_frame_completed(struct ath5k_hw *ah, struct sk_buff *skb,
1640 struct ath5k_txq *txq, struct ath5k_tx_status *ts,
1641 struct ath5k_buf *bf)
1642{
1643 struct ieee80211_tx_info *info;
1644 u8 tries[3];
1645 int i;
1646 int size = 0;
1647
1648 ah->stats.tx_all_count++;
1649 ah->stats.tx_bytes_count += skb->len;
1650 info = IEEE80211_SKB_CB(skb);
1651
1652 size = min_t(int, sizeof(info->status.rates), sizeof(bf->rates));
1653 memcpy(info->status.rates, bf->rates, size);
1654
1655 tries[0] = info->status.rates[0].count;
1656 tries[1] = info->status.rates[1].count;
1657 tries[2] = info->status.rates[2].count;
1658
1659 ieee80211_tx_info_clear_status(info);
1660
1661 for (i = 0; i < ts->ts_final_idx; i++) {
1662 struct ieee80211_tx_rate *r =
1663 &info->status.rates[i];
1664
1665 r->count = tries[i];
1666 }
1667
1668 info->status.rates[ts->ts_final_idx].count = ts->ts_final_retry;
1669 info->status.rates[ts->ts_final_idx + 1].idx = -1;
1670
1671 if (unlikely(ts->ts_status)) {
1672 ah->stats.ack_fail++;
1673 if (ts->ts_status & AR5K_TXERR_FILT) {
1674 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1675 ah->stats.txerr_filt++;
1676 }
1677 if (ts->ts_status & AR5K_TXERR_XRETRY)
1678 ah->stats.txerr_retry++;
1679 if (ts->ts_status & AR5K_TXERR_FIFO)
1680 ah->stats.txerr_fifo++;
1681 } else {
1682 info->flags |= IEEE80211_TX_STAT_ACK;
1683 info->status.ack_signal = ts->ts_rssi;
1684
1685
1686 info->status.rates[ts->ts_final_idx].count++;
1687 }
1688
1689
1690
1691
1692
1693 ath5k_remove_padding(skb);
1694
1695 if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
1696 ah->stats.antenna_tx[ts->ts_antenna]++;
1697 else
1698 ah->stats.antenna_tx[0]++;
1699
1700 trace_ath5k_tx_complete(ah, skb, txq, ts);
1701 ieee80211_tx_status(ah->hw, skb);
1702}
1703
1704static void
1705ath5k_tx_processq(struct ath5k_hw *ah, struct ath5k_txq *txq)
1706{
1707 struct ath5k_tx_status ts = {};
1708 struct ath5k_buf *bf, *bf0;
1709 struct ath5k_desc *ds;
1710 struct sk_buff *skb;
1711 int ret;
1712
1713 spin_lock(&txq->lock);
1714 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1715
1716 txq->txq_poll_mark = false;
1717
1718
1719 if (bf->skb != NULL) {
1720 ds = bf->desc;
1721
1722 ret = ah->ah_proc_tx_desc(ah, ds, &ts);
1723 if (unlikely(ret == -EINPROGRESS))
1724 break;
1725 else if (unlikely(ret)) {
1726 ATH5K_ERR(ah,
1727 "error %d while processing "
1728 "queue %u\n", ret, txq->qnum);
1729 break;
1730 }
1731
1732 skb = bf->skb;
1733 bf->skb = NULL;
1734
1735 dma_unmap_single(ah->dev, bf->skbaddr, skb->len,
1736 DMA_TO_DEVICE);
1737 ath5k_tx_frame_completed(ah, skb, txq, &ts, bf);
1738 }
1739
1740
1741
1742
1743
1744
1745
1746 if (ath5k_hw_get_txdp(ah, txq->qnum) != bf->daddr) {
1747 spin_lock(&ah->txbuflock);
1748 list_move_tail(&bf->list, &ah->txbuf);
1749 ah->txbuf_len++;
1750 txq->txq_len--;
1751 spin_unlock(&ah->txbuflock);
1752 }
1753 }
1754 spin_unlock(&txq->lock);
1755 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4)
1756 ieee80211_wake_queue(ah->hw, txq->qnum);
1757}
1758
1759static void
1760ath5k_tasklet_tx(unsigned long data)
1761{
1762 int i;
1763 struct ath5k_hw *ah = (void *)data;
1764
1765 for (i = 0; i < AR5K_NUM_TX_QUEUES; i++)
1766 if (ah->txqs[i].setup && (ah->ah_txq_isr_txok_all & BIT(i)))
1767 ath5k_tx_processq(ah, &ah->txqs[i]);
1768
1769 ah->tx_pending = false;
1770 ath5k_set_current_imask(ah);
1771}
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781static int
1782ath5k_beacon_setup(struct ath5k_hw *ah, struct ath5k_buf *bf)
1783{
1784 struct sk_buff *skb = bf->skb;
1785 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1786 struct ath5k_desc *ds;
1787 int ret = 0;
1788 u8 antenna;
1789 u32 flags;
1790 const int padsize = 0;
1791
1792 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len,
1793 DMA_TO_DEVICE);
1794 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1795 "skbaddr %llx\n", skb, skb->data, skb->len,
1796 (unsigned long long)bf->skbaddr);
1797
1798 if (dma_mapping_error(ah->dev, bf->skbaddr)) {
1799 ATH5K_ERR(ah, "beacon DMA mapping failed\n");
1800 dev_kfree_skb_any(skb);
1801 bf->skb = NULL;
1802 return -EIO;
1803 }
1804
1805 ds = bf->desc;
1806 antenna = ah->ah_tx_ant;
1807
1808 flags = AR5K_TXDESC_NOACK;
1809 if (ah->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
1810 ds->ds_link = bf->daddr;
1811 flags |= AR5K_TXDESC_VEOL;
1812 } else
1813 ds->ds_link = 0;
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
1834 antenna = ah->bsent & 4 ? 2 : 1;
1835
1836
1837
1838
1839
1840 ds->ds_data = bf->skbaddr;
1841 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
1842 ieee80211_get_hdrlen_from_skb(skb), padsize,
1843 AR5K_PKT_TYPE_BEACON,
1844 (ah->ah_txpower.txp_requested * 2),
1845 ieee80211_get_tx_rate(ah->hw, info)->hw_value,
1846 1, AR5K_TXKEYIX_INVALID,
1847 antenna, flags, 0, 0);
1848 if (ret)
1849 goto err_unmap;
1850
1851 return 0;
1852err_unmap:
1853 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
1854 return ret;
1855}
1856
1857
1858
1859
1860
1861
1862
1863
1864int
1865ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1866{
1867 int ret;
1868 struct ath5k_hw *ah = hw->priv;
1869 struct ath5k_vif *avf;
1870 struct sk_buff *skb;
1871
1872 if (WARN_ON(!vif)) {
1873 ret = -EINVAL;
1874 goto out;
1875 }
1876
1877 skb = ieee80211_beacon_get(hw, vif);
1878
1879 if (!skb) {
1880 ret = -ENOMEM;
1881 goto out;
1882 }
1883
1884 avf = (void *)vif->drv_priv;
1885 ath5k_txbuf_free_skb(ah, avf->bbuf);
1886 avf->bbuf->skb = skb;
1887 ret = ath5k_beacon_setup(ah, avf->bbuf);
1888out:
1889 return ret;
1890}
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900static void
1901ath5k_beacon_send(struct ath5k_hw *ah)
1902{
1903 struct ieee80211_vif *vif;
1904 struct ath5k_vif *avf;
1905 struct ath5k_buf *bf;
1906 struct sk_buff *skb;
1907 int err;
1908
1909 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "in beacon_send\n");
1910
1911
1912
1913
1914
1915
1916
1917
1918 if (unlikely(ath5k_hw_num_tx_pending(ah, ah->bhalq) != 0)) {
1919 ah->bmisscount++;
1920 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1921 "missed %u consecutive beacons\n", ah->bmisscount);
1922 if (ah->bmisscount > 10) {
1923 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1924 "stuck beacon time (%u missed)\n",
1925 ah->bmisscount);
1926 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
1927 "stuck beacon, resetting\n");
1928 ieee80211_queue_work(ah->hw, &ah->reset_work);
1929 }
1930 return;
1931 }
1932 if (unlikely(ah->bmisscount != 0)) {
1933 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1934 "resume beacon xmit after %u misses\n",
1935 ah->bmisscount);
1936 ah->bmisscount = 0;
1937 }
1938
1939 if ((ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs +
1940 ah->num_mesh_vifs > 1) ||
1941 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
1942 u64 tsf = ath5k_hw_get_tsf64(ah);
1943 u32 tsftu = TSF_TO_TU(tsf);
1944 int slot = ((tsftu % ah->bintval) * ATH_BCBUF) / ah->bintval;
1945 vif = ah->bslot[(slot + 1) % ATH_BCBUF];
1946 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1947 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
1948 (unsigned long long)tsf, tsftu, ah->bintval, slot, vif);
1949 } else
1950 vif = ah->bslot[0];
1951
1952 if (!vif)
1953 return;
1954
1955 avf = (void *)vif->drv_priv;
1956 bf = avf->bbuf;
1957
1958
1959
1960
1961
1962
1963 if (unlikely(ath5k_hw_stop_beacon_queue(ah, ah->bhalq))) {
1964 ATH5K_WARN(ah, "beacon queue %u didn't start/stop ?\n", ah->bhalq);
1965
1966 }
1967
1968
1969 if (ah->opmode == NL80211_IFTYPE_AP ||
1970 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
1971 err = ath5k_beacon_update(ah->hw, vif);
1972 if (err)
1973 return;
1974 }
1975
1976 if (unlikely(bf->skb == NULL || ah->opmode == NL80211_IFTYPE_STATION ||
1977 ah->opmode == NL80211_IFTYPE_MONITOR)) {
1978 ATH5K_WARN(ah, "bf=%p bf_skb=%p\n", bf, bf->skb);
1979 return;
1980 }
1981
1982 trace_ath5k_tx(ah, bf->skb, &ah->txqs[ah->bhalq]);
1983
1984 ath5k_hw_set_txdp(ah, ah->bhalq, bf->daddr);
1985 ath5k_hw_start_tx_dma(ah, ah->bhalq);
1986 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
1987 ah->bhalq, (unsigned long long)bf->daddr, bf->desc);
1988
1989 skb = ieee80211_get_buffered_bc(ah->hw, vif);
1990 while (skb) {
1991 ath5k_tx_queue(ah->hw, skb, ah->cabq, NULL);
1992
1993 if (ah->cabq->txq_len >= ah->cabq->txq_max)
1994 break;
1995
1996 skb = ieee80211_get_buffered_bc(ah->hw, vif);
1997 }
1998
1999 ah->bsent++;
2000}
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018void
2019ath5k_beacon_update_timers(struct ath5k_hw *ah, u64 bc_tsf)
2020{
2021 u32 nexttbtt, intval, hw_tu, bc_tu;
2022 u64 hw_tsf;
2023
2024 intval = ah->bintval & AR5K_BEACON_PERIOD;
2025 if (ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs
2026 + ah->num_mesh_vifs > 1) {
2027 intval /= ATH_BCBUF;
2028 if (intval < 15)
2029 ATH5K_WARN(ah, "intval %u is too low, min 15\n",
2030 intval);
2031 }
2032 if (WARN_ON(!intval))
2033 return;
2034
2035
2036 bc_tu = TSF_TO_TU(bc_tsf);
2037
2038
2039 hw_tsf = ath5k_hw_get_tsf64(ah);
2040 hw_tu = TSF_TO_TU(hw_tsf);
2041
2042#define FUDGE (AR5K_TUNE_SW_BEACON_RESP + 3)
2043
2044
2045
2046
2047 if (bc_tsf == -1) {
2048
2049
2050
2051
2052 nexttbtt = roundup(hw_tu + FUDGE, intval);
2053 } else if (bc_tsf == 0) {
2054
2055
2056
2057
2058 nexttbtt = intval;
2059 intval |= AR5K_BEACON_RESET_TSF;
2060 } else if (bc_tsf > hw_tsf) {
2061
2062
2063
2064
2065
2066
2067
2068 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2069 "need to wait for HW TSF sync\n");
2070 return;
2071 } else {
2072
2073
2074
2075
2076
2077
2078
2079 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2080 }
2081#undef FUDGE
2082
2083 ah->nexttbtt = nexttbtt;
2084
2085 intval |= AR5K_BEACON_ENA;
2086 ath5k_hw_init_beacon_timers(ah, nexttbtt, intval);
2087
2088
2089
2090
2091
2092 if (bc_tsf == -1)
2093 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2094 "reconfigured timers based on HW TSF\n");
2095 else if (bc_tsf == 0)
2096 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2097 "reset HW TSF and timers\n");
2098 else
2099 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2100 "updated timers based on beacon TSF\n");
2101
2102 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2103 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2104 (unsigned long long) bc_tsf,
2105 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2106 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2107 intval & AR5K_BEACON_PERIOD,
2108 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2109 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2110}
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120void
2121ath5k_beacon_config(struct ath5k_hw *ah)
2122{
2123 spin_lock_bh(&ah->block);
2124 ah->bmisscount = 0;
2125 ah->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2126
2127 if (ah->enable_beacon) {
2128
2129
2130
2131
2132
2133
2134
2135 ath5k_beaconq_config(ah);
2136
2137 ah->imask |= AR5K_INT_SWBA;
2138
2139 if (ah->opmode == NL80211_IFTYPE_ADHOC) {
2140 if (ath5k_hw_hasveol(ah))
2141 ath5k_beacon_send(ah);
2142 } else
2143 ath5k_beacon_update_timers(ah, -1);
2144 } else {
2145 ath5k_hw_stop_beacon_queue(ah, ah->bhalq);
2146 }
2147
2148 ath5k_hw_set_imr(ah, ah->imask);
2149 mmiowb();
2150 spin_unlock_bh(&ah->block);
2151}
2152
2153static void ath5k_tasklet_beacon(unsigned long data)
2154{
2155 struct ath5k_hw *ah = (struct ath5k_hw *) data;
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165 if (ah->opmode == NL80211_IFTYPE_ADHOC) {
2166
2167 u64 tsf = ath5k_hw_get_tsf64(ah);
2168 ah->nexttbtt += ah->bintval;
2169 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
2170 "SWBA nexttbtt: %x hw_tu: %x "
2171 "TSF: %llx\n",
2172 ah->nexttbtt,
2173 TSF_TO_TU(tsf),
2174 (unsigned long long) tsf);
2175 } else {
2176 spin_lock(&ah->block);
2177 ath5k_beacon_send(ah);
2178 spin_unlock(&ah->block);
2179 }
2180}
2181
2182
2183
2184
2185
2186
2187static void
2188ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2189{
2190 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2191 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) &&
2192 !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) {
2193
2194
2195
2196 ah->ah_cal_next_ani = jiffies +
2197 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2198 tasklet_schedule(&ah->ani_tasklet);
2199
2200 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_short) &&
2201 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) &&
2202 !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) {
2203
2204
2205
2206
2207
2208
2209
2210
2211 ah->ah_cal_next_short = jiffies +
2212 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT);
2213 ieee80211_queue_work(ah->hw, &ah->calib_work);
2214 }
2215
2216
2217
2218}
2219
2220static void
2221ath5k_schedule_rx(struct ath5k_hw *ah)
2222{
2223 ah->rx_pending = true;
2224 tasklet_schedule(&ah->rxtq);
2225}
2226
2227static void
2228ath5k_schedule_tx(struct ath5k_hw *ah)
2229{
2230 ah->tx_pending = true;
2231 tasklet_schedule(&ah->txtq);
2232}
2233
2234static irqreturn_t
2235ath5k_intr(int irq, void *dev_id)
2236{
2237 struct ath5k_hw *ah = dev_id;
2238 enum ath5k_int status;
2239 unsigned int counter = 1000;
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252 if (unlikely(test_bit(ATH_STAT_INVALID, ah->status) ||
2253 ((ath5k_get_bus_type(ah) != ATH_AHB) &&
2254 !ath5k_hw_is_intr_pending(ah))))
2255 return IRQ_NONE;
2256
2257
2258 do {
2259 ath5k_hw_get_isr(ah, &status);
2260
2261 ATH5K_DBG(ah, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2262 status, ah->imask);
2263
2264
2265
2266
2267
2268
2269
2270
2271 if (unlikely(status & AR5K_INT_FATAL)) {
2272
2273 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2274 "fatal int, resetting\n");
2275 ieee80211_queue_work(ah->hw, &ah->reset_work);
2276
2277
2278
2279
2280
2281
2282
2283
2284 } else if (unlikely(status & AR5K_INT_RXORN)) {
2285
2286
2287
2288
2289
2290
2291
2292 ah->stats.rxorn_intr++;
2293
2294 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
2295 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2296 "rx overrun, resetting\n");
2297 ieee80211_queue_work(ah->hw, &ah->reset_work);
2298 } else
2299 ath5k_schedule_rx(ah);
2300
2301 } else {
2302
2303
2304 if (status & AR5K_INT_SWBA)
2305 tasklet_hi_schedule(&ah->beacontq);
2306
2307
2308
2309
2310
2311
2312
2313
2314 if (status & AR5K_INT_RXEOL)
2315 ah->stats.rxeol_intr++;
2316
2317
2318
2319 if (status & AR5K_INT_TXURN)
2320 ath5k_hw_update_tx_triglevel(ah, true);
2321
2322
2323 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2324 ath5k_schedule_rx(ah);
2325
2326
2327 if (status & (AR5K_INT_TXOK
2328 | AR5K_INT_TXDESC
2329 | AR5K_INT_TXERR
2330 | AR5K_INT_TXEOL))
2331 ath5k_schedule_tx(ah);
2332
2333
2334
2335
2336
2337
2338 if (status & AR5K_INT_MIB) {
2339 ah->stats.mib_intr++;
2340 ath5k_hw_update_mib_counters(ah);
2341 ath5k_ani_mib_intr(ah);
2342 }
2343
2344
2345 if (status & AR5K_INT_GPIO)
2346 tasklet_schedule(&ah->rf_kill.toggleq);
2347
2348 }
2349
2350 if (ath5k_get_bus_type(ah) == ATH_AHB)
2351 break;
2352
2353 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
2354
2355
2356
2357
2358
2359
2360
2361 if (ah->rx_pending || ah->tx_pending)
2362 ath5k_set_current_imask(ah);
2363
2364 if (unlikely(!counter))
2365 ATH5K_WARN(ah, "too many interrupts, giving up for now\n");
2366
2367
2368 ath5k_intr_calibration_poll(ah);
2369
2370 return IRQ_HANDLED;
2371}
2372
2373
2374
2375
2376
2377static void
2378ath5k_calibrate_work(struct work_struct *work)
2379{
2380 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
2381 calib_work);
2382
2383
2384 if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
2385
2386 ah->ah_cal_next_full = jiffies +
2387 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2388 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
2389
2390 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE,
2391 "running full calibration\n");
2392
2393 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2394
2395
2396
2397
2398 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2399 "got new rfgain, resetting\n");
2400 ieee80211_queue_work(ah->hw, &ah->reset_work);
2401 }
2402 } else
2403 ah->ah_cal_mask |= AR5K_CALIBRATION_SHORT;
2404
2405
2406 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2407 ieee80211_frequency_to_channel(ah->curchan->center_freq),
2408 ah->curchan->hw_value);
2409
2410 if (ath5k_hw_phy_calibrate(ah, ah->curchan))
2411 ATH5K_ERR(ah, "calibration of channel %u failed\n",
2412 ieee80211_frequency_to_channel(
2413 ah->curchan->center_freq));
2414
2415
2416 if (ah->ah_cal_mask & AR5K_CALIBRATION_FULL)
2417 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
2418 else if (ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)
2419 ah->ah_cal_mask &= ~AR5K_CALIBRATION_SHORT;
2420}
2421
2422
2423static void
2424ath5k_tasklet_ani(unsigned long data)
2425{
2426 struct ath5k_hw *ah = (void *)data;
2427
2428 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2429 ath5k_ani_calibration(ah);
2430 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
2431}
2432
2433
2434static void
2435ath5k_tx_complete_poll_work(struct work_struct *work)
2436{
2437 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
2438 tx_complete_work.work);
2439 struct ath5k_txq *txq;
2440 int i;
2441 bool needreset = false;
2442
2443 if (!test_bit(ATH_STAT_STARTED, ah->status))
2444 return;
2445
2446 mutex_lock(&ah->lock);
2447
2448 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
2449 if (ah->txqs[i].setup) {
2450 txq = &ah->txqs[i];
2451 spin_lock_bh(&txq->lock);
2452 if (txq->txq_len > 1) {
2453 if (txq->txq_poll_mark) {
2454 ATH5K_DBG(ah, ATH5K_DEBUG_XMIT,
2455 "TX queue stuck %d\n",
2456 txq->qnum);
2457 needreset = true;
2458 txq->txq_stuck++;
2459 spin_unlock_bh(&txq->lock);
2460 break;
2461 } else {
2462 txq->txq_poll_mark = true;
2463 }
2464 }
2465 spin_unlock_bh(&txq->lock);
2466 }
2467 }
2468
2469 if (needreset) {
2470 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2471 "TX queues stuck, resetting\n");
2472 ath5k_reset(ah, NULL, true);
2473 }
2474
2475 mutex_unlock(&ah->lock);
2476
2477 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work,
2478 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2479}
2480
2481
2482
2483
2484
2485
2486static const struct ieee80211_iface_limit if_limits[] = {
2487 { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) },
2488 { .max = 4, .types =
2489#ifdef CONFIG_MAC80211_MESH
2490 BIT(NL80211_IFTYPE_MESH_POINT) |
2491#endif
2492 BIT(NL80211_IFTYPE_AP) },
2493};
2494
2495static const struct ieee80211_iface_combination if_comb = {
2496 .limits = if_limits,
2497 .n_limits = ARRAY_SIZE(if_limits),
2498 .max_interfaces = 2048,
2499 .num_different_channels = 1,
2500};
2501
2502int
2503ath5k_init_ah(struct ath5k_hw *ah, const struct ath_bus_ops *bus_ops)
2504{
2505 struct ieee80211_hw *hw = ah->hw;
2506 struct ath_common *common;
2507 int ret;
2508 int csz;
2509
2510
2511 SET_IEEE80211_DEV(hw, ah->dev);
2512 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
2513 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2514 IEEE80211_HW_SIGNAL_DBM |
2515 IEEE80211_HW_MFP_CAPABLE |
2516 IEEE80211_HW_REPORTS_TX_ACK_STATUS |
2517 IEEE80211_HW_SUPPORTS_RC_TABLE;
2518
2519 hw->wiphy->interface_modes =
2520 BIT(NL80211_IFTYPE_AP) |
2521 BIT(NL80211_IFTYPE_STATION) |
2522 BIT(NL80211_IFTYPE_ADHOC) |
2523 BIT(NL80211_IFTYPE_MESH_POINT);
2524
2525 hw->wiphy->iface_combinations = &if_comb;
2526 hw->wiphy->n_iface_combinations = 1;
2527
2528
2529 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
2530
2531 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ;
2532
2533
2534 hw->wiphy->available_antennas_tx = 0x3;
2535 hw->wiphy->available_antennas_rx = 0x3;
2536
2537 hw->extra_tx_headroom = 2;
2538
2539
2540
2541
2542
2543 __set_bit(ATH_STAT_INVALID, ah->status);
2544
2545 ah->opmode = NL80211_IFTYPE_STATION;
2546 ah->bintval = 1000;
2547 mutex_init(&ah->lock);
2548 spin_lock_init(&ah->rxbuflock);
2549 spin_lock_init(&ah->txbuflock);
2550 spin_lock_init(&ah->block);
2551 spin_lock_init(&ah->irqlock);
2552
2553
2554 ret = request_irq(ah->irq, ath5k_intr, IRQF_SHARED, "ath", ah);
2555 if (ret) {
2556 ATH5K_ERR(ah, "request_irq failed\n");
2557 goto err;
2558 }
2559
2560 common = ath5k_hw_common(ah);
2561 common->ops = &ath5k_common_ops;
2562 common->bus_ops = bus_ops;
2563 common->ah = ah;
2564 common->hw = hw;
2565 common->priv = ah;
2566 common->clockrate = 40;
2567
2568
2569
2570
2571
2572 ath5k_read_cachesize(common, &csz);
2573 common->cachelsz = csz << 2;
2574
2575 spin_lock_init(&common->cc_lock);
2576
2577
2578 ret = ath5k_hw_init(ah);
2579 if (ret)
2580 goto err_irq;
2581
2582
2583 if (ah->ah_capabilities.cap_has_mrr_support) {
2584 hw->max_rates = 4;
2585 hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT,
2586 AR5K_INIT_RETRY_LONG);
2587 }
2588
2589 hw->vif_data_size = sizeof(struct ath5k_vif);
2590
2591
2592 ret = ath5k_init(hw);
2593 if (ret)
2594 goto err_ah;
2595
2596 ATH5K_INFO(ah, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
2597 ath5k_chip_name(AR5K_VERSION_MAC, ah->ah_mac_srev),
2598 ah->ah_mac_srev,
2599 ah->ah_phy_revision);
2600
2601 if (!ah->ah_single_chip) {
2602
2603 if (ah->ah_radio_5ghz_revision &&
2604 !ah->ah_radio_2ghz_revision) {
2605
2606 if (!test_bit(AR5K_MODE_11A,
2607 ah->ah_capabilities.cap_mode)) {
2608 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n",
2609 ath5k_chip_name(AR5K_VERSION_RAD,
2610 ah->ah_radio_5ghz_revision),
2611 ah->ah_radio_5ghz_revision);
2612
2613
2614 } else if (!test_bit(AR5K_MODE_11B,
2615 ah->ah_capabilities.cap_mode)) {
2616 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n",
2617 ath5k_chip_name(AR5K_VERSION_RAD,
2618 ah->ah_radio_5ghz_revision),
2619 ah->ah_radio_5ghz_revision);
2620
2621 } else {
2622 ATH5K_INFO(ah, "RF%s multiband radio found"
2623 " (0x%x)\n",
2624 ath5k_chip_name(AR5K_VERSION_RAD,
2625 ah->ah_radio_5ghz_revision),
2626 ah->ah_radio_5ghz_revision);
2627 }
2628 }
2629
2630
2631 else if (ah->ah_radio_5ghz_revision &&
2632 ah->ah_radio_2ghz_revision) {
2633 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n",
2634 ath5k_chip_name(AR5K_VERSION_RAD,
2635 ah->ah_radio_5ghz_revision),
2636 ah->ah_radio_5ghz_revision);
2637 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n",
2638 ath5k_chip_name(AR5K_VERSION_RAD,
2639 ah->ah_radio_2ghz_revision),
2640 ah->ah_radio_2ghz_revision);
2641 }
2642 }
2643
2644 ath5k_debug_init_device(ah);
2645
2646
2647 __clear_bit(ATH_STAT_INVALID, ah->status);
2648
2649 return 0;
2650err_ah:
2651 ath5k_hw_deinit(ah);
2652err_irq:
2653 free_irq(ah->irq, ah);
2654err:
2655 return ret;
2656}
2657
2658static int
2659ath5k_stop_locked(struct ath5k_hw *ah)
2660{
2661
2662 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "invalid %u\n",
2663 test_bit(ATH_STAT_INVALID, ah->status));
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680 ieee80211_stop_queues(ah->hw);
2681
2682 if (!test_bit(ATH_STAT_INVALID, ah->status)) {
2683 ath5k_led_off(ah);
2684 ath5k_hw_set_imr(ah, 0);
2685 synchronize_irq(ah->irq);
2686 ath5k_rx_stop(ah);
2687 ath5k_hw_dma_stop(ah);
2688 ath5k_drain_tx_buffs(ah);
2689 ath5k_hw_phy_disable(ah);
2690 }
2691
2692 return 0;
2693}
2694
2695int ath5k_start(struct ieee80211_hw *hw)
2696{
2697 struct ath5k_hw *ah = hw->priv;
2698 struct ath_common *common = ath5k_hw_common(ah);
2699 int ret, i;
2700
2701 mutex_lock(&ah->lock);
2702
2703 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "mode %d\n", ah->opmode);
2704
2705
2706
2707
2708
2709 ath5k_stop_locked(ah);
2710
2711
2712
2713
2714
2715
2716
2717
2718 ah->curchan = ah->hw->conf.chandef.chan;
2719 ah->imask = AR5K_INT_RXOK
2720 | AR5K_INT_RXERR
2721 | AR5K_INT_RXEOL
2722 | AR5K_INT_RXORN
2723 | AR5K_INT_TXDESC
2724 | AR5K_INT_TXEOL
2725 | AR5K_INT_FATAL
2726 | AR5K_INT_GLOBAL
2727 | AR5K_INT_MIB;
2728
2729 ret = ath5k_reset(ah, NULL, false);
2730 if (ret)
2731 goto done;
2732
2733 if (!ath5k_modparam_no_hw_rfkill_switch)
2734 ath5k_rfkill_hw_start(ah);
2735
2736
2737
2738
2739
2740 for (i = 0; i < common->keymax; i++)
2741 ath_hw_keyreset(common, (u16) i);
2742
2743
2744
2745 ah->ah_ack_bitrate_high = true;
2746
2747 for (i = 0; i < ARRAY_SIZE(ah->bslot); i++)
2748 ah->bslot[i] = NULL;
2749
2750 ret = 0;
2751done:
2752 mmiowb();
2753 mutex_unlock(&ah->lock);
2754
2755 set_bit(ATH_STAT_STARTED, ah->status);
2756 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work,
2757 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2758
2759 return ret;
2760}
2761
2762static void ath5k_stop_tasklets(struct ath5k_hw *ah)
2763{
2764 ah->rx_pending = false;
2765 ah->tx_pending = false;
2766 tasklet_kill(&ah->rxtq);
2767 tasklet_kill(&ah->txtq);
2768 tasklet_kill(&ah->beacontq);
2769 tasklet_kill(&ah->ani_tasklet);
2770}
2771
2772
2773
2774
2775
2776
2777
2778void ath5k_stop(struct ieee80211_hw *hw)
2779{
2780 struct ath5k_hw *ah = hw->priv;
2781 int ret;
2782
2783 mutex_lock(&ah->lock);
2784 ret = ath5k_stop_locked(ah);
2785 if (ret == 0 && !test_bit(ATH_STAT_INVALID, ah->status)) {
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806 ret = ath5k_hw_on_hold(ah);
2807
2808 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2809 "putting device to sleep\n");
2810 }
2811
2812 mmiowb();
2813 mutex_unlock(&ah->lock);
2814
2815 ath5k_stop_tasklets(ah);
2816
2817 clear_bit(ATH_STAT_STARTED, ah->status);
2818 cancel_delayed_work_sync(&ah->tx_complete_work);
2819
2820 if (!ath5k_modparam_no_hw_rfkill_switch)
2821 ath5k_rfkill_hw_stop(ah);
2822}
2823
2824
2825
2826
2827
2828
2829
2830static int
2831ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
2832 bool skip_pcu)
2833{
2834 struct ath_common *common = ath5k_hw_common(ah);
2835 int ret, ani_mode;
2836 bool fast;
2837
2838 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "resetting\n");
2839
2840 ath5k_hw_set_imr(ah, 0);
2841 synchronize_irq(ah->irq);
2842 ath5k_stop_tasklets(ah);
2843
2844
2845
2846
2847 ani_mode = ah->ani_state.ani_mode;
2848 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF);
2849
2850
2851
2852
2853 ath5k_drain_tx_buffs(ah);
2854 if (chan)
2855 ah->curchan = chan;
2856
2857 fast = ((chan != NULL) && modparam_fastchanswitch) ? 1 : 0;
2858
2859 ret = ath5k_hw_reset(ah, ah->opmode, ah->curchan, fast, skip_pcu);
2860 if (ret) {
2861 ATH5K_ERR(ah, "can't reset hardware (%d)\n", ret);
2862 goto err;
2863 }
2864
2865 ret = ath5k_rx_start(ah);
2866 if (ret) {
2867 ATH5K_ERR(ah, "can't start recv logic\n");
2868 goto err;
2869 }
2870
2871 ath5k_ani_init(ah, ani_mode);
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884 ah->ah_cal_next_full = jiffies +
2885 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2886 ah->ah_cal_next_ani = jiffies +
2887 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2888 ah->ah_cal_next_short = jiffies +
2889 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT);
2890
2891 ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8);
2892
2893
2894 memset(&ah->survey, 0, sizeof(ah->survey));
2895 spin_lock_bh(&common->cc_lock);
2896 ath_hw_cycle_counters_update(common);
2897 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
2898 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
2899 spin_unlock_bh(&common->cc_lock);
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912 ath5k_beacon_config(ah);
2913
2914
2915 ieee80211_wake_queues(ah->hw);
2916
2917 return 0;
2918err:
2919 return ret;
2920}
2921
2922static void ath5k_reset_work(struct work_struct *work)
2923{
2924 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
2925 reset_work);
2926
2927 mutex_lock(&ah->lock);
2928 ath5k_reset(ah, NULL, true);
2929 mutex_unlock(&ah->lock);
2930}
2931
2932static int
2933ath5k_init(struct ieee80211_hw *hw)
2934{
2935
2936 struct ath5k_hw *ah = hw->priv;
2937 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
2938 struct ath5k_txq *txq;
2939 u8 mac[ETH_ALEN] = {};
2940 int ret;
2941
2942
2943
2944
2945
2946
2947
2948
2949 ret = ath5k_setup_bands(hw);
2950 if (ret) {
2951 ATH5K_ERR(ah, "can't get channels\n");
2952 goto err;
2953 }
2954
2955
2956
2957
2958 ret = ath5k_desc_alloc(ah);
2959 if (ret) {
2960 ATH5K_ERR(ah, "can't allocate descriptors\n");
2961 goto err;
2962 }
2963
2964
2965
2966
2967
2968
2969
2970 ret = ath5k_beaconq_setup(ah);
2971 if (ret < 0) {
2972 ATH5K_ERR(ah, "can't setup a beacon xmit queue\n");
2973 goto err_desc;
2974 }
2975 ah->bhalq = ret;
2976 ah->cabq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_CAB, 0);
2977 if (IS_ERR(ah->cabq)) {
2978 ATH5K_ERR(ah, "can't setup cab queue\n");
2979 ret = PTR_ERR(ah->cabq);
2980 goto err_bhal;
2981 }
2982
2983
2984
2985 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) {
2986
2987
2988 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
2989 if (IS_ERR(txq)) {
2990 ATH5K_ERR(ah, "can't setup xmit queue\n");
2991 ret = PTR_ERR(txq);
2992 goto err_queues;
2993 }
2994 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
2995 if (IS_ERR(txq)) {
2996 ATH5K_ERR(ah, "can't setup xmit queue\n");
2997 ret = PTR_ERR(txq);
2998 goto err_queues;
2999 }
3000 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
3001 if (IS_ERR(txq)) {
3002 ATH5K_ERR(ah, "can't setup xmit queue\n");
3003 ret = PTR_ERR(txq);
3004 goto err_queues;
3005 }
3006 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
3007 if (IS_ERR(txq)) {
3008 ATH5K_ERR(ah, "can't setup xmit queue\n");
3009 ret = PTR_ERR(txq);
3010 goto err_queues;
3011 }
3012 hw->queues = 4;
3013 } else {
3014
3015 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
3016 if (IS_ERR(txq)) {
3017 ATH5K_ERR(ah, "can't setup xmit queue\n");
3018 ret = PTR_ERR(txq);
3019 goto err_queues;
3020 }
3021 hw->queues = 1;
3022 }
3023
3024 tasklet_init(&ah->rxtq, ath5k_tasklet_rx, (unsigned long)ah);
3025 tasklet_init(&ah->txtq, ath5k_tasklet_tx, (unsigned long)ah);
3026 tasklet_init(&ah->beacontq, ath5k_tasklet_beacon, (unsigned long)ah);
3027 tasklet_init(&ah->ani_tasklet, ath5k_tasklet_ani, (unsigned long)ah);
3028
3029 INIT_WORK(&ah->reset_work, ath5k_reset_work);
3030 INIT_WORK(&ah->calib_work, ath5k_calibrate_work);
3031 INIT_DELAYED_WORK(&ah->tx_complete_work, ath5k_tx_complete_poll_work);
3032
3033 ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac);
3034 if (ret) {
3035 ATH5K_ERR(ah, "unable to read address from EEPROM\n");
3036 goto err_queues;
3037 }
3038
3039 SET_IEEE80211_PERM_ADDR(hw, mac);
3040
3041 ath5k_update_bssid_mask_and_opmode(ah, NULL);
3042
3043 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
3044 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
3045 if (ret) {
3046 ATH5K_ERR(ah, "can't initialize regulatory system\n");
3047 goto err_queues;
3048 }
3049
3050 ret = ieee80211_register_hw(hw);
3051 if (ret) {
3052 ATH5K_ERR(ah, "can't register ieee80211 hw\n");
3053 goto err_queues;
3054 }
3055
3056 if (!ath_is_world_regd(regulatory))
3057 regulatory_hint(hw->wiphy, regulatory->alpha2);
3058
3059 ath5k_init_leds(ah);
3060
3061 ath5k_sysfs_register(ah);
3062
3063 return 0;
3064err_queues:
3065 ath5k_txq_release(ah);
3066err_bhal:
3067 ath5k_hw_release_tx_queue(ah, ah->bhalq);
3068err_desc:
3069 ath5k_desc_free(ah);
3070err:
3071 return ret;
3072}
3073
3074void
3075ath5k_deinit_ah(struct ath5k_hw *ah)
3076{
3077 struct ieee80211_hw *hw = ah->hw;
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092 ieee80211_unregister_hw(hw);
3093 ath5k_desc_free(ah);
3094 ath5k_txq_release(ah);
3095 ath5k_hw_release_tx_queue(ah, ah->bhalq);
3096 ath5k_unregister_leds(ah);
3097
3098 ath5k_sysfs_unregister(ah);
3099
3100
3101
3102
3103
3104 ath5k_hw_deinit(ah);
3105 free_irq(ah->irq, ah);
3106}
3107
3108bool
3109ath5k_any_vif_assoc(struct ath5k_hw *ah)
3110{
3111 struct ath5k_vif_iter_data iter_data;
3112 iter_data.hw_macaddr = NULL;
3113 iter_data.any_assoc = false;
3114 iter_data.need_set_hw_addr = false;
3115 iter_data.found_active = true;
3116
3117 ieee80211_iterate_active_interfaces_atomic(
3118 ah->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
3119 ath5k_vif_iter, &iter_data);
3120 return iter_data.any_assoc;
3121}
3122
3123void
3124ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3125{
3126 struct ath5k_hw *ah = hw->priv;
3127 u32 rfilt;
3128 rfilt = ath5k_hw_get_rx_filter(ah);
3129 if (enable)
3130 rfilt |= AR5K_RX_FILTER_BEACON;
3131 else
3132 rfilt &= ~AR5K_RX_FILTER_BEACON;
3133 ath5k_hw_set_rx_filter(ah, rfilt);
3134 ah->filter_flags = rfilt;
3135}
3136
3137void _ath5k_printk(const struct ath5k_hw *ah, const char *level,
3138 const char *fmt, ...)
3139{
3140 struct va_format vaf;
3141 va_list args;
3142
3143 va_start(args, fmt);
3144
3145 vaf.fmt = fmt;
3146 vaf.va = &args;
3147
3148 if (ah && ah->hw)
3149 printk("%s" pr_fmt("%s: %pV"),
3150 level, wiphy_name(ah->hw->wiphy), &vaf);
3151 else
3152 printk("%s" pr_fmt("%pV"), level, &vaf);
3153
3154 va_end(args);
3155}
3156