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26#ifndef __il_core_h__
27#define __il_core_h__
28
29#include <linux/interrupt.h>
30#include <linux/pci.h>
31#include <linux/kernel.h>
32#include <linux/leds.h>
33#include <linux/wait.h>
34#include <linux/io.h>
35#include <net/mac80211.h>
36#include <net/ieee80211_radiotap.h>
37
38#include "commands.h"
39#include "csr.h"
40#include "prph.h"
41
42struct il_host_cmd;
43struct il_cmd;
44struct il_tx_queue;
45
46#define IL_ERR(f, a...) dev_err(&il->pci_dev->dev, f, ## a)
47#define IL_WARN(f, a...) dev_warn(&il->pci_dev->dev, f, ## a)
48#define IL_INFO(f, a...) dev_info(&il->pci_dev->dev, f, ## a)
49
50#define RX_QUEUE_SIZE 256
51#define RX_QUEUE_MASK 255
52#define RX_QUEUE_SIZE_LOG 8
53
54
55
56
57#define RX_FREE_BUFFERS 64
58#define RX_LOW_WATERMARK 8
59
60#define U32_PAD(n) ((4-(n))&0x3)
61
62
63#define CT_KILL_THRESHOLD_LEGACY 110
64
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74
75
76#define IL_NOISE_MEAS_NOT_AVAILABLE (-127)
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84
85
86#define DEFAULT_RTS_THRESHOLD 2347U
87#define MIN_RTS_THRESHOLD 0U
88#define MAX_RTS_THRESHOLD 2347U
89#define MAX_MSDU_SIZE 2304U
90#define MAX_MPDU_SIZE 2346U
91#define DEFAULT_BEACON_INTERVAL 100U
92#define DEFAULT_SHORT_RETRY_LIMIT 7U
93#define DEFAULT_LONG_RETRY_LIMIT 4U
94
95struct il_rx_buf {
96 dma_addr_t page_dma;
97 struct page *page;
98 struct list_head list;
99};
100
101#define rxb_addr(r) page_address(r->page)
102
103
104struct il_device_cmd;
105
106struct il_cmd_meta {
107
108 struct il_host_cmd *source;
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116 void (*callback) (struct il_priv *il, struct il_device_cmd *cmd,
117 struct il_rx_pkt *pkt);
118
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120
121 u32 flags;
122
123 DEFINE_DMA_UNMAP_ADDR(mapping);
124 DEFINE_DMA_UNMAP_LEN(len);
125};
126
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131
132struct il_queue {
133 int n_bd;
134 int write_ptr;
135 int read_ptr;
136
137 dma_addr_t dma_addr;
138 int n_win;
139 u32 id;
140 int low_mark;
141
142 int high_mark;
143
144};
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160
161#define TFD_TX_CMD_SLOTS 256
162#define TFD_CMD_SLOTS 32
163
164struct il_tx_queue {
165 struct il_queue q;
166 void *tfds;
167 struct il_device_cmd **cmd;
168 struct il_cmd_meta *meta;
169 struct sk_buff **skbs;
170 unsigned long time_stamp;
171 u8 need_update;
172 u8 sched_retry;
173 u8 active;
174 u8 swq_id;
175};
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184
185#define IL_EEPROM_ACCESS_TIMEOUT 5000
186
187#define IL_EEPROM_SEM_TIMEOUT 10
188#define IL_EEPROM_SEM_RETRY_LIMIT 1000
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205
206#define IL_NUM_TX_CALIB_GROUPS 5
207enum {
208 EEPROM_CHANNEL_VALID = (1 << 0),
209 EEPROM_CHANNEL_IBSS = (1 << 1),
210
211 EEPROM_CHANNEL_ACTIVE = (1 << 3),
212 EEPROM_CHANNEL_RADAR = (1 << 4),
213 EEPROM_CHANNEL_WIDE = (1 << 5),
214
215 EEPROM_CHANNEL_DFS = (1 << 7),
216};
217
218
219
220#define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE (1 << 0)
221#define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE (1 << 1)
222
223
224
225struct il_eeprom_channel {
226 u8 flags;
227 s8 max_power_avg;
228} __packed;
229
230
231#define EEPROM_3945_EEPROM_VERSION (0x2f)
232
233
234#define EEPROM_TX_POWER_TX_CHAINS (2)
235
236
237#define EEPROM_TX_POWER_BANDS (8)
238
239
240
241#define EEPROM_TX_POWER_MEASUREMENTS (3)
242
243
244
245#define EEPROM_4965_TX_POWER_VERSION (5)
246#define EEPROM_4965_EEPROM_VERSION (0x2f)
247#define EEPROM_4965_CALIB_VERSION_OFFSET (2*0xB6)
248#define EEPROM_4965_CALIB_TXPOWER_OFFSET (2*0xE8)
249#define EEPROM_4965_BOARD_REVISION (2*0x4F)
250#define EEPROM_4965_BOARD_PBA (2*0x56+1)
251
252
253extern const u8 il_eeprom_band_1[14];
254
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268
269struct il_eeprom_calib_measure {
270 u8 temperature;
271 u8 gain_idx;
272 u8 actual_pow;
273 s8 pa_det;
274} __packed;
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283
284struct il_eeprom_calib_ch_info {
285 u8 ch_num;
286 struct il_eeprom_calib_measure
287 measurements[EEPROM_TX_POWER_TX_CHAINS]
288 [EEPROM_TX_POWER_MEASUREMENTS];
289} __packed;
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301struct il_eeprom_calib_subband_info {
302 u8 ch_from;
303 u8 ch_to;
304 struct il_eeprom_calib_ch_info ch1;
305 struct il_eeprom_calib_ch_info ch2;
306} __packed;
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328struct il_eeprom_calib_info {
329 u8 saturation_power24;
330 u8 saturation_power52;
331 __le16 voltage;
332 struct il_eeprom_calib_subband_info band_info[EEPROM_TX_POWER_BANDS];
333} __packed;
334
335
336#define EEPROM_DEVICE_ID (2*0x08)
337#define EEPROM_MAC_ADDRESS (2*0x15)
338#define EEPROM_BOARD_REVISION (2*0x35)
339#define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1)
340#define EEPROM_VERSION (2*0x44)
341#define EEPROM_SKU_CAP (2*0x45)
342#define EEPROM_OEM_MODE (2*0x46)
343#define EEPROM_WOWLAN_MODE (2*0x47)
344#define EEPROM_RADIO_CONFIG (2*0x48)
345#define EEPROM_NUM_MAC_ADDRESS (2*0x4C)
346
347
348#define EEPROM_RF_CFG_TYPE_MSK(x) (x & 0x3)
349#define EEPROM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3)
350#define EEPROM_RF_CFG_DASH_MSK(x) ((x >> 4) & 0x3)
351#define EEPROM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3)
352#define EEPROM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF)
353#define EEPROM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF)
354
355#define EEPROM_3945_RF_CFG_TYPE_MAX 0x0
356#define EEPROM_4965_RF_CFG_TYPE_MAX 0x1
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369
370#define EEPROM_REGULATORY_SKU_ID (2*0x60)
371#define EEPROM_REGULATORY_BAND_1 (2*0x62)
372#define EEPROM_REGULATORY_BAND_1_CHANNELS (2*0x63)
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379#define EEPROM_REGULATORY_BAND_2 (2*0x71)
380#define EEPROM_REGULATORY_BAND_2_CHANNELS (2*0x72)
381
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386#define EEPROM_REGULATORY_BAND_3 (2*0x7F)
387#define EEPROM_REGULATORY_BAND_3_CHANNELS (2*0x80)
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393#define EEPROM_REGULATORY_BAND_4 (2*0x8C)
394#define EEPROM_REGULATORY_BAND_4_CHANNELS (2*0x8D)
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400#define EEPROM_REGULATORY_BAND_5 (2*0x98)
401#define EEPROM_REGULATORY_BAND_5_CHANNELS (2*0x99)
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418#define EEPROM_4965_REGULATORY_BAND_24_HT40_CHANNELS (2*0xA0)
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424#define EEPROM_4965_REGULATORY_BAND_52_HT40_CHANNELS (2*0xA8)
425
426#define EEPROM_REGULATORY_BAND_NO_HT40 (0)
427
428int il_eeprom_init(struct il_priv *il);
429void il_eeprom_free(struct il_priv *il);
430const u8 *il_eeprom_query_addr(const struct il_priv *il, size_t offset);
431u16 il_eeprom_query16(const struct il_priv *il, size_t offset);
432int il_init_channel_map(struct il_priv *il);
433void il_free_channel_map(struct il_priv *il);
434const struct il_channel_info *il_get_channel_info(const struct il_priv *il,
435 enum ieee80211_band band,
436 u16 channel);
437
438#define IL_NUM_SCAN_RATES (2)
439
440struct il4965_channel_tgd_info {
441 u8 type;
442 s8 max_power;
443};
444
445struct il4965_channel_tgh_info {
446 s64 last_radar_time;
447};
448
449#define IL4965_MAX_RATE (33)
450
451struct il3945_clip_group {
452
453
454 const s8 clip_powers[IL_MAX_RATES];
455};
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464struct il3945_channel_power_info {
465 struct il3945_tx_power tpc;
466 s8 power_table_idx;
467 s8 base_power_idx;
468 s8 requested_power;
469};
470
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473struct il3945_scan_power_info {
474 struct il3945_tx_power tpc;
475 s8 power_table_idx;
476 s8 requested_power;
477};
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484struct il_channel_info {
485 struct il4965_channel_tgd_info tgd;
486 struct il4965_channel_tgh_info tgh;
487 struct il_eeprom_channel eeprom;
488 struct il_eeprom_channel ht40_eeprom;
489
490
491 u8 channel;
492 u8 flags;
493 s8 max_power_avg;
494 s8 curr_txpow;
495 s8 min_power;
496 s8 scan_power;
497
498 u8 group_idx;
499 u8 band_idx;
500 enum ieee80211_band band;
501
502
503 s8 ht40_max_power_avg;
504 u8 ht40_flags;
505 u8 ht40_extension_channel;
506
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510 struct il3945_channel_power_info power_info[IL4965_MAX_RATE];
511
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513 struct il3945_scan_power_info scan_pwr_info[IL_NUM_SCAN_RATES];
514};
515
516#define IL_TX_FIFO_BK 0
517#define IL_TX_FIFO_BE 1
518#define IL_TX_FIFO_VI 2
519#define IL_TX_FIFO_VO 3
520#define IL_TX_FIFO_UNUSED -1
521
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524
525#define IL_MIN_NUM_QUEUES 10
526
527#define IL_DEFAULT_CMD_QUEUE_NUM 4
528
529#define IEEE80211_DATA_LEN 2304
530#define IEEE80211_4ADDR_LEN 30
531#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
532#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
533
534struct il_frame {
535 union {
536 struct ieee80211_hdr frame;
537 struct il_tx_beacon_cmd beacon;
538 u8 raw[IEEE80211_FRAME_LEN];
539 u8 cmd[360];
540 } u;
541 struct list_head list;
542};
543
544enum {
545 CMD_SYNC = 0,
546 CMD_SIZE_NORMAL = 0,
547 CMD_NO_SKB = 0,
548 CMD_SIZE_HUGE = (1 << 0),
549 CMD_ASYNC = (1 << 1),
550 CMD_WANT_SKB = (1 << 2),
551 CMD_MAPPED = (1 << 3),
552};
553
554#define DEF_CMD_PAYLOAD_SIZE 320
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563struct il_device_cmd {
564 struct il_cmd_header hdr;
565 union {
566 u32 flags;
567 u8 val8;
568 u16 val16;
569 u32 val32;
570 struct il_tx_cmd tx;
571 u8 payload[DEF_CMD_PAYLOAD_SIZE];
572 } __packed cmd;
573} __packed;
574
575#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct il_device_cmd))
576
577struct il_host_cmd {
578 const void *data;
579 unsigned long reply_page;
580 void (*callback) (struct il_priv *il, struct il_device_cmd *cmd,
581 struct il_rx_pkt *pkt);
582 u32 flags;
583 u16 len;
584 u8 id;
585};
586
587#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
588#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
589#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
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606struct il_rx_queue {
607 __le32 *bd;
608 dma_addr_t bd_dma;
609 struct il_rx_buf pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
610 struct il_rx_buf *queue[RX_QUEUE_SIZE];
611 u32 read;
612 u32 write;
613 u32 free_count;
614 u32 write_actual;
615 struct list_head rx_free;
616 struct list_head rx_used;
617 int need_update;
618 struct il_rb_status *rb_stts;
619 dma_addr_t rb_stts_dma;
620 spinlock_t lock;
621};
622
623#define IL_SUPPORTED_RATES_IE_LEN 8
624
625#define MAX_TID_COUNT 9
626
627#define IL_INVALID_RATE 0xFF
628#define IL_INVALID_VALUE -1
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644struct il_ht_agg {
645 u16 txq_id;
646 u16 frame_count;
647 u16 wait_for_ba;
648 u16 start_idx;
649 u64 bitmap;
650 u32 rate_n_flags;
651#define IL_AGG_OFF 0
652#define IL_AGG_ON 1
653#define IL_EMPTYING_HW_QUEUE_ADDBA 2
654#define IL_EMPTYING_HW_QUEUE_DELBA 3
655 u8 state;
656};
657
658struct il_tid_data {
659 u16 seq_number;
660 u16 tfds_in_queue;
661 struct il_ht_agg agg;
662};
663
664struct il_hw_key {
665 u32 cipher;
666 int keylen;
667 u8 keyidx;
668 u8 key[32];
669};
670
671union il_ht_rate_supp {
672 u16 rates;
673 struct {
674 u8 siso_rate;
675 u8 mimo_rate;
676 };
677};
678
679#define CFG_HT_RX_AMPDU_FACTOR_8K (0x0)
680#define CFG_HT_RX_AMPDU_FACTOR_16K (0x1)
681#define CFG_HT_RX_AMPDU_FACTOR_32K (0x2)
682#define CFG_HT_RX_AMPDU_FACTOR_64K (0x3)
683#define CFG_HT_RX_AMPDU_FACTOR_DEF CFG_HT_RX_AMPDU_FACTOR_64K
684#define CFG_HT_RX_AMPDU_FACTOR_MAX CFG_HT_RX_AMPDU_FACTOR_64K
685#define CFG_HT_RX_AMPDU_FACTOR_MIN CFG_HT_RX_AMPDU_FACTOR_8K
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694#define CFG_HT_MPDU_DENSITY_2USEC (0x4)
695#define CFG_HT_MPDU_DENSITY_4USEC (0x5)
696#define CFG_HT_MPDU_DENSITY_8USEC (0x6)
697#define CFG_HT_MPDU_DENSITY_16USEC (0x7)
698#define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_4USEC
699#define CFG_HT_MPDU_DENSITY_MAX CFG_HT_MPDU_DENSITY_16USEC
700#define CFG_HT_MPDU_DENSITY_MIN (0x1)
701
702struct il_ht_config {
703 bool single_chain_sufficient;
704 enum ieee80211_smps_mode smps;
705};
706
707
708struct il_qos_info {
709 int qos_active;
710 struct il_qosparam_cmd def_qos_parm;
711};
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719struct il_station_entry {
720 struct il_addsta_cmd sta;
721 struct il_tid_data tid[MAX_TID_COUNT];
722 u8 used;
723 struct il_hw_key keyinfo;
724 struct il_link_quality_cmd *lq;
725};
726
727struct il_station_priv_common {
728 u8 sta_id;
729};
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737struct il_vif_priv {
738 u8 ibss_bssid_sta_id;
739};
740
741
742struct fw_desc {
743 void *v_addr;
744 dma_addr_t p_addr;
745 u32 len;
746};
747
748
749struct il_ucode_header {
750 __le32 ver;
751 struct {
752 __le32 inst_size;
753 __le32 data_size;
754 __le32 init_size;
755 __le32 init_data_size;
756 __le32 boot_size;
757 u8 data[0];
758 } v1;
759};
760
761struct il4965_ibss_seq {
762 u8 mac[ETH_ALEN];
763 u16 seq_num;
764 u16 frag_num;
765 unsigned long packet_time;
766 struct list_head list;
767};
768
769struct il_sensitivity_ranges {
770 u16 min_nrg_cck;
771 u16 max_nrg_cck;
772
773 u16 nrg_th_cck;
774 u16 nrg_th_ofdm;
775
776 u16 auto_corr_min_ofdm;
777 u16 auto_corr_min_ofdm_mrc;
778 u16 auto_corr_min_ofdm_x1;
779 u16 auto_corr_min_ofdm_mrc_x1;
780
781 u16 auto_corr_max_ofdm;
782 u16 auto_corr_max_ofdm_mrc;
783 u16 auto_corr_max_ofdm_x1;
784 u16 auto_corr_max_ofdm_mrc_x1;
785
786 u16 auto_corr_max_cck;
787 u16 auto_corr_max_cck_mrc;
788 u16 auto_corr_min_cck;
789 u16 auto_corr_min_cck_mrc;
790
791 u16 barker_corr_th_min;
792 u16 barker_corr_th_min_mrc;
793 u16 nrg_th_cca;
794};
795
796#define KELVIN_TO_CELSIUS(x) ((x)-273)
797#define CELSIUS_TO_KELVIN(x) ((x)+273)
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821struct il_hw_params {
822 u8 bcast_id;
823 u8 max_txq_num;
824 u8 dma_chnl_num;
825 u16 scd_bc_tbls_size;
826 u32 tfd_size;
827 u8 tx_chains_num;
828 u8 rx_chains_num;
829 u8 valid_tx_ant;
830 u8 valid_rx_ant;
831 u16 max_rxq_size;
832 u16 max_rxq_log;
833 u32 rx_page_order;
834 u32 rx_wrt_ptr_reg;
835 u8 max_stations;
836 u8 ht40_channel;
837 u8 max_beacon_itrvl;
838 u32 max_inst_size;
839 u32 max_data_size;
840 u32 max_bsm_size;
841 u32 ct_kill_threshold;
842 u16 beacon_time_tsf_bits;
843 const struct il_sensitivity_ranges *sens;
844};
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861void il4965_update_chain_flags(struct il_priv *il);
862extern const u8 il_bcast_addr[ETH_ALEN];
863int il_queue_space(const struct il_queue *q);
864static inline int
865il_queue_used(const struct il_queue *q, int i)
866{
867 return q->write_ptr >= q->read_ptr ? (i >= q->read_ptr &&
868 i < q->write_ptr) : !(i <
869 q->read_ptr
870 && i >=
871 q->
872 write_ptr);
873}
874
875static inline u8
876il_get_cmd_idx(struct il_queue *q, u32 idx, int is_huge)
877{
878
879
880
881
882
883 if (is_huge)
884 return q->n_win;
885
886
887 return idx & (q->n_win - 1);
888}
889
890struct il_dma_ptr {
891 dma_addr_t dma;
892 void *addr;
893 size_t size;
894};
895
896#define IL_OPERATION_MODE_AUTO 0
897#define IL_OPERATION_MODE_HT_ONLY 1
898#define IL_OPERATION_MODE_MIXED 2
899#define IL_OPERATION_MODE_20MHZ 3
900
901#define IL_TX_CRC_SIZE 4
902#define IL_TX_DELIMITER_SIZE 4
903
904#define TX_POWER_IL_ILLEGAL_VOLTAGE -10000
905
906
907#define INITIALIZATION_VALUE 0xFFFF
908#define IL4965_CAL_NUM_BEACONS 20
909#define IL_CAL_NUM_BEACONS 16
910#define MAXIMUM_ALLOWED_PATHLOSS 15
911
912#define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3
913
914#define MAX_FA_OFDM 50
915#define MIN_FA_OFDM 5
916#define MAX_FA_CCK 50
917#define MIN_FA_CCK 5
918
919#define AUTO_CORR_STEP_OFDM 1
920
921#define AUTO_CORR_STEP_CCK 3
922#define AUTO_CORR_MAX_TH_CCK 160
923
924#define NRG_DIFF 2
925#define NRG_STEP_CCK 2
926#define NRG_MARGIN 8
927#define MAX_NUMBER_CCK_NO_FA 100
928
929#define AUTO_CORR_CCK_MIN_VAL_DEF (125)
930
931#define CHAIN_A 0
932#define CHAIN_B 1
933#define CHAIN_C 2
934#define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4
935#define ALL_BAND_FILTER 0xFF00
936#define IN_BAND_FILTER 0xFF
937#define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF
938
939#define NRG_NUM_PREV_STAT_L 20
940#define NUM_RX_CHAINS 3
941
942enum il4965_false_alarm_state {
943 IL_FA_TOO_MANY = 0,
944 IL_FA_TOO_FEW = 1,
945 IL_FA_GOOD_RANGE = 2,
946};
947
948enum il4965_chain_noise_state {
949 IL_CHAIN_NOISE_ALIVE = 0,
950 IL_CHAIN_NOISE_ACCUMULATE,
951 IL_CHAIN_NOISE_CALIBRATED,
952 IL_CHAIN_NOISE_DONE,
953};
954
955enum ucode_type {
956 UCODE_NONE = 0,
957 UCODE_INIT,
958 UCODE_RT
959};
960
961
962struct il_sensitivity_data {
963 u32 auto_corr_ofdm;
964 u32 auto_corr_ofdm_mrc;
965 u32 auto_corr_ofdm_x1;
966 u32 auto_corr_ofdm_mrc_x1;
967 u32 auto_corr_cck;
968 u32 auto_corr_cck_mrc;
969
970 u32 last_bad_plcp_cnt_ofdm;
971 u32 last_fa_cnt_ofdm;
972 u32 last_bad_plcp_cnt_cck;
973 u32 last_fa_cnt_cck;
974
975 u32 nrg_curr_state;
976 u32 nrg_prev_state;
977 u32 nrg_value[10];
978 u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L];
979 u32 nrg_silence_ref;
980 u32 nrg_energy_idx;
981 u32 nrg_silence_idx;
982 u32 nrg_th_cck;
983 s32 nrg_auto_corr_silence_diff;
984 u32 num_in_cck_no_fa;
985 u32 nrg_th_ofdm;
986
987 u16 barker_corr_th_min;
988 u16 barker_corr_th_min_mrc;
989 u16 nrg_th_cca;
990};
991
992
993struct il_chain_noise_data {
994 u32 active_chains;
995 u32 chain_noise_a;
996 u32 chain_noise_b;
997 u32 chain_noise_c;
998 u32 chain_signal_a;
999 u32 chain_signal_b;
1000 u32 chain_signal_c;
1001 u16 beacon_count;
1002 u8 disconn_array[NUM_RX_CHAINS];
1003 u8 delta_gain_code[NUM_RX_CHAINS];
1004 u8 radio_write;
1005 u8 state;
1006};
1007
1008#define EEPROM_SEM_TIMEOUT 10
1009#define EEPROM_SEM_RETRY_LIMIT 1000
1010
1011#define IL_TRAFFIC_ENTRIES (256)
1012#define IL_TRAFFIC_ENTRY_SIZE (64)
1013
1014enum {
1015 MEASUREMENT_READY = (1 << 0),
1016 MEASUREMENT_ACTIVE = (1 << 1),
1017};
1018
1019
1020struct isr_stats {
1021 u32 hw;
1022 u32 sw;
1023 u32 err_code;
1024 u32 sch;
1025 u32 alive;
1026 u32 rfkill;
1027 u32 ctkill;
1028 u32 wakeup;
1029 u32 rx;
1030 u32 handlers[IL_CN_MAX];
1031 u32 tx;
1032 u32 unhandled;
1033};
1034
1035
1036enum il_mgmt_stats {
1037 MANAGEMENT_ASSOC_REQ = 0,
1038 MANAGEMENT_ASSOC_RESP,
1039 MANAGEMENT_REASSOC_REQ,
1040 MANAGEMENT_REASSOC_RESP,
1041 MANAGEMENT_PROBE_REQ,
1042 MANAGEMENT_PROBE_RESP,
1043 MANAGEMENT_BEACON,
1044 MANAGEMENT_ATIM,
1045 MANAGEMENT_DISASSOC,
1046 MANAGEMENT_AUTH,
1047 MANAGEMENT_DEAUTH,
1048 MANAGEMENT_ACTION,
1049 MANAGEMENT_MAX,
1050};
1051
1052enum il_ctrl_stats {
1053 CONTROL_BACK_REQ = 0,
1054 CONTROL_BACK,
1055 CONTROL_PSPOLL,
1056 CONTROL_RTS,
1057 CONTROL_CTS,
1058 CONTROL_ACK,
1059 CONTROL_CFEND,
1060 CONTROL_CFENDACK,
1061 CONTROL_MAX,
1062};
1063
1064struct traffic_stats {
1065#ifdef CONFIG_IWLEGACY_DEBUGFS
1066 u32 mgmt[MANAGEMENT_MAX];
1067 u32 ctrl[CONTROL_MAX];
1068 u32 data_cnt;
1069 u64 data_bytes;
1070#endif
1071};
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081#define IL_HOST_INT_TIMEOUT_MAX (0xFF)
1082#define IL_HOST_INT_TIMEOUT_DEF (0x40)
1083#define IL_HOST_INT_TIMEOUT_MIN (0x0)
1084#define IL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF)
1085#define IL_HOST_INT_CALIB_TIMEOUT_DEF (0x10)
1086#define IL_HOST_INT_CALIB_TIMEOUT_MIN (0x0)
1087
1088#define IL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5)
1089
1090
1091#define IL_DEF_WD_TIMEOUT (2000)
1092#define IL_LONG_WD_TIMEOUT (10000)
1093#define IL_MAX_WD_TIMEOUT (120000)
1094
1095struct il_force_reset {
1096 int reset_request_count;
1097 int reset_success_count;
1098 int reset_reject_count;
1099 unsigned long reset_duration;
1100 unsigned long last_force_reset_jiffies;
1101};
1102
1103
1104
1105
1106
1107
1108
1109#define IL3945_EXT_BEACON_TIME_POS 24
1110
1111
1112
1113
1114
1115#define IL4965_EXT_BEACON_TIME_POS 22
1116
1117struct il_rxon_context {
1118 struct ieee80211_vif *vif;
1119};
1120
1121struct il_power_mgr {
1122 struct il_powertable_cmd sleep_cmd;
1123 struct il_powertable_cmd sleep_cmd_next;
1124 int debug_sleep_level_override;
1125 bool pci_pm;
1126 bool ps_disabled;
1127};
1128
1129struct il_priv {
1130 struct ieee80211_hw *hw;
1131 struct ieee80211_channel *ieee_channels;
1132 struct ieee80211_rate *ieee_rates;
1133
1134 struct il_cfg *cfg;
1135 const struct il_ops *ops;
1136#ifdef CONFIG_IWLEGACY_DEBUGFS
1137 const struct il_debugfs_ops *debugfs_ops;
1138#endif
1139
1140
1141 struct list_head free_frames;
1142 int frames_count;
1143
1144 enum ieee80211_band band;
1145 int alloc_rxb_page;
1146
1147 void (*handlers[IL_CN_MAX]) (struct il_priv *il,
1148 struct il_rx_buf *rxb);
1149
1150 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
1151
1152
1153 struct il_spectrum_notification measure_report;
1154 u8 measurement_status;
1155
1156
1157 u32 ucode_beacon_time;
1158 int missed_beacon_threshold;
1159
1160
1161 u32 ibss_manager;
1162
1163
1164 struct il_force_reset force_reset;
1165
1166
1167
1168 struct il_channel_info *channel_info;
1169 u8 channel_count;
1170
1171
1172 s32 temperature;
1173 s32 last_temperature;
1174
1175
1176 unsigned long scan_start;
1177 unsigned long scan_start_tsf;
1178 void *scan_cmd;
1179 enum ieee80211_band scan_band;
1180 struct cfg80211_scan_request *scan_request;
1181 struct ieee80211_vif *scan_vif;
1182 u8 scan_tx_ant[IEEE80211_NUM_BANDS];
1183 u8 mgmt_tx_ant;
1184
1185
1186 spinlock_t lock;
1187 spinlock_t hcmd_lock;
1188 spinlock_t reg_lock;
1189 struct mutex mutex;
1190
1191
1192 struct pci_dev *pci_dev;
1193
1194
1195 void __iomem *hw_base;
1196 u32 hw_rev;
1197 u32 hw_wa_rev;
1198 u8 rev_id;
1199
1200
1201 u8 cmd_queue;
1202
1203
1204 u8 sta_key_max_num;
1205
1206
1207 struct mac_address addresses[1];
1208
1209
1210 int fw_idx;
1211 u32 ucode_ver;
1212
1213 struct fw_desc ucode_code;
1214 struct fw_desc ucode_data;
1215 struct fw_desc ucode_data_backup;
1216 struct fw_desc ucode_init;
1217 struct fw_desc ucode_init_data;
1218 struct fw_desc ucode_boot;
1219 enum ucode_type ucode_type;
1220 u8 ucode_write_complete;
1221 char firmware_name[25];
1222
1223 struct ieee80211_vif *vif;
1224
1225 struct il_qos_info qos_data;
1226
1227 struct {
1228 bool enabled;
1229 bool is_40mhz;
1230 bool non_gf_sta_present;
1231 u8 protection;
1232 u8 extension_chan_offset;
1233 } ht;
1234
1235
1236
1237
1238
1239
1240
1241 const struct il_rxon_cmd active;
1242 struct il_rxon_cmd staging;
1243
1244 struct il_rxon_time_cmd timing;
1245
1246 __le16 switch_channel;
1247
1248
1249
1250 struct il_init_alive_resp card_alive_init;
1251 struct il_alive_resp card_alive;
1252
1253 u16 active_rate;
1254
1255 u8 start_calib;
1256 struct il_sensitivity_data sensitivity_data;
1257 struct il_chain_noise_data chain_noise_data;
1258 __le16 sensitivity_tbl[HD_TBL_SIZE];
1259
1260 struct il_ht_config current_ht_config;
1261
1262
1263 u8 retry_rate;
1264
1265 wait_queue_head_t wait_command_queue;
1266
1267 int activity_timer_active;
1268
1269
1270 struct il_rx_queue rxq;
1271 struct il_tx_queue *txq;
1272 unsigned long txq_ctx_active_msk;
1273 struct il_dma_ptr kw;
1274 struct il_dma_ptr scd_bc_tbls;
1275
1276 u32 scd_base_addr;
1277
1278 unsigned long status;
1279
1280
1281 struct traffic_stats tx_stats;
1282 struct traffic_stats rx_stats;
1283
1284
1285 struct isr_stats isr_stats;
1286
1287 struct il_power_mgr power_data;
1288
1289
1290 u8 bssid[ETH_ALEN];
1291
1292
1293
1294
1295 spinlock_t sta_lock;
1296 int num_stations;
1297 struct il_station_entry stations[IL_STATION_COUNT];
1298 unsigned long ucode_key_table;
1299
1300
1301#define IL_MAX_HW_QUEUES 32
1302 unsigned long queue_stopped[BITS_TO_LONGS(IL_MAX_HW_QUEUES)];
1303#define IL_STOP_REASON_PASSIVE 0
1304 unsigned long stop_reason;
1305
1306 atomic_t queue_stop_count[4];
1307
1308
1309 u8 is_open;
1310
1311 u8 mac80211_registered;
1312
1313
1314 u8 *eeprom;
1315 struct il_eeprom_calib_info *calib_info;
1316
1317 enum nl80211_iftype iw_mode;
1318
1319
1320 u64 timestamp;
1321
1322 union {
1323#if defined(CONFIG_IWL3945) || defined(CONFIG_IWL3945_MODULE)
1324 struct {
1325 void *shared_virt;
1326 dma_addr_t shared_phys;
1327
1328 struct delayed_work thermal_periodic;
1329 struct delayed_work rfkill_poll;
1330
1331 struct il3945_notif_stats stats;
1332#ifdef CONFIG_IWLEGACY_DEBUGFS
1333 struct il3945_notif_stats accum_stats;
1334 struct il3945_notif_stats delta_stats;
1335 struct il3945_notif_stats max_delta;
1336#endif
1337
1338 u32 sta_supp_rates;
1339 int last_rx_rssi;
1340
1341
1342 u32 last_beacon_time;
1343 u64 last_tsf;
1344
1345
1346
1347
1348
1349
1350 const struct il3945_clip_group clip_groups[5];
1351
1352 } _3945;
1353#endif
1354#if defined(CONFIG_IWL4965) || defined(CONFIG_IWL4965_MODULE)
1355 struct {
1356 struct il_rx_phy_res last_phy_res;
1357 bool last_phy_res_valid;
1358 u32 ampdu_ref;
1359
1360 struct completion firmware_loading_complete;
1361
1362
1363
1364
1365
1366
1367 u8 phy_calib_chain_noise_reset_cmd;
1368 u8 phy_calib_chain_noise_gain_cmd;
1369
1370 u8 key_mapping_keys;
1371 struct il_wep_key wep_keys[WEP_KEYS_MAX];
1372
1373 struct il_notif_stats stats;
1374#ifdef CONFIG_IWLEGACY_DEBUGFS
1375 struct il_notif_stats accum_stats;
1376 struct il_notif_stats delta_stats;
1377 struct il_notif_stats max_delta;
1378#endif
1379
1380 } _4965;
1381#endif
1382 };
1383
1384 struct il_hw_params hw_params;
1385
1386 u32 inta_mask;
1387
1388 struct workqueue_struct *workqueue;
1389
1390 struct work_struct restart;
1391 struct work_struct scan_completed;
1392 struct work_struct rx_replenish;
1393 struct work_struct abort_scan;
1394
1395 bool beacon_enabled;
1396 struct sk_buff *beacon_skb;
1397
1398 struct work_struct tx_flush;
1399
1400 struct tasklet_struct irq_tasklet;
1401
1402 struct delayed_work init_alive_start;
1403 struct delayed_work alive_start;
1404 struct delayed_work scan_check;
1405
1406
1407 s8 tx_power_user_lmt;
1408 s8 tx_power_device_lmt;
1409 s8 tx_power_next;
1410
1411#ifdef CONFIG_IWLEGACY_DEBUG
1412
1413 u32 debug_level;
1414
1415#endif
1416#ifdef CONFIG_IWLEGACY_DEBUGFS
1417
1418 u16 tx_traffic_idx;
1419 u16 rx_traffic_idx;
1420 u8 *tx_traffic;
1421 u8 *rx_traffic;
1422 struct dentry *debugfs_dir;
1423 u32 dbgfs_sram_offset, dbgfs_sram_len;
1424 bool disable_ht40;
1425#endif
1426
1427 struct work_struct txpower_work;
1428 u32 disable_sens_cal;
1429 u32 disable_chain_noise_cal;
1430 u32 disable_tx_power_cal;
1431 struct work_struct run_time_calib_work;
1432 struct timer_list stats_periodic;
1433 struct timer_list watchdog;
1434 bool hw_ready;
1435
1436 struct led_classdev led;
1437 unsigned long blink_on, blink_off;
1438 bool led_registered;
1439};
1440
1441static inline void
1442il_txq_ctx_activate(struct il_priv *il, int txq_id)
1443{
1444 set_bit(txq_id, &il->txq_ctx_active_msk);
1445}
1446
1447static inline void
1448il_txq_ctx_deactivate(struct il_priv *il, int txq_id)
1449{
1450 clear_bit(txq_id, &il->txq_ctx_active_msk);
1451}
1452
1453static inline int
1454il_is_associated(struct il_priv *il)
1455{
1456 return (il->active.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
1457}
1458
1459static inline int
1460il_is_any_associated(struct il_priv *il)
1461{
1462 return il_is_associated(il);
1463}
1464
1465static inline int
1466il_is_channel_valid(const struct il_channel_info *ch_info)
1467{
1468 if (ch_info == NULL)
1469 return 0;
1470 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
1471}
1472
1473static inline int
1474il_is_channel_radar(const struct il_channel_info *ch_info)
1475{
1476 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
1477}
1478
1479static inline u8
1480il_is_channel_a_band(const struct il_channel_info *ch_info)
1481{
1482 return ch_info->band == IEEE80211_BAND_5GHZ;
1483}
1484
1485static inline int
1486il_is_channel_passive(const struct il_channel_info *ch)
1487{
1488 return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0;
1489}
1490
1491static inline int
1492il_is_channel_ibss(const struct il_channel_info *ch)
1493{
1494 return (ch->flags & EEPROM_CHANNEL_IBSS) ? 1 : 0;
1495}
1496
1497static inline void
1498__il_free_pages(struct il_priv *il, struct page *page)
1499{
1500 __free_pages(page, il->hw_params.rx_page_order);
1501 il->alloc_rxb_page--;
1502}
1503
1504static inline void
1505il_free_pages(struct il_priv *il, unsigned long page)
1506{
1507 free_pages(page, il->hw_params.rx_page_order);
1508 il->alloc_rxb_page--;
1509}
1510
1511#define IWLWIFI_VERSION "in-tree:"
1512#define DRV_COPYRIGHT "Copyright(c) 2003-2011 Intel Corporation"
1513#define DRV_AUTHOR "<ilw@linux.intel.com>"
1514
1515#define IL_PCI_DEVICE(dev, subdev, cfg) \
1516 .vendor = PCI_VENDOR_ID_INTEL, .device = (dev), \
1517 .subvendor = PCI_ANY_ID, .subdevice = (subdev), \
1518 .driver_data = (kernel_ulong_t)&(cfg)
1519
1520#define TIME_UNIT 1024
1521
1522#define IL_SKU_G 0x1
1523#define IL_SKU_A 0x2
1524#define IL_SKU_N 0x8
1525
1526#define IL_CMD(x) case x: return #x
1527
1528
1529#define IL_RX_BUF_SIZE_3K (3 * 1000)
1530#define IL_RX_BUF_SIZE_4K (4 * 1024)
1531#define IL_RX_BUF_SIZE_8K (8 * 1024)
1532
1533#ifdef CONFIG_IWLEGACY_DEBUGFS
1534struct il_debugfs_ops {
1535 ssize_t(*rx_stats_read) (struct file *file, char __user *user_buf,
1536 size_t count, loff_t *ppos);
1537 ssize_t(*tx_stats_read) (struct file *file, char __user *user_buf,
1538 size_t count, loff_t *ppos);
1539 ssize_t(*general_stats_read) (struct file *file,
1540 char __user *user_buf, size_t count,
1541 loff_t *ppos);
1542};
1543#endif
1544
1545struct il_ops {
1546
1547 void (*txq_update_byte_cnt_tbl) (struct il_priv *il,
1548 struct il_tx_queue *txq,
1549 u16 byte_cnt);
1550 int (*txq_attach_buf_to_tfd) (struct il_priv *il,
1551 struct il_tx_queue *txq, dma_addr_t addr,
1552 u16 len, u8 reset, u8 pad);
1553 void (*txq_free_tfd) (struct il_priv *il, struct il_tx_queue *txq);
1554 int (*txq_init) (struct il_priv *il, struct il_tx_queue *txq);
1555
1556 void (*init_alive_start) (struct il_priv *il);
1557
1558 int (*is_valid_rtc_data_addr) (u32 addr);
1559
1560 int (*load_ucode) (struct il_priv *il);
1561
1562 void (*dump_nic_error_log) (struct il_priv *il);
1563 int (*dump_fh) (struct il_priv *il, char **buf, bool display);
1564 int (*set_channel_switch) (struct il_priv *il,
1565 struct ieee80211_channel_switch *ch_switch);
1566
1567 int (*apm_init) (struct il_priv *il);
1568
1569
1570 int (*send_tx_power) (struct il_priv *il);
1571 void (*update_chain_flags) (struct il_priv *il);
1572
1573
1574 int (*eeprom_acquire_semaphore) (struct il_priv *il);
1575 void (*eeprom_release_semaphore) (struct il_priv *il);
1576
1577 int (*rxon_assoc) (struct il_priv *il);
1578 int (*commit_rxon) (struct il_priv *il);
1579 void (*set_rxon_chain) (struct il_priv *il);
1580
1581 u16(*get_hcmd_size) (u8 cmd_id, u16 len);
1582 u16(*build_addsta_hcmd) (const struct il_addsta_cmd *cmd, u8 *data);
1583
1584 int (*request_scan) (struct il_priv *il, struct ieee80211_vif *vif);
1585 void (*post_scan) (struct il_priv *il);
1586 void (*post_associate) (struct il_priv *il);
1587 void (*config_ap) (struct il_priv *il);
1588
1589 int (*update_bcast_stations) (struct il_priv *il);
1590 int (*manage_ibss_station) (struct il_priv *il,
1591 struct ieee80211_vif *vif, bool add);
1592
1593 int (*send_led_cmd) (struct il_priv *il, struct il_led_cmd *led_cmd);
1594};
1595
1596struct il_mod_params {
1597 int sw_crypto;
1598 int disable_hw_scan;
1599 int num_of_queues;
1600 int disable_11n;
1601 int amsdu_size_8K;
1602 int antenna;
1603 int restart_fw;
1604};
1605
1606#define IL_LED_SOLID 11
1607#define IL_DEF_LED_INTRVL cpu_to_le32(1000)
1608
1609#define IL_LED_ACTIVITY (0<<1)
1610#define IL_LED_LINK (1<<1)
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620enum il_led_mode {
1621 IL_LED_DEFAULT,
1622 IL_LED_RF_STATE,
1623 IL_LED_BLINK,
1624};
1625
1626void il_leds_init(struct il_priv *il);
1627void il_leds_exit(struct il_priv *il);
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660struct il_cfg {
1661
1662 const char *name;
1663 const char *fw_name_pre;
1664 const unsigned int ucode_api_max;
1665 const unsigned int ucode_api_min;
1666 u8 valid_tx_ant;
1667 u8 valid_rx_ant;
1668 unsigned int sku;
1669 u16 eeprom_ver;
1670 u16 eeprom_calib_ver;
1671
1672 const struct il_mod_params *mod_params;
1673
1674 struct il_base_params *base_params;
1675
1676 u8 scan_rx_antennas[IEEE80211_NUM_BANDS];
1677 enum il_led_mode led_mode;
1678
1679 int eeprom_size;
1680 int num_of_queues;
1681 int num_of_ampdu_queues;
1682
1683 u32 pll_cfg_val;
1684 bool set_l0s;
1685 bool use_bsm;
1686
1687 u16 led_compensation;
1688 int chain_noise_num_beacons;
1689 unsigned int wd_timeout;
1690 bool temperature_kelvin;
1691 const bool ucode_tracing;
1692 const bool sensitivity_calib_by_driver;
1693 const bool chain_noise_calib_by_driver;
1694
1695 const u32 regulatory_bands[7];
1696};
1697
1698
1699
1700
1701
1702int il_mac_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1703 u16 queue, const struct ieee80211_tx_queue_params *params);
1704int il_mac_tx_last_beacon(struct ieee80211_hw *hw);
1705
1706void il_set_rxon_hwcrypto(struct il_priv *il, int hw_decrypt);
1707int il_check_rxon_cmd(struct il_priv *il);
1708int il_full_rxon_required(struct il_priv *il);
1709int il_set_rxon_channel(struct il_priv *il, struct ieee80211_channel *ch);
1710void il_set_flags_for_band(struct il_priv *il, enum ieee80211_band band,
1711 struct ieee80211_vif *vif);
1712u8 il_get_single_channel_number(struct il_priv *il, enum ieee80211_band band);
1713void il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf);
1714bool il_is_ht40_tx_allowed(struct il_priv *il,
1715 struct ieee80211_sta_ht_cap *ht_cap);
1716void il_connection_init_rx_config(struct il_priv *il);
1717void il_set_rate(struct il_priv *il);
1718int il_set_decrypted_flag(struct il_priv *il, struct ieee80211_hdr *hdr,
1719 u32 decrypt_res, struct ieee80211_rx_status *stats);
1720void il_irq_handle_error(struct il_priv *il);
1721int il_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
1722void il_mac_remove_interface(struct ieee80211_hw *hw,
1723 struct ieee80211_vif *vif);
1724int il_mac_change_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1725 enum nl80211_iftype newtype, bool newp2p);
1726void il_mac_flush(struct ieee80211_hw *hw, u32 queues, bool drop);
1727int il_alloc_txq_mem(struct il_priv *il);
1728void il_free_txq_mem(struct il_priv *il);
1729
1730#ifdef CONFIG_IWLEGACY_DEBUGFS
1731void il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len);
1732#else
1733static inline void
1734il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len)
1735{
1736}
1737#endif
1738
1739
1740
1741
1742void il_hdl_pm_sleep(struct il_priv *il, struct il_rx_buf *rxb);
1743void il_hdl_pm_debug_stats(struct il_priv *il, struct il_rx_buf *rxb);
1744void il_hdl_error(struct il_priv *il, struct il_rx_buf *rxb);
1745void il_hdl_csa(struct il_priv *il, struct il_rx_buf *rxb);
1746
1747
1748
1749
1750void il_cmd_queue_unmap(struct il_priv *il);
1751void il_cmd_queue_free(struct il_priv *il);
1752int il_rx_queue_alloc(struct il_priv *il);
1753void il_rx_queue_update_write_ptr(struct il_priv *il, struct il_rx_queue *q);
1754int il_rx_queue_space(const struct il_rx_queue *q);
1755void il_tx_cmd_complete(struct il_priv *il, struct il_rx_buf *rxb);
1756
1757void il_hdl_spectrum_measurement(struct il_priv *il, struct il_rx_buf *rxb);
1758void il_recover_from_stats(struct il_priv *il, struct il_rx_pkt *pkt);
1759void il_chswitch_done(struct il_priv *il, bool is_success);
1760
1761
1762
1763
1764void il_txq_update_write_ptr(struct il_priv *il, struct il_tx_queue *txq);
1765int il_tx_queue_init(struct il_priv *il, u32 txq_id);
1766void il_tx_queue_reset(struct il_priv *il, u32 txq_id);
1767void il_tx_queue_unmap(struct il_priv *il, int txq_id);
1768void il_tx_queue_free(struct il_priv *il, int txq_id);
1769void il_setup_watchdog(struct il_priv *il);
1770
1771
1772
1773int il_set_tx_power(struct il_priv *il, s8 tx_power, bool force);
1774
1775
1776
1777
1778
1779u8 il_get_lowest_plcp(struct il_priv *il);
1780
1781
1782
1783
1784void il_init_scan_params(struct il_priv *il);
1785int il_scan_cancel(struct il_priv *il);
1786int il_scan_cancel_timeout(struct il_priv *il, unsigned long ms);
1787void il_force_scan_end(struct il_priv *il);
1788int il_mac_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1789 struct cfg80211_scan_request *req);
1790void il_internal_short_hw_scan(struct il_priv *il);
1791int il_force_reset(struct il_priv *il, bool external);
1792u16 il_fill_probe_req(struct il_priv *il, struct ieee80211_mgmt *frame,
1793 const u8 *ta, const u8 *ie, int ie_len, int left);
1794void il_setup_rx_scan_handlers(struct il_priv *il);
1795u16 il_get_active_dwell_time(struct il_priv *il, enum ieee80211_band band,
1796 u8 n_probes);
1797u16 il_get_passive_dwell_time(struct il_priv *il, enum ieee80211_band band,
1798 struct ieee80211_vif *vif);
1799void il_setup_scan_deferred_work(struct il_priv *il);
1800void il_cancel_scan_deferred_work(struct il_priv *il);
1801
1802
1803
1804
1805
1806
1807
1808#define IL_ACTIVE_QUIET_TIME cpu_to_le16(10)
1809#define IL_PLCP_QUIET_THRESH cpu_to_le16(1)
1810
1811#define IL_SCAN_CHECK_WATCHDOG (HZ * 7)
1812
1813
1814
1815
1816
1817const char *il_get_cmd_string(u8 cmd);
1818int __must_check il_send_cmd_sync(struct il_priv *il, struct il_host_cmd *cmd);
1819int il_send_cmd(struct il_priv *il, struct il_host_cmd *cmd);
1820int __must_check il_send_cmd_pdu(struct il_priv *il, u8 id, u16 len,
1821 const void *data);
1822int il_send_cmd_pdu_async(struct il_priv *il, u8 id, u16 len, const void *data,
1823 void (*callback) (struct il_priv *il,
1824 struct il_device_cmd *cmd,
1825 struct il_rx_pkt *pkt));
1826
1827int il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd);
1828
1829
1830
1831
1832
1833void il_bg_watchdog(unsigned long data);
1834u32 il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval);
1835__le32 il_add_beacon_time(struct il_priv *il, u32 base, u32 addon,
1836 u32 beacon_interval);
1837
1838#ifdef CONFIG_PM_SLEEP
1839extern const struct dev_pm_ops il_pm_ops;
1840
1841#define IL_LEGACY_PM_OPS (&il_pm_ops)
1842
1843#else
1844
1845#define IL_LEGACY_PM_OPS NULL
1846
1847#endif
1848
1849
1850
1851
1852void il4965_dump_nic_error_log(struct il_priv *il);
1853#ifdef CONFIG_IWLEGACY_DEBUG
1854void il_print_rx_config_cmd(struct il_priv *il);
1855#else
1856static inline void
1857il_print_rx_config_cmd(struct il_priv *il)
1858{
1859}
1860#endif
1861
1862void il_clear_isr_stats(struct il_priv *il);
1863
1864
1865
1866
1867int il_init_geos(struct il_priv *il);
1868void il_free_geos(struct il_priv *il);
1869
1870
1871
1872#define S_HCMD_ACTIVE 0
1873
1874#define S_INT_ENABLED 2
1875#define S_RFKILL 3
1876#define S_CT_KILL 4
1877#define S_INIT 5
1878#define S_ALIVE 6
1879#define S_READY 7
1880#define S_TEMPERATURE 8
1881#define S_GEO_CONFIGURED 9
1882#define S_EXIT_PENDING 10
1883#define S_STATS 12
1884#define S_SCANNING 13
1885#define S_SCAN_ABORTING 14
1886#define S_SCAN_HW 15
1887#define S_POWER_PMI 16
1888#define S_FW_ERROR 17
1889#define S_CHANNEL_SWITCH_PENDING 18
1890
1891static inline int
1892il_is_ready(struct il_priv *il)
1893{
1894
1895
1896 return test_bit(S_READY, &il->status) &&
1897 test_bit(S_GEO_CONFIGURED, &il->status) &&
1898 !test_bit(S_EXIT_PENDING, &il->status);
1899}
1900
1901static inline int
1902il_is_alive(struct il_priv *il)
1903{
1904 return test_bit(S_ALIVE, &il->status);
1905}
1906
1907static inline int
1908il_is_init(struct il_priv *il)
1909{
1910 return test_bit(S_INIT, &il->status);
1911}
1912
1913static inline int
1914il_is_rfkill(struct il_priv *il)
1915{
1916 return test_bit(S_RFKILL, &il->status);
1917}
1918
1919static inline int
1920il_is_ctkill(struct il_priv *il)
1921{
1922 return test_bit(S_CT_KILL, &il->status);
1923}
1924
1925static inline int
1926il_is_ready_rf(struct il_priv *il)
1927{
1928
1929 if (il_is_rfkill(il))
1930 return 0;
1931
1932 return il_is_ready(il);
1933}
1934
1935void il_send_bt_config(struct il_priv *il);
1936int il_send_stats_request(struct il_priv *il, u8 flags, bool clear);
1937void il_apm_stop(struct il_priv *il);
1938void _il_apm_stop(struct il_priv *il);
1939
1940int il_apm_init(struct il_priv *il);
1941
1942int il_send_rxon_timing(struct il_priv *il);
1943
1944static inline int
1945il_send_rxon_assoc(struct il_priv *il)
1946{
1947 return il->ops->rxon_assoc(il);
1948}
1949
1950static inline int
1951il_commit_rxon(struct il_priv *il)
1952{
1953 return il->ops->commit_rxon(il);
1954}
1955
1956static inline const struct ieee80211_supported_band *
1957il_get_hw_mode(struct il_priv *il, enum ieee80211_band band)
1958{
1959 return il->hw->wiphy->bands[band];
1960}
1961
1962
1963int il_mac_config(struct ieee80211_hw *hw, u32 changed);
1964void il_mac_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
1965void il_mac_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1966 struct ieee80211_bss_conf *bss_conf, u32 changes);
1967void il_tx_cmd_protection(struct il_priv *il, struct ieee80211_tx_info *info,
1968 __le16 fc, __le32 *tx_flags);
1969
1970irqreturn_t il_isr(int irq, void *data);
1971
1972void il_set_bit(struct il_priv *p, u32 r, u32 m);
1973void il_clear_bit(struct il_priv *p, u32 r, u32 m);
1974bool _il_grab_nic_access(struct il_priv *il);
1975int _il_poll_bit(struct il_priv *il, u32 addr, u32 bits, u32 mask, int timeout);
1976int il_poll_bit(struct il_priv *il, u32 addr, u32 mask, int timeout);
1977u32 il_rd_prph(struct il_priv *il, u32 reg);
1978void il_wr_prph(struct il_priv *il, u32 addr, u32 val);
1979u32 il_read_targ_mem(struct il_priv *il, u32 addr);
1980void il_write_targ_mem(struct il_priv *il, u32 addr, u32 val);
1981
1982static inline bool il_need_reclaim(struct il_priv *il, struct il_rx_pkt *pkt)
1983{
1984
1985
1986
1987
1988
1989
1990 return !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
1991 pkt->hdr.cmd != N_STATS && pkt->hdr.cmd != C_TX &&
1992 pkt->hdr.cmd != N_RX_PHY && pkt->hdr.cmd != N_RX &&
1993 pkt->hdr.cmd != N_RX_MPDU && pkt->hdr.cmd != N_COMPRESSED_BA;
1994}
1995
1996static inline void
1997_il_write8(struct il_priv *il, u32 ofs, u8 val)
1998{
1999 writeb(val, il->hw_base + ofs);
2000}
2001#define il_write8(il, ofs, val) _il_write8(il, ofs, val)
2002
2003static inline void
2004_il_wr(struct il_priv *il, u32 ofs, u32 val)
2005{
2006 writel(val, il->hw_base + ofs);
2007}
2008
2009static inline u32
2010_il_rd(struct il_priv *il, u32 ofs)
2011{
2012 return readl(il->hw_base + ofs);
2013}
2014
2015static inline void
2016_il_clear_bit(struct il_priv *il, u32 reg, u32 mask)
2017{
2018 _il_wr(il, reg, _il_rd(il, reg) & ~mask);
2019}
2020
2021static inline void
2022_il_set_bit(struct il_priv *il, u32 reg, u32 mask)
2023{
2024 _il_wr(il, reg, _il_rd(il, reg) | mask);
2025}
2026
2027static inline void
2028_il_release_nic_access(struct il_priv *il)
2029{
2030 _il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2031
2032
2033
2034
2035
2036
2037 mmiowb();
2038}
2039
2040static inline u32
2041il_rd(struct il_priv *il, u32 reg)
2042{
2043 u32 value;
2044 unsigned long reg_flags;
2045
2046 spin_lock_irqsave(&il->reg_lock, reg_flags);
2047 _il_grab_nic_access(il);
2048 value = _il_rd(il, reg);
2049 _il_release_nic_access(il);
2050 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2051 return value;
2052}
2053
2054static inline void
2055il_wr(struct il_priv *il, u32 reg, u32 value)
2056{
2057 unsigned long reg_flags;
2058
2059 spin_lock_irqsave(&il->reg_lock, reg_flags);
2060 if (likely(_il_grab_nic_access(il))) {
2061 _il_wr(il, reg, value);
2062 _il_release_nic_access(il);
2063 }
2064 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2065}
2066
2067static inline u32
2068_il_rd_prph(struct il_priv *il, u32 reg)
2069{
2070 _il_wr(il, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
2071 return _il_rd(il, HBUS_TARG_PRPH_RDAT);
2072}
2073
2074static inline void
2075_il_wr_prph(struct il_priv *il, u32 addr, u32 val)
2076{
2077 _il_wr(il, HBUS_TARG_PRPH_WADDR, ((addr & 0x0000FFFF) | (3 << 24)));
2078 _il_wr(il, HBUS_TARG_PRPH_WDAT, val);
2079}
2080
2081static inline void
2082il_set_bits_prph(struct il_priv *il, u32 reg, u32 mask)
2083{
2084 unsigned long reg_flags;
2085
2086 spin_lock_irqsave(&il->reg_lock, reg_flags);
2087 if (likely(_il_grab_nic_access(il))) {
2088 _il_wr_prph(il, reg, (_il_rd_prph(il, reg) | mask));
2089 _il_release_nic_access(il);
2090 }
2091 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2092}
2093
2094static inline void
2095il_set_bits_mask_prph(struct il_priv *il, u32 reg, u32 bits, u32 mask)
2096{
2097 unsigned long reg_flags;
2098
2099 spin_lock_irqsave(&il->reg_lock, reg_flags);
2100 if (likely(_il_grab_nic_access(il))) {
2101 _il_wr_prph(il, reg, ((_il_rd_prph(il, reg) & mask) | bits));
2102 _il_release_nic_access(il);
2103 }
2104 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2105}
2106
2107static inline void
2108il_clear_bits_prph(struct il_priv *il, u32 reg, u32 mask)
2109{
2110 unsigned long reg_flags;
2111 u32 val;
2112
2113 spin_lock_irqsave(&il->reg_lock, reg_flags);
2114 if (likely(_il_grab_nic_access(il))) {
2115 val = _il_rd_prph(il, reg);
2116 _il_wr_prph(il, reg, (val & ~mask));
2117 _il_release_nic_access(il);
2118 }
2119 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2120}
2121
2122#define HW_KEY_DYNAMIC 0
2123#define HW_KEY_DEFAULT 1
2124
2125#define IL_STA_DRIVER_ACTIVE BIT(0)
2126#define IL_STA_UCODE_ACTIVE BIT(1)
2127#define IL_STA_UCODE_INPROGRESS BIT(2)
2128
2129#define IL_STA_LOCAL BIT(3)
2130
2131#define IL_STA_BCAST BIT(4)
2132
2133void il_restore_stations(struct il_priv *il);
2134void il_clear_ucode_stations(struct il_priv *il);
2135void il_dealloc_bcast_stations(struct il_priv *il);
2136int il_get_free_ucode_key_idx(struct il_priv *il);
2137int il_send_add_sta(struct il_priv *il, struct il_addsta_cmd *sta, u8 flags);
2138int il_add_station_common(struct il_priv *il, const u8 *addr, bool is_ap,
2139 struct ieee80211_sta *sta, u8 *sta_id_r);
2140int il_remove_station(struct il_priv *il, const u8 sta_id, const u8 * addr);
2141int il_mac_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2142 struct ieee80211_sta *sta);
2143
2144u8 il_prep_station(struct il_priv *il, const u8 *addr, bool is_ap,
2145 struct ieee80211_sta *sta);
2146
2147int il_send_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq,
2148 u8 flags, bool init);
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159static inline void
2160il_clear_driver_stations(struct il_priv *il)
2161{
2162 unsigned long flags;
2163
2164 spin_lock_irqsave(&il->sta_lock, flags);
2165 memset(il->stations, 0, sizeof(il->stations));
2166 il->num_stations = 0;
2167 il->ucode_key_table = 0;
2168 spin_unlock_irqrestore(&il->sta_lock, flags);
2169}
2170
2171static inline int
2172il_sta_id(struct ieee80211_sta *sta)
2173{
2174 if (WARN_ON(!sta))
2175 return IL_INVALID_STATION;
2176
2177 return ((struct il_station_priv_common *)sta->drv_priv)->sta_id;
2178}
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191static inline int
2192il_sta_id_or_broadcast(struct il_priv *il, struct ieee80211_sta *sta)
2193{
2194 int sta_id;
2195
2196 if (!sta)
2197 return il->hw_params.bcast_id;
2198
2199 sta_id = il_sta_id(sta);
2200
2201
2202
2203
2204
2205 WARN_ON(sta_id == IL_INVALID_STATION);
2206
2207 return sta_id;
2208}
2209
2210
2211
2212
2213
2214
2215static inline int
2216il_queue_inc_wrap(int idx, int n_bd)
2217{
2218 return ++idx & (n_bd - 1);
2219}
2220
2221
2222
2223
2224
2225
2226static inline int
2227il_queue_dec_wrap(int idx, int n_bd)
2228{
2229 return --idx & (n_bd - 1);
2230}
2231
2232
2233static inline void
2234il_free_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
2235{
2236 if (desc->v_addr)
2237 dma_free_coherent(&pci_dev->dev, desc->len, desc->v_addr,
2238 desc->p_addr);
2239 desc->v_addr = NULL;
2240 desc->len = 0;
2241}
2242
2243static inline int
2244il_alloc_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
2245{
2246 if (!desc->len) {
2247 desc->v_addr = NULL;
2248 return -EINVAL;
2249 }
2250
2251 desc->v_addr = dma_alloc_coherent(&pci_dev->dev, desc->len,
2252 &desc->p_addr, GFP_KERNEL);
2253 return (desc->v_addr != NULL) ? 0 : -ENOMEM;
2254}
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267static inline void
2268il_set_swq_id(struct il_tx_queue *txq, u8 ac, u8 hwq)
2269{
2270 BUG_ON(ac > 3);
2271 BUG_ON(hwq > 31);
2272
2273 txq->swq_id = (hwq << 2) | ac;
2274}
2275
2276static inline void
2277_il_wake_queue(struct il_priv *il, u8 ac)
2278{
2279 if (atomic_dec_return(&il->queue_stop_count[ac]) <= 0)
2280 ieee80211_wake_queue(il->hw, ac);
2281}
2282
2283static inline void
2284_il_stop_queue(struct il_priv *il, u8 ac)
2285{
2286 if (atomic_inc_return(&il->queue_stop_count[ac]) > 0)
2287 ieee80211_stop_queue(il->hw, ac);
2288}
2289static inline void
2290il_wake_queue(struct il_priv *il, struct il_tx_queue *txq)
2291{
2292 u8 queue = txq->swq_id;
2293 u8 ac = queue & 3;
2294 u8 hwq = (queue >> 2) & 0x1f;
2295
2296 if (test_and_clear_bit(hwq, il->queue_stopped))
2297 _il_wake_queue(il, ac);
2298}
2299
2300static inline void
2301il_stop_queue(struct il_priv *il, struct il_tx_queue *txq)
2302{
2303 u8 queue = txq->swq_id;
2304 u8 ac = queue & 3;
2305 u8 hwq = (queue >> 2) & 0x1f;
2306
2307 if (!test_and_set_bit(hwq, il->queue_stopped))
2308 _il_stop_queue(il, ac);
2309}
2310
2311static inline void
2312il_wake_queues_by_reason(struct il_priv *il, int reason)
2313{
2314 u8 ac;
2315
2316 if (test_and_clear_bit(reason, &il->stop_reason))
2317 for (ac = 0; ac < 4; ac++)
2318 _il_wake_queue(il, ac);
2319}
2320
2321static inline void
2322il_stop_queues_by_reason(struct il_priv *il, int reason)
2323{
2324 u8 ac;
2325
2326 if (!test_and_set_bit(reason, &il->stop_reason))
2327 for (ac = 0; ac < 4; ac++)
2328 _il_stop_queue(il, ac);
2329}
2330
2331#ifdef ieee80211_stop_queue
2332#undef ieee80211_stop_queue
2333#endif
2334
2335#define ieee80211_stop_queue DO_NOT_USE_ieee80211_stop_queue
2336
2337#ifdef ieee80211_wake_queue
2338#undef ieee80211_wake_queue
2339#endif
2340
2341#define ieee80211_wake_queue DO_NOT_USE_ieee80211_wake_queue
2342
2343static inline void
2344il_disable_interrupts(struct il_priv *il)
2345{
2346 clear_bit(S_INT_ENABLED, &il->status);
2347
2348
2349 _il_wr(il, CSR_INT_MASK, 0x00000000);
2350
2351
2352
2353 _il_wr(il, CSR_INT, 0xffffffff);
2354 _il_wr(il, CSR_FH_INT_STATUS, 0xffffffff);
2355}
2356
2357static inline void
2358il_enable_rfkill_int(struct il_priv *il)
2359{
2360 _il_wr(il, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
2361}
2362
2363static inline void
2364il_enable_interrupts(struct il_priv *il)
2365{
2366 set_bit(S_INT_ENABLED, &il->status);
2367 _il_wr(il, CSR_INT_MASK, il->inta_mask);
2368}
2369
2370
2371
2372
2373
2374
2375static inline u32
2376il_beacon_time_mask_low(struct il_priv *il, u16 tsf_bits)
2377{
2378 return (1 << tsf_bits) - 1;
2379}
2380
2381
2382
2383
2384
2385
2386static inline u32
2387il_beacon_time_mask_high(struct il_priv *il, u16 tsf_bits)
2388{
2389 return ((1 << (32 - tsf_bits)) - 1) << tsf_bits;
2390}
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402struct il_rb_status {
2403 __le16 closed_rb_num;
2404 __le16 closed_fr_num;
2405 __le16 finished_rb_num;
2406 __le16 finished_fr_nam;
2407 __le32 __unused;
2408} __packed;
2409
2410#define TFD_QUEUE_SIZE_MAX 256
2411#define TFD_QUEUE_SIZE_BC_DUP 64
2412#define TFD_QUEUE_BC_SIZE (TFD_QUEUE_SIZE_MAX + TFD_QUEUE_SIZE_BC_DUP)
2413#define IL_TX_DMA_MASK DMA_BIT_MASK(36)
2414#define IL_NUM_OF_TBS 20
2415
2416static inline u8
2417il_get_dma_hi_addr(dma_addr_t addr)
2418{
2419 return (sizeof(addr) > sizeof(u32) ? (addr >> 16) >> 16 : 0) & 0xF;
2420}
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432struct il_tfd_tb {
2433 __le32 lo;
2434 __le16 hi_n_len;
2435} __packed;
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465struct il_tfd {
2466 u8 __reserved1[3];
2467 u8 num_tbs;
2468 struct il_tfd_tb tbs[IL_NUM_OF_TBS];
2469 __le32 __pad;
2470} __packed;
2471
2472#define PCI_CFG_RETRY_TIMEOUT 0x041
2473
2474struct il_rate_info {
2475 u8 plcp;
2476 u8 plcp_siso;
2477 u8 plcp_mimo2;
2478 u8 ieee;
2479 u8 prev_ieee;
2480 u8 next_ieee;
2481 u8 prev_rs;
2482 u8 next_rs;
2483 u8 prev_rs_tgg;
2484 u8 next_rs_tgg;
2485};
2486
2487struct il3945_rate_info {
2488 u8 plcp;
2489 u8 ieee;
2490 u8 prev_ieee;
2491 u8 next_ieee;
2492 u8 prev_rs;
2493 u8 next_rs;
2494 u8 prev_rs_tgg;
2495 u8 next_rs_tgg;
2496 u8 table_rs_idx;
2497 u8 prev_table_rs;
2498};
2499
2500
2501
2502
2503
2504enum {
2505 RATE_1M_IDX = 0,
2506 RATE_2M_IDX,
2507 RATE_5M_IDX,
2508 RATE_11M_IDX,
2509 RATE_6M_IDX,
2510 RATE_9M_IDX,
2511 RATE_12M_IDX,
2512 RATE_18M_IDX,
2513 RATE_24M_IDX,
2514 RATE_36M_IDX,
2515 RATE_48M_IDX,
2516 RATE_54M_IDX,
2517 RATE_60M_IDX,
2518 RATE_COUNT,
2519 RATE_COUNT_LEGACY = RATE_COUNT - 1,
2520 RATE_COUNT_3945 = RATE_COUNT - 1,
2521 RATE_INVM_IDX = RATE_COUNT,
2522 RATE_INVALID = RATE_COUNT,
2523};
2524
2525enum {
2526 RATE_6M_IDX_TBL = 0,
2527 RATE_9M_IDX_TBL,
2528 RATE_12M_IDX_TBL,
2529 RATE_18M_IDX_TBL,
2530 RATE_24M_IDX_TBL,
2531 RATE_36M_IDX_TBL,
2532 RATE_48M_IDX_TBL,
2533 RATE_54M_IDX_TBL,
2534 RATE_1M_IDX_TBL,
2535 RATE_2M_IDX_TBL,
2536 RATE_5M_IDX_TBL,
2537 RATE_11M_IDX_TBL,
2538 RATE_INVM_IDX_TBL = RATE_INVM_IDX - 1,
2539};
2540
2541enum {
2542 IL_FIRST_OFDM_RATE = RATE_6M_IDX,
2543 IL39_LAST_OFDM_RATE = RATE_54M_IDX,
2544 IL_LAST_OFDM_RATE = RATE_60M_IDX,
2545 IL_FIRST_CCK_RATE = RATE_1M_IDX,
2546 IL_LAST_CCK_RATE = RATE_11M_IDX,
2547};
2548
2549
2550#define RATE_6M_MASK (1 << RATE_6M_IDX)
2551#define RATE_9M_MASK (1 << RATE_9M_IDX)
2552#define RATE_12M_MASK (1 << RATE_12M_IDX)
2553#define RATE_18M_MASK (1 << RATE_18M_IDX)
2554#define RATE_24M_MASK (1 << RATE_24M_IDX)
2555#define RATE_36M_MASK (1 << RATE_36M_IDX)
2556#define RATE_48M_MASK (1 << RATE_48M_IDX)
2557#define RATE_54M_MASK (1 << RATE_54M_IDX)
2558#define RATE_60M_MASK (1 << RATE_60M_IDX)
2559#define RATE_1M_MASK (1 << RATE_1M_IDX)
2560#define RATE_2M_MASK (1 << RATE_2M_IDX)
2561#define RATE_5M_MASK (1 << RATE_5M_IDX)
2562#define RATE_11M_MASK (1 << RATE_11M_IDX)
2563
2564
2565enum {
2566 RATE_6M_PLCP = 13,
2567 RATE_9M_PLCP = 15,
2568 RATE_12M_PLCP = 5,
2569 RATE_18M_PLCP = 7,
2570 RATE_24M_PLCP = 9,
2571 RATE_36M_PLCP = 11,
2572 RATE_48M_PLCP = 1,
2573 RATE_54M_PLCP = 3,
2574 RATE_60M_PLCP = 3,
2575 RATE_1M_PLCP = 10,
2576 RATE_2M_PLCP = 20,
2577 RATE_5M_PLCP = 55,
2578 RATE_11M_PLCP = 110,
2579
2580};
2581
2582
2583enum {
2584 RATE_SISO_6M_PLCP = 0,
2585 RATE_SISO_12M_PLCP = 1,
2586 RATE_SISO_18M_PLCP = 2,
2587 RATE_SISO_24M_PLCP = 3,
2588 RATE_SISO_36M_PLCP = 4,
2589 RATE_SISO_48M_PLCP = 5,
2590 RATE_SISO_54M_PLCP = 6,
2591 RATE_SISO_60M_PLCP = 7,
2592 RATE_MIMO2_6M_PLCP = 0x8,
2593 RATE_MIMO2_12M_PLCP = 0x9,
2594 RATE_MIMO2_18M_PLCP = 0xa,
2595 RATE_MIMO2_24M_PLCP = 0xb,
2596 RATE_MIMO2_36M_PLCP = 0xc,
2597 RATE_MIMO2_48M_PLCP = 0xd,
2598 RATE_MIMO2_54M_PLCP = 0xe,
2599 RATE_MIMO2_60M_PLCP = 0xf,
2600 RATE_SISO_INVM_PLCP,
2601 RATE_MIMO2_INVM_PLCP = RATE_SISO_INVM_PLCP,
2602};
2603
2604
2605enum {
2606 RATE_6M_IEEE = 12,
2607 RATE_9M_IEEE = 18,
2608 RATE_12M_IEEE = 24,
2609 RATE_18M_IEEE = 36,
2610 RATE_24M_IEEE = 48,
2611 RATE_36M_IEEE = 72,
2612 RATE_48M_IEEE = 96,
2613 RATE_54M_IEEE = 108,
2614 RATE_60M_IEEE = 120,
2615 RATE_1M_IEEE = 2,
2616 RATE_2M_IEEE = 4,
2617 RATE_5M_IEEE = 11,
2618 RATE_11M_IEEE = 22,
2619};
2620
2621#define IL_CCK_BASIC_RATES_MASK \
2622 (RATE_1M_MASK | \
2623 RATE_2M_MASK)
2624
2625#define IL_CCK_RATES_MASK \
2626 (IL_CCK_BASIC_RATES_MASK | \
2627 RATE_5M_MASK | \
2628 RATE_11M_MASK)
2629
2630#define IL_OFDM_BASIC_RATES_MASK \
2631 (RATE_6M_MASK | \
2632 RATE_12M_MASK | \
2633 RATE_24M_MASK)
2634
2635#define IL_OFDM_RATES_MASK \
2636 (IL_OFDM_BASIC_RATES_MASK | \
2637 RATE_9M_MASK | \
2638 RATE_18M_MASK | \
2639 RATE_36M_MASK | \
2640 RATE_48M_MASK | \
2641 RATE_54M_MASK)
2642
2643#define IL_BASIC_RATES_MASK \
2644 (IL_OFDM_BASIC_RATES_MASK | \
2645 IL_CCK_BASIC_RATES_MASK)
2646
2647#define RATES_MASK ((1 << RATE_COUNT) - 1)
2648#define RATES_MASK_3945 ((1 << RATE_COUNT_3945) - 1)
2649
2650#define IL_INVALID_VALUE -1
2651
2652#define IL_MIN_RSSI_VAL -100
2653#define IL_MAX_RSSI_VAL 0
2654
2655
2656
2657#define IL_LEGACY_FAILURE_LIMIT 160
2658#define IL_LEGACY_SUCCESS_LIMIT 480
2659#define IL_LEGACY_TBL_COUNT 160
2660
2661#define IL_NONE_LEGACY_FAILURE_LIMIT 400
2662#define IL_NONE_LEGACY_SUCCESS_LIMIT 4500
2663#define IL_NONE_LEGACY_TBL_COUNT 1500
2664
2665
2666#define IL_RS_GOOD_RATIO 12800
2667#define RATE_SCALE_SWITCH 10880
2668#define RATE_HIGH_TH 10880
2669#define RATE_INCREASE_TH 6400
2670#define RATE_DECREASE_TH 1920
2671
2672
2673#define IL_LEGACY_SWITCH_ANTENNA1 0
2674#define IL_LEGACY_SWITCH_ANTENNA2 1
2675#define IL_LEGACY_SWITCH_SISO 2
2676#define IL_LEGACY_SWITCH_MIMO2_AB 3
2677#define IL_LEGACY_SWITCH_MIMO2_AC 4
2678#define IL_LEGACY_SWITCH_MIMO2_BC 5
2679
2680
2681#define IL_SISO_SWITCH_ANTENNA1 0
2682#define IL_SISO_SWITCH_ANTENNA2 1
2683#define IL_SISO_SWITCH_MIMO2_AB 2
2684#define IL_SISO_SWITCH_MIMO2_AC 3
2685#define IL_SISO_SWITCH_MIMO2_BC 4
2686#define IL_SISO_SWITCH_GI 5
2687
2688
2689#define IL_MIMO2_SWITCH_ANTENNA1 0
2690#define IL_MIMO2_SWITCH_ANTENNA2 1
2691#define IL_MIMO2_SWITCH_SISO_A 2
2692#define IL_MIMO2_SWITCH_SISO_B 3
2693#define IL_MIMO2_SWITCH_SISO_C 4
2694#define IL_MIMO2_SWITCH_GI 5
2695
2696#define IL_MAX_SEARCH IL_MIMO2_SWITCH_GI
2697
2698#define IL_ACTION_LIMIT 3
2699
2700#define LQ_SIZE 2
2701
2702
2703#define IL_AGG_TPT_THREHOLD 0
2704#define IL_AGG_LOAD_THRESHOLD 10
2705#define IL_AGG_ALL_TID 0xff
2706#define TID_QUEUE_CELL_SPACING 50
2707#define TID_QUEUE_MAX_SIZE 20
2708#define TID_ROUND_VALUE 5
2709#define TID_MAX_LOAD_COUNT 8
2710
2711#define TID_MAX_TIME_DIFF ((TID_QUEUE_MAX_SIZE - 1) * TID_QUEUE_CELL_SPACING)
2712#define TIME_WRAP_AROUND(x, y) (((y) > (x)) ? (y) - (x) : (0-(x)) + (y))
2713
2714extern const struct il_rate_info il_rates[RATE_COUNT];
2715
2716enum il_table_type {
2717 LQ_NONE,
2718 LQ_G,
2719 LQ_A,
2720 LQ_SISO,
2721 LQ_MIMO2,
2722 LQ_MAX,
2723};
2724
2725#define is_legacy(tbl) ((tbl) == LQ_G || (tbl) == LQ_A)
2726#define is_siso(tbl) ((tbl) == LQ_SISO)
2727#define is_mimo2(tbl) ((tbl) == LQ_MIMO2)
2728#define is_mimo(tbl) (is_mimo2(tbl))
2729#define is_Ht(tbl) (is_siso(tbl) || is_mimo(tbl))
2730#define is_a_band(tbl) ((tbl) == LQ_A)
2731#define is_g_and(tbl) ((tbl) == LQ_G)
2732
2733#define ANT_NONE 0x0
2734#define ANT_A BIT(0)
2735#define ANT_B BIT(1)
2736#define ANT_AB (ANT_A | ANT_B)
2737#define ANT_C BIT(2)
2738#define ANT_AC (ANT_A | ANT_C)
2739#define ANT_BC (ANT_B | ANT_C)
2740#define ANT_ABC (ANT_AB | ANT_C)
2741
2742#define IL_MAX_MCS_DISPLAY_SIZE 12
2743
2744struct il_rate_mcs_info {
2745 char mbps[IL_MAX_MCS_DISPLAY_SIZE];
2746 char mcs[IL_MAX_MCS_DISPLAY_SIZE];
2747};
2748
2749
2750
2751
2752struct il_rate_scale_data {
2753 u64 data;
2754 s32 success_counter;
2755 s32 success_ratio;
2756 s32 counter;
2757 s32 average_tpt;
2758 unsigned long stamp;
2759};
2760
2761
2762
2763
2764
2765
2766
2767struct il_scale_tbl_info {
2768 enum il_table_type lq_type;
2769 u8 ant_type;
2770 u8 is_SGI;
2771 u8 is_ht40;
2772 u8 is_dup;
2773 u8 action;
2774 u8 max_search;
2775 s32 *expected_tpt;
2776 u32 current_rate;
2777 struct il_rate_scale_data win[RATE_COUNT];
2778};
2779
2780struct il_traffic_load {
2781 unsigned long time_stamp;
2782 u32 packet_count[TID_QUEUE_MAX_SIZE];
2783
2784 u32 total;
2785
2786 u8 queue_count;
2787
2788 u8 head;
2789};
2790
2791
2792
2793
2794
2795
2796struct il_lq_sta {
2797 u8 active_tbl;
2798 u8 enable_counter;
2799 u8 stay_in_tbl;
2800 u8 search_better_tbl;
2801 s32 last_tpt;
2802
2803
2804 u32 table_count_limit;
2805 u32 max_failure_limit;
2806 u32 max_success_limit;
2807 u32 table_count;
2808 u32 total_failed;
2809 u32 total_success;
2810 u64 flush_timer;
2811
2812 u8 action_counter;
2813 u8 is_green;
2814 u8 is_dup;
2815 enum ieee80211_band band;
2816
2817
2818 u32 supp_rates;
2819 u16 active_legacy_rate;
2820 u16 active_siso_rate;
2821 u16 active_mimo2_rate;
2822 s8 max_rate_idx;
2823 u8 missed_rate_counter;
2824
2825 struct il_link_quality_cmd lq;
2826 struct il_scale_tbl_info lq_info[LQ_SIZE];
2827 struct il_traffic_load load[TID_MAX_LOAD_COUNT];
2828 u8 tx_agg_tid_en;
2829#ifdef CONFIG_MAC80211_DEBUGFS
2830 struct dentry *rs_sta_dbgfs_scale_table_file;
2831 struct dentry *rs_sta_dbgfs_stats_table_file;
2832 struct dentry *rs_sta_dbgfs_rate_scale_data_file;
2833 struct dentry *rs_sta_dbgfs_tx_agg_tid_en_file;
2834 u32 dbg_fixed_rate;
2835#endif
2836 struct il_priv *drv;
2837
2838
2839 int last_txrate_idx;
2840
2841 u32 last_rate_n_flags;
2842
2843 u8 is_agg;
2844};
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856struct il_station_priv {
2857 struct il_station_priv_common common;
2858 struct il_lq_sta lq_sta;
2859 atomic_t pending_frames;
2860 bool client;
2861 bool asleep;
2862};
2863
2864static inline u8
2865il4965_num_of_ant(u8 m)
2866{
2867 return !!(m & ANT_A) + !!(m & ANT_B) + !!(m & ANT_C);
2868}
2869
2870static inline u8
2871il4965_first_antenna(u8 mask)
2872{
2873 if (mask & ANT_A)
2874 return ANT_A;
2875 if (mask & ANT_B)
2876 return ANT_B;
2877 return ANT_C;
2878}
2879
2880
2881
2882
2883
2884
2885
2886void il3945_rate_scale_init(struct ieee80211_hw *hw, s32 sta_id);
2887
2888
2889void il4965_rs_rate_init(struct il_priv *il, struct ieee80211_sta *sta,
2890 u8 sta_id);
2891void il3945_rs_rate_init(struct il_priv *il, struct ieee80211_sta *sta,
2892 u8 sta_id);
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904int il4965_rate_control_register(void);
2905int il3945_rate_control_register(void);
2906
2907
2908
2909
2910
2911
2912
2913void il4965_rate_control_unregister(void);
2914void il3945_rate_control_unregister(void);
2915
2916int il_power_update_mode(struct il_priv *il, bool force);
2917void il_power_initialize(struct il_priv *il);
2918
2919extern u32 il_debug_level;
2920
2921#ifdef CONFIG_IWLEGACY_DEBUG
2922
2923
2924
2925
2926
2927
2928
2929static inline u32
2930il_get_debug_level(struct il_priv *il)
2931{
2932 if (il->debug_level)
2933 return il->debug_level;
2934 else
2935 return il_debug_level;
2936}
2937#else
2938static inline u32
2939il_get_debug_level(struct il_priv *il)
2940{
2941 return il_debug_level;
2942}
2943#endif
2944
2945#define il_print_hex_error(il, p, len) \
2946do { \
2947 print_hex_dump(KERN_ERR, "iwl data: ", \
2948 DUMP_PREFIX_OFFSET, 16, 1, p, len, 1); \
2949} while (0)
2950
2951#ifdef CONFIG_IWLEGACY_DEBUG
2952#define IL_DBG(level, fmt, args...) \
2953do { \
2954 if (il_get_debug_level(il) & level) \
2955 dev_err(&il->hw->wiphy->dev, "%c %s " fmt, \
2956 in_interrupt() ? 'I' : 'U', __func__ , ##args); \
2957} while (0)
2958
2959#define il_print_hex_dump(il, level, p, len) \
2960do { \
2961 if (il_get_debug_level(il) & level) \
2962 print_hex_dump(KERN_DEBUG, "iwl data: ", \
2963 DUMP_PREFIX_OFFSET, 16, 1, p, len, 1); \
2964} while (0)
2965
2966#else
2967#define IL_DBG(level, fmt, args...)
2968static inline void
2969il_print_hex_dump(struct il_priv *il, int level, const void *p, u32 len)
2970{
2971}
2972#endif
2973
2974#ifdef CONFIG_IWLEGACY_DEBUGFS
2975int il_dbgfs_register(struct il_priv *il, const char *name);
2976void il_dbgfs_unregister(struct il_priv *il);
2977#else
2978static inline int
2979il_dbgfs_register(struct il_priv *il, const char *name)
2980{
2981 return 0;
2982}
2983
2984static inline void
2985il_dbgfs_unregister(struct il_priv *il)
2986{
2987}
2988#endif
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014#define IL_DL_INFO (1 << 0)
3015#define IL_DL_MAC80211 (1 << 1)
3016#define IL_DL_HCMD (1 << 2)
3017#define IL_DL_STATE (1 << 3)
3018
3019#define IL_DL_MACDUMP (1 << 4)
3020#define IL_DL_HCMD_DUMP (1 << 5)
3021#define IL_DL_EEPROM (1 << 6)
3022#define IL_DL_RADIO (1 << 7)
3023
3024#define IL_DL_POWER (1 << 8)
3025#define IL_DL_TEMP (1 << 9)
3026#define IL_DL_NOTIF (1 << 10)
3027#define IL_DL_SCAN (1 << 11)
3028
3029#define IL_DL_ASSOC (1 << 12)
3030#define IL_DL_DROP (1 << 13)
3031#define IL_DL_TXPOWER (1 << 14)
3032#define IL_DL_AP (1 << 15)
3033
3034#define IL_DL_FW (1 << 16)
3035#define IL_DL_RF_KILL (1 << 17)
3036#define IL_DL_FW_ERRORS (1 << 18)
3037#define IL_DL_LED (1 << 19)
3038
3039#define IL_DL_RATE (1 << 20)
3040#define IL_DL_CALIB (1 << 21)
3041#define IL_DL_WEP (1 << 22)
3042#define IL_DL_TX (1 << 23)
3043
3044#define IL_DL_RX (1 << 24)
3045#define IL_DL_ISR (1 << 25)
3046#define IL_DL_HT (1 << 26)
3047
3048#define IL_DL_11H (1 << 28)
3049#define IL_DL_STATS (1 << 29)
3050#define IL_DL_TX_REPLY (1 << 30)
3051#define IL_DL_QOS (1 << 31)
3052
3053#define D_INFO(f, a...) IL_DBG(IL_DL_INFO, f, ## a)
3054#define D_MAC80211(f, a...) IL_DBG(IL_DL_MAC80211, f, ## a)
3055#define D_MACDUMP(f, a...) IL_DBG(IL_DL_MACDUMP, f, ## a)
3056#define D_TEMP(f, a...) IL_DBG(IL_DL_TEMP, f, ## a)
3057#define D_SCAN(f, a...) IL_DBG(IL_DL_SCAN, f, ## a)
3058#define D_RX(f, a...) IL_DBG(IL_DL_RX, f, ## a)
3059#define D_TX(f, a...) IL_DBG(IL_DL_TX, f, ## a)
3060#define D_ISR(f, a...) IL_DBG(IL_DL_ISR, f, ## a)
3061#define D_LED(f, a...) IL_DBG(IL_DL_LED, f, ## a)
3062#define D_WEP(f, a...) IL_DBG(IL_DL_WEP, f, ## a)
3063#define D_HC(f, a...) IL_DBG(IL_DL_HCMD, f, ## a)
3064#define D_HC_DUMP(f, a...) IL_DBG(IL_DL_HCMD_DUMP, f, ## a)
3065#define D_EEPROM(f, a...) IL_DBG(IL_DL_EEPROM, f, ## a)
3066#define D_CALIB(f, a...) IL_DBG(IL_DL_CALIB, f, ## a)
3067#define D_FW(f, a...) IL_DBG(IL_DL_FW, f, ## a)
3068#define D_RF_KILL(f, a...) IL_DBG(IL_DL_RF_KILL, f, ## a)
3069#define D_DROP(f, a...) IL_DBG(IL_DL_DROP, f, ## a)
3070#define D_AP(f, a...) IL_DBG(IL_DL_AP, f, ## a)
3071#define D_TXPOWER(f, a...) IL_DBG(IL_DL_TXPOWER, f, ## a)
3072#define D_RATE(f, a...) IL_DBG(IL_DL_RATE, f, ## a)
3073#define D_NOTIF(f, a...) IL_DBG(IL_DL_NOTIF, f, ## a)
3074#define D_ASSOC(f, a...) IL_DBG(IL_DL_ASSOC, f, ## a)
3075#define D_HT(f, a...) IL_DBG(IL_DL_HT, f, ## a)
3076#define D_STATS(f, a...) IL_DBG(IL_DL_STATS, f, ## a)
3077#define D_TX_REPLY(f, a...) IL_DBG(IL_DL_TX_REPLY, f, ## a)
3078#define D_QOS(f, a...) IL_DBG(IL_DL_QOS, f, ## a)
3079#define D_RADIO(f, a...) IL_DBG(IL_DL_RADIO, f, ## a)
3080#define D_POWER(f, a...) IL_DBG(IL_DL_POWER, f, ## a)
3081#define D_11H(f, a...) IL_DBG(IL_DL_11H, f, ## a)
3082
3083#endif
3084