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30#include "../wifi.h"
31#include "../pci.h"
32#include "../ps.h"
33#include "../core.h"
34#include "reg.h"
35#include "def.h"
36#include "phy.h"
37#include "rf.h"
38#include "dm.h"
39#include "table.h"
40#include "sw.h"
41#include "hw.h"
42
43#define MAX_RF_IMR_INDEX 12
44#define MAX_RF_IMR_INDEX_NORMAL 13
45#define RF_REG_NUM_FOR_C_CUT_5G 6
46#define RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA 7
47#define RF_REG_NUM_FOR_C_CUT_2G 5
48#define RF_CHNL_NUM_5G 19
49#define RF_CHNL_NUM_5G_40M 17
50#define TARGET_CHNL_NUM_5G 221
51#define TARGET_CHNL_NUM_2G 14
52#define CV_CURVE_CNT 64
53
54static u32 rf_reg_for_5g_swchnl_normal[MAX_RF_IMR_INDEX_NORMAL] = {
55 0, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x0
56};
57
58static u8 rf_reg_for_c_cut_5g[RF_REG_NUM_FOR_C_CUT_5G] = {
59 RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G4, RF_SYN_G5, RF_SYN_G6
60};
61
62static u8 rf_reg_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = {
63 RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G7, RF_SYN_G8
64};
65
66static u8 rf_for_c_cut_5g_internal_pa[RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = {
67 0x0B, 0x48, 0x49, 0x4B, 0x03, 0x04, 0x0E
68};
69
70static u32 rf_reg_mask_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = {
71 BIT(19) | BIT(18) | BIT(17) | BIT(14) | BIT(1),
72 BIT(10) | BIT(9),
73 BIT(18) | BIT(17) | BIT(16) | BIT(1),
74 BIT(2) | BIT(1),
75 BIT(15) | BIT(14) | BIT(13) | BIT(12) | BIT(11)
76};
77
78static u8 rf_chnl_5g[RF_CHNL_NUM_5G] = {
79 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108,
80 112, 116, 120, 124, 128, 132, 136, 140
81};
82
83static u8 rf_chnl_5g_40m[RF_CHNL_NUM_5G_40M] = {
84 38, 42, 46, 50, 54, 58, 62, 102, 106, 110, 114,
85 118, 122, 126, 130, 134, 138
86};
87static u32 rf_reg_pram_c_5g[5][RF_REG_NUM_FOR_C_CUT_5G] = {
88 {0xE43BE, 0xFC638, 0x77C0A, 0xDE471, 0xd7110, 0x8EB04},
89 {0xE43BE, 0xFC078, 0xF7C1A, 0xE0C71, 0xD7550, 0xAEB04},
90 {0xE43BF, 0xFF038, 0xF7C0A, 0xDE471, 0xE5550, 0xAEB04},
91 {0xE43BF, 0xFF079, 0xF7C1A, 0xDE471, 0xE5550, 0xAEB04},
92 {0xE43BF, 0xFF038, 0xF7C1A, 0xDE471, 0xd7550, 0xAEB04}
93};
94
95static u32 rf_reg_param_for_c_cut_2g[3][RF_REG_NUM_FOR_C_CUT_2G] = {
96 {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840},
97 {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840},
98 {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41}
99};
100
101static u32 rf_syn_g4_for_c_cut_2g = 0xD1C31 & 0x7FF;
102
103static u32 rf_pram_c_5g_int_pa[3][RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = {
104 {0x01a00, 0x40443, 0x00eb5, 0x89bec, 0x94a12, 0x94a12, 0x94a12},
105 {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a52, 0x94a52, 0x94a52},
106 {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a12, 0x94a12, 0x94a12}
107};
108
109
110static u32 rf_imr_param_normal[1][3][MAX_RF_IMR_INDEX_NORMAL] = {
111 {
112
113 {
114 0x70000, 0x00ff0, 0x4400f, 0x00ff0, 0x0, 0x0, 0x0,
115 0x0, 0x0, 0x64888, 0xe266c, 0x00090, 0x22fff
116 },
117
118 {
119 0x70000, 0x22880, 0x4470f, 0x55880, 0x00070, 0x88000,
120 0x0, 0x88080, 0x70000, 0x64a82, 0xe466c, 0x00090,
121 0x32c9a
122 },
123
124 {
125 0x70000, 0x44880, 0x4477f, 0x77880, 0x00070, 0x88000,
126 0x0, 0x880b0, 0x0, 0x64b82, 0xe466c, 0x00090, 0x32c9a
127 }
128 }
129};
130
131static u32 curveindex_5g[TARGET_CHNL_NUM_5G] = {0};
132
133static u32 curveindex_2g[TARGET_CHNL_NUM_2G] = {0};
134
135static u32 targetchnl_5g[TARGET_CHNL_NUM_5G] = {
136 25141, 25116, 25091, 25066, 25041,
137 25016, 24991, 24966, 24941, 24917,
138 24892, 24867, 24843, 24818, 24794,
139 24770, 24765, 24721, 24697, 24672,
140 24648, 24624, 24600, 24576, 24552,
141 24528, 24504, 24480, 24457, 24433,
142 24409, 24385, 24362, 24338, 24315,
143 24291, 24268, 24245, 24221, 24198,
144 24175, 24151, 24128, 24105, 24082,
145 24059, 24036, 24013, 23990, 23967,
146 23945, 23922, 23899, 23876, 23854,
147 23831, 23809, 23786, 23764, 23741,
148 23719, 23697, 23674, 23652, 23630,
149 23608, 23586, 23564, 23541, 23519,
150 23498, 23476, 23454, 23432, 23410,
151 23388, 23367, 23345, 23323, 23302,
152 23280, 23259, 23237, 23216, 23194,
153 23173, 23152, 23130, 23109, 23088,
154 23067, 23046, 23025, 23003, 22982,
155 22962, 22941, 22920, 22899, 22878,
156 22857, 22837, 22816, 22795, 22775,
157 22754, 22733, 22713, 22692, 22672,
158 22652, 22631, 22611, 22591, 22570,
159 22550, 22530, 22510, 22490, 22469,
160 22449, 22429, 22409, 22390, 22370,
161 22350, 22336, 22310, 22290, 22271,
162 22251, 22231, 22212, 22192, 22173,
163 22153, 22134, 22114, 22095, 22075,
164 22056, 22037, 22017, 21998, 21979,
165 21960, 21941, 21921, 21902, 21883,
166 21864, 21845, 21826, 21807, 21789,
167 21770, 21751, 21732, 21713, 21695,
168 21676, 21657, 21639, 21620, 21602,
169 21583, 21565, 21546, 21528, 21509,
170 21491, 21473, 21454, 21436, 21418,
171 21400, 21381, 21363, 21345, 21327,
172 21309, 21291, 21273, 21255, 21237,
173 21219, 21201, 21183, 21166, 21148,
174 21130, 21112, 21095, 21077, 21059,
175 21042, 21024, 21007, 20989, 20972,
176 25679, 25653, 25627, 25601, 25575,
177 25549, 25523, 25497, 25471, 25446,
178 25420, 25394, 25369, 25343, 25318,
179 25292, 25267, 25242, 25216, 25191,
180 25166
181};
182
183
184static u32 targetchnl_2g[TARGET_CHNL_NUM_2G] = {
185 26084, 26030, 25976, 25923, 25869, 25816, 25764,
186 25711, 25658, 25606, 25554, 25502, 25451, 25328
187};
188
189static u32 _rtl92d_phy_calculate_bit_shift(u32 bitmask)
190{
191 u32 i;
192
193 for (i = 0; i <= 31; i++) {
194 if (((bitmask >> i) & 0x1) == 1)
195 break;
196 }
197
198 return i;
199}
200
201u32 rtl92d_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
202{
203 struct rtl_priv *rtlpriv = rtl_priv(hw);
204 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
205 u32 returnvalue, originalvalue, bitshift;
206 u8 dbi_direct;
207
208 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n",
209 regaddr, bitmask);
210 if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob) {
211
212
213 if (rtlhal->during_mac1init_radioa)
214 dbi_direct = BIT(3);
215 else if (rtlhal->during_mac0init_radiob)
216 dbi_direct = BIT(3) | BIT(2);
217 originalvalue = rtl92de_read_dword_dbi(hw, (u16)regaddr,
218 dbi_direct);
219 } else {
220 originalvalue = rtl_read_dword(rtlpriv, regaddr);
221 }
222 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
223 returnvalue = (originalvalue & bitmask) >> bitshift;
224 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
225 "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
226 bitmask, regaddr, originalvalue);
227 return returnvalue;
228}
229
230void rtl92d_phy_set_bb_reg(struct ieee80211_hw *hw,
231 u32 regaddr, u32 bitmask, u32 data)
232{
233 struct rtl_priv *rtlpriv = rtl_priv(hw);
234 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
235 u8 dbi_direct = 0;
236 u32 originalvalue, bitshift;
237
238 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
239 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
240 regaddr, bitmask, data);
241 if (rtlhal->during_mac1init_radioa)
242 dbi_direct = BIT(3);
243 else if (rtlhal->during_mac0init_radiob)
244
245 dbi_direct = BIT(3) | BIT(2);
246 if (bitmask != MASKDWORD) {
247 if (rtlhal->during_mac1init_radioa ||
248 rtlhal->during_mac0init_radiob)
249 originalvalue = rtl92de_read_dword_dbi(hw,
250 (u16) regaddr,
251 dbi_direct);
252 else
253 originalvalue = rtl_read_dword(rtlpriv, regaddr);
254 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
255 data = ((originalvalue & (~bitmask)) | (data << bitshift));
256 }
257 if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob)
258 rtl92de_write_dword_dbi(hw, (u16) regaddr, data, dbi_direct);
259 else
260 rtl_write_dword(rtlpriv, regaddr, data);
261 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
262 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
263 regaddr, bitmask, data);
264}
265
266static u32 _rtl92d_phy_rf_serial_read(struct ieee80211_hw *hw,
267 enum radio_path rfpath, u32 offset)
268{
269
270 struct rtl_priv *rtlpriv = rtl_priv(hw);
271 struct rtl_phy *rtlphy = &(rtlpriv->phy);
272 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
273 u32 newoffset;
274 u32 tmplong, tmplong2;
275 u8 rfpi_enable = 0;
276 u32 retvalue;
277
278 newoffset = offset;
279 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
280 if (rfpath == RF90_PATH_A)
281 tmplong2 = tmplong;
282 else
283 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
284 tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
285 (newoffset << 23) | BLSSIREADEDGE;
286 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
287 tmplong & (~BLSSIREADEDGE));
288 udelay(10);
289 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
290 udelay(50);
291 udelay(50);
292 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
293 tmplong | BLSSIREADEDGE);
294 udelay(10);
295 if (rfpath == RF90_PATH_A)
296 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
297 BIT(8));
298 else if (rfpath == RF90_PATH_B)
299 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
300 BIT(8));
301 if (rfpi_enable)
302 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
303 BLSSIREADBACKDATA);
304 else
305 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
306 BLSSIREADBACKDATA);
307 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x] = 0x%x\n",
308 rfpath, pphyreg->rf_rb, retvalue);
309 return retvalue;
310}
311
312static void _rtl92d_phy_rf_serial_write(struct ieee80211_hw *hw,
313 enum radio_path rfpath,
314 u32 offset, u32 data)
315{
316 u32 data_and_addr;
317 u32 newoffset;
318 struct rtl_priv *rtlpriv = rtl_priv(hw);
319 struct rtl_phy *rtlphy = &(rtlpriv->phy);
320 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
321
322 newoffset = offset;
323
324 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
325 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
326 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
327 rfpath, pphyreg->rf3wire_offset, data_and_addr);
328}
329
330u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw,
331 enum radio_path rfpath, u32 regaddr, u32 bitmask)
332{
333 struct rtl_priv *rtlpriv = rtl_priv(hw);
334 u32 original_value, readback_value, bitshift;
335 unsigned long flags;
336
337 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
338 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
339 regaddr, rfpath, bitmask);
340 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
341 original_value = _rtl92d_phy_rf_serial_read(hw, rfpath, regaddr);
342 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
343 readback_value = (original_value & bitmask) >> bitshift;
344 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
345 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
346 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
347 regaddr, rfpath, bitmask, original_value);
348 return readback_value;
349}
350
351void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
352 u32 regaddr, u32 bitmask, u32 data)
353{
354 struct rtl_priv *rtlpriv = rtl_priv(hw);
355 struct rtl_phy *rtlphy = &(rtlpriv->phy);
356 u32 original_value, bitshift;
357 unsigned long flags;
358
359 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
360 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
361 regaddr, bitmask, data, rfpath);
362 if (bitmask == 0)
363 return;
364 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
365 if (rtlphy->rf_mode != RF_OP_BY_FW) {
366 if (bitmask != RFREG_OFFSET_MASK) {
367 original_value = _rtl92d_phy_rf_serial_read(hw,
368 rfpath, regaddr);
369 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
370 data = ((original_value & (~bitmask)) |
371 (data << bitshift));
372 }
373 _rtl92d_phy_rf_serial_write(hw, rfpath, regaddr, data);
374 }
375 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
376 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
377 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
378 regaddr, bitmask, data, rfpath);
379}
380
381bool rtl92d_phy_mac_config(struct ieee80211_hw *hw)
382{
383 struct rtl_priv *rtlpriv = rtl_priv(hw);
384 u32 i;
385 u32 arraylength;
386 u32 *ptrarray;
387
388 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl819XMACPHY_Array\n");
389 arraylength = MAC_2T_ARRAYLENGTH;
390 ptrarray = rtl8192de_mac_2tarray;
391 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Img:Rtl819XMAC_Array\n");
392 for (i = 0; i < arraylength; i = i + 2)
393 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
394 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) {
395
396
397
398
399 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x0B);
400 } else {
401
402 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x07);
403 }
404 return true;
405}
406
407static void _rtl92d_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
408{
409 struct rtl_priv *rtlpriv = rtl_priv(hw);
410 struct rtl_phy *rtlphy = &(rtlpriv->phy);
411
412
413
414 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
415
416 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
417
418 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
419
420
421 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
422
423
424 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
425
426 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
427
428 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
429
430 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
431
432
433
434 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
435
436 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
437
438
439
440 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
441
442 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
443
444
445
446 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
447 RFPGA0_XA_LSSIPARAMETER;
448 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
449 RFPGA0_XB_LSSIPARAMETER;
450
451
452
453 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
454 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
455 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
456 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
457
458
459
460 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
461
462 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
463
464 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
465
466 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
467
468
469
470 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
471
472 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
473
474
475
476 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
477
478 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
479
480
481
482 rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
483 rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
484 rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
485 rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
486
487
488 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
489 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
490 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
491 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
492
493
494 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
495 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
496 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
497 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
498
499
500 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;
501 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;
502 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBALANCE;
503 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;
504
505
506 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
507 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
508 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
509 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
510
511
512 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATxIQIMBALANCE;
513 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTxIQIMBALANCE;
514 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTxIQIMBALANCE;
515 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTxIQIMBALANCE;
516
517
518 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATxAFE;
519 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTxAFE;
520 rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTxAFE;
521 rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTxAFE;
522
523
524 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
525 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
526 rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;
527 rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;
528
529
530 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVERA_HSPI_READBACK;
531 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVERB_HSPI_READBACK;
532}
533
534static bool _rtl92d_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
535 u8 configtype)
536{
537 int i;
538 u32 *phy_regarray_table;
539 u32 *agctab_array_table = NULL;
540 u32 *agctab_5garray_table;
541 u16 phy_reg_arraylen, agctab_arraylen = 0, agctab_5garraylen;
542 struct rtl_priv *rtlpriv = rtl_priv(hw);
543 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
544
545
546 if (rtlhal->interfaceindex == 0) {
547 agctab_arraylen = AGCTAB_ARRAYLENGTH;
548 agctab_array_table = rtl8192de_agctab_array;
549 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
550 " ===> phy:MAC0, Rtl819XAGCTAB_Array\n");
551 } else {
552 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
553 agctab_arraylen = AGCTAB_2G_ARRAYLENGTH;
554 agctab_array_table = rtl8192de_agctab_2garray;
555 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
556 " ===> phy:MAC1, Rtl819XAGCTAB_2GArray\n");
557 } else {
558 agctab_5garraylen = AGCTAB_5G_ARRAYLENGTH;
559 agctab_5garray_table = rtl8192de_agctab_5garray;
560 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
561 " ===> phy:MAC1, Rtl819XAGCTAB_5GArray\n");
562
563 }
564 }
565 phy_reg_arraylen = PHY_REG_2T_ARRAYLENGTH;
566 phy_regarray_table = rtl8192de_phy_reg_2tarray;
567 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
568 " ===> phy:Rtl819XPHY_REG_Array_PG\n");
569 if (configtype == BASEBAND_CONFIG_PHY_REG) {
570 for (i = 0; i < phy_reg_arraylen; i = i + 2) {
571 rtl_addr_delay(phy_regarray_table[i]);
572 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
573 phy_regarray_table[i + 1]);
574 udelay(1);
575 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
576 "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
577 phy_regarray_table[i],
578 phy_regarray_table[i + 1]);
579 }
580 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
581 if (rtlhal->interfaceindex == 0) {
582 for (i = 0; i < agctab_arraylen; i = i + 2) {
583 rtl_set_bbreg(hw, agctab_array_table[i],
584 MASKDWORD,
585 agctab_array_table[i + 1]);
586
587
588 udelay(1);
589 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
590 "The Rtl819XAGCTAB_Array_Table[0] is %ul Rtl819XPHY_REGArray[1] is %ul\n",
591 agctab_array_table[i],
592 agctab_array_table[i + 1]);
593 }
594 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
595 "Normal Chip, MAC0, load Rtl819XAGCTAB_Array\n");
596 } else {
597 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
598 for (i = 0; i < agctab_arraylen; i = i + 2) {
599 rtl_set_bbreg(hw, agctab_array_table[i],
600 MASKDWORD,
601 agctab_array_table[i + 1]);
602
603
604 udelay(1);
605 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
606 "The Rtl819XAGCTAB_Array_Table[0] is %ul Rtl819XPHY_REGArray[1] is %ul\n",
607 agctab_array_table[i],
608 agctab_array_table[i + 1]);
609 }
610 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
611 "Load Rtl819XAGCTAB_2GArray\n");
612 } else {
613 for (i = 0; i < agctab_5garraylen; i = i + 2) {
614 rtl_set_bbreg(hw,
615 agctab_5garray_table[i],
616 MASKDWORD,
617 agctab_5garray_table[i + 1]);
618
619
620 udelay(1);
621 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
622 "The Rtl819XAGCTAB_5GArray_Table[0] is %ul Rtl819XPHY_REGArray[1] is %ul\n",
623 agctab_5garray_table[i],
624 agctab_5garray_table[i + 1]);
625 }
626 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
627 "Load Rtl819XAGCTAB_5GArray\n");
628 }
629 }
630 }
631 return true;
632}
633
634static void _rtl92d_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw,
635 u32 regaddr, u32 bitmask,
636 u32 data)
637{
638 struct rtl_priv *rtlpriv = rtl_priv(hw);
639 struct rtl_phy *rtlphy = &(rtlpriv->phy);
640 int index;
641
642 if (regaddr == RTXAGC_A_RATE18_06)
643 index = 0;
644 else if (regaddr == RTXAGC_A_RATE54_24)
645 index = 1;
646 else if (regaddr == RTXAGC_A_CCK1_MCS32)
647 index = 6;
648 else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00)
649 index = 7;
650 else if (regaddr == RTXAGC_A_MCS03_MCS00)
651 index = 2;
652 else if (regaddr == RTXAGC_A_MCS07_MCS04)
653 index = 3;
654 else if (regaddr == RTXAGC_A_MCS11_MCS08)
655 index = 4;
656 else if (regaddr == RTXAGC_A_MCS15_MCS12)
657 index = 5;
658 else if (regaddr == RTXAGC_B_RATE18_06)
659 index = 8;
660 else if (regaddr == RTXAGC_B_RATE54_24)
661 index = 9;
662 else if (regaddr == RTXAGC_B_CCK1_55_MCS32)
663 index = 14;
664 else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff)
665 index = 15;
666 else if (regaddr == RTXAGC_B_MCS03_MCS00)
667 index = 10;
668 else if (regaddr == RTXAGC_B_MCS07_MCS04)
669 index = 11;
670 else if (regaddr == RTXAGC_B_MCS11_MCS08)
671 index = 12;
672 else if (regaddr == RTXAGC_B_MCS15_MCS12)
673 index = 13;
674 else
675 return;
676
677 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index] = data;
678 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
679 "MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%ulx\n",
680 rtlphy->pwrgroup_cnt, index,
681 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index]);
682 if (index == 13)
683 rtlphy->pwrgroup_cnt++;
684}
685
686static bool _rtl92d_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
687 u8 configtype)
688{
689 struct rtl_priv *rtlpriv = rtl_priv(hw);
690 int i;
691 u32 *phy_regarray_table_pg;
692 u16 phy_regarray_pg_len;
693
694 phy_regarray_pg_len = PHY_REG_ARRAY_PG_LENGTH;
695 phy_regarray_table_pg = rtl8192de_phy_reg_array_pg;
696 if (configtype == BASEBAND_CONFIG_PHY_REG) {
697 for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
698 rtl_addr_delay(phy_regarray_table_pg[i]);
699 _rtl92d_store_pwrindex_diffrate_offset(hw,
700 phy_regarray_table_pg[i],
701 phy_regarray_table_pg[i + 1],
702 phy_regarray_table_pg[i + 2]);
703 }
704 } else {
705 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
706 "configtype != BaseBand_Config_PHY_REG\n");
707 }
708 return true;
709}
710
711static bool _rtl92d_phy_bb_config(struct ieee80211_hw *hw)
712{
713 struct rtl_priv *rtlpriv = rtl_priv(hw);
714 struct rtl_phy *rtlphy = &(rtlpriv->phy);
715 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
716 bool rtstatus = true;
717
718 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "==>\n");
719 rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw,
720 BASEBAND_CONFIG_PHY_REG);
721 if (!rtstatus) {
722 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Write BB Reg Fail!!\n");
723 return false;
724 }
725
726
727
728
729
730
731 if (rtlefuse->autoload_failflag == false) {
732 rtlphy->pwrgroup_cnt = 0;
733 rtstatus = _rtl92d_phy_config_bb_with_pgheaderfile(hw,
734 BASEBAND_CONFIG_PHY_REG);
735 }
736 if (!rtstatus) {
737 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "BB_PG Reg Fail!!\n");
738 return false;
739 }
740 rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw,
741 BASEBAND_CONFIG_AGC_TAB);
742 if (!rtstatus) {
743 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "AGC Table Fail\n");
744 return false;
745 }
746 rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw,
747 RFPGA0_XA_HSSIPARAMETER2, 0x200));
748
749 return true;
750}
751
752bool rtl92d_phy_bb_config(struct ieee80211_hw *hw)
753{
754 struct rtl_priv *rtlpriv = rtl_priv(hw);
755 u16 regval;
756 u32 regvaldw;
757 u8 value;
758
759 _rtl92d_phy_init_bb_rf_register_definition(hw);
760 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
761 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
762 regval | BIT(13) | BIT(0) | BIT(1));
763 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
764 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
765
766 value = rtl_read_byte(rtlpriv, REG_RF_CTRL);
767 rtl_write_byte(rtlpriv, REG_RF_CTRL, value | RF_EN | RF_RSTB |
768 RF_SDMRSTB);
769 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_PPLL | FEN_PCIEA |
770 FEN_DIO_PCIE | FEN_BB_GLB_RSTn | FEN_BBRSTB);
771 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
772 if (!(IS_92D_SINGLEPHY(rtlpriv->rtlhal.version))) {
773 regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0);
774 rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23));
775 }
776
777 return _rtl92d_phy_bb_config(hw);
778}
779
780bool rtl92d_phy_rf_config(struct ieee80211_hw *hw)
781{
782 return rtl92d_phy_rf6052_config(hw);
783}
784
785bool rtl92d_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
786 enum rf_content content,
787 enum radio_path rfpath)
788{
789 int i;
790 u32 *radioa_array_table;
791 u32 *radiob_array_table;
792 u16 radioa_arraylen, radiob_arraylen;
793 struct rtl_priv *rtlpriv = rtl_priv(hw);
794
795 radioa_arraylen = RADIOA_2T_ARRAYLENGTH;
796 radioa_array_table = rtl8192de_radioa_2tarray;
797 radiob_arraylen = RADIOB_2T_ARRAYLENGTH;
798 radiob_array_table = rtl8192de_radiob_2tarray;
799 if (rtlpriv->efuse.internal_pa_5g[0]) {
800 radioa_arraylen = RADIOA_2T_INT_PA_ARRAYLENGTH;
801 radioa_array_table = rtl8192de_radioa_2t_int_paarray;
802 }
803 if (rtlpriv->efuse.internal_pa_5g[1]) {
804 radiob_arraylen = RADIOB_2T_INT_PA_ARRAYLENGTH;
805 radiob_array_table = rtl8192de_radiob_2t_int_paarray;
806 }
807 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
808 "PHY_ConfigRFWithHeaderFile() Radio_A:Rtl819XRadioA_1TArray\n");
809 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
810 "PHY_ConfigRFWithHeaderFile() Radio_B:Rtl819XRadioB_1TArray\n");
811 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Radio No %x\n", rfpath);
812
813
814
815
816 if ((content == radiob_txt) && (rfpath == RF90_PATH_A)) {
817 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
818 " ===> althougth Path A, we load radiob.txt\n");
819 radioa_arraylen = radiob_arraylen;
820 radioa_array_table = radiob_array_table;
821 }
822 switch (rfpath) {
823 case RF90_PATH_A:
824 for (i = 0; i < radioa_arraylen; i = i + 2) {
825 rtl_rfreg_delay(hw, rfpath, radioa_array_table[i],
826 RFREG_OFFSET_MASK,
827 radioa_array_table[i + 1]);
828 }
829 break;
830 case RF90_PATH_B:
831 for (i = 0; i < radiob_arraylen; i = i + 2) {
832 rtl_rfreg_delay(hw, rfpath, radiob_array_table[i],
833 RFREG_OFFSET_MASK,
834 radiob_array_table[i + 1]);
835 }
836 break;
837 case RF90_PATH_C:
838 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
839 "switch case not processed\n");
840 break;
841 case RF90_PATH_D:
842 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
843 "switch case not processed\n");
844 break;
845 }
846 return true;
847}
848
849void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
850{
851 struct rtl_priv *rtlpriv = rtl_priv(hw);
852 struct rtl_phy *rtlphy = &(rtlpriv->phy);
853
854 rtlphy->default_initialgain[0] =
855 (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
856 rtlphy->default_initialgain[1] =
857 (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
858 rtlphy->default_initialgain[2] =
859 (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
860 rtlphy->default_initialgain[3] =
861 (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
862 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
863 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
864 rtlphy->default_initialgain[0],
865 rtlphy->default_initialgain[1],
866 rtlphy->default_initialgain[2],
867 rtlphy->default_initialgain[3]);
868 rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3,
869 MASKBYTE0);
870 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
871 MASKDWORD);
872 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
873 "Default framesync (0x%x) = 0x%x\n",
874 ROFDM0_RXDETECTOR3, rtlphy->framesync);
875}
876
877static void _rtl92d_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
878 u8 *cckpowerlevel, u8 *ofdmpowerlevel)
879{
880 struct rtl_priv *rtlpriv = rtl_priv(hw);
881 struct rtl_phy *rtlphy = &(rtlpriv->phy);
882 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
883 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
884 u8 index = (channel - 1);
885
886
887 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
888
889 cckpowerlevel[RF90_PATH_A] =
890 rtlefuse->txpwrlevel_cck[RF90_PATH_A][index];
891
892 cckpowerlevel[RF90_PATH_B] =
893 rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];
894 } else {
895 cckpowerlevel[RF90_PATH_A] = 0;
896 cckpowerlevel[RF90_PATH_B] = 0;
897 }
898
899 if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) {
900
901 ofdmpowerlevel[RF90_PATH_A] =
902 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index];
903 ofdmpowerlevel[RF90_PATH_B] =
904 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];
905 } else if (rtlphy->rf_type == RF_2T2R) {
906
907 ofdmpowerlevel[RF90_PATH_A] =
908 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index];
909 ofdmpowerlevel[RF90_PATH_B] =
910 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index];
911 }
912}
913
914static void _rtl92d_ccxpower_index_check(struct ieee80211_hw *hw,
915 u8 channel, u8 *cckpowerlevel, u8 *ofdmpowerlevel)
916{
917 struct rtl_priv *rtlpriv = rtl_priv(hw);
918 struct rtl_phy *rtlphy = &(rtlpriv->phy);
919
920 rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
921 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
922}
923
924static u8 _rtl92c_phy_get_rightchnlplace(u8 chnl)
925{
926 u8 channel_5g[59] = {
927 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
928 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,
929 60, 62, 64, 100, 102, 104, 106, 108, 110, 112,
930 114, 116, 118, 120, 122, 124, 126, 128,
931 130, 132, 134, 136, 138, 140, 149, 151,
932 153, 155, 157, 159, 161, 163, 165
933 };
934 u8 place = chnl;
935
936 if (chnl > 14) {
937 for (place = 14; place < sizeof(channel_5g); place++) {
938 if (channel_5g[place] == chnl) {
939 place++;
940 break;
941 }
942 }
943 }
944 return place;
945}
946
947void rtl92d_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
948{
949 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
950 struct rtl_priv *rtlpriv = rtl_priv(hw);
951 u8 cckpowerlevel[2], ofdmpowerlevel[2];
952
953 if (!rtlefuse->txpwr_fromeprom)
954 return;
955 channel = _rtl92c_phy_get_rightchnlplace(channel);
956 _rtl92d_get_txpower_index(hw, channel, &cckpowerlevel[0],
957 &ofdmpowerlevel[0]);
958 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G)
959 _rtl92d_ccxpower_index_check(hw, channel, &cckpowerlevel[0],
960 &ofdmpowerlevel[0]);
961 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G)
962 rtl92d_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);
963 rtl92d_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel);
964}
965
966void rtl92d_phy_set_bw_mode(struct ieee80211_hw *hw,
967 enum nl80211_channel_type ch_type)
968{
969 struct rtl_priv *rtlpriv = rtl_priv(hw);
970 struct rtl_phy *rtlphy = &(rtlpriv->phy);
971 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
972 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
973 unsigned long flag = 0;
974 u8 reg_prsr_rsc;
975 u8 reg_bw_opmode;
976
977 if (rtlphy->set_bwmode_inprogress)
978 return;
979 if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) {
980 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
981 "FALSE driver sleep or unload\n");
982 return;
983 }
984 rtlphy->set_bwmode_inprogress = true;
985 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
986 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
987 "20MHz" : "40MHz");
988 reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
989 reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
990 switch (rtlphy->current_chan_bw) {
991 case HT_CHANNEL_WIDTH_20:
992 reg_bw_opmode |= BW_OPMODE_20MHZ;
993 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
994 break;
995 case HT_CHANNEL_WIDTH_20_40:
996 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
997 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
998
999 reg_prsr_rsc = (reg_prsr_rsc & 0x90) |
1000 (mac->cur_40_prime_sc << 5);
1001 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
1002 break;
1003 default:
1004 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1005 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
1006 break;
1007 }
1008 switch (rtlphy->current_chan_bw) {
1009 case HT_CHANNEL_WIDTH_20:
1010 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
1011 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
1012
1013 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |
1014 BIT(11), 3);
1015 break;
1016 case HT_CHANNEL_WIDTH_20_40:
1017 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
1018 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
1019
1020
1021 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1022 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
1023 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCKSIDEBAND,
1024 (mac->cur_40_prime_sc >> 1));
1025 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
1026 }
1027 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
1028
1029 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |
1030 BIT(11), 0);
1031 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
1032 (mac->cur_40_prime_sc ==
1033 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
1034 break;
1035 default:
1036 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1037 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
1038 break;
1039
1040 }
1041 rtl92d_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
1042 rtlphy->set_bwmode_inprogress = false;
1043 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
1044}
1045
1046static void _rtl92d_phy_stop_trx_before_changeband(struct ieee80211_hw *hw)
1047{
1048 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0);
1049 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0);
1050 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x00);
1051 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x0);
1052}
1053
1054static void rtl92d_phy_switch_wirelessband(struct ieee80211_hw *hw, u8 band)
1055{
1056 struct rtl_priv *rtlpriv = rtl_priv(hw);
1057 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1058 u8 value8;
1059
1060 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n");
1061 rtlhal->bandset = band;
1062 rtlhal->current_bandtype = band;
1063 if (IS_92D_SINGLEPHY(rtlhal->version))
1064 rtlhal->bandset = BAND_ON_BOTH;
1065
1066 _rtl92d_phy_stop_trx_before_changeband(hw);
1067
1068 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1069
1070 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "====>2.4G\n");
1071 if (rtlhal->interfaceindex == 1)
1072 _rtl92d_phy_config_bb_with_headerfile(hw,
1073 BASEBAND_CONFIG_AGC_TAB);
1074 } else {
1075
1076 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "====>5G\n");
1077 if (rtlhal->interfaceindex == 1)
1078 _rtl92d_phy_config_bb_with_headerfile(hw,
1079 BASEBAND_CONFIG_AGC_TAB);
1080 }
1081 rtl92d_update_bbrf_configuration(hw);
1082 if (rtlhal->current_bandtype == BAND_ON_2_4G)
1083 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1084 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1085
1086
1087
1088 rtlhal->reloadtxpowerindex = true;
1089
1090 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1091 value8 = rtl_read_byte(rtlpriv, (rtlhal->interfaceindex ==
1092 0 ? REG_MAC0 : REG_MAC1));
1093 value8 |= BIT(1);
1094 rtl_write_byte(rtlpriv, (rtlhal->interfaceindex ==
1095 0 ? REG_MAC0 : REG_MAC1), value8);
1096 } else {
1097 value8 = rtl_read_byte(rtlpriv, (rtlhal->interfaceindex ==
1098 0 ? REG_MAC0 : REG_MAC1));
1099 value8 &= (~BIT(1));
1100 rtl_write_byte(rtlpriv, (rtlhal->interfaceindex ==
1101 0 ? REG_MAC0 : REG_MAC1), value8);
1102 }
1103 mdelay(1);
1104 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<==Switch Band OK\n");
1105}
1106
1107static void _rtl92d_phy_reload_imr_setting(struct ieee80211_hw *hw,
1108 u8 channel, u8 rfpath)
1109{
1110 struct rtl_priv *rtlpriv = rtl_priv(hw);
1111 u32 imr_num = MAX_RF_IMR_INDEX;
1112 u32 rfmask = RFREG_OFFSET_MASK;
1113 u8 group, i;
1114 unsigned long flag = 0;
1115
1116 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>path %d\n", rfpath);
1117 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {
1118 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n");
1119 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0);
1120 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
1121
1122 if (channel > 99)
1123 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) |
1124 BIT(14), 2);
1125 else
1126 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) |
1127 BIT(14), 1);
1128
1129 group = channel <= 64 ? 1 : 2;
1130 imr_num = MAX_RF_IMR_INDEX_NORMAL;
1131 for (i = 0; i < imr_num; i++)
1132 rtl_set_rfreg(hw, (enum radio_path)rfpath,
1133 rf_reg_for_5g_swchnl_normal[i], rfmask,
1134 rf_imr_param_normal[0][group][i]);
1135 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0);
1136 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 1);
1137 } else {
1138
1139 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
1140 "Load RF IMR parameters for G band. IMR already setting %d\n",
1141 rtlpriv->rtlhal.load_imrandiqk_setting_for2g);
1142 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n");
1143 if (!rtlpriv->rtlhal.load_imrandiqk_setting_for2g) {
1144 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
1145 "Load RF IMR parameters for G band. %d\n",
1146 rfpath);
1147 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
1148 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0);
1149 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4,
1150 0x00f00000, 0xf);
1151 imr_num = MAX_RF_IMR_INDEX_NORMAL;
1152 for (i = 0; i < imr_num; i++) {
1153 rtl_set_rfreg(hw, (enum radio_path)rfpath,
1154 rf_reg_for_5g_swchnl_normal[i],
1155 RFREG_OFFSET_MASK,
1156 rf_imr_param_normal[0][0][i]);
1157 }
1158 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4,
1159 0x00f00000, 0);
1160 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN | BCCKEN, 3);
1161 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
1162 }
1163 }
1164 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
1165}
1166
1167static void _rtl92d_phy_enable_rf_env(struct ieee80211_hw *hw,
1168 u8 rfpath, u32 *pu4_regval)
1169{
1170 struct rtl_priv *rtlpriv = rtl_priv(hw);
1171 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1172 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
1173
1174 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "====>\n");
1175
1176 switch (rfpath) {
1177 case RF90_PATH_A:
1178 case RF90_PATH_C:
1179 *pu4_regval = rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV);
1180 break;
1181 case RF90_PATH_B:
1182 case RF90_PATH_D:
1183 *pu4_regval =
1184 rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16);
1185 break;
1186 }
1187
1188 rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
1189 udelay(1);
1190
1191 rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
1192 udelay(1);
1193
1194
1195 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREADDRESSLENGTH, 0x0);
1196 udelay(1);
1197
1198 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
1199 udelay(1);
1200 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "<====\n");
1201}
1202
1203static void _rtl92d_phy_restore_rf_env(struct ieee80211_hw *hw, u8 rfpath,
1204 u32 *pu4_regval)
1205{
1206 struct rtl_priv *rtlpriv = rtl_priv(hw);
1207 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1208 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
1209
1210 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "=====>\n");
1211
1212 switch (rfpath) {
1213 case RF90_PATH_A:
1214 case RF90_PATH_C:
1215 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV, *pu4_regval);
1216 break;
1217 case RF90_PATH_B:
1218 case RF90_PATH_D:
1219 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16,
1220 *pu4_regval);
1221 break;
1222 }
1223 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "<=====\n");
1224}
1225
1226static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel)
1227{
1228 struct rtl_priv *rtlpriv = rtl_priv(hw);
1229 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1230 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
1231 u8 path = rtlhal->current_bandtype ==
1232 BAND_ON_5G ? RF90_PATH_A : RF90_PATH_B;
1233 u8 index = 0, i = 0, rfpath = RF90_PATH_A;
1234 bool need_pwr_down = false, internal_pa = false;
1235 u32 u4regvalue, mask = 0x1C000, value = 0, u4tmp, u4tmp2;
1236
1237 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>\n");
1238
1239 if (rtlhal->current_bandtype == BAND_ON_5G) {
1240 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n");
1241 u4tmp = curveindex_5g[channel - 1];
1242 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1243 "ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp);
1244 for (i = 0; i < RF_CHNL_NUM_5G; i++) {
1245 if (channel == rf_chnl_5g[i] && channel <= 140)
1246 index = 0;
1247 }
1248 for (i = 0; i < RF_CHNL_NUM_5G_40M; i++) {
1249 if (channel == rf_chnl_5g_40m[i] && channel <= 140)
1250 index = 1;
1251 }
1252 if (channel == 149 || channel == 155 || channel == 161)
1253 index = 2;
1254 else if (channel == 151 || channel == 153 || channel == 163
1255 || channel == 165)
1256 index = 3;
1257 else if (channel == 157 || channel == 159)
1258 index = 4;
1259
1260 if (rtlhal->macphymode == DUALMAC_DUALPHY
1261 && rtlhal->interfaceindex == 1) {
1262 need_pwr_down = rtl92d_phy_enable_anotherphy(hw, false);
1263 rtlhal->during_mac1init_radioa = true;
1264
1265 if (need_pwr_down)
1266 _rtl92d_phy_enable_rf_env(hw, path,
1267 &u4regvalue);
1268 }
1269 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_5G; i++) {
1270 if (i == 0 && (rtlhal->macphymode == DUALMAC_DUALPHY)) {
1271 rtl_set_rfreg(hw, (enum radio_path)path,
1272 rf_reg_for_c_cut_5g[i],
1273 RFREG_OFFSET_MASK, 0xE439D);
1274 } else if (rf_reg_for_c_cut_5g[i] == RF_SYN_G4) {
1275 u4tmp2 = (rf_reg_pram_c_5g[index][i] &
1276 0x7FF) | (u4tmp << 11);
1277 if (channel == 36)
1278 u4tmp2 &= ~(BIT(7) | BIT(6));
1279 rtl_set_rfreg(hw, (enum radio_path)path,
1280 rf_reg_for_c_cut_5g[i],
1281 RFREG_OFFSET_MASK, u4tmp2);
1282 } else {
1283 rtl_set_rfreg(hw, (enum radio_path)path,
1284 rf_reg_for_c_cut_5g[i],
1285 RFREG_OFFSET_MASK,
1286 rf_reg_pram_c_5g[index][i]);
1287 }
1288 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
1289 "offset 0x%x value 0x%x path %d index %d readback 0x%x\n",
1290 rf_reg_for_c_cut_5g[i],
1291 rf_reg_pram_c_5g[index][i],
1292 path, index,
1293 rtl_get_rfreg(hw, (enum radio_path)path,
1294 rf_reg_for_c_cut_5g[i],
1295 RFREG_OFFSET_MASK));
1296 }
1297 if (need_pwr_down)
1298 _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue);
1299 if (rtlhal->during_mac1init_radioa)
1300 rtl92d_phy_powerdown_anotherphy(hw, false);
1301 if (channel < 149)
1302 value = 0x07;
1303 else if (channel >= 149)
1304 value = 0x02;
1305 if (channel >= 36 && channel <= 64)
1306 index = 0;
1307 else if (channel >= 100 && channel <= 140)
1308 index = 1;
1309 else
1310 index = 2;
1311 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
1312 rfpath++) {
1313 if (rtlhal->macphymode == DUALMAC_DUALPHY &&
1314 rtlhal->interfaceindex == 1)
1315 internal_pa = rtlpriv->efuse.internal_pa_5g[1];
1316 else
1317 internal_pa =
1318 rtlpriv->efuse.internal_pa_5g[rfpath];
1319 if (internal_pa) {
1320 for (i = 0;
1321 i < RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA;
1322 i++) {
1323 rtl_set_rfreg(hw, rfpath,
1324 rf_for_c_cut_5g_internal_pa[i],
1325 RFREG_OFFSET_MASK,
1326 rf_pram_c_5g_int_pa[index][i]);
1327 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
1328 "offset 0x%x value 0x%x path %d index %d\n",
1329 rf_for_c_cut_5g_internal_pa[i],
1330 rf_pram_c_5g_int_pa[index][i],
1331 rfpath, index);
1332 }
1333 } else {
1334 rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B,
1335 mask, value);
1336 }
1337 }
1338 } else if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1339 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n");
1340 u4tmp = curveindex_2g[channel - 1];
1341 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1342 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp);
1343 if (channel == 1 || channel == 2 || channel == 4 || channel == 9
1344 || channel == 10 || channel == 11 || channel == 12)
1345 index = 0;
1346 else if (channel == 3 || channel == 13 || channel == 14)
1347 index = 1;
1348 else if (channel >= 5 && channel <= 8)
1349 index = 2;
1350 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
1351 path = RF90_PATH_A;
1352 if (rtlhal->interfaceindex == 0) {
1353 need_pwr_down =
1354 rtl92d_phy_enable_anotherphy(hw, true);
1355 rtlhal->during_mac0init_radiob = true;
1356
1357 if (need_pwr_down)
1358 _rtl92d_phy_enable_rf_env(hw, path,
1359 &u4regvalue);
1360 }
1361 }
1362 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_2G; i++) {
1363 if (rf_reg_for_c_cut_2g[i] == RF_SYN_G7)
1364 rtl_set_rfreg(hw, (enum radio_path)path,
1365 rf_reg_for_c_cut_2g[i],
1366 RFREG_OFFSET_MASK,
1367 (rf_reg_param_for_c_cut_2g[index][i] |
1368 BIT(17)));
1369 else
1370 rtl_set_rfreg(hw, (enum radio_path)path,
1371 rf_reg_for_c_cut_2g[i],
1372 RFREG_OFFSET_MASK,
1373 rf_reg_param_for_c_cut_2g
1374 [index][i]);
1375 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
1376 "offset 0x%x value 0x%x mak 0x%x path %d index %d readback 0x%x\n",
1377 rf_reg_for_c_cut_2g[i],
1378 rf_reg_param_for_c_cut_2g[index][i],
1379 rf_reg_mask_for_c_cut_2g[i], path, index,
1380 rtl_get_rfreg(hw, (enum radio_path)path,
1381 rf_reg_for_c_cut_2g[i],
1382 RFREG_OFFSET_MASK));
1383 }
1384 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1385 "cosa ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n",
1386 rf_syn_g4_for_c_cut_2g | (u4tmp << 11));
1387
1388 rtl_set_rfreg(hw, (enum radio_path)path, RF_SYN_G4,
1389 RFREG_OFFSET_MASK,
1390 rf_syn_g4_for_c_cut_2g | (u4tmp << 11));
1391 if (need_pwr_down)
1392 _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue);
1393 if (rtlhal->during_mac0init_radiob)
1394 rtl92d_phy_powerdown_anotherphy(hw, true);
1395 }
1396 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
1397}
1398
1399u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl)
1400{
1401 u8 channel_all[59] = {
1402 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
1403 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,
1404 60, 62, 64, 100, 102, 104, 106, 108, 110, 112,
1405 114, 116, 118, 120, 122, 124, 126, 128, 130,
1406 132, 134, 136, 138, 140, 149, 151, 153, 155,
1407 157, 159, 161, 163, 165
1408 };
1409 u8 place = chnl;
1410
1411 if (chnl > 14) {
1412 for (place = 14; place < sizeof(channel_all); place++) {
1413 if (channel_all[place] == chnl)
1414 return place - 13;
1415 }
1416 }
1417
1418 return 0;
1419}
1420
1421#define MAX_TOLERANCE 5
1422#define IQK_DELAY_TIME 1
1423#define MAX_TOLERANCE_92D 3
1424
1425
1426static u8 _rtl92d_phy_patha_iqk(struct ieee80211_hw *hw, bool configpathb)
1427{
1428 struct rtl_priv *rtlpriv = rtl_priv(hw);
1429 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1430 u32 regeac, rege94, rege9c, regea4;
1431 u8 result = 0;
1432
1433 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK!\n");
1434
1435 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n");
1436 if (rtlhal->interfaceindex == 0) {
1437 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f);
1438 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f);
1439 } else {
1440 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c22);
1441 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c22);
1442 }
1443 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102);
1444 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160206);
1445
1446 if (configpathb) {
1447 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22);
1448 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22);
1449 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102);
1450 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160206);
1451 }
1452
1453 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n");
1454 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911);
1455
1456 RTPRINT(rtlpriv, FINIT, INIT_IQK, "One shot, path A LOK & IQK!\n");
1457 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
1458 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1459
1460 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1461 "Delay %d ms for One shot, path A LOK & IQK\n",
1462 IQK_DELAY_TIME);
1463 mdelay(IQK_DELAY_TIME);
1464
1465 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1466 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac);
1467 rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1468 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94);
1469 rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1470 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c);
1471 regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
1472 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4);
1473 if (!(regeac & BIT(28)) && (((rege94 & 0x03FF0000) >> 16) != 0x142) &&
1474 (((rege9c & 0x03FF0000) >> 16) != 0x42))
1475 result |= 0x01;
1476 else
1477 return result;
1478
1479 if (!(regeac & BIT(27)) && (((regea4 & 0x03FF0000) >> 16) != 0x132) &&
1480 (((regeac & 0x03FF0000) >> 16) != 0x36))
1481 result |= 0x02;
1482 else
1483 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A Rx IQK fail!!\n");
1484 return result;
1485}
1486
1487
1488static u8 _rtl92d_phy_patha_iqk_5g_normal(struct ieee80211_hw *hw,
1489 bool configpathb)
1490{
1491 struct rtl_priv *rtlpriv = rtl_priv(hw);
1492 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1493 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1494 u32 regeac, rege94, rege9c, regea4;
1495 u8 result = 0;
1496 u8 i;
1497 u8 retrycount = 2;
1498 u32 TxOKBit = BIT(28), RxOKBit = BIT(27);
1499
1500 if (rtlhal->interfaceindex == 1) {
1501 TxOKBit = BIT(31);
1502 RxOKBit = BIT(30);
1503 }
1504 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK!\n");
1505
1506 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n");
1507 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f);
1508 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f);
1509 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140307);
1510 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68160960);
1511
1512 if (configpathb) {
1513 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f);
1514 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f);
1515 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82110000);
1516 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68110000);
1517 }
1518
1519 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n");
1520 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911);
1521
1522 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x07000f60);
1523 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, 0x66e60e30);
1524 for (i = 0; i < retrycount; i++) {
1525
1526 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1527 "One shot, path A LOK & IQK!\n");
1528 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
1529 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1530
1531 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1532 "Delay %d ms for One shot, path A LOK & IQK.\n",
1533 IQK_DELAY_TIME);
1534 mdelay(IQK_DELAY_TIME * 10);
1535
1536 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1537 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac);
1538 rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1539 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94);
1540 rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1541 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c);
1542 regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
1543 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4);
1544 if (!(regeac & TxOKBit) &&
1545 (((rege94 & 0x03FF0000) >> 16) != 0x142)) {
1546 result |= 0x01;
1547 } else {
1548 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1549 "Path A Tx IQK fail!!\n");
1550 continue;
1551 }
1552
1553
1554 if (!(regeac & RxOKBit) &&
1555 (((regea4 & 0x03FF0000) >> 16) != 0x132)) {
1556 result |= 0x02;
1557 break;
1558 } else {
1559 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1560 "Path A Rx IQK fail!!\n");
1561 }
1562 }
1563
1564 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD,
1565 rtlphy->iqk_bb_backup[0]);
1566 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD,
1567 rtlphy->iqk_bb_backup[1]);
1568 return result;
1569}
1570
1571
1572static u8 _rtl92d_phy_pathb_iqk(struct ieee80211_hw *hw)
1573{
1574 struct rtl_priv *rtlpriv = rtl_priv(hw);
1575 u32 regeac, regeb4, regebc, regec4, regecc;
1576 u8 result = 0;
1577
1578 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQK!\n");
1579
1580 RTPRINT(rtlpriv, FINIT, INIT_IQK, "One shot, path A LOK & IQK!\n");
1581 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002);
1582 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000);
1583
1584 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1585 "Delay %d ms for One shot, path B LOK & IQK\n", IQK_DELAY_TIME);
1586 mdelay(IQK_DELAY_TIME);
1587
1588 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1589 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac);
1590 regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
1591 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4);
1592 regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
1593 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc);
1594 regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
1595 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4);
1596 regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
1597 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc);
1598 if (!(regeac & BIT(31)) && (((regeb4 & 0x03FF0000) >> 16) != 0x142) &&
1599 (((regebc & 0x03FF0000) >> 16) != 0x42))
1600 result |= 0x01;
1601 else
1602 return result;
1603 if (!(regeac & BIT(30)) && (((regec4 & 0x03FF0000) >> 16) != 0x132) &&
1604 (((regecc & 0x03FF0000) >> 16) != 0x36))
1605 result |= 0x02;
1606 else
1607 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B Rx IQK fail!!\n");
1608 return result;
1609}
1610
1611
1612static u8 _rtl92d_phy_pathb_iqk_5g_normal(struct ieee80211_hw *hw)
1613{
1614 struct rtl_priv *rtlpriv = rtl_priv(hw);
1615 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1616 u32 regeac, regeb4, regebc, regec4, regecc;
1617 u8 result = 0;
1618 u8 i;
1619 u8 retrycount = 2;
1620
1621 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQK!\n");
1622
1623 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n");
1624 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f);
1625 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f);
1626 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82110000);
1627 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68110000);
1628
1629
1630 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f);
1631 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f);
1632 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140307);
1633 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68160960);
1634
1635
1636 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n");
1637 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911);
1638
1639
1640 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x0f600700);
1641 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, 0x061f0d30);
1642
1643 for (i = 0; i < retrycount; i++) {
1644
1645 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1646 "One shot, path A LOK & IQK!\n");
1647 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xfa000000);
1648 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1649
1650
1651 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1652 "Delay %d ms for One shot, path B LOK & IQK.\n", 10);
1653 mdelay(IQK_DELAY_TIME * 10);
1654
1655
1656 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1657 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac);
1658 regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
1659 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4);
1660 regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
1661 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc);
1662 regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
1663 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4);
1664 regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
1665 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc);
1666 if (!(regeac & BIT(31)) &&
1667 (((regeb4 & 0x03FF0000) >> 16) != 0x142))
1668 result |= 0x01;
1669 else
1670 continue;
1671 if (!(regeac & BIT(30)) &&
1672 (((regec4 & 0x03FF0000) >> 16) != 0x132)) {
1673 result |= 0x02;
1674 break;
1675 } else {
1676 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1677 "Path B Rx IQK fail!!\n");
1678 }
1679 }
1680
1681
1682 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD,
1683 rtlphy->iqk_bb_backup[0]);
1684 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD,
1685 rtlphy->iqk_bb_backup[2]);
1686 return result;
1687}
1688
1689static void _rtl92d_phy_save_adda_registers(struct ieee80211_hw *hw,
1690 u32 *adda_reg, u32 *adda_backup,
1691 u32 regnum)
1692{
1693 struct rtl_priv *rtlpriv = rtl_priv(hw);
1694 u32 i;
1695
1696 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Save ADDA parameters.\n");
1697 for (i = 0; i < regnum; i++)
1698 adda_backup[i] = rtl_get_bbreg(hw, adda_reg[i], MASKDWORD);
1699}
1700
1701static void _rtl92d_phy_save_mac_registers(struct ieee80211_hw *hw,
1702 u32 *macreg, u32 *macbackup)
1703{
1704 struct rtl_priv *rtlpriv = rtl_priv(hw);
1705 u32 i;
1706
1707 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Save MAC parameters.\n");
1708 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1709 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
1710 macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
1711}
1712
1713static void _rtl92d_phy_reload_adda_registers(struct ieee80211_hw *hw,
1714 u32 *adda_reg, u32 *adda_backup,
1715 u32 regnum)
1716{
1717 struct rtl_priv *rtlpriv = rtl_priv(hw);
1718 u32 i;
1719
1720 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1721 "Reload ADDA power saving parameters !\n");
1722 for (i = 0; i < regnum; i++)
1723 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, adda_backup[i]);
1724}
1725
1726static void _rtl92d_phy_reload_mac_registers(struct ieee80211_hw *hw,
1727 u32 *macreg, u32 *macbackup)
1728{
1729 struct rtl_priv *rtlpriv = rtl_priv(hw);
1730 u32 i;
1731
1732 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Reload MAC parameters !\n");
1733 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1734 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]);
1735 rtl_write_byte(rtlpriv, macreg[i], macbackup[i]);
1736}
1737
1738static void _rtl92d_phy_path_adda_on(struct ieee80211_hw *hw,
1739 u32 *adda_reg, bool patha_on, bool is2t)
1740{
1741 struct rtl_priv *rtlpriv = rtl_priv(hw);
1742 u32 pathon;
1743 u32 i;
1744
1745 RTPRINT(rtlpriv, FINIT, INIT_IQK, "ADDA ON.\n");
1746 pathon = patha_on ? 0x04db25a4 : 0x0b1b25a4;
1747 if (patha_on)
1748 pathon = rtlpriv->rtlhal.interfaceindex == 0 ?
1749 0x04db25a4 : 0x0b1b25a4;
1750 for (i = 0; i < IQK_ADDA_REG_NUM; i++)
1751 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, pathon);
1752}
1753
1754static void _rtl92d_phy_mac_setting_calibration(struct ieee80211_hw *hw,
1755 u32 *macreg, u32 *macbackup)
1756{
1757 struct rtl_priv *rtlpriv = rtl_priv(hw);
1758 u32 i;
1759
1760 RTPRINT(rtlpriv, FINIT, INIT_IQK, "MAC settings for Calibration.\n");
1761 rtl_write_byte(rtlpriv, macreg[0], 0x3F);
1762
1763 for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
1764 rtl_write_byte(rtlpriv, macreg[i], (u8)(macbackup[i] &
1765 (~BIT(3))));
1766 rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5))));
1767}
1768
1769static void _rtl92d_phy_patha_standby(struct ieee80211_hw *hw)
1770{
1771 struct rtl_priv *rtlpriv = rtl_priv(hw);
1772 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A standby mode!\n");
1773
1774 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
1775 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, 0x00010000);
1776 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1777}
1778
1779static void _rtl92d_phy_pimode_switch(struct ieee80211_hw *hw, bool pi_mode)
1780{
1781 struct rtl_priv *rtlpriv = rtl_priv(hw);
1782 u32 mode;
1783
1784 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1785 "BB Switch to %s mode!\n", pi_mode ? "PI" : "SI");
1786 mode = pi_mode ? 0x01000100 : 0x01000000;
1787 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);
1788 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);
1789}
1790
1791static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
1792 u8 t, bool is2t)
1793{
1794 struct rtl_priv *rtlpriv = rtl_priv(hw);
1795 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1796 u32 i;
1797 u8 patha_ok, pathb_ok;
1798 static u32 adda_reg[IQK_ADDA_REG_NUM] = {
1799 RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74,
1800 0xe78, 0xe7c, 0xe80, 0xe84,
1801 0xe88, 0xe8c, 0xed0, 0xed4,
1802 0xed8, 0xedc, 0xee0, 0xeec
1803 };
1804 static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1805 0x522, 0x550, 0x551, 0x040
1806 };
1807 static u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
1808 RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE,
1809 RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR,
1810 RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE,
1811 RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4,
1812 ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1
1813 };
1814 const u32 retrycount = 2;
1815 u32 bbvalue;
1816
1817 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK for 2.4G :Start!!!\n");
1818 if (t == 0) {
1819 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD);
1820 RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue);
1821 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n",
1822 is2t ? "2T2R" : "1T1R");
1823
1824
1825 _rtl92d_phy_save_adda_registers(hw, adda_reg,
1826 rtlphy->adda_backup, IQK_ADDA_REG_NUM);
1827 _rtl92d_phy_save_mac_registers(hw, iqk_mac_reg,
1828 rtlphy->iqk_mac_backup);
1829 _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
1830 rtlphy->iqk_bb_backup, IQK_BB_REG_NUM);
1831 }
1832 _rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t);
1833 if (t == 0)
1834 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
1835 RFPGA0_XA_HSSIPARAMETER1, BIT(8));
1836
1837
1838 if (!rtlphy->rfpi_enable)
1839 _rtl92d_phy_pimode_switch(hw, true);
1840
1841 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00);
1842 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600);
1843 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4);
1844 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22204000);
1845 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f);
1846 if (is2t) {
1847 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD,
1848 0x00010000);
1849 rtl_set_bbreg(hw, RFPGA0_XB_LSSIPARAMETER, MASKDWORD,
1850 0x00010000);
1851 }
1852
1853 _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg,
1854 rtlphy->iqk_mac_backup);
1855
1856 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000);
1857 if (is2t)
1858 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000);
1859
1860 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK setting!\n");
1861 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1862 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00);
1863 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
1864 for (i = 0; i < retrycount; i++) {
1865 patha_ok = _rtl92d_phy_patha_iqk(hw, is2t);
1866 if (patha_ok == 0x03) {
1867 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1868 "Path A IQK Success!!\n");
1869 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1870 0x3FF0000) >> 16;
1871 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1872 0x3FF0000) >> 16;
1873 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
1874 0x3FF0000) >> 16;
1875 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
1876 0x3FF0000) >> 16;
1877 break;
1878 } else if (i == (retrycount - 1) && patha_ok == 0x01) {
1879
1880 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1881 "Path A IQK Only Tx Success!!\n");
1882
1883 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1884 0x3FF0000) >> 16;
1885 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1886 0x3FF0000) >> 16;
1887 }
1888 }
1889 if (0x00 == patha_ok)
1890 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK failed!!\n");
1891 if (is2t) {
1892 _rtl92d_phy_patha_standby(hw);
1893
1894 _rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t);
1895 for (i = 0; i < retrycount; i++) {
1896 pathb_ok = _rtl92d_phy_pathb_iqk(hw);
1897 if (pathb_ok == 0x03) {
1898 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1899 "Path B IQK Success!!\n");
1900 result[t][4] = (rtl_get_bbreg(hw, 0xeb4,
1901 MASKDWORD) & 0x3FF0000) >> 16;
1902 result[t][5] = (rtl_get_bbreg(hw, 0xebc,
1903 MASKDWORD) & 0x3FF0000) >> 16;
1904 result[t][6] = (rtl_get_bbreg(hw, 0xec4,
1905 MASKDWORD) & 0x3FF0000) >> 16;
1906 result[t][7] = (rtl_get_bbreg(hw, 0xecc,
1907 MASKDWORD) & 0x3FF0000) >> 16;
1908 break;
1909 } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
1910
1911 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1912 "Path B Only Tx IQK Success!!\n");
1913 result[t][4] = (rtl_get_bbreg(hw, 0xeb4,
1914 MASKDWORD) & 0x3FF0000) >> 16;
1915 result[t][5] = (rtl_get_bbreg(hw, 0xebc,
1916 MASKDWORD) & 0x3FF0000) >> 16;
1917 }
1918 }
1919 if (0x00 == pathb_ok)
1920 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1921 "Path B IQK failed!!\n");
1922 }
1923
1924
1925 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1926 "IQK:Back to BB mode, load original value!\n");
1927
1928 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
1929 if (t != 0) {
1930
1931 if (!rtlphy->rfpi_enable)
1932 _rtl92d_phy_pimode_switch(hw, false);
1933
1934 _rtl92d_phy_reload_adda_registers(hw, adda_reg,
1935 rtlphy->adda_backup, IQK_ADDA_REG_NUM);
1936
1937 _rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg,
1938 rtlphy->iqk_mac_backup);
1939 if (is2t)
1940 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
1941 rtlphy->iqk_bb_backup,
1942 IQK_BB_REG_NUM);
1943 else
1944 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
1945 rtlphy->iqk_bb_backup,
1946 IQK_BB_REG_NUM - 1);
1947
1948 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00);
1949 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00);
1950 }
1951 RTPRINT(rtlpriv, FINIT, INIT_IQK, "<==\n");
1952}
1953
1954static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw,
1955 long result[][8], u8 t)
1956{
1957 struct rtl_priv *rtlpriv = rtl_priv(hw);
1958 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1959 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
1960 u8 patha_ok, pathb_ok;
1961 static u32 adda_reg[IQK_ADDA_REG_NUM] = {
1962 RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74,
1963 0xe78, 0xe7c, 0xe80, 0xe84,
1964 0xe88, 0xe8c, 0xed0, 0xed4,
1965 0xed8, 0xedc, 0xee0, 0xeec
1966 };
1967 static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1968 0x522, 0x550, 0x551, 0x040
1969 };
1970 static u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
1971 RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE,
1972 RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR,
1973 RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE,
1974 RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4,
1975 ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1
1976 };
1977 u32 bbvalue;
1978 bool is2t = IS_92D_SINGLEPHY(rtlhal->version);
1979
1980
1981
1982
1983 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK for 5G NORMAL:Start!!!\n");
1984 mdelay(IQK_DELAY_TIME * 20);
1985 if (t == 0) {
1986 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD);
1987 RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue);
1988 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n",
1989 is2t ? "2T2R" : "1T1R");
1990
1991 _rtl92d_phy_save_adda_registers(hw, adda_reg,
1992 rtlphy->adda_backup,
1993 IQK_ADDA_REG_NUM);
1994 _rtl92d_phy_save_mac_registers(hw, iqk_mac_reg,
1995 rtlphy->iqk_mac_backup);
1996 if (is2t)
1997 _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
1998 rtlphy->iqk_bb_backup,
1999 IQK_BB_REG_NUM);
2000 else
2001 _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
2002 rtlphy->iqk_bb_backup,
2003 IQK_BB_REG_NUM - 1);
2004 }
2005 _rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t);
2006
2007 _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg,
2008 rtlphy->iqk_mac_backup);
2009 if (t == 0)
2010 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
2011 RFPGA0_XA_HSSIPARAMETER1, BIT(8));
2012
2013 if (!rtlphy->rfpi_enable)
2014 _rtl92d_phy_pimode_switch(hw, true);
2015 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00);
2016 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600);
2017 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4);
2018 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208000);
2019 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f);
2020
2021
2022 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000);
2023 if (is2t)
2024 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000);
2025
2026 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK setting!\n");
2027 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
2028 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x10007c00);
2029 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
2030 patha_ok = _rtl92d_phy_patha_iqk_5g_normal(hw, is2t);
2031 if (patha_ok == 0x03) {
2032 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK Success!!\n");
2033 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
2034 0x3FF0000) >> 16;
2035 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
2036 0x3FF0000) >> 16;
2037 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
2038 0x3FF0000) >> 16;
2039 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
2040 0x3FF0000) >> 16;
2041 } else if (patha_ok == 0x01) {
2042 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2043 "Path A IQK Only Tx Success!!\n");
2044
2045 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
2046 0x3FF0000) >> 16;
2047 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
2048 0x3FF0000) >> 16;
2049 } else {
2050 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK Fail!!\n");
2051 }
2052 if (is2t) {
2053
2054
2055 _rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t);
2056 pathb_ok = _rtl92d_phy_pathb_iqk_5g_normal(hw);
2057 if (pathb_ok == 0x03) {
2058 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2059 "Path B IQK Success!!\n");
2060 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) &
2061 0x3FF0000) >> 16;
2062 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
2063 0x3FF0000) >> 16;
2064 result[t][6] = (rtl_get_bbreg(hw, 0xec4, MASKDWORD) &
2065 0x3FF0000) >> 16;
2066 result[t][7] = (rtl_get_bbreg(hw, 0xecc, MASKDWORD) &
2067 0x3FF0000) >> 16;
2068 } else if (pathb_ok == 0x01) {
2069 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2070 "Path B Only Tx IQK Success!!\n");
2071 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) &
2072 0x3FF0000) >> 16;
2073 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
2074 0x3FF0000) >> 16;
2075 } else {
2076 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2077 "Path B IQK failed!!\n");
2078 }
2079 }
2080
2081
2082 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2083 "IQK:Back to BB mode, load original value!\n");
2084 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
2085 if (t != 0) {
2086 if (is2t)
2087 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2088 rtlphy->iqk_bb_backup,
2089 IQK_BB_REG_NUM);
2090 else
2091 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2092 rtlphy->iqk_bb_backup,
2093 IQK_BB_REG_NUM - 1);
2094
2095 _rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg,
2096 rtlphy->iqk_mac_backup);
2097
2098 if (!rtlphy->rfpi_enable)
2099 _rtl92d_phy_pimode_switch(hw, false);
2100
2101 _rtl92d_phy_reload_adda_registers(hw, adda_reg,
2102 rtlphy->adda_backup,
2103 IQK_ADDA_REG_NUM);
2104 }
2105 RTPRINT(rtlpriv, FINIT, INIT_IQK, "<==\n");
2106}
2107
2108static bool _rtl92d_phy_simularity_compare(struct ieee80211_hw *hw,
2109 long result[][8], u8 c1, u8 c2)
2110{
2111 struct rtl_priv *rtlpriv = rtl_priv(hw);
2112 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2113 u32 i, j, diff, sim_bitmap, bound;
2114 u8 final_candidate[2] = {0xFF, 0xFF};
2115 bool bresult = true;
2116 bool is2t = IS_92D_SINGLEPHY(rtlhal->version);
2117
2118 if (is2t)
2119 bound = 8;
2120 else
2121 bound = 4;
2122 sim_bitmap = 0;
2123 for (i = 0; i < bound; i++) {
2124 diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] -
2125 result[c2][i]) : (result[c2][i] - result[c1][i]);
2126 if (diff > MAX_TOLERANCE_92D) {
2127 if ((i == 2 || i == 6) && !sim_bitmap) {
2128 if (result[c1][i] + result[c1][i + 1] == 0)
2129 final_candidate[(i / 4)] = c2;
2130 else if (result[c2][i] + result[c2][i + 1] == 0)
2131 final_candidate[(i / 4)] = c1;
2132 else
2133 sim_bitmap = sim_bitmap | (1 << i);
2134 } else {
2135 sim_bitmap = sim_bitmap | (1 << i);
2136 }
2137 }
2138 }
2139 if (sim_bitmap == 0) {
2140 for (i = 0; i < (bound / 4); i++) {
2141 if (final_candidate[i] != 0xFF) {
2142 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2143 result[3][j] =
2144 result[final_candidate[i]][j];
2145 bresult = false;
2146 }
2147 }
2148 return bresult;
2149 }
2150 if (!(sim_bitmap & 0x0F)) {
2151 for (i = 0; i < 4; i++)
2152 result[3][i] = result[c1][i];
2153 } else if (!(sim_bitmap & 0x03)) {
2154 for (i = 0; i < 2; i++)
2155 result[3][i] = result[c1][i];
2156 }
2157 if (!(sim_bitmap & 0xF0) && is2t) {
2158 for (i = 4; i < 8; i++)
2159 result[3][i] = result[c1][i];
2160 } else if (!(sim_bitmap & 0x30)) {
2161 for (i = 4; i < 6; i++)
2162 result[3][i] = result[c1][i];
2163 }
2164 return false;
2165}
2166
2167static void _rtl92d_phy_patha_fill_iqk_matrix(struct ieee80211_hw *hw,
2168 bool iqk_ok, long result[][8],
2169 u8 final_candidate, bool txonly)
2170{
2171 struct rtl_priv *rtlpriv = rtl_priv(hw);
2172 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2173 u32 oldval_0, val_x, tx0_a, reg;
2174 long val_y, tx0_c;
2175 bool is2t = IS_92D_SINGLEPHY(rtlhal->version) ||
2176 rtlhal->macphymode == DUALMAC_DUALPHY;
2177
2178 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2179 "Path A IQ Calibration %s !\n", iqk_ok ? "Success" : "Failed");
2180 if (final_candidate == 0xFF) {
2181 return;
2182 } else if (iqk_ok) {
2183 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
2184 MASKDWORD) >> 22) & 0x3FF;
2185 val_x = result[final_candidate][0];
2186 if ((val_x & 0x00000200) != 0)
2187 val_x = val_x | 0xFFFFFC00;
2188 tx0_a = (val_x * oldval_0) >> 8;
2189 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2190 "X = 0x%x, tx0_a = 0x%x, oldval_0 0x%x\n",
2191 val_x, tx0_a, oldval_0);
2192 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 0x3FF, tx0_a);
2193 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24),
2194 ((val_x * oldval_0 >> 7) & 0x1));
2195 val_y = result[final_candidate][1];
2196 if ((val_y & 0x00000200) != 0)
2197 val_y = val_y | 0xFFFFFC00;
2198
2199 if (rtlhal->interfaceindex == 1 &&
2200 rtlhal->current_bandtype == BAND_ON_5G)
2201 val_y += 3;
2202 tx0_c = (val_y * oldval_0) >> 8;
2203 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2204 "Y = 0x%lx, tx0_c = 0x%lx\n",
2205 val_y, tx0_c);
2206 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, 0xF0000000,
2207 ((tx0_c & 0x3C0) >> 6));
2208 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 0x003F0000,
2209 (tx0_c & 0x3F));
2210 if (is2t)
2211 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(26),
2212 ((val_y * oldval_0 >> 7) & 0x1));
2213 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xC80 = 0x%x\n",
2214 rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
2215 MASKDWORD));
2216 if (txonly) {
2217 RTPRINT(rtlpriv, FINIT, INIT_IQK, "only Tx OK\n");
2218 return;
2219 }
2220 reg = result[final_candidate][2];
2221 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
2222 reg = result[final_candidate][3] & 0x3F;
2223 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
2224 reg = (result[final_candidate][3] >> 6) & 0xF;
2225 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
2226 }
2227}
2228
2229static void _rtl92d_phy_pathb_fill_iqk_matrix(struct ieee80211_hw *hw,
2230 bool iqk_ok, long result[][8], u8 final_candidate, bool txonly)
2231{
2232 struct rtl_priv *rtlpriv = rtl_priv(hw);
2233 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2234 u32 oldval_1, val_x, tx1_a, reg;
2235 long val_y, tx1_c;
2236
2237 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQ Calibration %s !\n",
2238 iqk_ok ? "Success" : "Failed");
2239 if (final_candidate == 0xFF) {
2240 return;
2241 } else if (iqk_ok) {
2242 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTxIQIMBALANCE,
2243 MASKDWORD) >> 22) & 0x3FF;
2244 val_x = result[final_candidate][4];
2245 if ((val_x & 0x00000200) != 0)
2246 val_x = val_x | 0xFFFFFC00;
2247 tx1_a = (val_x * oldval_1) >> 8;
2248 RTPRINT(rtlpriv, FINIT, INIT_IQK, "X = 0x%x, tx1_a = 0x%x\n",
2249 val_x, tx1_a);
2250 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 0x3FF, tx1_a);
2251 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28),
2252 ((val_x * oldval_1 >> 7) & 0x1));
2253 val_y = result[final_candidate][5];
2254 if ((val_y & 0x00000200) != 0)
2255 val_y = val_y | 0xFFFFFC00;
2256 if (rtlhal->current_bandtype == BAND_ON_5G)
2257 val_y += 3;
2258 tx1_c = (val_y * oldval_1) >> 8;
2259 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Y = 0x%lx, tx1_c = 0x%lx\n",
2260 val_y, tx1_c);
2261 rtl_set_bbreg(hw, ROFDM0_XDTxAFE, 0xF0000000,
2262 ((tx1_c & 0x3C0) >> 6));
2263 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 0x003F0000,
2264 (tx1_c & 0x3F));
2265 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30),
2266 ((val_y * oldval_1 >> 7) & 0x1));
2267 if (txonly)
2268 return;
2269 reg = result[final_candidate][6];
2270 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg);
2271 reg = result[final_candidate][7] & 0x3F;
2272 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg);
2273 reg = (result[final_candidate][7] >> 6) & 0xF;
2274 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg);
2275 }
2276}
2277
2278void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw)
2279{
2280 struct rtl_priv *rtlpriv = rtl_priv(hw);
2281 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2282 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2283 long result[4][8];
2284 u8 i, final_candidate, indexforchannel;
2285 bool patha_ok, pathb_ok;
2286 long rege94, rege9c, regea4, regeac, regeb4;
2287 long regebc, regec4, regecc, regtmp = 0;
2288 bool is12simular, is13simular, is23simular;
2289 unsigned long flag = 0;
2290
2291 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2292 "IQK:Start!!!channel %d\n", rtlphy->current_channel);
2293 for (i = 0; i < 8; i++) {
2294 result[0][i] = 0;
2295 result[1][i] = 0;
2296 result[2][i] = 0;
2297 result[3][i] = 0;
2298 }
2299 final_candidate = 0xff;
2300 patha_ok = false;
2301 pathb_ok = false;
2302 is12simular = false;
2303 is23simular = false;
2304 is13simular = false;
2305 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2306 "IQK !!!currentband %d\n", rtlhal->current_bandtype);
2307 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
2308 for (i = 0; i < 3; i++) {
2309 if (rtlhal->current_bandtype == BAND_ON_5G) {
2310 _rtl92d_phy_iq_calibrate_5g_normal(hw, result, i);
2311 } else if (rtlhal->current_bandtype == BAND_ON_2_4G) {
2312 if (IS_92D_SINGLEPHY(rtlhal->version))
2313 _rtl92d_phy_iq_calibrate(hw, result, i, true);
2314 else
2315 _rtl92d_phy_iq_calibrate(hw, result, i, false);
2316 }
2317 if (i == 1) {
2318 is12simular = _rtl92d_phy_simularity_compare(hw, result,
2319 0, 1);
2320 if (is12simular) {
2321 final_candidate = 0;
2322 break;
2323 }
2324 }
2325 if (i == 2) {
2326 is13simular = _rtl92d_phy_simularity_compare(hw, result,
2327 0, 2);
2328 if (is13simular) {
2329 final_candidate = 0;
2330 break;
2331 }
2332 is23simular = _rtl92d_phy_simularity_compare(hw, result,
2333 1, 2);
2334 if (is23simular) {
2335 final_candidate = 1;
2336 } else {
2337 for (i = 0; i < 8; i++)
2338 regtmp += result[3][i];
2339
2340 if (regtmp != 0)
2341 final_candidate = 3;
2342 else
2343 final_candidate = 0xFF;
2344 }
2345 }
2346 }
2347 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
2348 for (i = 0; i < 4; i++) {
2349 rege94 = result[i][0];
2350 rege9c = result[i][1];
2351 regea4 = result[i][2];
2352 regeac = result[i][3];
2353 regeb4 = result[i][4];
2354 regebc = result[i][5];
2355 regec4 = result[i][6];
2356 regecc = result[i][7];
2357 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2358 "IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n",
2359 rege94, rege9c, regea4, regeac, regeb4, regebc, regec4,
2360 regecc);
2361 }
2362 if (final_candidate != 0xff) {
2363 rtlphy->reg_e94 = rege94 = result[final_candidate][0];
2364 rtlphy->reg_e9c = rege9c = result[final_candidate][1];
2365 regea4 = result[final_candidate][2];
2366 regeac = result[final_candidate][3];
2367 rtlphy->reg_eb4 = regeb4 = result[final_candidate][4];
2368 rtlphy->reg_ebc = regebc = result[final_candidate][5];
2369 regec4 = result[final_candidate][6];
2370 regecc = result[final_candidate][7];
2371 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2372 "IQK: final_candidate is %x\n", final_candidate);
2373 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2374 "IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n",
2375 rege94, rege9c, regea4, regeac, regeb4, regebc, regec4,
2376 regecc);
2377 patha_ok = pathb_ok = true;
2378 } else {
2379 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100;
2380 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0;
2381 }
2382 if ((rege94 != 0) )
2383 _rtl92d_phy_patha_fill_iqk_matrix(hw, patha_ok, result,
2384 final_candidate, (regea4 == 0));
2385 if (IS_92D_SINGLEPHY(rtlhal->version)) {
2386 if ((regeb4 != 0) )
2387 _rtl92d_phy_pathb_fill_iqk_matrix(hw, pathb_ok, result,
2388 final_candidate, (regec4 == 0));
2389 }
2390 if (final_candidate != 0xFF) {
2391 indexforchannel = rtl92d_get_rightchnlplace_for_iqk(
2392 rtlphy->current_channel);
2393
2394 for (i = 0; i < IQK_MATRIX_REG_NUM; i++)
2395 rtlphy->iqk_matrix[indexforchannel].
2396 value[0][i] = result[final_candidate][i];
2397 rtlphy->iqk_matrix[indexforchannel].iqk_done =
2398 true;
2399
2400 RT_TRACE(rtlpriv, COMP_SCAN | COMP_MLME, DBG_LOUD,
2401 "IQK OK indexforchannel %d\n", indexforchannel);
2402 }
2403}
2404
2405void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel)
2406{
2407 struct rtl_priv *rtlpriv = rtl_priv(hw);
2408 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2409 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2410 u8 indexforchannel;
2411
2412 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "channel %d\n", channel);
2413
2414 indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel);
2415 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "indexforchannel %d done %d\n",
2416 indexforchannel,
2417 rtlphy->iqk_matrix[indexforchannel].iqk_done);
2418 if (0 && !rtlphy->iqk_matrix[indexforchannel].iqk_done &&
2419 rtlphy->need_iqk) {
2420
2421 RT_TRACE(rtlpriv, COMP_SCAN | COMP_INIT, DBG_LOUD,
2422 "Do IQK Matrix reg for channel:%d....\n", channel);
2423 rtl92d_phy_iq_calibrate(hw);
2424 } else {
2425
2426
2427 if (((!rtlhal->load_imrandiqk_setting_for2g) &&
2428 indexforchannel == 0) || indexforchannel > 0) {
2429 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
2430 "Just Read IQK Matrix reg for channel:%d....\n",
2431 channel);
2432 if ((rtlphy->iqk_matrix[indexforchannel].
2433 value[0] != NULL)
2434 )
2435 _rtl92d_phy_patha_fill_iqk_matrix(hw, true,
2436 rtlphy->iqk_matrix[
2437 indexforchannel].value, 0,
2438 (rtlphy->iqk_matrix[
2439 indexforchannel].value[0][2] == 0));
2440 if (IS_92D_SINGLEPHY(rtlhal->version)) {
2441 if ((rtlphy->iqk_matrix[
2442 indexforchannel].value[0][4] != 0)
2443 )
2444 _rtl92d_phy_pathb_fill_iqk_matrix(hw,
2445 true,
2446 rtlphy->iqk_matrix[
2447 indexforchannel].value, 0,
2448 (rtlphy->iqk_matrix[
2449 indexforchannel].value[0][6]
2450 == 0));
2451 }
2452 }
2453 }
2454 rtlphy->need_iqk = false;
2455 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
2456}
2457
2458static u32 _rtl92d_phy_get_abs(u32 val1, u32 val2)
2459{
2460 u32 ret;
2461
2462 if (val1 >= val2)
2463 ret = val1 - val2;
2464 else
2465 ret = val2 - val1;
2466 return ret;
2467}
2468
2469static bool _rtl92d_is_legal_5g_channel(struct ieee80211_hw *hw, u8 channel)
2470{
2471
2472 int i;
2473 u8 channel_5g[45] = {
2474 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,
2475 60, 62, 64, 100, 102, 104, 106, 108, 110, 112,
2476 114, 116, 118, 120, 122, 124, 126, 128, 130, 132,
2477 134, 136, 138, 140, 149, 151, 153, 155, 157, 159,
2478 161, 163, 165
2479 };
2480
2481 for (i = 0; i < sizeof(channel_5g); i++)
2482 if (channel == channel_5g[i])
2483 return true;
2484 return false;
2485}
2486
2487static void _rtl92d_phy_calc_curvindex(struct ieee80211_hw *hw,
2488 u32 *targetchnl, u32 * curvecount_val,
2489 bool is5g, u32 *curveindex)
2490{
2491 struct rtl_priv *rtlpriv = rtl_priv(hw);
2492 u32 smallest_abs_val = 0xffffffff, u4tmp;
2493 u8 i, j;
2494 u8 chnl_num = is5g ? TARGET_CHNL_NUM_5G : TARGET_CHNL_NUM_2G;
2495
2496 for (i = 0; i < chnl_num; i++) {
2497 if (is5g && !_rtl92d_is_legal_5g_channel(hw, i + 1))
2498 continue;
2499 curveindex[i] = 0;
2500 for (j = 0; j < (CV_CURVE_CNT * 2); j++) {
2501 u4tmp = _rtl92d_phy_get_abs(targetchnl[i],
2502 curvecount_val[j]);
2503
2504 if (u4tmp < smallest_abs_val) {
2505 curveindex[i] = j;
2506 smallest_abs_val = u4tmp;
2507 }
2508 }
2509 smallest_abs_val = 0xffffffff;
2510 RTPRINT(rtlpriv, FINIT, INIT_IQK, "curveindex[%d] = %x\n",
2511 i, curveindex[i]);
2512 }
2513}
2514
2515static void _rtl92d_phy_reload_lck_setting(struct ieee80211_hw *hw,
2516 u8 channel)
2517{
2518 struct rtl_priv *rtlpriv = rtl_priv(hw);
2519 u8 erfpath = rtlpriv->rtlhal.current_bandtype ==
2520 BAND_ON_5G ? RF90_PATH_A :
2521 IS_92D_SINGLEPHY(rtlpriv->rtlhal.version) ?
2522 RF90_PATH_B : RF90_PATH_A;
2523 u32 u4tmp = 0, u4regvalue = 0;
2524 bool bneed_powerdown_radio = false;
2525
2526 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "path %d\n", erfpath);
2527 RTPRINT(rtlpriv, FINIT, INIT_IQK, "band type = %d\n",
2528 rtlpriv->rtlhal.current_bandtype);
2529 RTPRINT(rtlpriv, FINIT, INIT_IQK, "channel = %d\n", channel);
2530 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {
2531 u4tmp = curveindex_5g[channel-1];
2532 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2533 "ver 1 set RF-A, 5G, 0x28 = 0x%ulx !!\n", u4tmp);
2534 if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY &&
2535 rtlpriv->rtlhal.interfaceindex == 1) {
2536 bneed_powerdown_radio =
2537 rtl92d_phy_enable_anotherphy(hw, false);
2538 rtlpriv->rtlhal.during_mac1init_radioa = true;
2539
2540 if (bneed_powerdown_radio)
2541 _rtl92d_phy_enable_rf_env(hw, erfpath,
2542 &u4regvalue);
2543 }
2544 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp);
2545 if (bneed_powerdown_radio)
2546 _rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue);
2547 if (rtlpriv->rtlhal.during_mac1init_radioa)
2548 rtl92d_phy_powerdown_anotherphy(hw, false);
2549 } else if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) {
2550 u4tmp = curveindex_2g[channel-1];
2551 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2552 "ver 3 set RF-B, 2G, 0x28 = 0x%ulx !!\n", u4tmp);
2553 if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY &&
2554 rtlpriv->rtlhal.interfaceindex == 0) {
2555 bneed_powerdown_radio =
2556 rtl92d_phy_enable_anotherphy(hw, true);
2557 rtlpriv->rtlhal.during_mac0init_radiob = true;
2558 if (bneed_powerdown_radio)
2559 _rtl92d_phy_enable_rf_env(hw, erfpath,
2560 &u4regvalue);
2561 }
2562 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp);
2563 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2564 "ver 3 set RF-B, 2G, 0x28 = 0x%ulx !!\n",
2565 rtl_get_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800));
2566 if (bneed_powerdown_radio)
2567 _rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue);
2568 if (rtlpriv->rtlhal.during_mac0init_radiob)
2569 rtl92d_phy_powerdown_anotherphy(hw, true);
2570 }
2571 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
2572}
2573
2574static void _rtl92d_phy_lc_calibrate_sw(struct ieee80211_hw *hw, bool is2t)
2575{
2576 struct rtl_priv *rtlpriv = rtl_priv(hw);
2577 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2578 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2579 u8 tmpreg, index, rf_mode[2];
2580 u8 path = is2t ? 2 : 1;
2581 u8 i;
2582 u32 u4tmp, offset;
2583 u32 curvecount_val[CV_CURVE_CNT * 2] = {0};
2584 u16 timeout = 800, timecount = 0;
2585
2586
2587 tmpreg = rtl_read_byte(rtlpriv, 0xd03);
2588
2589
2590 if ((tmpreg & 0x70) != 0)
2591 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
2592 else
2593 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
2594 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x0F);
2595 for (index = 0; index < path; index++) {
2596
2597 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1;
2598 rf_mode[index] = rtl_read_byte(rtlpriv, offset);
2599
2600 rtl_set_rfreg(hw, (enum radio_path)index, RF_AC,
2601 RFREG_OFFSET_MASK, 0x010000);
2602 if (rtlpci->init_ready) {
2603
2604 rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7,
2605 BIT(17), 0x0);
2606
2607 rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW,
2608 0x08000, 0x01);
2609 }
2610 u4tmp = rtl_get_rfreg(hw, (enum radio_path)index, RF_SYN_G6,
2611 RFREG_OFFSET_MASK);
2612 while ((!(u4tmp & BIT(11))) && timecount <= timeout) {
2613 mdelay(50);
2614 timecount += 50;
2615 u4tmp = rtl_get_rfreg(hw, (enum radio_path)index,
2616 RF_SYN_G6, RFREG_OFFSET_MASK);
2617 }
2618 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2619 "PHY_LCK finish delay for %d ms=2\n", timecount);
2620 u4tmp = rtl_get_rfreg(hw, index, RF_SYN_G4, RFREG_OFFSET_MASK);
2621 if (index == 0 && rtlhal->interfaceindex == 0) {
2622 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2623 "path-A / 5G LCK\n");
2624 } else {
2625 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2626 "path-B / 2.4G LCK\n");
2627 }
2628 memset(&curvecount_val[0], 0, CV_CURVE_CNT * 2);
2629
2630 rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW,
2631 0x08000, 0x0);
2632 RTPRINT(rtlpriv, FINIT, INIT_IQK, "set RF 0x18[15] = 0\n");
2633
2634 for (i = 0; i < CV_CURVE_CNT; i++) {
2635 u32 readval = 0, readval2 = 0;
2636 rtl_set_rfreg(hw, (enum radio_path)index, 0x3F,
2637 0x7f, i);
2638
2639 rtl_set_rfreg(hw, (enum radio_path)index, 0x4D,
2640 RFREG_OFFSET_MASK, 0x0);
2641 readval = rtl_get_rfreg(hw, (enum radio_path)index,
2642 0x4F, RFREG_OFFSET_MASK);
2643 curvecount_val[2 * i + 1] = (readval & 0xfffe0) >> 5;
2644
2645
2646 readval2 = rtl_get_rfreg(hw, (enum radio_path)index,
2647 0x50, 0xffc00);
2648 curvecount_val[2 * i] = (((readval & 0x1F) << 10) |
2649 readval2);
2650 }
2651 if (index == 0 && rtlhal->interfaceindex == 0)
2652 _rtl92d_phy_calc_curvindex(hw, targetchnl_5g,
2653 curvecount_val,
2654 true, curveindex_5g);
2655 else
2656 _rtl92d_phy_calc_curvindex(hw, targetchnl_2g,
2657 curvecount_val,
2658 false, curveindex_2g);
2659
2660 rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7,
2661 BIT(17), 0x1);
2662 }
2663
2664
2665 for (index = 0; index < path; index++) {
2666 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1;
2667 rtl_write_byte(rtlpriv, offset, 0x50);
2668 rtl_write_byte(rtlpriv, offset, rf_mode[index]);
2669 }
2670 if ((tmpreg & 0x70) != 0)
2671 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
2672 else
2673 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2674 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x00);
2675 _rtl92d_phy_reload_lck_setting(hw, rtlpriv->phy.current_channel);
2676}
2677
2678static void _rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
2679{
2680 struct rtl_priv *rtlpriv = rtl_priv(hw);
2681
2682 RTPRINT(rtlpriv, FINIT, INIT_IQK, "cosa PHY_LCK ver=2\n");
2683 _rtl92d_phy_lc_calibrate_sw(hw, is2t);
2684}
2685
2686void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw)
2687{
2688 struct rtl_priv *rtlpriv = rtl_priv(hw);
2689 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2690 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2691 u32 timeout = 2000, timecount = 0;
2692
2693 while (rtlpriv->mac80211.act_scanning && timecount < timeout) {
2694 udelay(50);
2695 timecount += 50;
2696 }
2697
2698 rtlphy->lck_inprogress = true;
2699 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2700 "LCK:Start!!! currentband %x delay %d ms\n",
2701 rtlhal->current_bandtype, timecount);
2702 if (IS_92D_SINGLEPHY(rtlhal->version)) {
2703 _rtl92d_phy_lc_calibrate(hw, true);
2704 } else {
2705
2706 _rtl92d_phy_lc_calibrate(hw, false);
2707 }
2708 rtlphy->lck_inprogress = false;
2709 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LCK:Finish!!!\n");
2710}
2711
2712void rtl92d_phy_ap_calibrate(struct ieee80211_hw *hw, char delta)
2713{
2714 return;
2715}
2716
2717static bool _rtl92d_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
2718 u32 cmdtableidx, u32 cmdtablesz, enum swchnlcmd_id cmdid,
2719 u32 para1, u32 para2, u32 msdelay)
2720{
2721 struct swchnlcmd *pcmd;
2722
2723 if (cmdtable == NULL) {
2724 RT_ASSERT(false, "cmdtable cannot be NULL\n");
2725 return false;
2726 }
2727 if (cmdtableidx >= cmdtablesz)
2728 return false;
2729
2730 pcmd = cmdtable + cmdtableidx;
2731 pcmd->cmdid = cmdid;
2732 pcmd->para1 = para1;
2733 pcmd->para2 = para2;
2734 pcmd->msdelay = msdelay;
2735 return true;
2736}
2737
2738void rtl92d_phy_reset_iqk_result(struct ieee80211_hw *hw)
2739{
2740 struct rtl_priv *rtlpriv = rtl_priv(hw);
2741 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2742 u8 i;
2743
2744 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2745 "settings regs %d default regs %d\n",
2746 (int)(sizeof(rtlphy->iqk_matrix) /
2747 sizeof(struct iqk_matrix_regs)),
2748 IQK_MATRIX_REG_NUM);
2749
2750 for (i = 0; i < IQK_MATRIX_SETTINGS_NUM; i++) {
2751 rtlphy->iqk_matrix[i].value[0][0] = 0x100;
2752 rtlphy->iqk_matrix[i].value[0][2] = 0x100;
2753 rtlphy->iqk_matrix[i].value[0][4] = 0x100;
2754 rtlphy->iqk_matrix[i].value[0][6] = 0x100;
2755 rtlphy->iqk_matrix[i].value[0][1] = 0x0;
2756 rtlphy->iqk_matrix[i].value[0][3] = 0x0;
2757 rtlphy->iqk_matrix[i].value[0][5] = 0x0;
2758 rtlphy->iqk_matrix[i].value[0][7] = 0x0;
2759 rtlphy->iqk_matrix[i].iqk_done = false;
2760 }
2761}
2762
2763static bool _rtl92d_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
2764 u8 channel, u8 *stage, u8 *step,
2765 u32 *delay)
2766{
2767 struct rtl_priv *rtlpriv = rtl_priv(hw);
2768 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2769 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
2770 u32 precommoncmdcnt;
2771 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
2772 u32 postcommoncmdcnt;
2773 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
2774 u32 rfdependcmdcnt;
2775 struct swchnlcmd *currentcmd = NULL;
2776 u8 rfpath;
2777 u8 num_total_rfpath = rtlphy->num_total_rfpath;
2778
2779 precommoncmdcnt = 0;
2780 _rtl92d_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
2781 MAX_PRECMD_CNT,
2782 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
2783 _rtl92d_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
2784 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
2785 postcommoncmdcnt = 0;
2786 _rtl92d_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
2787 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
2788 rfdependcmdcnt = 0;
2789 _rtl92d_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
2790 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
2791 RF_CHNLBW, channel, 0);
2792 _rtl92d_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
2793 MAX_RFDEPENDCMD_CNT, CMDID_END,
2794 0, 0, 0);
2795
2796 do {
2797 switch (*stage) {
2798 case 0:
2799 currentcmd = &precommoncmd[*step];
2800 break;
2801 case 1:
2802 currentcmd = &rfdependcmd[*step];
2803 break;
2804 case 2:
2805 currentcmd = &postcommoncmd[*step];
2806 break;
2807 }
2808 if (currentcmd->cmdid == CMDID_END) {
2809 if ((*stage) == 2) {
2810 return true;
2811 } else {
2812 (*stage)++;
2813 (*step) = 0;
2814 continue;
2815 }
2816 }
2817 switch (currentcmd->cmdid) {
2818 case CMDID_SET_TXPOWEROWER_LEVEL:
2819 rtl92d_phy_set_txpower_level(hw, channel);
2820 break;
2821 case CMDID_WRITEPORT_ULONG:
2822 rtl_write_dword(rtlpriv, currentcmd->para1,
2823 currentcmd->para2);
2824 break;
2825 case CMDID_WRITEPORT_USHORT:
2826 rtl_write_word(rtlpriv, currentcmd->para1,
2827 (u16)currentcmd->para2);
2828 break;
2829 case CMDID_WRITEPORT_UCHAR:
2830 rtl_write_byte(rtlpriv, currentcmd->para1,
2831 (u8)currentcmd->para2);
2832 break;
2833 case CMDID_RF_WRITEREG:
2834 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
2835 rtlphy->rfreg_chnlval[rfpath] =
2836 ((rtlphy->rfreg_chnlval[rfpath] &
2837 0xffffff00) | currentcmd->para2);
2838 if (rtlpriv->rtlhal.current_bandtype ==
2839 BAND_ON_5G) {
2840 if (currentcmd->para2 > 99)
2841 rtlphy->rfreg_chnlval[rfpath] =
2842 rtlphy->rfreg_chnlval
2843 [rfpath] | (BIT(18));
2844 else
2845 rtlphy->rfreg_chnlval[rfpath] =
2846 rtlphy->rfreg_chnlval
2847 [rfpath] & (~BIT(18));
2848 rtlphy->rfreg_chnlval[rfpath] |=
2849 (BIT(16) | BIT(8));
2850 } else {
2851 rtlphy->rfreg_chnlval[rfpath] &=
2852 ~(BIT(8) | BIT(16) | BIT(18));
2853 }
2854 rtl_set_rfreg(hw, (enum radio_path)rfpath,
2855 currentcmd->para1,
2856 RFREG_OFFSET_MASK,
2857 rtlphy->rfreg_chnlval[rfpath]);
2858 _rtl92d_phy_reload_imr_setting(hw, channel,
2859 rfpath);
2860 }
2861 _rtl92d_phy_switch_rf_setting(hw, channel);
2862
2863 rtl92d_phy_reload_iqk_setting(hw, channel);
2864 break;
2865 default:
2866 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2867 "switch case not processed\n");
2868 break;
2869 }
2870 break;
2871 } while (true);
2872 (*delay) = currentcmd->msdelay;
2873 (*step)++;
2874 return false;
2875}
2876
2877u8 rtl92d_phy_sw_chnl(struct ieee80211_hw *hw)
2878{
2879 struct rtl_priv *rtlpriv = rtl_priv(hw);
2880 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2881 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2882 u32 delay;
2883 u32 timeout = 1000, timecount = 0;
2884 u8 channel = rtlphy->current_channel;
2885 u32 ret_value;
2886
2887 if (rtlphy->sw_chnl_inprogress)
2888 return 0;
2889 if (rtlphy->set_bwmode_inprogress)
2890 return 0;
2891
2892 if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) {
2893 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
2894 "sw_chnl_inprogress false driver sleep or unload\n");
2895 return 0;
2896 }
2897 while (rtlphy->lck_inprogress && timecount < timeout) {
2898 mdelay(50);
2899 timecount += 50;
2900 }
2901 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY &&
2902 rtlhal->bandset == BAND_ON_BOTH) {
2903 ret_value = rtl_get_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
2904 MASKDWORD);
2905 if (rtlphy->current_channel > 14 && !(ret_value & BIT(0)))
2906 rtl92d_phy_switch_wirelessband(hw, BAND_ON_5G);
2907 else if (rtlphy->current_channel <= 14 && (ret_value & BIT(0)))
2908 rtl92d_phy_switch_wirelessband(hw, BAND_ON_2_4G);
2909 }
2910 switch (rtlhal->current_bandtype) {
2911 case BAND_ON_5G:
2912
2913
2914 if (channel <= 14)
2915 return 0;
2916 RT_ASSERT((channel > 14), "5G but channel<=14\n");
2917 break;
2918 case BAND_ON_2_4G:
2919
2920
2921 if (channel > 14)
2922 return 0;
2923 RT_ASSERT((channel <= 14), "2G but channel>14\n");
2924 break;
2925 default:
2926 RT_ASSERT(false, "Invalid WirelessMode(%#x)!!\n",
2927 rtlpriv->mac80211.mode);
2928 break;
2929 }
2930 rtlphy->sw_chnl_inprogress = true;
2931 if (channel == 0)
2932 channel = 1;
2933 rtlphy->sw_chnl_stage = 0;
2934 rtlphy->sw_chnl_step = 0;
2935 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
2936 "switch to channel%d\n", rtlphy->current_channel);
2937
2938 do {
2939 if (!rtlphy->sw_chnl_inprogress)
2940 break;
2941 if (!_rtl92d_phy_sw_chnl_step_by_step(hw,
2942 rtlphy->current_channel,
2943 &rtlphy->sw_chnl_stage, &rtlphy->sw_chnl_step, &delay)) {
2944 if (delay > 0)
2945 mdelay(delay);
2946 else
2947 continue;
2948 } else {
2949 rtlphy->sw_chnl_inprogress = false;
2950 }
2951 break;
2952 } while (true);
2953 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
2954 rtlphy->sw_chnl_inprogress = false;
2955 return 1;
2956}
2957
2958static void rtl92d_phy_set_io(struct ieee80211_hw *hw)
2959{
2960 struct rtl_priv *rtlpriv = rtl_priv(hw);
2961 struct dig_t *de_digtable = &rtlpriv->dm_digtable;
2962 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2963
2964 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2965 "--->Cmd(%#x), set_io_inprogress(%d)\n",
2966 rtlphy->current_io_type, rtlphy->set_io_inprogress);
2967 switch (rtlphy->current_io_type) {
2968 case IO_CMD_RESUME_DM_BY_SCAN:
2969 de_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1;
2970 rtl92d_dm_write_dig(hw);
2971 rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel);
2972 break;
2973 case IO_CMD_PAUSE_DM_BY_SCAN:
2974 rtlphy->initgain_backup.xaagccore1 = de_digtable->cur_igvalue;
2975 de_digtable->cur_igvalue = 0x37;
2976 rtl92d_dm_write_dig(hw);
2977 break;
2978 default:
2979 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2980 "switch case not processed\n");
2981 break;
2982 }
2983 rtlphy->set_io_inprogress = false;
2984 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "<---(%#x)\n",
2985 rtlphy->current_io_type);
2986}
2987
2988bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
2989{
2990 struct rtl_priv *rtlpriv = rtl_priv(hw);
2991 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2992 bool postprocessing = false;
2993
2994 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2995 "-->IO Cmd(%#x), set_io_inprogress(%d)\n",
2996 iotype, rtlphy->set_io_inprogress);
2997 do {
2998 switch (iotype) {
2999 case IO_CMD_RESUME_DM_BY_SCAN:
3000 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
3001 "[IO CMD] Resume DM after scan\n");
3002 postprocessing = true;
3003 break;
3004 case IO_CMD_PAUSE_DM_BY_SCAN:
3005 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
3006 "[IO CMD] Pause DM before scan\n");
3007 postprocessing = true;
3008 break;
3009 default:
3010 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
3011 "switch case not processed\n");
3012 break;
3013 }
3014 } while (false);
3015 if (postprocessing && !rtlphy->set_io_inprogress) {
3016 rtlphy->set_io_inprogress = true;
3017 rtlphy->current_io_type = iotype;
3018 } else {
3019 return false;
3020 }
3021 rtl92d_phy_set_io(hw);
3022 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "<--IO Type(%#x)\n", iotype);
3023 return true;
3024}
3025
3026static void _rtl92d_phy_set_rfon(struct ieee80211_hw *hw)
3027{
3028 struct rtl_priv *rtlpriv = rtl_priv(hw);
3029
3030
3031
3032 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY)
3033 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
3034
3035 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3036
3037
3038 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
3039
3040
3041 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3042 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3043
3044 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
3045}
3046
3047static void _rtl92d_phy_set_rfsleep(struct ieee80211_hw *hw)
3048{
3049 struct rtl_priv *rtlpriv = rtl_priv(hw);
3050 u32 u4btmp;
3051 u8 delay = 5;
3052
3053
3054 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
3055
3056 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
3057
3058 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
3059
3060
3061
3062
3063
3064 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
3065 while (u4btmp != 0 && delay > 0) {
3066 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
3067 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
3068 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
3069 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
3070 delay--;
3071 }
3072 if (delay == 0) {
3073
3074 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
3075
3076 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3077 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3078 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
3079 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
3080 "Fail !!! Switch RF timeout\n");
3081 return;
3082 }
3083
3084 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3085
3086 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY)
3087 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
3088
3089}
3090
3091bool rtl92d_phy_set_rf_power_state(struct ieee80211_hw *hw,
3092 enum rf_pwrstate rfpwr_state)
3093{
3094
3095 bool bresult = true;
3096 struct rtl_priv *rtlpriv = rtl_priv(hw);
3097 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3098 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3099 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
3100 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
3101 u8 i, queue_id;
3102 struct rtl8192_tx_ring *ring = NULL;
3103
3104 if (rfpwr_state == ppsc->rfpwr_state)
3105 return false;
3106 switch (rfpwr_state) {
3107 case ERFON:
3108 if ((ppsc->rfpwr_state == ERFOFF) &&
3109 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
3110 bool rtstatus;
3111 u32 InitializeCount = 0;
3112 do {
3113 InitializeCount++;
3114 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3115 "IPS Set eRf nic enable\n");
3116 rtstatus = rtl_ps_enable_nic(hw);
3117 } while (!rtstatus && (InitializeCount < 10));
3118
3119 RT_CLEAR_PS_LEVEL(ppsc,
3120 RT_RF_OFF_LEVL_HALT_NIC);
3121 } else {
3122 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
3123 "awake, sleeped:%d ms state_inap:%x\n",
3124 jiffies_to_msecs(jiffies -
3125 ppsc->last_sleep_jiffies),
3126 rtlpriv->psc.state_inap);
3127 ppsc->last_awake_jiffies = jiffies;
3128 _rtl92d_phy_set_rfon(hw);
3129 }
3130
3131 if (mac->link_state == MAC80211_LINKED)
3132 rtlpriv->cfg->ops->led_control(hw,
3133 LED_CTL_LINK);
3134 else
3135 rtlpriv->cfg->ops->led_control(hw,
3136 LED_CTL_NO_LINK);
3137 break;
3138 case ERFOFF:
3139 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
3140 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3141 "IPS Set eRf nic disable\n");
3142 rtl_ps_disable_nic(hw);
3143 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
3144 } else {
3145 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
3146 rtlpriv->cfg->ops->led_control(hw,
3147 LED_CTL_NO_LINK);
3148 else
3149 rtlpriv->cfg->ops->led_control(hw,
3150 LED_CTL_POWER_OFF);
3151 }
3152 break;
3153 case ERFSLEEP:
3154 if (ppsc->rfpwr_state == ERFOFF)
3155 return false;
3156
3157 for (queue_id = 0, i = 0;
3158 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
3159 ring = &pcipriv->dev.tx_ring[queue_id];
3160 if (skb_queue_len(&ring->queue) == 0 ||
3161 queue_id == BEACON_QUEUE) {
3162 queue_id++;
3163 continue;
3164 } else if (rtlpci->pdev->current_state != PCI_D0) {
3165 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
3166 "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 but lower power state!\n",
3167 i + 1, queue_id);
3168 break;
3169 } else {
3170 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
3171 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
3172 i + 1, queue_id,
3173 skb_queue_len(&ring->queue));
3174 udelay(10);
3175 i++;
3176 }
3177
3178 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
3179 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
3180 "ERFOFF: %d times TcbBusyQueue[%d] = %d !\n",
3181 MAX_DOZE_WAITING_TIMES_9x, queue_id,
3182 skb_queue_len(&ring->queue));
3183 break;
3184 }
3185 }
3186 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
3187 "Set rfsleep awaked:%d ms\n",
3188 jiffies_to_msecs(jiffies - ppsc->last_awake_jiffies));
3189 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
3190 "sleep awaked:%d ms state_inap:%x\n",
3191 jiffies_to_msecs(jiffies -
3192 ppsc->last_awake_jiffies),
3193 rtlpriv->psc.state_inap);
3194 ppsc->last_sleep_jiffies = jiffies;
3195 _rtl92d_phy_set_rfsleep(hw);
3196 break;
3197 default:
3198 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
3199 "switch case not processed\n");
3200 bresult = false;
3201 break;
3202 }
3203 if (bresult)
3204 ppsc->rfpwr_state = rfpwr_state;
3205 return bresult;
3206}
3207
3208void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw)
3209{
3210 struct rtl_priv *rtlpriv = rtl_priv(hw);
3211 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3212 u8 offset = REG_MAC_PHY_CTRL_NORMAL;
3213
3214 switch (rtlhal->macphymode) {
3215 case DUALMAC_DUALPHY:
3216 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3217 "MacPhyMode: DUALMAC_DUALPHY\n");
3218 rtl_write_byte(rtlpriv, offset, 0xF3);
3219 break;
3220 case SINGLEMAC_SINGLEPHY:
3221 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3222 "MacPhyMode: SINGLEMAC_SINGLEPHY\n");
3223 rtl_write_byte(rtlpriv, offset, 0xF4);
3224 break;
3225 case DUALMAC_SINGLEPHY:
3226 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3227 "MacPhyMode: DUALMAC_SINGLEPHY\n");
3228 rtl_write_byte(rtlpriv, offset, 0xF1);
3229 break;
3230 }
3231}
3232
3233void rtl92d_phy_config_macphymode_info(struct ieee80211_hw *hw)
3234{
3235 struct rtl_priv *rtlpriv = rtl_priv(hw);
3236 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3237 struct rtl_phy *rtlphy = &(rtlpriv->phy);
3238
3239 switch (rtlhal->macphymode) {
3240 case DUALMAC_SINGLEPHY:
3241 rtlphy->rf_type = RF_2T2R;
3242 rtlhal->version |= RF_TYPE_2T2R;
3243 rtlhal->bandset = BAND_ON_BOTH;
3244 rtlhal->current_bandtype = BAND_ON_2_4G;
3245 break;
3246
3247 case SINGLEMAC_SINGLEPHY:
3248 rtlphy->rf_type = RF_2T2R;
3249 rtlhal->version |= RF_TYPE_2T2R;
3250 rtlhal->bandset = BAND_ON_BOTH;
3251 rtlhal->current_bandtype = BAND_ON_2_4G;
3252 break;
3253
3254 case DUALMAC_DUALPHY:
3255 rtlphy->rf_type = RF_1T1R;
3256 rtlhal->version &= RF_TYPE_1T1R;
3257
3258 if (rtlhal->interfaceindex == 0) {
3259 rtlhal->bandset = BAND_ON_5G;
3260 rtlhal->current_bandtype = BAND_ON_5G;
3261 } else {
3262 rtlhal->bandset = BAND_ON_2_4G;
3263 rtlhal->current_bandtype = BAND_ON_2_4G;
3264 }
3265 break;
3266 default:
3267 break;
3268 }
3269}
3270
3271u8 rtl92d_get_chnlgroup_fromarray(u8 chnl)
3272{
3273 u8 group;
3274 u8 channel_info[59] = {
3275 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
3276 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56,
3277 58, 60, 62, 64, 100, 102, 104, 106, 108,
3278 110, 112, 114, 116, 118, 120, 122, 124,
3279 126, 128, 130, 132, 134, 136, 138, 140,
3280 149, 151, 153, 155, 157, 159, 161, 163,
3281 165
3282 };
3283
3284 if (channel_info[chnl] <= 3)
3285 group = 0;
3286 else if (channel_info[chnl] <= 9)
3287 group = 1;
3288 else if (channel_info[chnl] <= 14)
3289 group = 2;
3290 else if (channel_info[chnl] <= 44)
3291 group = 3;
3292 else if (channel_info[chnl] <= 54)
3293 group = 4;
3294 else if (channel_info[chnl] <= 64)
3295 group = 5;
3296 else if (channel_info[chnl] <= 112)
3297 group = 6;
3298 else if (channel_info[chnl] <= 126)
3299 group = 7;
3300 else if (channel_info[chnl] <= 140)
3301 group = 8;
3302 else if (channel_info[chnl] <= 153)
3303 group = 9;
3304 else if (channel_info[chnl] <= 159)
3305 group = 10;
3306 else
3307 group = 11;
3308 return group;
3309}
3310
3311void rtl92d_phy_set_poweron(struct ieee80211_hw *hw)
3312{
3313 struct rtl_priv *rtlpriv = rtl_priv(hw);
3314 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3315 unsigned long flags;
3316 u8 value8;
3317 u16 i;
3318 u32 mac_reg = (rtlhal->interfaceindex == 0 ? REG_MAC0 : REG_MAC1);
3319
3320
3321 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3322 value8 = rtl_read_byte(rtlpriv, mac_reg);
3323 value8 |= BIT(1);
3324 rtl_write_byte(rtlpriv, mac_reg, value8);
3325 } else {
3326 value8 = rtl_read_byte(rtlpriv, mac_reg);
3327 value8 &= (~BIT(1));
3328 rtl_write_byte(rtlpriv, mac_reg, value8);
3329 }
3330
3331 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) {
3332 value8 = rtl_read_byte(rtlpriv, REG_MAC0);
3333 rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON);
3334 } else {
3335 spin_lock_irqsave(&globalmutex_power, flags);
3336 if (rtlhal->interfaceindex == 0) {
3337 value8 = rtl_read_byte(rtlpriv, REG_MAC0);
3338 rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON);
3339 } else {
3340 value8 = rtl_read_byte(rtlpriv, REG_MAC1);
3341 rtl_write_byte(rtlpriv, REG_MAC1, value8 | MAC1_ON);
3342 }
3343 value8 = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
3344 spin_unlock_irqrestore(&globalmutex_power, flags);
3345 for (i = 0; i < 200; i++) {
3346 if ((value8 & BIT(7)) == 0) {
3347 break;
3348 } else {
3349 udelay(500);
3350 spin_lock_irqsave(&globalmutex_power, flags);
3351 value8 = rtl_read_byte(rtlpriv,
3352 REG_POWER_OFF_IN_PROCESS);
3353 spin_unlock_irqrestore(&globalmutex_power,
3354 flags);
3355 }
3356 }
3357 if (i == 200)
3358 RT_ASSERT(false, "Another mac power off over time\n");
3359 }
3360}
3361
3362void rtl92d_phy_config_maccoexist_rfpage(struct ieee80211_hw *hw)
3363{
3364 struct rtl_priv *rtlpriv = rtl_priv(hw);
3365
3366 switch (rtlpriv->rtlhal.macphymode) {
3367 case DUALMAC_DUALPHY:
3368 rtl_write_byte(rtlpriv, REG_DMC, 0x0);
3369 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08);
3370 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff);
3371 break;
3372 case DUALMAC_SINGLEPHY:
3373 rtl_write_byte(rtlpriv, REG_DMC, 0xf8);
3374 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08);
3375 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff);
3376 break;
3377 case SINGLEMAC_SINGLEPHY:
3378 rtl_write_byte(rtlpriv, REG_DMC, 0x0);
3379 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x10);
3380 rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF);
3381 break;
3382 default:
3383 break;
3384 }
3385}
3386
3387void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw)
3388{
3389 struct rtl_priv *rtlpriv = rtl_priv(hw);
3390 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3391 struct rtl_phy *rtlphy = &(rtlpriv->phy);
3392 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3393 u8 rfpath, i;
3394
3395 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n");
3396
3397 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3398
3399 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x0);
3400 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x0);
3401 if (rtlhal->macphymode != DUALMAC_DUALPHY) {
3402 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x0);
3403 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x0);
3404 }
3405
3406 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x0);
3407
3408 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x0);
3409
3410 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa);
3411
3412 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD,
3413 0x40000100);
3414 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD,
3415 0x40000100);
3416 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
3417 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3418 BIT(10) | BIT(6) | BIT(5),
3419 ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) |
3420 (rtlefuse->eeprom_c9 & BIT(1)) |
3421 ((rtlefuse->eeprom_cc & BIT(1)) << 4));
3422 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
3423 BIT(10) | BIT(6) | BIT(5),
3424 ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) |
3425 ((rtlefuse->eeprom_c9 & BIT(0)) << 1) |
3426 ((rtlefuse->eeprom_cc & BIT(0)) << 5));
3427 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0);
3428 } else {
3429 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3430 BIT(26) | BIT(22) | BIT(21) | BIT(10) |
3431 BIT(6) | BIT(5),
3432 ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) |
3433 (rtlefuse->eeprom_c9 & BIT(1)) |
3434 ((rtlefuse->eeprom_cc & BIT(1)) << 4) |
3435 ((rtlefuse->eeprom_c9 & BIT(7)) << 9) |
3436 ((rtlefuse->eeprom_c9 & BIT(5)) << 12) |
3437 ((rtlefuse->eeprom_cc & BIT(3)) << 18));
3438 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
3439 BIT(10) | BIT(6) | BIT(5),
3440 ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) |
3441 ((rtlefuse->eeprom_c9 & BIT(0)) << 1) |
3442 ((rtlefuse->eeprom_cc & BIT(0)) << 5));
3443 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
3444 BIT(10) | BIT(6) | BIT(5),
3445 ((rtlefuse->eeprom_c9 & BIT(6)) >> 6) |
3446 ((rtlefuse->eeprom_c9 & BIT(4)) >> 3) |
3447 ((rtlefuse->eeprom_cc & BIT(2)) << 3));
3448 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
3449 BIT(31) | BIT(15), 0);
3450 }
3451
3452 } else {
3453
3454 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x1);
3455 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x1);
3456 if (rtlhal->macphymode != DUALMAC_DUALPHY) {
3457 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x1);
3458 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x1);
3459 }
3460
3461 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x1);
3462
3463 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x1);
3464
3465 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0);
3466
3467 if (rtlefuse->internal_pa_5g[0])
3468 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD,
3469 0x2d4000b5);
3470 else
3471 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD,
3472 0x20000080);
3473 if (rtlefuse->internal_pa_5g[1])
3474 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD,
3475 0x2d4000b5);
3476 else
3477 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD,
3478 0x20000080);
3479 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
3480 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3481 BIT(10) | BIT(6) | BIT(5),
3482 (rtlefuse->eeprom_cc & BIT(5)));
3483 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10),
3484 ((rtlefuse->eeprom_cc & BIT(4)) >> 4));
3485 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15),
3486 (rtlefuse->eeprom_cc & BIT(4)) >> 4);
3487 } else {
3488 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3489 BIT(26) | BIT(22) | BIT(21) | BIT(10) |
3490 BIT(6) | BIT(5),
3491 (rtlefuse->eeprom_cc & BIT(5)) |
3492 ((rtlefuse->eeprom_cc & BIT(7)) << 14));
3493 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10),
3494 ((rtlefuse->eeprom_cc & BIT(4)) >> 4));
3495 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10),
3496 ((rtlefuse->eeprom_cc & BIT(6)) >> 6));
3497 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
3498 BIT(31) | BIT(15),
3499 ((rtlefuse->eeprom_cc & BIT(4)) >> 4) |
3500 ((rtlefuse->eeprom_cc & BIT(6)) << 10));
3501 }
3502 }
3503
3504 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100);
3505 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100);
3506 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, 0xF0000000, 0x00);
3507 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30) | BIT(28) |
3508 BIT(26) | BIT(24), 0x00);
3509 rtl_set_bbreg(hw, ROFDM0_XDTxAFE, 0xF0000000, 0x00);
3510 rtl_set_bbreg(hw, 0xca0, 0xF0000000, 0x00);
3511 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, 0x00);
3512
3513
3514 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
3515 rfpath++) {
3516 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3517
3518 rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) | BIT(16) |
3519 BIT(18), 0);
3520
3521 rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B,
3522 0x1c000, 0x07);
3523 } else {
3524
3525 rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) |
3526 BIT(16) | BIT(18),
3527 (BIT(16) | BIT(8)) >> 8);
3528 }
3529 }
3530
3531
3532 if (rtlphy->rf_type == RF_1T1R) {
3533
3534 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x11);
3535 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x1);
3536
3537
3538 if (rtlhal->interfaceindex == 0) {
3539 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) |
3540 BIT(13), 0x3);
3541 } else {
3542 rtl92d_phy_enable_anotherphy(hw, false);
3543 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3544 "MAC1 use DBI to update 0x888\n");
3545
3546 rtl92de_write_dword_dbi(hw, RFPGA0_ADDALLOCKEN,
3547 rtl92de_read_dword_dbi(hw,
3548 RFPGA0_ADDALLOCKEN,
3549 BIT(3)) | BIT(12) | BIT(13),
3550 BIT(3));
3551 rtl92d_phy_powerdown_anotherphy(hw, false);
3552 }
3553 } else {
3554
3555
3556 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x33);
3557 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x3);
3558
3559 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | BIT(13), 0);
3560 }
3561 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
3562 rfpath++) {
3563 rtlphy->rfreg_chnlval[rfpath] = rtl_get_rfreg(hw, rfpath,
3564 RF_CHNLBW, RFREG_OFFSET_MASK);
3565 rtlphy->reg_rf3c[rfpath] = rtl_get_rfreg(hw, rfpath, 0x3C,
3566 RFREG_OFFSET_MASK);
3567 }
3568 for (i = 0; i < 2; i++)
3569 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "RF 0x18 = 0x%x\n",
3570 rtlphy->rfreg_chnlval[i]);
3571 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<==\n");
3572
3573}
3574
3575bool rtl92d_phy_check_poweroff(struct ieee80211_hw *hw)
3576{
3577 struct rtl_priv *rtlpriv = rtl_priv(hw);
3578 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3579 u8 u1btmp;
3580 unsigned long flags;
3581
3582 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) {
3583 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3584 rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON));
3585 return true;
3586 }
3587 spin_lock_irqsave(&globalmutex_power, flags);
3588 if (rtlhal->interfaceindex == 0) {
3589 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3590 rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON));
3591 u1btmp = rtl_read_byte(rtlpriv, REG_MAC1);
3592 u1btmp &= MAC1_ON;
3593 } else {
3594 u1btmp = rtl_read_byte(rtlpriv, REG_MAC1);
3595 rtl_write_byte(rtlpriv, REG_MAC1, u1btmp & (~MAC1_ON));
3596 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3597 u1btmp &= MAC0_ON;
3598 }
3599 if (u1btmp) {
3600 spin_unlock_irqrestore(&globalmutex_power, flags);
3601 return false;
3602 }
3603 u1btmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
3604 u1btmp |= BIT(7);
3605 rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1btmp);
3606 spin_unlock_irqrestore(&globalmutex_power, flags);
3607 return true;
3608}
3609
