1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31#ifndef __RTL8723E_DEF_H__
32#define __RTL8723E_DEF_H__
33
34#define HAL_PRIME_CHNL_OFFSET_LOWER 1
35
36#define RX_MPDU_QUEUE 0
37
38#define CHIP_8723 BIT(0)
39#define NORMAL_CHIP BIT(3)
40#define RF_TYPE_1T2R BIT(4)
41#define RF_TYPE_2T2R BIT(5)
42#define CHIP_VENDOR_UMC BIT(7)
43#define B_CUT_VERSION BIT(12)
44#define C_CUT_VERSION BIT(13)
45#define D_CUT_VERSION ((BIT(12)|BIT(13)))
46#define E_CUT_VERSION BIT(14)
47#define RF_RL_ID (BIT(31)|BIT(30)|BIT(29)|BIT(28))
48
49
50
51#define IC_TYPE_MASK (BIT(0)|BIT(1)|BIT(2))
52#define CHIP_TYPE_MASK BIT(3)
53#define RF_TYPE_MASK (BIT(4)|BIT(5)|BIT(6))
54#define MANUFACTUER_MASK BIT(7)
55#define ROM_VERSION_MASK (BIT(11)|BIT(10)|BIT(9)|BIT(8))
56#define CUT_VERSION_MASK (BIT(15)|BIT(14)|BIT(13)|BIT(12))
57
58
59#define GET_CVID_IC_TYPE(version) ((version) & IC_TYPE_MASK)
60#define GET_CVID_MANUFACTUER(version) ((version) & MANUFACTUER_MASK)
61#define GET_CVID_CUT_VERSION(version) ((version) & CUT_VERSION_MASK)
62
63#define IS_81XXC(version) ((GET_CVID_IC_TYPE(version) == 0) ?\
64 true : false)
65#define IS_8723_SERIES(version) \
66 ((GET_CVID_IC_TYPE(version) == CHIP_8723) ? true : false)
67#define IS_CHIP_VENDOR_UMC(version) \
68 ((GET_CVID_MANUFACTUER(version)) ? true : false)
69
70#define IS_VENDOR_UMC_A_CUT(version) ((IS_CHIP_VENDOR_UMC(version)) ? \
71 ((GET_CVID_CUT_VERSION(version)) ? false : true) : false)
72#define IS_VENDOR_8723_A_CUT(version) ((IS_8723_SERIES(version)) ? \
73 ((GET_CVID_CUT_VERSION(version)) ? false : true) : false)
74#define IS_81xxC_VENDOR_UMC_B_CUT(version) ((IS_CHIP_VENDOR_UMC(version)) \
75 ? ((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? \
76 true : false) : false)
77
78enum rf_optype {
79 RF_OP_BY_SW_3WIRE = 0,
80 RF_OP_BY_FW,
81 RF_OP_MAX
82};
83
84enum rf_power_state {
85 RF_ON,
86 RF_OFF,
87 RF_SLEEP,
88 RF_SHUT_DOWN,
89};
90
91enum power_save_mode {
92 POWER_SAVE_MODE_ACTIVE,
93 POWER_SAVE_MODE_SAVE,
94};
95
96enum power_polocy_config {
97 POWERCFG_MAX_POWER_SAVINGS,
98 POWERCFG_GLOBAL_POWER_SAVINGS,
99 POWERCFG_LOCAL_POWER_SAVINGS,
100 POWERCFG_LENOVO,
101};
102
103enum interface_select_pci {
104 INTF_SEL1_MINICARD = 0,
105 INTF_SEL0_PCIE = 1,
106 INTF_SEL2_RSV = 2,
107 INTF_SEL3_RSV = 3,
108};
109
110enum hal_fw_c2h_cmd_id {
111 HAL_FW_C2H_CMD_Read_MACREG = 0,
112 HAL_FW_C2H_CMD_Read_BBREG = 1,
113 HAL_FW_C2H_CMD_Read_RFREG = 2,
114 HAL_FW_C2H_CMD_Read_EEPROM = 3,
115 HAL_FW_C2H_CMD_Read_EFUSE = 4,
116 HAL_FW_C2H_CMD_Read_CAM = 5,
117 HAL_FW_C2H_CMD_Get_BasicRate = 6,
118 HAL_FW_C2H_CMD_Get_DataRate = 7,
119 HAL_FW_C2H_CMD_Survey = 8,
120 HAL_FW_C2H_CMD_SurveyDone = 9,
121 HAL_FW_C2H_CMD_JoinBss = 10,
122 HAL_FW_C2H_CMD_AddSTA = 11,
123 HAL_FW_C2H_CMD_DelSTA = 12,
124 HAL_FW_C2H_CMD_AtimDone = 13,
125 HAL_FW_C2H_CMD_TX_Report = 14,
126 HAL_FW_C2H_CMD_CCX_Report = 15,
127 HAL_FW_C2H_CMD_DTM_Report = 16,
128 HAL_FW_C2H_CMD_TX_Rate_Statistics = 17,
129 HAL_FW_C2H_CMD_C2HLBK = 18,
130 HAL_FW_C2H_CMD_C2HDBG = 19,
131 HAL_FW_C2H_CMD_C2HFEEDBACK = 20,
132 HAL_FW_C2H_CMD_MAX
133};
134
135enum rtl_desc_qsel {
136 QSLT_BK = 0x2,
137 QSLT_BE = 0x0,
138 QSLT_VI = 0x5,
139 QSLT_VO = 0x7,
140 QSLT_BEACON = 0x10,
141 QSLT_HIGH = 0x11,
142 QSLT_MGNT = 0x12,
143 QSLT_CMD = 0x13,
144};
145
146struct phy_sts_cck_8723e_t {
147 u8 adc_pwdb_X[4];
148 u8 sq_rpt;
149 u8 cck_agc_rpt;
150};
151
152struct h2c_cmd_8723e {
153 u8 element_id;
154 u32 cmd_len;
155 u8 *p_cmdbuffer;
156};
157
158#endif
159