1/****************************************************************************** 2 * 3 * Copyright(c) 2009-2014 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26#ifndef __RTL8723BE_REG_H__ 27#define __RTL8723BE_REG_H__ 28 29#define TXPKT_BUF_SELECT 0x69 30#define RXPKT_BUF_SELECT 0xA5 31#define DISABLE_TRXPKT_BUF_ACCESS 0x0 32 33#define REG_SYS_ISO_CTRL 0x0000 34#define REG_SYS_FUNC_EN 0x0002 35#define REG_APS_FSMCO 0x0004 36#define REG_SYS_CLKR 0x0008 37#define REG_9346CR 0x000A 38#define REG_EE_VPD 0x000C 39#define REG_AFE_MISC 0x0010 40#define REG_SPS0_CTRL 0x0011 41#define REG_SPS_OCP_CFG 0x0018 42#define REG_RSV_CTRL 0x001C 43#define REG_RF_CTRL 0x001F 44#define REG_LDOA15_CTRL 0x0020 45#define REG_LDOV12D_CTRL 0x0021 46#define REG_LDOHCI12_CTRL 0x0022 47#define REG_LPLDO_CTRL 0x0023 48#define REG_AFE_XTAL_CTRL 0x0024 49/* 1.5v for 8188EE test chip, 1.4v for MP chip */ 50#define REG_AFE_LDO_CTRL 0x0027 51#define REG_AFE_PLL_CTRL 0x0028 52#define REG_MAC_PHY_CTRL 0x002c 53#define REG_EFUSE_CTRL 0x0030 54#define REG_EFUSE_TEST 0x0034 55#define REG_PWR_DATA 0x0038 56#define REG_CAL_TIMER 0x003C 57#define REG_ACLK_MON 0x003E 58#define REG_GPIO_MUXCFG 0x0040 59#define REG_GPIO_IO_SEL 0x0042 60#define REG_MAC_PINMUX_CFG 0x0043 61#define REG_GPIO_PIN_CTRL 0x0044 62#define REG_GPIO_INTM 0x0048 63#define REG_LEDCFG0 0x004C 64#define REG_LEDCFG1 0x004D 65#define REG_LEDCFG2 0x004E 66#define REG_LEDCFG3 0x004F 67#define REG_FSIMR 0x0050 68#define REG_FSISR 0x0054 69#define REG_HSIMR 0x0058 70#define REG_HSISR 0x005c 71#define REG_GPIO_PIN_CTRL_2 0x0060 72#define REG_GPIO_IO_SEL_2 0x0062 73#define REG_MULTI_FUNC_CTRL 0x0068 74#define REG_GPIO_OUTPUT 0x006c 75#define REG_AFE_XTAL_CTRL_EXT 0x0078 76#define REG_XCK_OUT_CTRL 0x007c 77#define REG_MCUFWDL 0x0080 78#define REG_WOL_EVENT 0x0081 79#define REG_MCUTSTCFG 0x0084 80 81 82#define REG_HIMR 0x00B0 83#define REG_HISR 0x00B4 84#define REG_HIMRE 0x00B8 85#define REG_HISRE 0x00BC 86 87#define REG_EFUSE_ACCESS 0x00CF 88 89#define REG_BIST_SCAN 0x00D0 90#define REG_BIST_RPT 0x00D4 91#define REG_BIST_ROM_RPT 0x00D8 92#define REG_USB_SIE_INTF 0x00E0 93#define REG_PCIE_MIO_INTF 0x00E4 94#define REG_PCIE_MIO_INTD 0x00E8 95#define REG_HPON_FSM 0x00EC 96#define REG_SYS_CFG 0x00F0 97#define REG_GPIO_OUTSTS 0x00F4 98#define REG_SYS_CFG1 0x00F0 99#define REG_ROM_VERSION 0x00FD 100 101#define REG_CR 0x0100 102#define REG_PBP 0x0104 103#define REG_PKT_BUFF_ACCESS_CTRL 0x0106 104#define REG_TRXDMA_CTRL 0x010C 105#define REG_TRXFF_BNDY 0x0114 106#define REG_TRXFF_STATUS 0x0118 107#define REG_RXFF_PTR 0x011C 108 109#define REG_CPWM 0x012F 110#define REG_FWIMR 0x0130 111#define REG_FWISR 0x0134 112#define REG_PKTBUF_DBG_CTRL 0x0140 113#define REG_PKTBUF_DBG_DATA_L 0x0144 114#define REG_PKTBUF_DBG_DATA_H 0x0148 115#define REG_RXPKTBUF_CTRL (REG_PKTBUF_DBG_CTRL + 2) 116 117#define REG_TC0_CTRL 0x0150 118#define REG_TC1_CTRL 0x0154 119#define REG_TC2_CTRL 0x0158 120#define REG_TC3_CTRL 0x015C 121#define REG_TC4_CTRL 0x0160 122#define REG_TCUNIT_BASE 0x0164 123#define REG_MBIST_START 0x0174 124#define REG_MBIST_DONE 0x0178 125#define REG_MBIST_FAIL 0x017C 126#define REG_32K_CTRL 0x0194 127#define REG_C2HEVT_MSG_NORMAL 0x01A0 128#define REG_C2HEVT_CLEAR 0x01AF 129#define REG_C2HEVT_MSG_TEST 0x01B8 130#define REG_MCUTST_1 0x01c0 131#define REG_FMETHR 0x01C8 132#define REG_HMETFR 0x01CC 133#define REG_HMEBOX_0 0x01D0 134#define REG_HMEBOX_1 0x01D4 135#define REG_HMEBOX_2 0x01D8 136#define REG_HMEBOX_3 0x01DC 137 138#define REG_LLT_INIT 0x01E0 139#define REG_BB_ACCEESS_CTRL 0x01E8 140#define REG_BB_ACCESS_DATA 0x01EC 141 142#define REG_HMEBOX_EXT_0 0x01F0 143#define REG_HMEBOX_EXT_1 0x01F4 144#define REG_HMEBOX_EXT_2 0x01F8 145#define REG_HMEBOX_EXT_3 0x01FC 146 147#define REG_RQPN 0x0200 148#define REG_FIFOPAGE 0x0204 149#define REG_TDECTRL 0x0208 150#define REG_TXDMA_OFFSET_CHK 0x020C 151#define REG_TXDMA_STATUS 0x0210 152#define REG_RQPN_NPQ 0x0214 153 154#define REG_RXDMA_AGG_PG_TH 0x0280 155/* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */ 156#define REG_FW_UPD_RDPTR 0x0284 157/* Control the RX DMA.*/ 158#define REG_RXDMA_CONTROL 0x0286 159/* The number of packets in RXPKTBUF. */ 160#define REG_RXPKT_NUM 0x0287 161 162#define REG_PCIE_CTRL_REG 0x0300 163#define REG_INT_MIG 0x0304 164#define REG_BCNQ_DESA 0x0308 165#define REG_HQ_DESA 0x0310 166#define REG_MGQ_DESA 0x0318 167#define REG_VOQ_DESA 0x0320 168#define REG_VIQ_DESA 0x0328 169#define REG_BEQ_DESA 0x0330 170#define REG_BKQ_DESA 0x0338 171#define REG_RX_DESA 0x0340 172 173#define REG_DBI 0x0348 174#define REG_MDIO 0x0354 175#define REG_DBG_SEL 0x0360 176#define REG_PCIE_HRPWM 0x0361 177#define REG_PCIE_HCPWM 0x0363 178#define REG_UART_CTRL 0x0364 179#define REG_WATCH_DOG 0x0368 180#define REG_UART_TX_DESA 0x0370 181#define REG_UART_RX_DESA 0x0378 182 183 184#define REG_HDAQ_DESA_NODEF 0x0000 185#define REG_CMDQ_DESA_NODEF 0x0000 186 187#define REG_VOQ_INFORMATION 0x0400 188#define REG_VIQ_INFORMATION 0x0404 189#define REG_BEQ_INFORMATION 0x0408 190#define REG_BKQ_INFORMATION 0x040C 191#define REG_MGQ_INFORMATION 0x0410 192#define REG_HGQ_INFORMATION 0x0414 193#define REG_BCNQ_INFORMATION 0x0418 194#define REG_TXPKT_EMPTY 0x041A 195 196 197#define REG_CPU_MGQ_INFORMATION 0x041C 198#define REG_FWHW_TXQ_CTRL 0x0420 199#define REG_HWSEQ_CTRL 0x0423 200#define REG_TXPKTBUF_BCNQ_BDNY 0x0424 201#define REG_TXPKTBUF_MGQ_BDNY 0x0425 202#define REG_MULTI_BCNQ_EN 0x0426 203#define REG_MULTI_BCNQ_OFFSET 0x0427 204#define REG_SPEC_SIFS 0x0428 205#define REG_RL 0x042A 206#define REG_DARFRC 0x0430 207#define REG_RARFRC 0x0438 208#define REG_RRSR 0x0440 209#define REG_ARFR0 0x0444 210#define REG_ARFR1 0x0448 211#define REG_ARFR2 0x044C 212#define REG_ARFR3 0x0450 213#define REG_AMPDU_MAX_TIME 0x0456 214#define REG_AGGLEN_LMT 0x0458 215#define REG_AMPDU_MIN_SPACE 0x045C 216#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D 217#define REG_FAST_EDCA_CTRL 0x0460 218#define REG_RD_RESP_PKT_TH 0x0463 219#define REG_INIRTS_RATE_SEL 0x0480 220#define REG_INIDATA_RATE_SEL 0x0484 221#define REG_POWER_STATUS 0x04A4 222#define REG_POWER_STAGE1 0x04B4 223#define REG_POWER_STAGE2 0x04B8 224#define REG_PKT_LIFE_TIME 0x04C0 225#define REG_STBC_SETTING 0x04C4 226#define REG_PROT_MODE_CTRL 0x04C8 227#define REG_BAR_MODE_CTRL 0x04CC 228#define REG_RA_TRY_RATE_AGG_LMT 0x04CF 229#define REG_EARLY_MODE_CONTROL 0x04D0 230#define REG_NQOS_SEQ 0x04DC 231#define REG_QOS_SEQ 0x04DE 232#define REG_NEED_CPU_HANDLE 0x04E0 233#define REG_PKT_LOSE_RPT 0x04E1 234#define REG_PTCL_ERR_STATUS 0x04E2 235#define REG_TX_RPT_CTRL 0x04EC 236#define REG_TX_RPT_TIME 0x04F0 237#define REG_DUMMY 0x04FC 238 239#define REG_EDCA_VO_PARAM 0x0500 240#define REG_EDCA_VI_PARAM 0x0504 241#define REG_EDCA_BE_PARAM 0x0508 242#define REG_EDCA_BK_PARAM 0x050C 243#define REG_BCNTCFG 0x0510 244#define REG_PIFS 0x0512 245#define REG_RDG_PIFS 0x0513 246#define REG_SIFS_CTX 0x0514 247#define REG_SIFS_TRX 0x0516 248#define REG_AGGR_BREAK_TIME 0x051A 249#define REG_SLOT 0x051B 250#define REG_TX_PTCL_CTRL 0x0520 251#define REG_TXPAUSE 0x0522 252#define REG_DIS_TXREQ_CLR 0x0523 253#define REG_RD_CTRL 0x0524 254#define REG_TBTT_PROHIBIT 0x0540 255#define REG_RD_NAV_NXT 0x0544 256#define REG_NAV_PROT_LEN 0x0546 257#define REG_BCN_CTRL 0x0550 258#define REG_USTIME_TSF 0x0551 259#define REG_MBID_NUM 0x0552 260#define REG_DUAL_TSF_RST 0x0553 261#define REG_BCN_INTERVAL 0x0554 262#define REG_MBSSID_BCN_SPACE 0x0554 263#define REG_DRVERLYINT 0x0558 264#define REG_BCNDMATIM 0x0559 265#define REG_ATIMWND 0x055A 266#define REG_BCN_MAX_ERR 0x055D 267#define REG_RXTSF_OFFSET_CCK 0x055E 268#define REG_RXTSF_OFFSET_OFDM 0x055F 269#define REG_TSFTR 0x0560 270#define REG_INIT_TSFTR 0x0564 271#define REG_SECONDARY_CCA_CTRL 0x0577 272#define REG_PSTIMER 0x0580 273#define REG_TIMER0 0x0584 274#define REG_TIMER1 0x0588 275#define REG_ACMHWCTRL 0x05C0 276#define REG_ACMRSTCTRL 0x05C1 277#define REG_ACMAVG 0x05C2 278#define REG_VO_ADMTIME 0x05C4 279#define REG_VI_ADMTIME 0x05C6 280#define REG_BE_ADMTIME 0x05C8 281#define REG_EDCA_RANDOM_GEN 0x05CC 282#define REG_SCH_TXCMD 0x05D0 283 284#define REG_APSD_CTRL 0x0600 285#define REG_BWOPMODE 0x0603 286#define REG_TCR 0x0604 287#define REG_RCR 0x0608 288#define REG_RX_PKT_LIMIT 0x060C 289#define REG_RX_DLK_TIME 0x060D 290#define REG_RX_DRVINFO_SZ 0x060F 291 292#define REG_MACID 0x0610 293#define REG_BSSID 0x0618 294#define REG_MAR 0x0620 295#define REG_MBIDCAMCFG 0x0628 296 297#define REG_USTIME_EDCA 0x0638 298#define REG_MAC_SPEC_SIFS 0x063A 299#define REG_RESP_SIFS_CCK 0x063C 300#define REG_RESP_SIFS_OFDM 0x063E 301#define REG_ACKTO 0x0640 302#define REG_CTS2TO 0x0641 303#define REG_EIFS 0x0642 304 305#define REG_NAV_CTRL 0x0650 306#define REG_BACAMCMD 0x0654 307#define REG_BACAMCONTENT 0x0658 308#define REG_LBDLY 0x0660 309#define REG_FWDLY 0x0661 310#define REG_RXERR_RPT 0x0664 311#define REG_TRXPTCL_CTL 0x0668 312 313#define REG_CAMCMD 0x0670 314#define REG_CAMWRITE 0x0674 315#define REG_CAMREAD 0x0678 316#define REG_CAMDBG 0x067C 317#define REG_SECCFG 0x0680 318 319#define REG_WOW_CTRL 0x0690 320#define REG_PSSTATUS 0x0691 321#define REG_PS_RX_INFO 0x0692 322#define REG_UAPSD_TID 0x0693 323#define REG_LPNAV_CTRL 0x0694 324#define REG_WKFMCAM_NUM 0x0698 325#define REG_WKFMCAM_RWD 0x069C 326#define REG_RXFLTMAP0 0x06A0 327#define REG_RXFLTMAP1 0x06A2 328#define REG_RXFLTMAP2 0x06A4 329#define REG_BCN_PSR_RPT 0x06A8 330#define REG_CALB32K_CTRL 0x06AC 331#define REG_PKT_MON_CTRL 0x06B4 332#define REG_BT_COEX_TABLE 0x06C0 333#define REG_WMAC_RESP_TXINFO 0x06D8 334 335#define REG_USB_INFO 0xFE17 336#define REG_USB_SPECIAL_OPTION 0xFE55 337#define REG_USB_DMA_AGG_TO 0xFE5B 338#define REG_USB_AGG_TO 0xFE5C 339#define REG_USB_AGG_TH 0xFE5D 340 341#define REG_TEST_USB_TXQS 0xFE48 342#define REG_TEST_SIE_VID 0xFE60 343#define REG_TEST_SIE_PID 0xFE62 344#define REG_TEST_SIE_OPTIONAL 0xFE64 345#define REG_TEST_SIE_CHIRP_K 0xFE65 346#define REG_TEST_SIE_PHY 0xFE66 347#define REG_TEST_SIE_MAC_ADDR 0xFE70 348#define REG_TEST_SIE_STRING 0xFE80 349 350#define REG_NORMAL_SIE_VID 0xFE60 351#define REG_NORMAL_SIE_PID 0xFE62 352#define REG_NORMAL_SIE_OPTIONAL 0xFE64 353#define REG_NORMAL_SIE_EP 0xFE65 354#define REG_NORMAL_SIE_PHY 0xFE68 355#define REG_NORMAL_SIE_MAC_ADDR 0xFE70 356#define REG_NORMAL_SIE_STRING 0xFE80 357 358#define CR9346 REG_9346CR 359#define MSR (REG_CR + 2) 360#define ISR REG_HISR 361#define TSFR REG_TSFTR 362 363#define MACIDR0 REG_MACID 364#define MACIDR4 (REG_MACID + 4) 365 366#define PBP REG_PBP 367 368#define IDR0 MACIDR0 369#define IDR4 MACIDR4 370 371#define UNUSED_REGISTER 0x1BF 372#define DCAM UNUSED_REGISTER 373#define PSR UNUSED_REGISTER 374#define BBADDR UNUSED_REGISTER 375#define PHYDATAR UNUSED_REGISTER 376 377#define INVALID_BBRF_VALUE 0x12345678 378 379#define MAX_MSS_DENSITY_2T 0x13 380#define MAX_MSS_DENSITY_1T 0x0A 381 382#define CMDEEPROM_EN BIT(5) 383#define CMDEEPROM_SEL BIT(4) 384#define CMD9346CR_9356SEL BIT(4) 385#define AUTOLOAD_EEPROM (CMDEEPROM_EN | CMDEEPROM_SEL) 386#define AUTOLOAD_EFUSE CMDEEPROM_EN 387 388#define GPIOSEL_GPIO 0 389#define GPIOSEL_ENBT BIT(5) 390 391#define GPIO_IN REG_GPIO_PIN_CTRL 392#define GPIO_OUT (REG_GPIO_PIN_CTRL + 1) 393#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL + 2) 394#define GPIO_MOD (REG_GPIO_PIN_CTRL + 3) 395 396/* 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte) */ 397#define HSIMR_GPIO12_0_INT_EN BIT(0) 398#define HSIMR_SPS_OCP_INT_EN BIT(5) 399#define HSIMR_RON_INT_EN BIT(6) 400#define HSIMR_PDN_INT_EN BIT(7) 401#define HSIMR_GPIO9_INT_EN BIT(25) 402 403/* 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) */ 404 405#define HSISR_GPIO12_0_INT BIT(0) 406#define HSISR_SPS_OCP_INT BIT(5) 407#define HSISR_RON_INT_EN BIT(6) 408#define HSISR_PDNINT BIT(7) 409#define HSISR_GPIO9_INT BIT(25) 410 411#define MSR_NOLINK 0x00 412#define MSR_ADHOC 0x01 413#define MSR_INFRA 0x02 414#define MSR_AP 0x03 415 416#define RRSR_RSC_OFFSET 21 417#define RRSR_SHORT_OFFSET 23 418#define RRSR_RSC_BW_40M 0x600000 419#define RRSR_RSC_UPSUBCHNL 0x400000 420#define RRSR_RSC_LOWSUBCHNL 0x200000 421#define RRSR_SHORT 0x800000 422#define RRSR_1M BIT(0) 423#define RRSR_2M BIT(1) 424#define RRSR_5_5M BIT(2) 425#define RRSR_11M BIT(3) 426#define RRSR_6M BIT(4) 427#define RRSR_9M BIT(5) 428#define RRSR_12M BIT(6) 429#define RRSR_18M BIT(7) 430#define RRSR_24M BIT(8) 431#define RRSR_36M BIT(9) 432#define RRSR_48M BIT(10) 433#define RRSR_54M BIT(11) 434#define RRSR_MCS0 BIT(12) 435#define RRSR_MCS1 BIT(13) 436#define RRSR_MCS2 BIT(14) 437#define RRSR_MCS3 BIT(15) 438#define RRSR_MCS4 BIT(16) 439#define RRSR_MCS5 BIT(17) 440#define RRSR_MCS6 BIT(18) 441#define RRSR_MCS7 BIT(19) 442#define BRSR_ACKSHORTPMB BIT(23) 443 444#define RATR_1M 0x00000001 445#define RATR_2M 0x00000002 446#define RATR_55M 0x00000004 447#define RATR_11M 0x00000008 448#define RATR_6M 0x00000010 449#define RATR_9M 0x00000020 450#define RATR_12M 0x00000040 451#define RATR_18M 0x00000080 452#define RATR_24M 0x00000100 453#define RATR_36M 0x00000200 454#define RATR_48M 0x00000400 455#define RATR_54M 0x00000800 456#define RATR_MCS0 0x00001000 457#define RATR_MCS1 0x00002000 458#define RATR_MCS2 0x00004000 459#define RATR_MCS3 0x00008000 460#define RATR_MCS4 0x00010000 461#define RATR_MCS5 0x00020000 462#define RATR_MCS6 0x00040000 463#define RATR_MCS7 0x00080000 464#define RATR_MCS8 0x00100000 465#define RATR_MCS9 0x00200000 466#define RATR_MCS10 0x00400000 467#define RATR_MCS11 0x00800000 468#define RATR_MCS12 0x01000000 469#define RATR_MCS13 0x02000000 470#define RATR_MCS14 0x04000000 471#define RATR_MCS15 0x08000000 472 473#define RATE_1M BIT(0) 474#define RATE_2M BIT(1) 475#define RATE_5_5M BIT(2) 476#define RATE_11M BIT(3) 477#define RATE_6M BIT(4) 478#define RATE_9M BIT(5) 479#define RATE_12M BIT(6) 480#define RATE_18M BIT(7) 481#define RATE_24M BIT(8) 482#define RATE_36M BIT(9) 483#define RATE_48M BIT(10) 484#define RATE_54M BIT(11) 485#define RATE_MCS0 BIT(12) 486#define RATE_MCS1 BIT(13) 487#define RATE_MCS2 BIT(14) 488#define RATE_MCS3 BIT(15) 489#define RATE_MCS4 BIT(16) 490#define RATE_MCS5 BIT(17) 491#define RATE_MCS6 BIT(18) 492#define RATE_MCS7 BIT(19) 493#define RATE_MCS8 BIT(20) 494#define RATE_MCS9 BIT(21) 495#define RATE_MCS10 BIT(22) 496#define RATE_MCS11 BIT(23) 497#define RATE_MCS12 BIT(24) 498#define RATE_MCS13 BIT(25) 499#define RATE_MCS14 BIT(26) 500#define RATE_MCS15 BIT(27) 501 502#define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M) 503#define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | RATR_18M |\ 504 RATR_24M | RATR_36M | RATR_48M | RATR_54M) 505#define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 |\ 506 RATR_MCS3 | RATR_MCS4 | RATR_MCS5 |\ 507 RATR_MCS6 | RATR_MCS7) 508#define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 |\ 509 RATR_MCS11 | RATR_MCS12 | RATR_MCS13 |\ 510 RATR_MCS14 | RATR_MCS15) 511 512#define BW_OPMODE_20MHZ BIT(2) 513#define BW_OPMODE_5G BIT(1) 514#define BW_OPMODE_11J BIT(0) 515 516#define CAM_VALID BIT(15) 517#define CAM_NOTVALID 0x0000 518#define CAM_USEDK BIT(5) 519 520#define CAM_NONE 0x0 521#define CAM_WEP40 0x01 522#define CAM_TKIP 0x02 523#define CAM_AES 0x04 524#define CAM_WEP104 0x05 525 526#define TOTAL_CAM_ENTRY 32 527#define HALF_CAM_ENTRY 16 528 529#define CAM_WRITE BIT(16) 530#define CAM_READ 0x00000000 531#define CAM_POLLINIG BIT(31) 532 533#define SCR_USEDK 0x01 534#define SCR_TXSEC_ENABLE 0x02 535#define SCR_RXSEC_ENABLE 0x04 536 537#define WOW_PMEN BIT(0) 538#define WOW_WOMEN BIT(1) 539#define WOW_MAGIC BIT(2) 540#define WOW_UWF BIT(3) 541 542/********************************************* 543* 8723BE IMR/ISR bits 544**********************************************/ 545#define IMR_DISABLED 0x0 546/* IMR DW0(0x0060-0063) Bit 0-31 */ 547#define IMR_TXCCK BIT(30) /* TXRPT interrupt when 548 * CCX bit of the packet is set 549 */ 550#define IMR_PSTIMEOUT BIT(29) /* Power Save Time Out Interrupt */ 551#define IMR_GTINT4 BIT(28) /* When GTIMER4 expires, 552 * this bit is set to 1 553 */ 554#define IMR_GTINT3 BIT(27) /* When GTIMER3 expires, 555 * this bit is set to 1 556 */ 557#define IMR_TBDER BIT(26) /* Transmit Beacon0 Error */ 558#define IMR_TBDOK BIT(25) /* Transmit Beacon0 OK */ 559#define IMR_TSF_BIT32_TOGGLE BIT(24) /* TSF Timer BIT32 toggle 560 * indication interrupt 561 */ 562#define IMR_BCNDMAINT0 BIT(20) /* Beacon DMA Interrupt 0 */ 563#define IMR_BCNDOK0 BIT(16) /* Beacon Queue DMA OK0 */ 564#define IMR_HSISR_IND_ON_INT BIT(15) /* HSISR Indicator (HSIMR & HSISR is 565 * true, this bit is set to 1) 566 */ 567#define IMR_BCNDMAINT_E BIT(14) /* Beacon DMA Interrupt 568 * Extension for Win7 569 */ 570#define IMR_ATIMEND BIT(12) /* CTWidnow End or ATIM Window End */ 571#define IMR_HISR1_IND_INT BIT(11) /* HISR1 Indicator (HISR1 & HIMR1 is 572 * true, this bit is set to 1) 573 */ 574#define IMR_C2HCMD BIT(10) /* CPU to Host Command INT Status, 575 * Write 1 clear 576 */ 577#define IMR_CPWM2 BIT(9) /* CPU power Mode exchange INT Status, 578 * Write 1 clear 579 */ 580#define IMR_CPWM BIT(8) /* CPU power Mode exchange INT Status, 581 * Write 1 clear 582 */ 583#define IMR_HIGHDOK BIT(7) /* High Queue DMA OK */ 584#define IMR_MGNTDOK BIT(6) /* Management Queue DMA OK */ 585#define IMR_BKDOK BIT(5) /* AC_BK DMA OK */ 586#define IMR_BEDOK BIT(4) /* AC_BE DMA OK */ 587#define IMR_VIDOK BIT(3) /* AC_VI DMA OK */ 588#define IMR_VODOK BIT(2) /* AC_VO DMA OK */ 589#define IMR_RDU BIT(1) /* Rx Descriptor Unavailable */ 590#define IMR_ROK BIT(0) /* Receive DMA OK */ 591 592/* IMR DW1(0x00B4-00B7) Bit 0-31 */ 593#define IMR_BCNDMAINT7 BIT(27) /* Beacon DMA Interrupt 7 */ 594#define IMR_BCNDMAINT6 BIT(26) /* Beacon DMA Interrupt 6 */ 595#define IMR_BCNDMAINT5 BIT(25) /* Beacon DMA Interrupt 5 */ 596#define IMR_BCNDMAINT4 BIT(24) /* Beacon DMA Interrupt 4 */ 597#define IMR_BCNDMAINT3 BIT(23) /* Beacon DMA Interrupt 3 */ 598#define IMR_BCNDMAINT2 BIT(22) /* Beacon DMA Interrupt 2 */ 599#define IMR_BCNDMAINT1 BIT(21) /* Beacon DMA Interrupt 1 */ 600#define IMR_BCNDOK7 BIT(20) /* Beacon Queue DMA OK Interrup 7 */ 601#define IMR_BCNDOK6 BIT(19) /* Beacon Queue DMA OK Interrup 6 */ 602#define IMR_BCNDOK5 BIT(18) /* Beacon Queue DMA OK Interrup 5 */ 603#define IMR_BCNDOK4 BIT(17) /* Beacon Queue DMA OK Interrup 4 */ 604#define IMR_BCNDOK3 BIT(16) /* Beacon Queue DMA OK Interrup 3 */ 605#define IMR_BCNDOK2 BIT(15) /* Beacon Queue DMA OK Interrup 2 */ 606#define IMR_BCNDOK1 BIT(14) /* Beacon Queue DMA OK Interrup 1 */ 607#define IMR_ATIMEND_E BIT(13) /* ATIM Window End Extension for Win7 */ 608#define IMR_TXERR BIT(11) /* Tx Error Flag Interrupt Status, 609 * write 1 clear. 610 */ 611#define IMR_RXERR BIT(10) /* Rx Error Flag INT Status, 612 * Write 1 clear 613 */ 614#define IMR_TXFOVW BIT(9) /* Transmit FIFO Overflow */ 615#define IMR_RXFOVW BIT(8) /* Receive FIFO Overflow */ 616 617#define HWSET_MAX_SIZE 512 618#define EFUSE_MAX_SECTION 64 619#define EFUSE_REAL_CONTENT_LEN 256 620#define EFUSE_OOB_PROTECT_BYTES 18 /* PG data exclude header, 621 * dummy 7 bytes frome CP test 622 * and reserved 1byte. 623 */ 624 625#define EEPROM_DEFAULT_TSSI 0x0 626#define EEPROM_DEFAULT_TXPOWERDIFF 0x0 627#define EEPROM_DEFAULT_CRYSTALCAP 0x5 628#define EEPROM_DEFAULT_BOARDTYPE 0x02 629#define EEPROM_DEFAULT_TXPOWER 0x1010 630#define EEPROM_DEFAULT_HT2T_TXPWR 0x10 631 632#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3 633#define EEPROM_DEFAULT_THERMALMETER 0x18 634#define EEPROM_DEFAULT_ANTTXPOWERDIFF 0x0 635#define EEPROM_DEFAULT_TXPWDIFF_CRYSTALCAP 0x5 636#define EEPROM_DEFAULT_TXPOWERLEVEL 0x22 637#define EEPROM_DEFAULT_HT40_2SDIFF 0x0 638#define EEPROM_DEFAULT_HT20_DIFF 2 639#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3 640#define EEPROM_DEFAULT_HT40_PWRMAXOFFSET 0 641#define EEPROM_DEFAULT_HT20_PWRMAXOFFSET 0 642 643#define RF_OPTION1 0x79 644#define RF_OPTION2 0x7A 645#define RF_OPTION3 0x7B 646#define RF_OPTION4 0xC3 647 648#define EEPROM_DEFAULT_PID 0x1234 649#define EEPROM_DEFAULT_VID 0x5678 650#define EEPROM_DEFAULT_CUSTOMERID 0xAB 651#define EEPROM_DEFAULT_SUBCUSTOMERID 0xCD 652#define EEPROM_DEFAULT_VERSION 0 653 654#define EEPROM_CHANNEL_PLAN_FCC 0x0 655#define EEPROM_CHANNEL_PLAN_IC 0x1 656#define EEPROM_CHANNEL_PLAN_ETSI 0x2 657#define EEPROM_CHANNEL_PLAN_SPAIN 0x3 658#define EEPROM_CHANNEL_PLAN_FRANCE 0x4 659#define EEPROM_CHANNEL_PLAN_MKK 0x5 660#define EEPROM_CHANNEL_PLAN_MKK1 0x6 661#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 662#define EEPROM_CHANNEL_PLAN_TELEC 0x8 663#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9 664#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA 665#define EEPROM_CHANNEL_PLAN_NCC 0xB 666#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 667 668#define EEPROM_CID_DEFAULT 0x0 669#define EEPROM_CID_TOSHIBA 0x4 670#define EEPROM_CID_CCX 0x10 671#define EEPROM_CID_QMI 0x0D 672#define EEPROM_CID_WHQL 0xFE 673 674#define RTL8723BE_EEPROM_ID 0x8129 675 676#define EEPROM_HPON 0x02 677#define EEPROM_CLK 0x06 678#define EEPROM_TESTR 0x08 679 680 681#define EEPROM_TXPOWERCCK 0x10 682#define EEPROM_TXPOWERHT40_1S 0x16 683#define EEPROM_TXPOWERHT20DIFF 0x1B 684#define EEPROM_TXPOWER_OFDMDIFF 0x1B 685 686 687 688#define EEPROM_TX_PWR_INX 0x10 689 690#define EEPROM_CHANNELPLAN 0xB8 691#define EEPROM_XTAL_8723BE 0xB9 692#define EEPROM_THERMAL_METER_88E 0xBA 693#define EEPROM_IQK_LCK_88E 0xBB 694 695#define EEPROM_RF_BOARD_OPTION_88E 0xC1 696#define EEPROM_RF_FEATURE_OPTION_88E 0xC2 697#define EEPROM_RF_BT_SETTING_88E 0xC3 698#define EEPROM_VERSION 0xC4 699#define EEPROM_CUSTOMER_ID 0xC5 700#define EEPROM_RF_ANTENNA_OPT_88E 0xC9 701 702#define EEPROM_MAC_ADDR 0xD0 703#define EEPROM_VID 0xD6 704#define EEPROM_DID 0xD8 705#define EEPROM_SVID 0xDA 706#define EEPROM_SMID 0xDC 707 708#define STOPBECON BIT(6) 709#define STOPHIGHT BIT(5) 710#define STOPMGT BIT(4) 711#define STOPVO BIT(3) 712#define STOPVI BIT(2) 713#define STOPBE BIT(1) 714#define STOPBK BIT(0) 715 716#define RCR_APPFCS BIT(31) 717#define RCR_APP_MIC BIT(30) 718#define RCR_APP_ICV BIT(29) 719#define RCR_APP_PHYST_RXFF BIT(28) 720#define RCR_APP_BA_SSN BIT(27) 721#define RCR_ENMBID BIT(24) 722#define RCR_LSIGEN BIT(23) 723#define RCR_MFBEN BIT(22) 724#define RCR_HTC_LOC_CTRL BIT(14) 725#define RCR_AMF BIT(13) 726#define RCR_ACF BIT(12) 727#define RCR_ADF BIT(11) 728#define RCR_AICV BIT(9) 729#define RCR_ACRC32 BIT(8) 730#define RCR_CBSSID_BCN BIT(7) 731#define RCR_CBSSID_DATA BIT(6) 732#define RCR_CBSSID RCR_CBSSID_DATA 733#define RCR_APWRMGT BIT(5) 734#define RCR_ADD3 BIT(4) 735#define RCR_AB BIT(3) 736#define RCR_AM BIT(2) 737#define RCR_APM BIT(1) 738#define RCR_AAP BIT(0) 739#define RCR_MXDMA_OFFSET 8 740#define RCR_FIFO_OFFSET 13 741 742#define RSV_CTRL 0x001C 743#define RD_CTRL 0x0524 744 745#define REG_USB_INFO 0xFE17 746#define REG_USB_SPECIAL_OPTION 0xFE55 747#define REG_USB_DMA_AGG_TO 0xFE5B 748#define REG_USB_AGG_TO 0xFE5C 749#define REG_USB_AGG_TH 0xFE5D 750 751#define REG_USB_VID 0xFE60 752#define REG_USB_PID 0xFE62 753#define REG_USB_OPTIONAL 0xFE64 754#define REG_USB_CHIRP_K 0xFE65 755#define REG_USB_PHY 0xFE66 756#define REG_USB_MAC_ADDR 0xFE70 757#define REG_USB_HRPWM 0xFE58 758#define REG_USB_HCPWM 0xFE57 759 760#define SW18_FPWM BIT(3) 761 762#define ISO_MD2PP BIT(0) 763#define ISO_UA2USB BIT(1) 764#define ISO_UD2CORE BIT(2) 765#define ISO_PA2PCIE BIT(3) 766#define ISO_PD2CORE BIT(4) 767#define ISO_IP2MAC BIT(5) 768#define ISO_DIOP BIT(6) 769#define ISO_DIOE BIT(7) 770#define ISO_EB2CORE BIT(8) 771#define ISO_DIOR BIT(9) 772 773#define PWC_EV25V BIT(14) 774#define PWC_EV12V BIT(15) 775 776#define FEN_BBRSTB BIT(0) 777#define FEN_BB_GLB_RSTN BIT(1) 778#define FEN_USBA BIT(2) 779#define FEN_UPLL BIT(3) 780#define FEN_USBD BIT(4) 781#define FEN_DIO_PCIE BIT(5) 782#define FEN_PCIEA BIT(6) 783#define FEN_PPLL BIT(7) 784#define FEN_PCIED BIT(8) 785#define FEN_DIOE BIT(9) 786#define FEN_CPUEN BIT(10) 787#define FEN_DCORE BIT(11) 788#define FEN_ELDR BIT(12) 789#define FEN_DIO_RF BIT(13) 790#define FEN_HWPDN BIT(14) 791#define FEN_MREGEN BIT(15) 792 793#define PFM_LDALL BIT(0) 794#define PFM_ALDN BIT(1) 795#define PFM_LDKP BIT(2) 796#define PFM_WOWL BIT(3) 797#define ENPDN BIT(4) 798#define PDN_PL BIT(5) 799#define APFM_ONMAC BIT(8) 800#define APFM_OFF BIT(9) 801#define APFM_RSM BIT(10) 802#define AFSM_HSUS BIT(11) 803#define AFSM_PCIE BIT(12) 804#define APDM_MAC BIT(13) 805#define APDM_HOST BIT(14) 806#define APDM_HPDN BIT(15) 807#define RDY_MACON BIT(16) 808#define SUS_HOST BIT(17) 809#define ROP_ALD BIT(20) 810#define ROP_PWR BIT(21) 811#define ROP_SPS BIT(22) 812#define SOP_MRST BIT(25) 813#define SOP_FUSE BIT(26) 814#define SOP_ABG BIT(27) 815#define SOP_AMB BIT(28) 816#define SOP_RCK BIT(29) 817#define SOP_A8M BIT(30) 818#define XOP_BTCK BIT(31) 819 820#define ANAD16V_EN BIT(0) 821#define ANA8M BIT(1) 822#define MACSLP BIT(4) 823#define LOADER_CLK_EN BIT(5) 824#define _80M_SSC_DIS BIT(7) 825#define _80M_SSC_EN_HO BIT(8) 826#define PHY_SSC_RSTB BIT(9) 827#define SEC_CLK_EN BIT(10) 828#define MAC_CLK_EN BIT(11) 829#define SYS_CLK_EN BIT(12) 830#define RING_CLK_EN BIT(13) 831 832#define BOOT_FROM_EEPROM BIT(4) 833#define EEPROM_EN BIT(5) 834 835#define AFE_BGEN BIT(0) 836#define AFE_MBEN BIT(1) 837#define MAC_ID_EN BIT(7) 838 839#define WLOCK_ALL BIT(0) 840#define WLOCK_00 BIT(1) 841#define WLOCK_04 BIT(2) 842#define WLOCK_08 BIT(3) 843#define WLOCK_40 BIT(4) 844#define R_DIS_PRST_0 BIT(5) 845#define R_DIS_PRST_1 BIT(6) 846#define LOCK_ALL_EN BIT(7) 847 848#define RF_EN BIT(0) 849#define RF_RSTB BIT(1) 850#define RF_SDMRSTB BIT(2) 851 852#define LDA15_EN BIT(0) 853#define LDA15_STBY BIT(1) 854#define LDA15_OBUF BIT(2) 855#define LDA15_REG_VOS BIT(3) 856#define _LDA15_VOADJ(x) (((x) & 0x7) << 4) 857 858#define LDV12_EN BIT(0) 859#define LDV12_SDBY BIT(1) 860#define LPLDO_HSM BIT(2) 861#define LPLDO_LSM_DIS BIT(3) 862#define _LDV12_VADJ(x) (((x) & 0xF) << 4) 863 864#define XTAL_EN BIT(0) 865#define XTAL_BSEL BIT(1) 866#define _XTAL_BOSC(x) (((x) & 0x3) << 2) 867#define _XTAL_CADJ(x) (((x) & 0xF) << 4) 868#define XTAL_GATE_USB BIT(8) 869#define _XTAL_USB_DRV(x) (((x) & 0x3) << 9) 870#define XTAL_GATE_AFE BIT(11) 871#define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12) 872#define XTAL_RF_GATE BIT(14) 873#define _XTAL_RF_DRV(x) (((x) & 0x3) << 15) 874#define XTAL_GATE_DIG BIT(17) 875#define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18) 876#define XTAL_BT_GATE BIT(20) 877#define _XTAL_BT_DRV(x) (((x) & 0x3) << 21) 878#define _XTAL_GPIO(x) (((x) & 0x7) << 23) 879 880#define CKDLY_AFE BIT(26) 881#define CKDLY_USB BIT(27) 882#define CKDLY_DIG BIT(28) 883#define CKDLY_BT BIT(29) 884 885#define APLL_EN BIT(0) 886#define APLL_320_EN BIT(1) 887#define APLL_FREF_SEL BIT(2) 888#define APLL_EDGE_SEL BIT(3) 889#define APLL_WDOGB BIT(4) 890#define APLL_LPFEN BIT(5) 891 892#define APLL_REF_CLK_13MHZ 0x1 893#define APLL_REF_CLK_19_2MHZ 0x2 894#define APLL_REF_CLK_20MHZ 0x3 895#define APLL_REF_CLK_25MHZ 0x4 896#define APLL_REF_CLK_26MHZ 0x5 897#define APLL_REF_CLK_38_4MHZ 0x6 898#define APLL_REF_CLK_40MHZ 0x7 899 900#define APLL_320EN BIT(14) 901#define APLL_80EN BIT(15) 902#define APLL_1MEN BIT(24) 903 904#define ALD_EN BIT(18) 905#define EF_PD BIT(19) 906#define EF_FLAG BIT(31) 907 908#define EF_TRPT BIT(7) 909#define LDOE25_EN BIT(31) 910 911#define RSM_EN BIT(0) 912#define TIMER_EN BIT(4) 913 914#define TRSW0EN BIT(2) 915#define TRSW1EN BIT(3) 916#define EROM_EN BIT(4) 917#define ENBT BIT(5) 918#define ENUART BIT(8) 919#define UART_910 BIT(9) 920#define ENPMAC BIT(10) 921#define SIC_SWRST BIT(11) 922#define ENSIC BIT(12) 923#define SIC_23 BIT(13) 924#define ENHDP BIT(14) 925#define SIC_LBK BIT(15) 926 927#define LED0PL BIT(4) 928#define LED1PL BIT(12) 929#define LED0DIS BIT(7) 930 931#define MCUFWDL_EN BIT(0) 932#define MCUFWDL_RDY BIT(1) 933#define FWDL_CHKSUM_RPT BIT(2) 934#define MACINI_RDY BIT(3) 935#define BBINI_RDY BIT(4) 936#define RFINI_RDY BIT(5) 937#define WINTINI_RDY BIT(6) 938#define CPRST BIT(23) 939 940#define XCLK_VLD BIT(0) 941#define ACLK_VLD BIT(1) 942#define UCLK_VLD BIT(2) 943#define PCLK_VLD BIT(3) 944#define PCIRSTB BIT(4) 945#define V15_VLD BIT(5) 946#define TRP_B15V_EN BIT(7) 947#define SIC_IDLE BIT(8) 948#define BD_MAC2 BIT(9) 949#define BD_MAC1 BIT(10) 950#define IC_MACPHY_MODE BIT(11) 951#define VENDOR_ID BIT(19) 952#define PAD_HWPD_IDN BIT(22) 953#define TRP_VAUX_EN BIT(23) 954#define TRP_BT_EN BIT(24) 955#define BD_PKG_SEL BIT(25) 956#define BD_HCI_SEL BIT(26) 957#define TYPE_ID BIT(27) 958 959#define CHIP_VER_RTL_MASK 0xF000 960#define CHIP_VER_RTL_SHIFT 12 961 962#define REG_LBMODE (REG_CR + 3) 963 964#define HCI_TXDMA_EN BIT(0) 965#define HCI_RXDMA_EN BIT(1) 966#define TXDMA_EN BIT(2) 967#define RXDMA_EN BIT(3) 968#define PROTOCOL_EN BIT(4) 969#define SCHEDULE_EN BIT(5) 970#define MACTXEN BIT(6) 971#define MACRXEN BIT(7) 972#define ENSWBCN BIT(8) 973#define ENSEC BIT(9) 974 975#define _NETTYPE(x) (((x) & 0x3) << 16) 976#define MASK_NETTYPE 0x30000 977#define NT_NO_LINK 0x0 978#define NT_LINK_AD_HOC 0x1 979#define NT_LINK_AP 0x2 980#define NT_AS_AP 0x3 981 982#define _LBMODE(x) (((x) & 0xF) << 24) 983#define MASK_LBMODE 0xF000000 984#define LOOPBACK_NORMAL 0x0 985#define LOOPBACK_IMMEDIATELY 0xB 986#define LOOPBACK_MAC_DELAY 0x3 987#define LOOPBACK_PHY 0x1 988#define LOOPBACK_DMA 0x7 989 990#define GET_RX_PAGE_SIZE(value) ((value) & 0xF) 991#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) 992#define _PSRX_MASK 0xF 993#define _PSTX_MASK 0xF0 994#define _PSRX(x) (x) 995#define _PSTX(x) ((x) << 4) 996 997#define PBP_64 0x0 998#define PBP_128 0x1 999#define PBP_256 0x2 1000#define PBP_512 0x3
1001#define PBP_1024 0x4 1002 1003#define RXDMA_ARBBW_EN BIT(0) 1004#define RXSHFT_EN BIT(1) 1005#define RXDMA_AGG_EN BIT(2) 1006#define QS_VO_QUEUE BIT(8) 1007#define QS_VI_QUEUE BIT(9) 1008#define QS_BE_QUEUE BIT(10) 1009#define QS_BK_QUEUE BIT(11) 1010#define QS_MANAGER_QUEUE BIT(12) 1011#define QS_HIGH_QUEUE BIT(13) 1012 1013#define HQSEL_VOQ BIT(0) 1014#define HQSEL_VIQ BIT(1) 1015#define HQSEL_BEQ BIT(2) 1016#define HQSEL_BKQ BIT(3) 1017#define HQSEL_MGTQ BIT(4) 1018#define HQSEL_HIQ BIT(5) 1019 1020#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) 1021#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) 1022#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) 1023#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8) 1024#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6) 1025#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4) 1026 1027#define QUEUE_LOW 1 1028#define QUEUE_NORMAL 2 1029#define QUEUE_HIGH 3 1030 1031#define _LLT_NO_ACTIVE 0x0 1032#define _LLT_WRITE_ACCESS 0x1 1033#define _LLT_READ_ACCESS 0x2 1034 1035#define _LLT_INIT_DATA(x) ((x) & 0xFF) 1036#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) 1037#define _LLT_OP(x) (((x) & 0x3) << 30) 1038#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) 1039 1040#define BB_WRITE_READ_MASK (BIT(31) | BIT(30)) 1041#define BB_WRITE_EN BIT(30) 1042#define BB_READ_EN BIT(31) 1043 1044#define _HPQ(x) ((x) & 0xFF) 1045#define _LPQ(x) (((x) & 0xFF) << 8) 1046#define _PUBQ(x) (((x) & 0xFF) << 16) 1047#define _NPQ(x) ((x) & 0xFF) 1048 1049#define HPQ_PUBLIC_DIS BIT(24) 1050#define LPQ_PUBLIC_DIS BIT(25) 1051#define LD_RQPN BIT(31) 1052 1053#define BCN_VALID BIT(16) 1054#define BCN_HEAD(x) (((x) & 0xFF) << 8) 1055#define BCN_HEAD_MASK 0xFF00 1056 1057#define BLK_DESC_NUM_SHIFT 4 1058#define BLK_DESC_NUM_MASK 0xF 1059 1060#define DROP_DATA_EN BIT(9) 1061 1062#define EN_AMPDU_RTY_NEW BIT(7) 1063 1064#define _INIRTSMCS_SEL(x) ((x) & 0x3F) 1065 1066#define _SPEC_SIFS_CCK(x) ((x) & 0xFF) 1067#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) 1068 1069#define RATE_REG_BITMAP_ALL 0xFFFFF 1070 1071#define _RRSC_BITMAP(x) ((x) & 0xFFFFF) 1072 1073#define _RRSR_RSC(x) (((x) & 0x3) << 21) 1074#define RRSR_RSC_RESERVED 0x0 1075#define RRSR_RSC_UPPER_SUBCHANNEL 0x1 1076#define RRSR_RSC_LOWER_SUBCHANNEL 0x2 1077#define RRSR_RSC_DUPLICATE_MODE 0x3 1078 1079#define USE_SHORT_G1 BIT(20) 1080 1081#define _AGGLMT_MCS0(x) ((x) & 0xF) 1082#define _AGGLMT_MCS1(x) (((x) & 0xF) << 4) 1083#define _AGGLMT_MCS2(x) (((x) & 0xF) << 8) 1084#define _AGGLMT_MCS3(x) (((x) & 0xF) << 12) 1085#define _AGGLMT_MCS4(x) (((x) & 0xF) << 16) 1086#define _AGGLMT_MCS5(x) (((x) & 0xF) << 20) 1087#define _AGGLMT_MCS6(x) (((x) & 0xF) << 24) 1088#define _AGGLMT_MCS7(x) (((x) & 0xF) << 28) 1089 1090#define RETRY_LIMIT_SHORT_SHIFT 8 1091#define RETRY_LIMIT_LONG_SHIFT 0 1092 1093#define _DARF_RC1(x) ((x) & 0x1F) 1094#define _DARF_RC2(x) (((x) & 0x1F) << 8) 1095#define _DARF_RC3(x) (((x) & 0x1F) << 16) 1096#define _DARF_RC4(x) (((x) & 0x1F) << 24) 1097#define _DARF_RC5(x) ((x) & 0x1F) 1098#define _DARF_RC6(x) (((x) & 0x1F) << 8) 1099#define _DARF_RC7(x) (((x) & 0x1F) << 16) 1100#define _DARF_RC8(x) (((x) & 0x1F) << 24) 1101 1102#define _RARF_RC1(x) ((x) & 0x1F) 1103#define _RARF_RC2(x) (((x) & 0x1F) << 8) 1104#define _RARF_RC3(x) (((x) & 0x1F) << 16) 1105#define _RARF_RC4(x) (((x) & 0x1F) << 24) 1106#define _RARF_RC5(x) ((x) & 0x1F) 1107#define _RARF_RC6(x) (((x) & 0x1F) << 8) 1108#define _RARF_RC7(x) (((x) & 0x1F) << 16) 1109#define _RARF_RC8(x) (((x) & 0x1F) << 24) 1110 1111#define AC_PARAM_TXOP_LIMIT_OFFSET 16 1112#define AC_PARAM_ECW_MAX_OFFSET 12 1113#define AC_PARAM_ECW_MIN_OFFSET 8 1114#define AC_PARAM_AIFS_OFFSET 0 1115 1116#define _AIFS(x) (x) 1117#define _ECW_MAX_MIN(x) ((x) << 8) 1118#define _TXOP_LIMIT(x) ((x) << 16) 1119 1120#define _BCNIFS(x) ((x) & 0xFF) 1121#define _BCNECW(x) ((((x) & 0xF)) << 8) 1122 1123#define _LRL(x) ((x) & 0x3F) 1124#define _SRL(x) (((x) & 0x3F) << 8) 1125 1126#define _SIFS_CCK_CTX(x) ((x) & 0xFF) 1127#define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8) 1128 1129#define _SIFS_OFDM_CTX(x) ((x) & 0xFF) 1130#define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8) 1131 1132#define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8) 1133 1134#define DIS_EDCA_CNT_DWN BIT(11) 1135 1136#define EN_MBSSID BIT(1) 1137#define EN_TXBCN_RPT BIT(2) 1138#define EN_BCN_FUNCTION BIT(3) 1139 1140#define TSFTR_RST BIT(0) 1141#define TSFTR1_RST BIT(1) 1142 1143#define STOP_BCNQ BIT(6) 1144 1145#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) 1146#define DIS_TSF_UDT0_TEST_CHIP BIT(5) 1147 1148#define ACMHW_HWEN BIT(0) 1149#define ACMHW_BEQEN BIT(1) 1150#define ACMHW_VIQEN BIT(2) 1151#define ACMHW_VOQEN BIT(3) 1152#define ACMHW_BEQSTATUS BIT(4) 1153#define ACMHW_VIQSTATUS BIT(5) 1154#define ACMHW_VOQSTATUS BIT(6) 1155 1156#define APSDOFF BIT(6) 1157#define APSDOFF_STATUS BIT(7) 1158 1159#define BW_20MHZ BIT(2) 1160 1161#define RATE_BITMAP_ALL 0xFFFFF 1162 1163#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1 1164 1165#define TSFRST BIT(0) 1166#define DIS_GCLK BIT(1) 1167#define PAD_SEL BIT(2) 1168#define PWR_ST BIT(6) 1169#define PWRBIT_OW_EN BIT(7) 1170#define ACRC BIT(8) 1171#define CFENDFORM BIT(9) 1172#define ICV BIT(10) 1173 1174#define AAP BIT(0) 1175#define APM BIT(1) 1176#define AM BIT(2) 1177#define AB BIT(3) 1178#define ADD3 BIT(4) 1179#define APWRMGT BIT(5) 1180#define CBSSID BIT(6) 1181#define CBSSID_DATA BIT(6) 1182#define CBSSID_BCN BIT(7) 1183#define ACRC32 BIT(8) 1184#define AICV BIT(9) 1185#define ADF BIT(11) 1186#define ACF BIT(12) 1187#define AMF BIT(13) 1188#define HTC_LOC_CTRL BIT(14) 1189#define UC_DATA_EN BIT(16) 1190#define BM_DATA_EN BIT(17) 1191#define MFBEN BIT(22) 1192#define LSIGEN BIT(23) 1193#define ENMBID BIT(24) 1194#define APP_BASSN BIT(27) 1195#define APP_PHYSTS BIT(28) 1196#define APP_ICV BIT(29) 1197#define APP_MIC BIT(30) 1198#define APP_FCS BIT(31) 1199 1200#define _MIN_SPACE(x) ((x) & 0x7) 1201#define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3) 1202 1203#define RXERR_TYPE_OFDM_PPDU 0 1204#define RXERR_TYPE_OFDM_FALSE_ALARM 1 1205#define RXERR_TYPE_OFDM_MPDU_OK 2 1206#define RXERR_TYPE_OFDM_MPDU_FAIL 3 1207#define RXERR_TYPE_CCK_PPDU 4 1208#define RXERR_TYPE_CCK_FALSE_ALARM 5 1209#define RXERR_TYPE_CCK_MPDU_OK 6 1210#define RXERR_TYPE_CCK_MPDU_FAIL 7 1211#define RXERR_TYPE_HT_PPDU 8 1212#define RXERR_TYPE_HT_FALSE_ALARM 9 1213#define RXERR_TYPE_HT_MPDU_TOTAL 10 1214#define RXERR_TYPE_HT_MPDU_OK 11 1215#define RXERR_TYPE_HT_MPDU_FAIL 12 1216#define RXERR_TYPE_RX_FULL_DROP 15 1217 1218#define RXERR_COUNTER_MASK 0xFFFFF 1219#define RXERR_RPT_RST BIT(27) 1220#define _RXERR_RPT_SEL(type) ((type) << 28) 1221 1222#define SCR_TXUSEDK BIT(0) 1223#define SCR_RXUSEDK BIT(1) 1224#define SCR_TXENCENABLE BIT(2) 1225#define SCR_RXDECENABLE BIT(3) 1226#define SCR_SKBYA2 BIT(4) 1227#define SCR_NOSKMC BIT(5) 1228#define SCR_TXBCUSEDK BIT(6) 1229#define SCR_RXBCUSEDK BIT(7) 1230 1231#define XCLK_VLD BIT(0) 1232#define ACLK_VLD BIT(1) 1233#define UCLK_VLD BIT(2) 1234#define PCLK_VLD BIT(3) 1235#define PCIRSTB BIT(4) 1236#define V15_VLD BIT(5) 1237#define TRP_B15V_EN BIT(7) 1238#define SIC_IDLE BIT(8) 1239#define BD_MAC2 BIT(9) 1240#define BD_MAC1 BIT(10) 1241#define IC_MACPHY_MODE BIT(11) 1242#define BT_FUNC BIT(16) 1243#define VENDOR_ID BIT(19) 1244#define PAD_HWPD_IDN BIT(22) 1245#define TRP_VAUX_EN BIT(23) 1246#define TRP_BT_EN BIT(24) 1247#define BD_PKG_SEL BIT(25) 1248#define BD_HCI_SEL BIT(26) 1249#define TYPE_ID BIT(27) 1250 1251#define USB_IS_HIGH_SPEED 0 1252#define USB_IS_FULL_SPEED 1 1253#define USB_SPEED_MASK BIT(5) 1254 1255#define USB_NORMAL_SIE_EP_MASK 0xF 1256#define USB_NORMAL_SIE_EP_SHIFT 4 1257 1258#define USB_TEST_EP_MASK 0x30 1259#define USB_TEST_EP_SHIFT 4 1260 1261#define USB_AGG_EN BIT(3) 1262 1263#define MAC_ADDR_LEN 6 1264#define LAST_ENTRY_OF_TX_PKT_BUFFER 175/*255 88e*/ 1265 1266#define POLLING_LLT_THRESHOLD 20 1267#define POLLING_READY_TIMEOUT_COUNT 3000 1268 1269#define MAX_MSS_DENSITY_2T 0x13 1270#define MAX_MSS_DENSITY_1T 0x0A 1271 1272#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6)) 1273#define EPROM_CMD_CONFIG 0x3 1274#define EPROM_CMD_LOAD 1 1275 1276#define HWSET_MAX_SIZE_92S HWSET_MAX_SIZE 1277 1278#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2) 1279 1280#define RPMAC_RESET 0x100 1281#define RPMAC_TXSTART 0x104 1282#define RPMAC_TXLEGACYSIG 0x108 1283#define RPMAC_TXHTSIG1 0x10c 1284#define RPMAC_TXHTSIG2 0x110 1285#define RPMAC_PHYDEBUG 0x114 1286#define RPMAC_TXPACKETNUM 0x118 1287#define RPMAC_TXIDLE 0x11c 1288#define RPMAC_TXMACHEADER0 0x120 1289#define RPMAC_TXMACHEADER1 0x124 1290#define RPMAC_TXMACHEADER2 0x128 1291#define RPMAC_TXMACHEADER3 0x12c 1292#define RPMAC_TXMACHEADER4 0x130 1293#define RPMAC_TXMACHEADER5 0x134 1294#define RPMAC_TXDADATYPE 0x138 1295#define RPMAC_TXRANDOMSEED 0x13c 1296#define RPMAC_CCKPLCPPREAMBLE 0x140 1297#define RPMAC_CCKPLCPHEADER 0x144 1298#define RPMAC_CCKCRC16 0x148 1299#define RPMAC_OFDMRXCRC32OK 0x170 1300#define RPMAC_OFDMRXCRC32ER 0x174 1301#define RPMAC_OFDMRXPARITYER 0x178 1302#define RPMAC_OFDMRXCRC8ER 0x17c 1303#define RPMAC_CCKCRXRC16ER 0x180 1304#define RPMAC_CCKCRXRC32ER 0x184 1305#define RPMAC_CCKCRXRC32OK 0x188 1306#define RPMAC_TXSTATUS 0x18c 1307 1308#define RFPGA0_RFMOD 0x800 1309 1310#define RFPGA0_TXINFO 0x804 1311#define RFPGA0_PSDFUNCTION 0x808 1312 1313#define RFPGA0_TXGAINSTAGE 0x80c 1314 1315#define RFPGA0_RFTIMING1 0x810 1316#define RFPGA0_RFTIMING2 0x814 1317 1318#define RFPGA0_XA_HSSIPARAMETER1 0x820 1319#define RFPGA0_XA_HSSIPARAMETER2 0x824 1320#define RFPGA0_XB_HSSIPARAMETER1 0x828 1321#define RFPGA0_XB_HSSIPARAMETER2 0x82c 1322 1323#define RFPGA0_XA_LSSIPARAMETER 0x840 1324#define RFPGA0_XB_LSSIPARAMETER 0x844 1325 1326#define RFPGA0_RFWAKEUPPARAMETER 0x850 1327#define RFPGA0_RFSLEEPUPPARAMETER 0x854 1328 1329#define RFPGA0_XAB_SWITCHCONTROL 0x858 1330#define RFPGA0_XCD_SWITCHCONTROL 0x85c 1331 1332#define RFPGA0_XA_RFINTERFACEOE 0x860 1333#define RFPGA0_XB_RFINTERFACEOE 0x864 1334 1335#define RFPGA0_XAB_RFINTERFACESW 0x870 1336#define RFPGA0_XCD_RFINTERFACESW 0x874 1337 1338#define RFPGA0_XAB_RFPARAMETER 0x878 1339#define RFPGA0_XCD_RFPARAMETER 0x87c 1340 1341#define RFPGA0_ANALOGPARAMETER1 0x880 1342#define RFPGA0_ANALOGPARAMETER2 0x884 1343#define RFPGA0_ANALOGPARAMETER3 0x888 1344#define RFPGA0_ANALOGPARAMETER4 0x88c 1345 1346#define RFPGA0_XA_LSSIREADBACK 0x8a0 1347#define RFPGA0_XB_LSSIREADBACK 0x8a4 1348#define RFPGA0_XC_LSSIREADBACK 0x8a8 1349#define RFPGA0_XD_LSSIREADBACK 0x8ac 1350 1351#define RFPGA0_PSDREPORT 0x8b4 1352#define TRANSCEIVEA_HSPI_READBACK 0x8b8 1353#define TRANSCEIVEB_HSPI_READBACK 0x8bc 1354#define REG_SC_CNT 0x8c4 1355#define RFPGA0_XAB_RFINTERFACERB 0x8e0 1356#define RFPGA0_XCD_RFINTERFACERB 0x8e4 1357 1358#define RFPGA1_RFMOD 0x900 1359 1360#define RFPGA1_TXBLOCK 0x904 1361#define RFPGA1_DEBUGSELECT 0x908 1362#define RFPGA1_TXINFO 0x90c 1363 1364#define RCCK0_SYSTEM 0xa00 1365 1366#define RCCK0_AFESETTING 0xa04 1367#define RCCK0_CCA 0xa08 1368 1369#define RCCK0_RXAGC1 0xa0c 1370#define RCCK0_RXAGC2 0xa10 1371 1372#define RCCK0_RXHP 0xa14 1373 1374#define RCCK0_DSPPARAMETER1 0xa18 1375#define RCCK0_DSPPARAMETER2 0xa1c 1376 1377#define RCCK0_TXFILTER1 0xa20 1378#define RCCK0_TXFILTER2 0xa24 1379#define RCCK0_DEBUGPORT 0xa28 1380#define RCCK0_FALSEALARMREPORT 0xa2c 1381#define RCCK0_TRSSIREPORT 0xa50 1382#define RCCK0_RXREPORT 0xa54 1383#define RCCK0_FACOUNTERLOWER 0xa5c 1384#define RCCK0_FACOUNTERUPPER 0xa58 1385#define RCCK0_CCA_CNT 0xa60 1386 1387 1388/* PageB(0xB00) */ 1389#define RPDP_ANTA 0xb00 1390#define RPDP_ANTA_4 0xb04 1391#define RPDP_ANTA_8 0xb08 1392#define RPDP_ANTA_C 0xb0c 1393#define RPDP_ANTA_10 0xb10 1394#define RPDP_ANTA_14 0xb14 1395#define RPDP_ANTA_18 0xb18 1396#define RPDP_ANTA_1C 0xb1c 1397#define RPDP_ANTA_20 0xb20 1398#define RPDP_ANTA_24 0xb24 1399 1400#define RCONFIG_PMPD_ANTA 0xb28 1401#define CONFIG_RAM64X16 0xb2c 1402 1403#define RBNDA 0xb30 1404#define RHSSIPAR 0xb34 1405 1406#define RCONFIG_ANTA 0xb68 1407#define RCONFIG_ANTB 0xb6c 1408 1409#define RPDP_ANTB 0xb70 1410#define RPDP_ANTB_4 0xb74 1411#define RPDP_ANTB_8 0xb78 1412#define RPDP_ANTB_C 0xb7c 1413#define RPDP_ANTB_10 0xb80 1414#define RPDP_ANTB_14 0xb84 1415#define RPDP_ANTB_18 0xb88 1416#define RPDP_ANTB_1C 0xb8c 1417#define RPDP_ANTB_20 0xb90 1418#define RPDP_ANTB_24 0xb94 1419 1420#define RCONFIG_PMPD_ANTB 0xb98 1421 1422#define RBNDB 0xba0 1423 1424#define RAPK 0xbd8 1425#define RPM_RX0_ANTA 0xbdc 1426#define RPM_RX1_ANTA 0xbe0 1427#define RPM_RX2_ANTA 0xbe4 1428#define RPM_RX3_ANTA 0xbe8 1429#define RPM_RX0_ANTB 0xbec 1430#define RPM_RX1_ANTB 0xbf0 1431#define RPM_RX2_ANTB 0xbf4 1432#define RPM_RX3_ANTB 0xbf8 1433 1434/*Page C*/ 1435#define ROFDM0_LSTF 0xc00 1436 1437#define ROFDM0_TRXPATHENABLE 0xc04 1438#define ROFDM0_TRMUXPAR 0xc08 1439#define ROFDM0_TRSWISOLATION 0xc0c 1440 1441#define ROFDM0_XARXAFE 0xc10 1442#define ROFDM0_XARXIQIMBALANCE 0xc14 1443#define ROFDM0_XBRXAFE 0xc18 1444#define ROFDM0_XBRXIQIMBALANCE 0xc1c 1445#define ROFDM0_XCRXAFE 0xc20 1446#define ROFDM0_XCRXIQIMBANLANCE 0xc24 1447#define ROFDM0_XDRXAFE 0xc28 1448#define ROFDM0_XDRXIQIMBALANCE 0xc2c 1449 1450#define ROFDM0_RXDETECTOR1 0xc30 1451#define ROFDM0_RXDETECTOR2 0xc34 1452#define ROFDM0_RXDETECTOR3 0xc38 1453#define ROFDM0_RXDETECTOR4 0xc3c 1454 1455#define ROFDM0_RXDSP 0xc40 1456#define ROFDM0_CFOANDDAGC 0xc44 1457#define ROFDM0_CCADROPTHRESHOLD 0xc48 1458#define ROFDM0_ECCATHRESHOLD 0xc4c 1459 1460#define ROFDM0_XAAGCCORE1 0xc50 1461#define ROFDM0_XAAGCCORE2 0xc54 1462#define ROFDM0_XBAGCCORE1 0xc58 1463#define ROFDM0_XBAGCCORE2 0xc5c 1464#define ROFDM0_XCAGCCORE1 0xc60 1465#define ROFDM0_XCAGCCORE2 0xc64 1466#define ROFDM0_XDAGCCORE1 0xc68 1467#define ROFDM0_XDAGCCORE2 0xc6c 1468 1469#define ROFDM0_AGCPARAMETER1 0xc70 1470#define ROFDM0_AGCPARAMETER2 0xc74 1471#define ROFDM0_AGCRSSITABLE 0xc78 1472#define ROFDM0_HTSTFAGC 0xc7c 1473 1474#define ROFDM0_XATXIQIMBALANCE 0xc80 1475#define ROFDM0_XATXAFE 0xc84 1476#define ROFDM0_XBTXIQIMBALANCE 0xc88 1477#define ROFDM0_XBTXAFE 0xc8c 1478#define ROFDM0_XCTXIQIMBALANCE 0xc90 1479#define ROFDM0_XCTXAFE 0xc94 1480#define ROFDM0_XDTXIQIMBALANCE 0xc98 1481#define ROFDM0_XDTXAFE 0xc9c 1482 1483#define ROFDM0_RXIQEXTANTA 0xca0 1484#define ROFDM0_TXCOEFF1 0xca4 1485#define ROFDM0_TXCOEFF2 0xca8 1486#define ROFDM0_TXCOEFF3 0xcac 1487#define ROFDM0_TXCOEFF4 0xcb0 1488#define ROFDM0_TXCOEFF5 0xcb4 1489#define ROFDM0_TXCOEFF6 0xcb8 1490 1491#define ROFDM0_RXHPPARAMETER 0xce0 1492#define ROFDM0_TXPSEUDONOISEWGT 0xce4 1493#define ROFDM0_FRAMESYNC 0xcf0 1494#define ROFDM0_DFSREPORT 0xcf4 1495 1496 1497#define ROFDM1_LSTF 0xd00 1498#define ROFDM1_TRXPATHENABLE 0xd04 1499 1500#define ROFDM1_CF0 0xd08 1501#define ROFDM1_CSI1 0xd10 1502#define ROFDM1_SBD 0xd14 1503#define ROFDM1_CSI2 0xd18 1504#define ROFDM1_CFOTRACKING 0xd2c 1505#define ROFDM1_TRXMESAURE1 0xd34 1506#define ROFDM1_INTFDET 0xd3c 1507#define ROFDM1_PSEUDONOISESTATEAB 0xd50 1508#define ROFDM1_PSEUDONOISESTATECD 0xd54 1509#define ROFDM1_RXPSEUDONOISEWGT 0xd58 1510 1511#define ROFDM_PHYCOUNTER1 0xda0 1512#define ROFDM_PHYCOUNTER2 0xda4 1513#define ROFDM_PHYCOUNTER3 0xda8 1514 1515#define ROFDM_SHORTCFOAB 0xdac 1516#define ROFDM_SHORTCFOCD 0xdb0 1517#define ROFDM_LONGCFOAB 0xdb4 1518#define ROFDM_LONGCFOCD 0xdb8 1519#define ROFDM_TAILCF0AB 0xdbc 1520#define ROFDM_TAILCF0CD 0xdc0 1521#define ROFDM_PWMEASURE1 0xdc4 1522#define ROFDM_PWMEASURE2 0xdc8 1523#define ROFDM_BWREPORT 0xdcc 1524#define ROFDM_AGCREPORT 0xdd0 1525#define ROFDM_RXSNR 0xdd4 1526#define ROFDM_RXEVMCSI 0xdd8 1527#define ROFDM_SIGREPORT 0xddc 1528 1529#define RTXAGC_A_RATE18_06 0xe00 1530#define RTXAGC_A_RATE54_24 0xe04 1531#define RTXAGC_A_CCK1_MCS32 0xe08 1532#define RTXAGC_A_MCS03_MCS00 0xe10 1533#define RTXAGC_A_MCS07_MCS04 0xe14 1534#define RTXAGC_A_MCS11_MCS08 0xe18 1535#define RTXAGC_A_MCS15_MCS12 0xe1c 1536 1537#define RTXAGC_B_RATE18_06 0x830 1538#define RTXAGC_B_RATE54_24 0x834 1539#define RTXAGC_B_CCK1_55_MCS32 0x838 1540#define RTXAGC_B_MCS03_MCS00 0x83c 1541#define RTXAGC_B_MCS07_MCS04 0x848 1542#define RTXAGC_B_MCS11_MCS08 0x84c 1543#define RTXAGC_B_MCS15_MCS12 0x868 1544#define RTXAGC_B_CCK11_A_CCK2_11 0x86c 1545 1546#define RFPGA0_IQK 0xe28 1547#define RTX_IQK_TONE_A 0xe30 1548#define RRX_IQK_TONE_A 0xe34 1549#define RTX_IQK_PI_A 0xe38 1550#define RRX_IQK_PI_A 0xe3c 1551 1552#define RTX_IQK 0xe40 1553#define RRX_IQK 0xe44 1554#define RIQK_AGC_PTS 0xe48 1555#define RIQK_AGC_RSP 0xe4c 1556#define RTX_IQK_TONE_B 0xe50 1557#define RRX_IQK_TONE_B 0xe54 1558#define RTX_IQK_PI_B 0xe58 1559#define RRX_IQK_PI_B 0xe5c 1560#define RIQK_AGC_CONT 0xe60 1561 1562#define RBLUE_TOOTH 0xe6c 1563#define RRX_WAIT_CCA 0xe70 1564#define RTX_CCK_RFON 0xe74 1565#define RTX_CCK_BBON 0xe78 1566#define RTX_OFDM_RFON 0xe7c 1567#define RTX_OFDM_BBON 0xe80 1568#define RTX_TO_RX 0xe84 1569#define RTX_TO_TX 0xe88 1570#define RRX_CCK 0xe8c 1571 1572#define RTX_POWER_BEFORE_IQK_A 0xe94 1573#define RTX_POWER_AFTER_IQK_A 0xe9c 1574 1575#define RRX_POWER_BEFORE_IQK_A 0xea0 1576#define RRX_POWER_BEFORE_IQK_A_2 0xea4 1577#define RRX_POWER_AFTER_IQK_A 0xea8 1578#define RRX_POWER_AFTER_IQK_A_2 0xeac 1579 1580#define RTX_POWER_BEFORE_IQK_B 0xeb4 1581#define RTX_POWER_AFTER_IQK_B 0xebc 1582 1583#define RRX_POWER_BEFORE_IQK_B 0xec0 1584#define RRX_POWER_BEFORE_IQK_B_2 0xec4 1585#define RRX_POWER_AFTER_IQK_B 0xec8 1586#define RRX_POWER_AFTER_IQK_B_2 0xecc 1587 1588#define RRX_OFDM 0xed0 1589#define RRX_WAIT_RIFS 0xed4 1590#define RRX_TO_RX 0xed8 1591#define RSTANDBY 0xedc 1592#define RSLEEP 0xee0 1593#define RPMPD_ANAEN 0xeec 1594 1595#define RZEBRA1_HSSIENABLE 0x0 1596#define RZEBRA1_TRXENABLE1 0x1 1597#define RZEBRA1_TRXENABLE2 0x2 1598#define RZEBRA1_AGC 0x4 1599#define RZEBRA1_CHARGEPUMP 0x5 1600#define RZEBRA1_CHANNEL 0x7 1601 1602#define RZEBRA1_TXGAIN 0x8 1603#define RZEBRA1_TXLPF 0x9 1604#define RZEBRA1_RXLPF 0xb 1605#define RZEBRA1_RXHPFCORNER 0xc 1606 1607#define RGLOBALCTRL 0 1608#define RRTL8256_TXLPF 19 1609#define RRTL8256_RXLPF 11 1610#define RRTL8258_TXLPF 0x11 1611#define RRTL8258_RXLPF 0x13 1612#define RRTL8258_RSSILPF 0xa 1613 1614#define RF_AC 0x00 1615 1616#define RF_IQADJ_G1 0x01 1617#define RF_IQADJ_G2 0x02 1618#define RF_POW_TRSW 0x05 1619 1620#define RF_GAIN_RX 0x06 1621#define RF_GAIN_TX 0x07 1622 1623#define RF_TXM_IDAC 0x08 1624#define RF_BS_IQGEN 0x0F 1625 1626#define RF_MODE1 0x10 1627#define RF_MODE2 0x11 1628 1629#define RF_RX_AGC_HP 0x12 1630#define RF_TX_AGC 0x13 1631#define RF_BIAS 0x14 1632#define RF_IPA 0x15 1633#define RF_POW_ABILITY 0x17 1634#define RF_MODE_AG 0x18 1635#define RRFCHANNEL 0x18 1636#define RF_CHNLBW 0x18 1637#define RF_TOP 0x19 1638 1639#define RF_RX_G1 0x1A 1640#define RF_RX_G2 0x1B 1641 1642#define RF_RX_BB2 0x1C 1643#define RF_RX_BB1 0x1D 1644 1645#define RF_RCK1 0x1E 1646#define RF_RCK2 0x1F 1647 1648#define RF_TX_G1 0x20 1649#define RF_TX_G2 0x21 1650#define RF_TX_G3 0x22 1651 1652#define RF_TX_BB1 0x23 1653#define RF_T_METER 0x42 1654 1655#define RF_SYN_G1 0x25 1656#define RF_SYN_G2 0x26 1657#define RF_SYN_G3 0x27 1658#define RF_SYN_G4 0x28 1659#define RF_SYN_G5 0x29 1660#define RF_SYN_G6 0x2A 1661#define RF_SYN_G7 0x2B 1662#define RF_SYN_G8 0x2C 1663 1664#define RF_RCK_OS 0x30 1665#define RF_TXPA_G1 0x31 1666#define RF_TXPA_G2 0x32 1667#define RF_TXPA_G3 0x33 1668 1669#define RF_TX_BIAS_A 0x35 1670#define RF_TX_BIAS_D 0x36 1671#define RF_LOBF_9 0x38 1672#define RF_RXRF_A3 0x3C 1673#define RF_TRSW 0x3F 1674 1675#define RF_TXRF_A2 0x41 1676#define RF_TXPA_G4 0x46 1677#define RF_TXPA_A4 0x4B 1678 1679#define RF_WE_LUT 0xEF 1680 1681#define BBBRESETB 0x100 1682#define BGLOBALRESETB 0x200 1683#define BOFDMTXSTART 0x4 1684#define BCCKTXSTART 0x8 1685#define BCRC32DEBUG 0x100 1686#define BPMACLOOPBACK 0x10 1687#define BTXLSIG 0xffffff 1688#define BOFDMTXRATE 0xf 1689#define BOFDMTXRESERVED 0x10 1690#define BOFDMTXLENGTH 0x1ffe0 1691#define BOFDMTXPARITY 0x20000 1692#define BTXHTSIG1 0xffffff 1693#define BTXHTMCSRATE 0x7f 1694#define BTXHTBW 0x80 1695#define BTXHTLENGTH 0xffff00 1696#define BTXHTSIG2 0xffffff 1697#define BTXHTSMOOTHING 0x1 1698#define BTXHTSOUNDING 0x2 1699#define BTXHTRESERVED 0x4 1700#define BTXHTAGGREATION 0x8 1701#define BTXHTSTBC 0x30 1702#define BTXHTADVANCECODING 0x40 1703#define BTXHTSHORTGI 0x80 1704#define BTXHTNUMBERHT_LTF 0x300 1705#define BTXHTCRC8 0x3fc00 1706#define BCOUNTERRESET 0x10000 1707#define BNUMOFOFDMTX 0xffff 1708#define BNUMOFCCKTX 0xffff0000 1709#define BTXIDLEINTERVAL 0xffff 1710#define BOFDMSERVICE 0xffff0000 1711#define BTXMACHEADER 0xffffffff 1712#define BTXDATAINIT 0xff 1713#define BTXHTMODE 0x100 1714#define BTXDATATYPE 0x30000 1715#define BTXRANDOMSEED 0xffffffff 1716#define BCCKTXPREAMBLE 0x1 1717#define BCCKTXSFD 0xffff0000 1718#define BCCKTXSIG 0xff 1719#define BCCKTXSERVICE 0xff00 1720#define BCCKLENGTHEXT 0x8000 1721#define BCCKTXLENGHT 0xffff0000 1722#define BCCKTXCRC16 0xffff 1723#define BCCKTXSTATUS 0x1 1724#define BOFDMTXSTATUS 0x2 1725#define IS_BB_REG_OFFSET_92S(_offset) \ 1726 ((_offset >= 0x800) && (_offset <= 0xfff)) 1727 1728#define BRFMOD 0x1 1729#define BJAPANMODE 0x2 1730#define BCCKTXSC 0x30 1731#define BCCKEN 0x1000000 1732#define BOFDMEN 0x2000000 1733 1734#define BOFDMRXADCPHASE 0x10000 1735#define BOFDMTXDACPHASE 0x40000 1736#define BXATXAGC 0x3f 1737 1738#define BXBTXAGC 0xf00 1739#define BXCTXAGC 0xf000 1740#define BXDTXAGC 0xf0000 1741 1742#define BPASTART 0xf0000000 1743#define BTRSTART 0x00f00000 1744#define BRFSTART 0x0000f000 1745#define BBBSTART 0x000000f0 1746#define BBBCCKSTART 0x0000000f 1747#define BPAEND 0xf 1748#define BTREND 0x0f000000 1749#define BRFEND 0x000f0000 1750#define BCCAMASK 0x000000f0 1751#define BR2RCCAMASK 0x00000f00 1752#define BHSSI_R2TDELAY 0xf8000000 1753#define BHSSI_T2RDELAY 0xf80000 1754#define BCONTXHSSI 0x400 1755#define BIGFROMCCK 0x200 1756#define BAGCADDRESS 0x3f 1757#define BRXHPTX 0x7000 1758#define BRXHP2RX 0x38000 1759#define BRXHPCCKINI 0xc0000 1760#define BAGCTXCODE 0xc00000 1761#define BAGCRXCODE 0x300000 1762 1763#define B3WIREDATALENGTH 0x800 1764#define B3WIREADDREAALENGTH 0x400 1765 1766#define B3WIRERFPOWERDOWN 0x1 1767#define B5GPAPEPOLARITY 0x40000000 1768#define B2GPAPEPOLARITY 0x80000000 1769#define BRFSW_TXDEFAULTANT 0x3 1770#define BRFSW_TXOPTIONANT 0x30 1771#define BRFSW_RXDEFAULTANT 0x300 1772#define BRFSW_RXOPTIONANT 0x3000 1773#define BRFSI_3WIREDATA 0x1 1774#define BRFSI_3WIRECLOCK 0x2 1775#define BRFSI_3WIRELOAD 0x4 1776#define BRFSI_3WIRERW 0x8 1777#define BRFSI_3WIRE 0xf 1778 1779#define BRFSI_RFENV 0x10 1780 1781#define BRFSI_TRSW 0x20 1782#define BRFSI_TRSWB 0x40 1783#define BRFSI_ANTSW 0x100 1784#define BRFSI_ANTSWB 0x200 1785#define BRFSI_PAPE 0x400 1786#define BRFSI_PAPE5G 0x800 1787#define BBANDSELECT 0x1 1788#define BHTSIG2_GI 0x80 1789#define BHTSIG2_SMOOTHING 0x01 1790#define BHTSIG2_SOUNDING 0x02 1791#define BHTSIG2_AGGREATON 0x08 1792#define BHTSIG2_STBC 0x30 1793#define BHTSIG2_ADVCODING 0x40 1794#define BHTSIG2_NUMOFHTLTF 0x300 1795#define BHTSIG2_CRC8 0x3fc 1796#define BHTSIG1_MCS 0x7f 1797#define BHTSIG1_BANDWIDTH 0x80 1798#define BHTSIG1_HTLENGTH 0xffff 1799#define BLSIG_RATE 0xf 1800#define BLSIG_RESERVED 0x10 1801#define BLSIG_LENGTH 0x1fffe 1802#define BLSIG_PARITY 0x20 1803#define BCCKRXPHASE 0x4 1804 1805#define BLSSIREADADDRESS 0x7f800000 1806#define BLSSIREADEDGE 0x80000000 1807 1808#define BLSSIREADBACKDATA 0xfffff 1809 1810#define BLSSIREADOKFLAG 0x1000 1811#define BCCKSAMPLERATE 0x8 1812#define BREGULATOR0STANDBY 0x1 1813#define BREGULATORPLLSTANDBY 0x2 1814#define BREGULATOR1STANDBY 0x4 1815#define BPLLPOWERUP 0x8 1816#define BDPLLPOWERUP 0x10 1817#define BDA10POWERUP 0x20 1818#define BAD7POWERUP 0x200 1819#define BDA6POWERUP 0x2000 1820#define BXTALPOWERUP 0x4000 1821#define B40MDCLKPOWERUP 0x8000 1822#define BDA6DEBUGMODE 0x20000 1823#define BDA6SWING 0x380000 1824 1825#define BADCLKPHASE 0x4000000 1826#define B80MCLKDELAY 0x18000000 1827#define BAFEWATCHDOGENABLE 0x20000000 1828 1829#define BXTALCAP01 0xc0000000 1830#define BXTALCAP23 0x3 1831#define BXTALCAP92X 0x0f000000 1832#define BXTALCAP 0x0f000000 1833 1834#define BINTDIFCLKENABLE 0x400 1835#define BEXTSIGCLKENABLE 0x800 1836#define BBANDGAP_MBIAS_POWERUP 0x10000 1837#define BAD11SH_GAIN 0xc0000 1838#define BAD11NPUT_RANGE 0x700000 1839#define BAD110P_CURRENT 0x3800000 1840#define BLPATH_LOOPBACK 0x4000000 1841#define BQPATH_LOOPBACK 0x8000000 1842#define BAFE_LOOPBACK 0x10000000 1843#define BDA10_SWING 0x7e0 1844#define BDA10_REVERSE 0x800 1845#define BDA_CLK_SOURCE 0x1000 1846#define BDA7INPUT_RANGE 0x6000 1847#define BDA7_GAIN 0x38000 1848#define BDA7OUTPUT_CM_MODE 0x40000 1849#define BDA7INPUT_CM_MODE 0x380000 1850#define BDA7CURRENT 0xc00000 1851#define BREGULATOR_ADJUST 0x7000000 1852#define BAD11POWERUP_ATTX 0x1 1853#define BDA10PS_ATTX 0x10 1854#define BAD11POWERUP_ATRX 0x100 1855#define BDA10PS_ATRX 0x1000 1856#define BCCKRX_AGC_FORMAT 0x200 1857#define BPSDFFT_SAMPLE_POINT 0xc000 1858#define BPSD_AVERAGE_NUM 0x3000 1859#define BIQPATH_CONTROL 0xc00 1860#define BPSD_FREQ 0x3ff 1861#define BPSD_ANTENNA_PATH 0x30 1862#define BPSD_IQ_SWITCH 0x40 1863#define BPSD_RX_TRIGGER 0x400000 1864#define BPSD_TX_TRIGGER 0x80000000 1865#define BPSD_SINE_TONE_SCALE 0x7f000000 1866#define BPSD_REPORT 0xffff 1867 1868#define BOFDM_TXSC 0x30000000 1869#define BCCK_TXON 0x1 1870#define BOFDM_TXON 0x2 1871#define BDEBUG_PAGE 0xfff 1872#define BDEBUG_ITEM 0xff 1873#define BANTL 0x10 1874#define BANT_NONHT 0x100 1875#define BANT_HT1 0x1000 1876#define BANT_HT2 0x10000 1877#define BANT_HT1S1 0x100000 1878#define BANT_NONHTS1 0x1000000 1879 1880#define BCCK_BBMODE 0x3 1881#define BCCK_TXPOWERSAVING 0x80 1882#define BCCK_RXPOWERSAVING 0x40 1883 1884#define BCCK_SIDEBAND 0x10 1885 1886#define BCCK_SCRAMBLE 0x8 1887#define BCCK_ANTDIVERSITY 0x8000 1888#define BCCK_CARRIER_RECOVERY 0x4000 1889#define BCCK_TXRATE 0x3000 1890#define BCCK_DCCANCEL 0x0800 1891#define BCCK_ISICANCEL 0x0400 1892#define BCCK_MATCH_FILTER 0x0200 1893#define BCCK_EQUALIZER 0x0100 1894#define BCCK_PREAMBLE_DETECT 0x800000 1895#define BCCK_FAST_FALSECCA 0x400000 1896#define BCCK_CH_ESTSTART 0x300000 1897#define BCCK_CCA_COUNT 0x080000 1898#define BCCK_CS_LIM 0x070000 1899#define BCCK_BIST_MODE 0x80000000 1900#define BCCK_CCAMASK 0x40000000 1901#define BCCK_TX_DAC_PHASE 0x4 1902#define BCCK_RX_ADC_PHASE 0x20000000 1903#define BCCKR_CP_MODE 0x0100 1904#define BCCK_TXDC_OFFSET 0xf0 1905#define BCCK_RXDC_OFFSET 0xf 1906#define BCCK_CCA_MODE 0xc000 1907#define BCCK_FALSECS_LIM 0x3f00 1908#define BCCK_CS_RATIO 0xc00000 1909#define BCCK_CORGBIT_SEL 0x300000 1910#define BCCK_PD_LIM 0x0f0000 1911#define BCCK_NEWCCA 0x80000000 1912#define BCCK_RXHP_OF_IG 0x8000 1913#define BCCK_RXIG 0x7f00 1914#define BCCK_LNA_POLARITY 0x800000 1915#define BCCK_RX1ST_BAIN 0x7f0000 1916#define BCCK_RF_EXTEND 0x20000000 1917#define BCCK_RXAGC_SATLEVEL 0x1f000000 1918#define BCCK_RXAGC_SATCOUNT 0xe0 1919#define BCCKRXRFSETTLE 0x1f 1920#define BCCK_FIXED_RXAGC 0x8000 1921#define BCCK_ANTENNA_POLARITY 0x2000 1922#define BCCK_TXFILTER_TYPE 0x0c00 1923#define BCCK_RXAGC_REPORTTYPE 0x0300 1924#define BCCK_RXDAGC_EN 0x80000000 1925#define BCCK_RXDAGC_PERIOD 0x20000000 1926#define BCCK_RXDAGC_SATLEVEL 0x1f000000 1927#define BCCK_TIMING_RECOVERY 0x800000 1928#define BCCK_TXC0 0x3f0000 1929#define BCCK_TXC1 0x3f000000 1930#define BCCK_TXC2 0x3f 1931#define BCCK_TXC3 0x3f00 1932#define BCCK_TXC4 0x3f0000 1933#define BCCK_TXC5 0x3f000000 1934#define BCCK_TXC6 0x3f 1935#define BCCK_TXC7 0x3f00 1936#define BCCK_DEBUGPORT 0xff0000 1937#define BCCK_DAC_DEBUG 0x0f000000 1938#define BCCK_FALSEALARM_ENABLE 0x8000 1939#define BCCK_FALSEALARM_READ 0x4000 1940#define BCCK_TRSSI 0x7f 1941#define BCCK_RXAGC_REPORT 0xfe 1942#define BCCK_RXREPORT_ANTSEL 0x80000000 1943#define BCCK_RXREPORT_MFOFF 0x40000000 1944#define BCCK_RXREPORT_SQLOSS 0x20000000 1945#define BCCK_RXREPORT_PKTLOSS 0x10000000 1946#define BCCK_RXREPORT_LOCKEDBIT 0x08000000 1947#define BCCK_RXREPORT_RATEERROR 0x04000000 1948#define BCCK_RXREPORT_RXRATE 0x03000000 1949#define BCCK_RXFA_COUNTER_LOWER 0xff 1950#define BCCK_RXFA_COUNTER_UPPER 0xff000000 1951#define BCCK_RXHPAGC_START 0xe000 1952#define BCCK_RXHPAGC_FINAL 0x1c00 1953#define BCCK_RXFALSEALARM_ENABLE 0x8000 1954#define BCCK_FACOUNTER_FREEZE 0x4000 1955#define BCCK_TXPATH_SEL 0x10000000 1956#define BCCK_DEFAULT_RXPATH 0xc000000 1957#define BCCK_OPTION_RXPATH 0x3000000 1958 1959#define BNUM_OFSTF 0x3 1960#define BSHIFT_L 0xc0 1961#define BGI_TH 0xc 1962#define BRXPATH_A 0x1 1963#define BRXPATH_B 0x2 1964#define BRXPATH_C 0x4 1965#define BRXPATH_D 0x8 1966#define BTXPATH_A 0x1 1967#define BTXPATH_B 0x2 1968#define BTXPATH_C 0x4 1969#define BTXPATH_D 0x8 1970#define BTRSSI_FREQ 0x200 1971#define BADC_BACKOFF 0x3000 1972#define BDFIR_BACKOFF 0xc000 1973#define BTRSSI_LATCH_PHASE 0x10000 1974#define BRX_LDC_OFFSET 0xff 1975#define BRX_QDC_OFFSET 0xff00 1976#define BRX_DFIR_MODE 0x1800000 1977#define BRX_DCNF_TYPE 0xe000000 1978#define BRXIQIMB_A 0x3ff 1979#define BRXIQIMB_B 0xfc00 1980#define BRXIQIMB_C 0x3f0000 1981#define BRXIQIMB_D 0xffc00000 1982#define BDC_DC_NOTCH 0x60000 1983#define BRXNB_NOTCH 0x1f000000 1984#define BPD_TH 0xf 1985#define BPD_TH_OPT2 0xc000 1986#define BPWED_TH 0x700 1987#define BIFMF_WIN_L 0x800 1988#define BPD_OPTION 0x1000 1989#define BMF_WIN_L 0xe000 1990#define BBW_SEARCH_L 0x30000 1991#define BWIN_ENH_L 0xc0000 1992#define BBW_TH 0x700000 1993#define BED_TH2 0x3800000 1994#define BBW_OPTION 0x4000000 1995#define BRADIO_TH 0x18000000 1996#define BWINDOW_L 0xe0000000 1997#define BSBD_OPTION 0x1 1998#define BFRAME_TH 0x1c 1999#define BFS_OPTION 0x60 2000#define BDC_SLOPE_CHECK 0x80
2001#define BFGUARD_COUNTER_DC_L 0xe00 2002#define BFRAME_WEIGHT_SHORT 0x7000 2003#define BSUB_TUNE 0xe00000 2004#define BFRAME_DC_LENGTH 0xe000000 2005#define BSBD_START_OFFSET 0x30000000 2006#define BFRAME_TH_2 0x7 2007#define BFRAME_GI2_TH 0x38 2008#define BGI2_SYNC_EN 0x40 2009#define BSARCH_SHORT_EARLY 0x300 2010#define BSARCH_SHORT_LATE 0xc00 2011#define BSARCH_GI2_LATE 0x70000 2012#define BCFOANTSUM 0x1 2013#define BCFOACC 0x2 2014#define BCFOSTARTOFFSET 0xc 2015#define BCFOLOOPBACK 0x70 2016#define BCFOSUMWEIGHT 0x80 2017#define BDAGCENABLE 0x10000 2018#define BTXIQIMB_A 0x3ff 2019#define BTXIQIMB_b 0xfc00 2020#define BTXIQIMB_C 0x3f0000 2021#define BTXIQIMB_D 0xffc00000 2022#define BTXIDCOFFSET 0xff 2023#define BTXIQDCOFFSET 0xff00 2024#define BTXDFIRMODE 0x10000 2025#define BTXPESUDO_NOISEON 0x4000000 2026#define BTXPESUDO_NOISE_A 0xff 2027#define BTXPESUDO_NOISE_B 0xff00 2028#define BTXPESUDO_NOISE_C 0xff0000 2029#define BTXPESUDO_NOISE_D 0xff000000 2030#define BCCA_DROPOPTION 0x20000 2031#define BCCA_DROPTHRES 0xfff00000 2032#define BEDCCA_H 0xf 2033#define BEDCCA_L 0xf0 2034#define BLAMBDA_ED 0x300 2035#define BRX_INITIALGAIN 0x7f 2036#define BRX_ANTDIV_EN 0x80 2037#define BRX_AGC_ADDRESS_FOR_LNA 0x7f00 2038#define BRX_HIGHPOWER_FLOW 0x8000 2039#define BRX_AGC_FREEZE_THRES 0xc0000 2040#define BRX_FREEZESTEP_AGC1 0x300000 2041#define BRX_FREEZESTEP_AGC2 0xc00000 2042#define BRX_FREEZESTEP_AGC3 0x3000000 2043#define BRX_FREEZESTEP_AGC0 0xc000000 2044#define BRXRSSI_CMP_EN 0x10000000 2045#define BRXQUICK_AGCEN 0x20000000 2046#define BRXAGC_FREEZE_THRES_MODE 0x40000000 2047#define BRX_OVERFLOW_CHECKTYPE 0x80000000 2048#define BRX_AGCSHIFT 0x7f 2049#define BTRSW_TRI_ONLY 0x80 2050#define BPOWER_THRES 0x300 2051#define BRXAGC_EN 0x1 2052#define BRXAGC_TOGETHER_EN 0x2 2053#define BRXAGC_MIN 0x4 2054#define BRXHP_INI 0x7 2055#define BRXHP_TRLNA 0x70 2056#define BRXHP_RSSI 0x700 2057#define BRXHP_BBP1 0x7000 2058#define BRXHP_BBP2 0x70000 2059#define BRXHP_BBP3 0x700000 2060#define BRSSI_H 0x7f0000 2061#define BRSSI_GEN 0x7f000000 2062#define BRXSETTLE_TRSW 0x7 2063#define BRXSETTLE_LNA 0x38 2064#define BRXSETTLE_RSSI 0x1c0 2065#define BRXSETTLE_BBP 0xe00 2066#define BRXSETTLE_RXHP 0x7000 2067#define BRXSETTLE_ANTSW_RSSI 0x38000 2068#define BRXSETTLE_ANTSW 0xc0000 2069#define BRXPROCESS_TIME_DAGC 0x300000 2070#define BRXSETTLE_HSSI 0x400000 2071#define BRXPROCESS_TIME_BBPPW 0x800000 2072#define BRXANTENNA_POWER_SHIFT 0x3000000 2073#define BRSSI_TABLE_SELECT 0xc000000 2074#define BRXHP_FINAL 0x7000000 2075#define BRXHPSETTLE_BBP 0x7 2076#define BRXHTSETTLE_HSSI 0x8 2077#define BRXHTSETTLE_RXHP 0x70 2078#define BRXHTSETTLE_BBPPW 0x80 2079#define BRXHTSETTLE_IDLE 0x300 2080#define BRXHTSETTLE_RESERVED 0x1c00 2081#define BRXHT_RXHP_EN 0x8000 2082#define BRXAGC_FREEZE_THRES 0x30000 2083#define BRXAGC_TOGETHEREN 0x40000 2084#define BRXHTAGC_MIN 0x80000 2085#define BRXHTAGC_EN 0x100000 2086#define BRXHTDAGC_EN 0x200000 2087#define BRXHT_RXHP_BBP 0x1c00000 2088#define BRXHT_RXHP_FINAL 0xe0000000 2089#define BRXPW_RADIO_TH 0x3 2090#define BRXPW_RADIO_EN 0x4 2091#define BRXMF_HOLD 0x3800 2092#define BRXPD_DELAY_TH1 0x38 2093#define BRXPD_DELAY_TH2 0x1c0 2094#define BRXPD_DC_COUNT_MAX 0x600 2095#define BRXPD_DELAY_TH 0x8000 2096#define BRXPROCESS_DELAY 0xf0000 2097#define BRXSEARCHRANGE_GI2_EARLY 0x700000 2098#define BRXFRAME_FUARD_COUNTER_L 0x3800000 2099#define BRXSGI_GUARD_L 0xc000000 2100#define BRXSGI_SEARCH_L 0x30000000 2101#define BRXSGI_TH 0xc0000000 2102#define BDFSCNT0 0xff 2103#define BDFSCNT1 0xff00 2104#define BDFSFLAG 0xf0000 2105#define BMF_WEIGHT_SUM 0x300000 2106#define BMINIDX_TH 0x7f000000 2107#define BDAFORMAT 0x40000 2108#define BTXCH_EMU_ENABLE 0x01000000 2109#define BTRSW_ISOLATION_A 0x7f 2110#define BTRSW_ISOLATION_B 0x7f00 2111#define BTRSW_ISOLATION_C 0x7f0000 2112#define BTRSW_ISOLATION_D 0x7f000000 2113#define BEXT_LNA_GAIN 0x7c00 2114 2115#define BSTBC_EN 0x4 2116#define BANTENNA_MAPPING 0x10 2117#define BNSS 0x20 2118#define BCFO_ANTSUM_ID 0x200 2119#define BPHY_COUNTER_RESET 0x8000000 2120#define BCFO_REPORT_GET 0x4000000 2121#define BOFDM_CONTINUE_TX 0x10000000 2122#define BOFDM_SINGLE_CARRIER 0x20000000 2123#define BOFDM_SINGLE_TONE 0x40000000 2124#define BHT_DETECT 0x100 2125#define BCFOEN 0x10000 2126#define BCFOVALUE 0xfff00000 2127#define BSIGTONE_RE 0x3f 2128#define BSIGTONE_IM 0x7f00 2129#define BCOUNTER_CCA 0xffff 2130#define BCOUNTER_PARITYFAIL 0xffff0000 2131#define BCOUNTER_RATEILLEGAL 0xffff 2132#define BCOUNTER_CRC8FAIL 0xffff0000 2133#define BCOUNTER_MCSNOSUPPORT 0xffff 2134#define BCOUNTER_FASTSYNC 0xffff 2135#define BSHORTCFO 0xfff 2136#define BSHORTCFOT_LENGTH 12 2137#define BSHORTCFOF_LENGTH 11 2138#define BLONGCFO 0x7ff 2139#define BLONGCFOT_LENGTH 11 2140#define BLONGCFOF_LENGTH 11 2141#define BTAILCFO 0x1fff 2142#define BTAILCFOT_LENGTH 13 2143#define BTAILCFOF_LENGTH 12 2144#define BNOISE_EN_PWDB 0xffff 2145#define BCC_POWER_DB 0xffff0000 2146#define BMOISE_PWDB 0xffff 2147#define BPOWERMEAST_LENGTH 10 2148#define BPOWERMEASF_LENGTH 3 2149#define BRX_HT_BW 0x1 2150#define BRXSC 0x6 2151#define BRX_HT 0x8 2152#define BNB_INTF_DET_ON 0x1 2153#define BINTF_WIN_LEN_CFG 0x30 2154#define BNB_INTF_TH_CFG 0x1c0 2155#define BRFGAIN 0x3f 2156#define BTABLESEL 0x40 2157#define BTRSW 0x80 2158#define BRXSNR_A 0xff 2159#define BRXSNR_B 0xff00 2160#define BRXSNR_C 0xff0000 2161#define BRXSNR_D 0xff000000 2162#define BSNR_EVMT_LENGTH 8 2163#define BSNR_EVMF_LENGTH 1 2164#define BCSI1ST 0xff 2165#define BCSI2ND 0xff00 2166#define BRXEVM1ST 0xff0000 2167#define BRXEVM2ND 0xff000000 2168#define BSIGEVM 0xff 2169#define BPWDB 0xff00 2170#define BSGIEN 0x10000 2171 2172#define BSFACTOR_QMA1 0xf 2173#define BSFACTOR_QMA2 0xf0 2174#define BSFACTOR_QMA3 0xf00 2175#define BSFACTOR_QMA4 0xf000 2176#define BSFACTOR_QMA5 0xf0000 2177#define BSFACTOR_QMA6 0xf0000 2178#define BSFACTOR_QMA7 0xf00000 2179#define BSFACTOR_QMA8 0xf000000 2180#define BSFACTOR_QMA9 0xf0000000 2181#define BCSI_SCHEME 0x100000 2182 2183#define BNOISE_LVL_TOP_SET 0x3 2184#define BCHSMOOTH 0x4 2185#define BCHSMOOTH_CFG1 0x38 2186#define BCHSMOOTH_CFG2 0x1c0 2187#define BCHSMOOTH_CFG3 0xe00 2188#define BCHSMOOTH_CFG4 0x7000 2189#define BMRCMODE 0x800000 2190#define BTHEVMCFG 0x7000000 2191 2192#define BLOOP_FIT_TYPE 0x1 2193#define BUPD_CFO 0x40 2194#define BUPD_CFO_OFFDATA 0x80 2195#define BADV_UPD_CFO 0x100 2196#define BADV_TIME_CTRL 0x800 2197#define BUPD_CLKO 0x1000 2198#define BFC 0x6000 2199#define BTRACKING_MODE 0x8000 2200#define BPHCMP_ENABLE 0x10000 2201#define BUPD_CLKO_LTF 0x20000 2202#define BCOM_CH_CFO 0x40000 2203#define BCSI_ESTI_MODE 0x80000 2204#define BADV_UPD_EQZ 0x100000 2205#define BUCHCFG 0x7000000 2206#define BUPDEQZ 0x8000000 2207 2208#define BRX_PESUDO_NOISE_ON 0x20000000 2209#define BRX_PESUDO_NOISE_A 0xff 2210#define BRX_PESUDO_NOISE_B 0xff00 2211#define BRX_PESUDO_NOISE_C 0xff0000 2212#define BRX_PESUDO_NOISE_D 0xff000000 2213#define BRX_PESUDO_NOISESTATE_A 0xffff 2214#define BRX_PESUDO_NOISESTATE_B 0xffff0000 2215#define BRX_PESUDO_NOISESTATE_C 0xffff 2216#define BRX_PESUDO_NOISESTATE_D 0xffff0000 2217 2218#define BZEBRA1_HSSIENABLE 0x8 2219#define BZEBRA1_TRXCONTROL 0xc00 2220#define BZEBRA1_TRXGAINSETTING 0x07f 2221#define BZEBRA1_RXCOUNTER 0xc00 2222#define BZEBRA1_TXCHANGEPUMP 0x38 2223#define BZEBRA1_RXCHANGEPUMP 0x7 2224#define BZEBRA1_CHANNEL_NUM 0xf80 2225#define BZEBRA1_TXLPFBW 0x400 2226#define BZEBRA1_RXLPFBW 0x600 2227 2228#define BRTL8256REG_MODE_CTRL1 0x100 2229#define BRTL8256REG_MODE_CTRL0 0x40 2230#define BRTL8256REG_TXLPFBW 0x18 2231#define BRTL8256REG_RXLPFBW 0x600 2232 2233#define BRTL8258_TXLPFBW 0xc 2234#define BRTL8258_RXLPFBW 0xc00 2235#define BRTL8258_RSSILPFBW 0xc0 2236 2237#define BBYTE0 0x1 2238#define BBYTE1 0x2 2239#define BBYTE2 0x4 2240#define BBYTE3 0x8 2241#define BWORD0 0x3 2242#define BWORD1 0xc 2243#define BWORD 0xf 2244 2245#define BENABLE 0x1 2246#define BDISABLE 0x0 2247 2248#define LEFT_ANTENNA 0x0 2249#define RIGHT_ANTENNA 0x1 2250 2251#define TCHECK_TXSTATUS 500 2252#define TUPDATE_RXCOUNTER 100 2253 2254#define REG_UN_used_register 0x01bf 2255 2256/* WOL bit information */ 2257#define HAL92C_WOL_PTK_UPDATE_EVENT BIT(0) 2258#define HAL92C_WOL_GTK_UPDATE_EVENT BIT(1) 2259#define HAL92C_WOL_DISASSOC_EVENT BIT(2) 2260#define HAL92C_WOL_DEAUTH_EVENT BIT(3) 2261#define HAL92C_WOL_FW_DISCONNECT_EVENT BIT(4) 2262 2263#define WOL_REASON_PTK_UPDATE BIT(0) 2264#define WOL_REASON_GTK_UPDATE BIT(1) 2265#define WOL_REASON_DISASSOC BIT(2) 2266#define WOL_REASON_DEAUTH BIT(3) 2267#define WOL_REASON_FW_DISCONNECT BIT(4) 2268 2269/* 2 EFUSE_TEST (For RTL8723 partially) */ 2270#define EFUSE_SEL(x) (((x) & 0x3) << 8) 2271#define EFUSE_SEL_MASK 0x300 2272#define EFUSE_WIFI_SEL_0 0x0 2273 2274#define WL_HWPDN_EN BIT(0) /* Enable GPIO[9] as WiFi HW PDn source*/ 2275#define WL_HWPDN_SL BIT(1) /* WiFi HW PDn polarity control*/ 2276 2277#endif 2278