LXR linux/drivers/spi/spi-sirf.c

   1/*
   2 * SPI bus driver for CSR SiRFprimaII
   3 *
   4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
   5 *
   6 * Licensed under GPLv2 or later.
   7 */
   8
   9#include <linux/module.h>
  10#include <linux/kernel.h>
  11#include <linux/slab.h>
  12#include <linux/clk.h>
  13#include <linux/interrupt.h>
  14#include <linux/io.h>
  15#include <linux/of.h>
  16#include <linux/bitops.h>
  17#include <linux/err.h>
  18#include <linux/platform_device.h>
  19#include <linux/of_gpio.h>
  20#include <linux/spi/spi.h>
  21#include <linux/spi/spi_bitbang.h>
  22#include <linux/dmaengine.h>
  23#include <linux/dma-direction.h>
  24#include <linux/dma-mapping.h>
  25
  26#define DRIVER_NAME "sirfsoc_spi"
  27
  28#define SIRFSOC_SPI_CTRL                0x0000
  29#define SIRFSOC_SPI_CMD                 0x0004
  30#define SIRFSOC_SPI_TX_RX_EN            0x0008
  31#define SIRFSOC_SPI_INT_EN              0x000C
  32#define SIRFSOC_SPI_INT_STATUS          0x0010
  33#define SIRFSOC_SPI_TX_DMA_IO_CTRL      0x0100
  34#define SIRFSOC_SPI_TX_DMA_IO_LEN       0x0104
  35#define SIRFSOC_SPI_TXFIFO_CTRL         0x0108
  36#define SIRFSOC_SPI_TXFIFO_LEVEL_CHK    0x010C
  37#define SIRFSOC_SPI_TXFIFO_OP           0x0110
  38#define SIRFSOC_SPI_TXFIFO_STATUS       0x0114
  39#define SIRFSOC_SPI_TXFIFO_DATA         0x0118
  40#define SIRFSOC_SPI_RX_DMA_IO_CTRL      0x0120
  41#define SIRFSOC_SPI_RX_DMA_IO_LEN       0x0124
  42#define SIRFSOC_SPI_RXFIFO_CTRL         0x0128
  43#define SIRFSOC_SPI_RXFIFO_LEVEL_CHK    0x012C
  44#define SIRFSOC_SPI_RXFIFO_OP           0x0130
  45#define SIRFSOC_SPI_RXFIFO_STATUS       0x0134
  46#define SIRFSOC_SPI_RXFIFO_DATA         0x0138
  47#define SIRFSOC_SPI_DUMMY_DELAY_CTL     0x0144
  48
  49/* SPI CTRL register defines */
  50#define SIRFSOC_SPI_SLV_MODE            BIT(16)
  51#define SIRFSOC_SPI_CMD_MODE            BIT(17)
  52#define SIRFSOC_SPI_CS_IO_OUT           BIT(18)
  53#define SIRFSOC_SPI_CS_IO_MODE          BIT(19)
  54#define SIRFSOC_SPI_CLK_IDLE_STAT       BIT(20)
  55#define SIRFSOC_SPI_CS_IDLE_STAT        BIT(21)
  56#define SIRFSOC_SPI_TRAN_MSB            BIT(22)
  57#define SIRFSOC_SPI_DRV_POS_EDGE        BIT(23)
  58#define SIRFSOC_SPI_CS_HOLD_TIME        BIT(24)
  59#define SIRFSOC_SPI_CLK_SAMPLE_MODE     BIT(25)
  60#define SIRFSOC_SPI_TRAN_DAT_FORMAT_8   (0 << 26)
  61#define SIRFSOC_SPI_TRAN_DAT_FORMAT_12  (1 << 26)
  62#define SIRFSOC_SPI_TRAN_DAT_FORMAT_16  (2 << 26)
  63#define SIRFSOC_SPI_TRAN_DAT_FORMAT_32  (3 << 26)
  64#define SIRFSOC_SPI_CMD_BYTE_NUM(x)             ((x & 3) << 28)
  65#define SIRFSOC_SPI_ENA_AUTO_CLR                BIT(30)
  66#define SIRFSOC_SPI_MUL_DAT_MODE                BIT(31)
  67
  68/* Interrupt Enable */
  69#define SIRFSOC_SPI_RX_DONE_INT_EN              BIT(0)
  70#define SIRFSOC_SPI_TX_DONE_INT_EN              BIT(1)
  71#define SIRFSOC_SPI_RX_OFLOW_INT_EN             BIT(2)
  72#define SIRFSOC_SPI_TX_UFLOW_INT_EN             BIT(3)
  73#define SIRFSOC_SPI_RX_IO_DMA_INT_EN    BIT(4)
  74#define SIRFSOC_SPI_TX_IO_DMA_INT_EN    BIT(5)
  75#define SIRFSOC_SPI_RXFIFO_FULL_INT_EN  BIT(6)
  76#define SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN BIT(7)
  77#define SIRFSOC_SPI_RXFIFO_THD_INT_EN   BIT(8)
  78#define SIRFSOC_SPI_TXFIFO_THD_INT_EN   BIT(9)
  79#define SIRFSOC_SPI_FRM_END_INT_EN      BIT(10)
  80
  81#define SIRFSOC_SPI_INT_MASK_ALL                0x1FFF
  82
  83/* Interrupt status */
  84#define SIRFSOC_SPI_RX_DONE             BIT(0)
  85#define SIRFSOC_SPI_TX_DONE             BIT(1)
  86#define SIRFSOC_SPI_RX_OFLOW            BIT(2)
  87#define SIRFSOC_SPI_TX_UFLOW            BIT(3)
  88#define SIRFSOC_SPI_RX_FIFO_FULL        BIT(6)
  89#define SIRFSOC_SPI_TXFIFO_EMPTY        BIT(7)
  90#define SIRFSOC_SPI_RXFIFO_THD_REACH    BIT(8)
  91#define SIRFSOC_SPI_TXFIFO_THD_REACH    BIT(9)
  92#define SIRFSOC_SPI_FRM_END             BIT(10)
  93
  94/* TX RX enable */
  95#define SIRFSOC_SPI_RX_EN               BIT(0)
  96#define SIRFSOC_SPI_TX_EN               BIT(1)
  97#define SIRFSOC_SPI_CMD_TX_EN           BIT(2)
  98
  99#define SIRFSOC_SPI_IO_MODE_SEL         BIT(0)
 100#define SIRFSOC_SPI_RX_DMA_FLUSH        BIT(2)
 101
 102/* FIFO OPs */
 103#define SIRFSOC_SPI_FIFO_RESET          BIT(0)
 104#define SIRFSOC_SPI_FIFO_START          BIT(1)
 105
 106/* FIFO CTRL */
 107#define SIRFSOC_SPI_FIFO_WIDTH_BYTE     (0 << 0)
 108#define SIRFSOC_SPI_FIFO_WIDTH_WORD     (1 << 0)
 109#define SIRFSOC_SPI_FIFO_WIDTH_DWORD    (2 << 0)
 110
 111/* FIFO Status */
 112#define SIRFSOC_SPI_FIFO_LEVEL_MASK     0xFF
 113#define SIRFSOC_SPI_FIFO_FULL           BIT(8)
 114#define SIRFSOC_SPI_FIFO_EMPTY          BIT(9)
 115
 116/* 256 bytes rx/tx FIFO */
 117#define SIRFSOC_SPI_FIFO_SIZE           256
 118#define SIRFSOC_SPI_DAT_FRM_LEN_MAX     (64 * 1024)
 119
 120#define SIRFSOC_SPI_FIFO_SC(x)          ((x) & 0x3F)
 121#define SIRFSOC_SPI_FIFO_LC(x)          (((x) & 0x3F) << 10)
 122#define SIRFSOC_SPI_FIFO_HC(x)          (((x) & 0x3F) << 20)
 123#define SIRFSOC_SPI_FIFO_THD(x)         (((x) & 0xFF) << 2)
 124
 125/*
 126 * only if the rx/tx buffer and transfer size are 4-bytes aligned, we use dma
 127 * due to the limitation of dma controller
 128 */
 129
 130#define ALIGNED(x) (!((u32)x & 0x3))
 131#define IS_DMA_VALID(x) (x && ALIGNED(x->tx_buf) && ALIGNED(x->rx_buf) && \
 132        ALIGNED(x->len) && (x->len < 2 * PAGE_SIZE))
 133
 134#define SIRFSOC_MAX_CMD_BYTES   4
 135
 136struct sirfsoc_spi {
 137        struct spi_bitbang bitbang;
 138        struct completion rx_done;
 139        struct completion tx_done;
 140
 141        void __iomem *base;
 142        u32 ctrl_freq;  /* SPI controller clock speed */
 143        struct clk *clk;
 144
 145        /* rx & tx bufs from the spi_transfer */
 146        const void *tx;
 147        void *rx;
 148
 149        /* place received word into rx buffer */
 150        void (*rx_word) (struct sirfsoc_spi *);
 151        /* get word from tx buffer for sending */
 152        void (*tx_word) (struct sirfsoc_spi *);
 153
 154        /* number of words left to be tranmitted/received */
 155        unsigned int left_tx_word;
 156        unsigned int left_rx_word;
 157
 158        /* rx & tx DMA channels */
 159        struct dma_chan *rx_chan;
 160        struct dma_chan *tx_chan;
 161        dma_addr_t src_start;
 162        dma_addr_t dst_start;
 163        void *dummypage;
 164        int word_width; /* in bytes */
 165
 166        /*
 167         * if tx size is not more than 4 and rx size is NULL, use
 168         * command model
 169         */
 170        bool    tx_by_cmd;
 171
 172        int chipselect[0];
 173};
 174
 175static void spi_sirfsoc_rx_word_u8(struct sirfsoc_spi *sspi)
 176{
 177        u32 data;
 178        u8 *rx = sspi->rx;
 179
 180        data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA);
 181
 182        if (rx) {
 183                *rx++ = (u8) data;
 184                sspi->rx = rx;
 185        }
 186
 187        sspi->left_rx_word--;
 188}
 189
 190static void spi_sirfsoc_tx_word_u8(struct sirfsoc_spi *sspi)
 191{
 192        u32 data = 0;
 193        const u8 *tx = sspi->tx;
 194
 195        if (tx) {
 196                data = *tx++;
 197                sspi->tx = tx;
 198        }
 199
 200        writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);
 201        sspi->left_tx_word--;
 202}
 203
 204static void spi_sirfsoc_rx_word_u16(struct sirfsoc_spi *sspi)
 205{
 206        u32 data;
 207        u16 *rx = sspi->rx;
 208
 209        data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA);
 210
 211        if (rx) {
 212                *rx++ = (u16) data;
 213                sspi->rx = rx;
 214        }
 215
 216        sspi->left_rx_word--;
 217}
 218
 219static void spi_sirfsoc_tx_word_u16(struct sirfsoc_spi *sspi)
 220{
 221        u32 data = 0;
 222        const u16 *tx = sspi->tx;
 223
 224        if (tx) {
 225                data = *tx++;
 226                sspi->tx = tx;
 227        }
 228
 229        writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);
 230        sspi->left_tx_word--;
 231}
 232
 233static void spi_sirfsoc_rx_word_u32(struct sirfsoc_spi *sspi)
 234{
 235        u32 data;
 236        u32 *rx = sspi->rx;
 237
 238        data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA);
 239
 240        if (rx) {
 241                *rx++ = (u32) data;
 242                sspi->rx = rx;
 243        }
 244
 245        sspi->left_rx_word--;
 246
 247}
 248
 249static void spi_sirfsoc_tx_word_u32(struct sirfsoc_spi *sspi)
 250{
 251        u32 data = 0;
 252        const u32 *tx = sspi->tx;
 253
 254        if (tx) {
 255                data = *tx++;
 256                sspi->tx = tx;
 257        }
 258
 259        writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);
 260        sspi->left_tx_word--;
 261}
 262
 263static irqreturn_t spi_sirfsoc_irq(int irq, void *dev_id)
 264{
 265        struct sirfsoc_spi *sspi = dev_id;
 266        u32 spi_stat = readl(sspi->base + SIRFSOC_SPI_INT_STATUS);
 267
 268        writel(spi_stat, sspi->base + SIRFSOC_SPI_INT_STATUS);
 269
 270        if (sspi->tx_by_cmd && (spi_stat & SIRFSOC_SPI_FRM_END)) {
 271                complete(&sspi->tx_done);
 272                writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
 273                return IRQ_HANDLED;
 274        }
 275
 276        /* Error Conditions */
 277        if (spi_stat & SIRFSOC_SPI_RX_OFLOW ||
 278                        spi_stat & SIRFSOC_SPI_TX_UFLOW) {
 279                complete(&sspi->rx_done);
 280                writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
 281        }
 282
 283        if (spi_stat & (SIRFSOC_SPI_FRM_END
 284                        | SIRFSOC_SPI_RXFIFO_THD_REACH))
 285                while (!((readl(sspi->base + SIRFSOC_SPI_RXFIFO_STATUS)
 286                                & SIRFSOC_SPI_FIFO_EMPTY)) &&
 287                                sspi->left_rx_word)
 288                        sspi->rx_word(sspi);
 289
 290        if (spi_stat & (SIRFSOC_SPI_TXFIFO_EMPTY |
 291                        SIRFSOC_SPI_TXFIFO_THD_REACH))
 292                while (!((readl(sspi->base + SIRFSOC_SPI_TXFIFO_STATUS)
 293                                & SIRFSOC_SPI_FIFO_FULL)) &&
 294                                sspi->left_tx_word)
 295                        sspi->tx_word(sspi);
 296
 297        /* Received all words */
 298        if ((sspi->left_rx_word == 0) && (sspi->left_tx_word == 0)) {
 299                complete(&sspi->rx_done);
 300                writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
 301        }
 302        return IRQ_HANDLED;
 303}
 304
 305static void spi_sirfsoc_dma_fini_callback(void *data)
 306{
 307        struct completion *dma_complete = data;
 308
 309        complete(dma_complete);
 310}
 311
 312static int spi_sirfsoc_transfer(struct spi_device *spi, struct spi_transfer *t)
 313{
 314        struct sirfsoc_spi *sspi;
 315        int timeout = t->len * 10;
 316        sspi = spi_master_get_devdata(spi->master);
 317
 318        sspi->tx = t->tx_buf ? t->tx_buf : sspi->dummypage;
 319        sspi->rx = t->rx_buf ? t->rx_buf : sspi->dummypage;
 320        sspi->left_tx_word = sspi->left_rx_word = t->len / sspi->word_width;
 321        reinit_completion(&sspi->rx_done);
 322        reinit_completion(&sspi->tx_done);
 323
 324        writel(SIRFSOC_SPI_INT_MASK_ALL, sspi->base + SIRFSOC_SPI_INT_STATUS);
 325
 326        /*
 327         * fill tx_buf into command register and wait for its completion
 328         */
 329        if (sspi->tx_by_cmd) {
 330                u32 cmd;
 331                memcpy(&cmd, sspi->tx, t->len);
 332
 333                if (sspi->word_width == 1 && !(spi->mode & SPI_LSB_FIRST))
 334                        cmd = cpu_to_be32(cmd) >>
 335                                ((SIRFSOC_MAX_CMD_BYTES - t->len) * 8);
 336                if (sspi->word_width == 2 && t->len == 4 &&
 337                                (!(spi->mode & SPI_LSB_FIRST)))
 338                        cmd = ((cmd & 0xffff) << 16) | (cmd >> 16);
 339
 340                writel(cmd, sspi->base + SIRFSOC_SPI_CMD);
 341                writel(SIRFSOC_SPI_FRM_END_INT_EN,
 342                        sspi->base + SIRFSOC_SPI_INT_EN);
 343                writel(SIRFSOC_SPI_CMD_TX_EN,
 344                        sspi->base + SIRFSOC_SPI_TX_RX_EN);
 345
 346                if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) {
 347                        dev_err(&spi->dev, "transfer timeout\n");
 348                        return 0;
 349                }
 350
 351                return t->len;
 352        }
 353
 354        if (sspi->left_tx_word == 1) {
 355                writel(readl(sspi->base + SIRFSOC_SPI_CTRL) |
 356                        SIRFSOC_SPI_ENA_AUTO_CLR,
 357                        sspi->base + SIRFSOC_SPI_CTRL);
 358                writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
 359                writel(0, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
 360        } else if ((sspi->left_tx_word > 1) && (sspi->left_tx_word <
 361                                SIRFSOC_SPI_DAT_FRM_LEN_MAX)) {
 362                writel(readl(sspi->base + SIRFSOC_SPI_CTRL) |
 363                                SIRFSOC_SPI_MUL_DAT_MODE |
 364                                SIRFSOC_SPI_ENA_AUTO_CLR,
 365                        sspi->base + SIRFSOC_SPI_CTRL);
 366                writel(sspi->left_tx_word - 1,
 367                                sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
 368                writel(sspi->left_tx_word - 1,
 369                                sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
 370        } else {
 371                writel(readl(sspi->base + SIRFSOC_SPI_CTRL),
 372                        sspi->base + SIRFSOC_SPI_CTRL);
 373                writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
 374                writel(0, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
 375        }
 376
 377        writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 378        writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 379        writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 380        writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 381
 382        if (IS_DMA_VALID(t)) {
 383                struct dma_async_tx_descriptor *rx_desc, *tx_desc;
 384
 385                sspi->dst_start = dma_map_single(&spi->dev, sspi->rx, t->len, DMA_FROM_DEVICE);
 386                rx_desc = dmaengine_prep_slave_single(sspi->rx_chan,
 387                        sspi->dst_start, t->len, DMA_DEV_TO_MEM,
 388                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 389                rx_desc->callback = spi_sirfsoc_dma_fini_callback;
 390                rx_desc->callback_param = &sspi->rx_done;
 391
 392                sspi->src_start = dma_map_single(&spi->dev, (void *)sspi->tx, t->len, DMA_TO_DEVICE);
 393                tx_desc = dmaengine_prep_slave_single(sspi->tx_chan,
 394                        sspi->src_start, t->len, DMA_MEM_TO_DEV,
 395                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 396                tx_desc->callback = spi_sirfsoc_dma_fini_callback;
 397                tx_desc->callback_param = &sspi->tx_done;
 398
 399                dmaengine_submit(tx_desc);
 400                dmaengine_submit(rx_desc);
 401                dma_async_issue_pending(sspi->tx_chan);
 402                dma_async_issue_pending(sspi->rx_chan);
 403        } else {
 404                /* Send the first word to trigger the whole tx/rx process */
 405                sspi->tx_word(sspi);
 406
 407                writel(SIRFSOC_SPI_RX_OFLOW_INT_EN | SIRFSOC_SPI_TX_UFLOW_INT_EN |
 408                        SIRFSOC_SPI_RXFIFO_THD_INT_EN | SIRFSOC_SPI_TXFIFO_THD_INT_EN |
 409                        SIRFSOC_SPI_FRM_END_INT_EN | SIRFSOC_SPI_RXFIFO_FULL_INT_EN |
 410                        SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN, sspi->base + SIRFSOC_SPI_INT_EN);
 411        }
 412
 413        writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN, sspi->base + SIRFSOC_SPI_TX_RX_EN);
 414
 415        if (!IS_DMA_VALID(t)) { /* for PIO */
 416                if (wait_for_completion_timeout(&sspi->rx_done, timeout) == 0)
 417                        dev_err(&spi->dev, "transfer timeout\n");
 418        } else if (wait_for_completion_timeout(&sspi->rx_done, timeout) == 0) {
 419                dev_err(&spi->dev, "transfer timeout\n");
 420                dmaengine_terminate_all(sspi->rx_chan);
 421        } else
 422                sspi->left_rx_word = 0;
 423
 424        /*
 425         * we only wait tx-done event if transferring by DMA. for PIO,
 426         * we get rx data by writing tx data, so if rx is done, tx has
 427         * done earlier
 428         */
 429        if (IS_DMA_VALID(t)) {
 430                if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) {
 431                        dev_err(&spi->dev, "transfer timeout\n");
 432                        dmaengine_terminate_all(sspi->tx_chan);
 433                }
 434        }
 435
 436        if (IS_DMA_VALID(t)) {
 437                dma_unmap_single(&spi->dev, sspi->src_start, t->len, DMA_TO_DEVICE);
 438                dma_unmap_single(&spi->dev, sspi->dst_start, t->len, DMA_FROM_DEVICE);
 439        }
 440
 441        /* TX, RX FIFO stop */
 442        writel(0, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 443        writel(0, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 444        writel(0, sspi->base + SIRFSOC_SPI_TX_RX_EN);
 445        writel(0, sspi->base + SIRFSOC_SPI_INT_EN);
 446
 447        return t->len - sspi->left_rx_word * sspi->word_width;
 448}
 449
 450static void spi_sirfsoc_chipselect(struct spi_device *spi, int value)
 451{
 452        struct sirfsoc_spi *sspi = spi_master_get_devdata(spi->master);
 453
 454        if (sspi->chipselect[spi->chip_select] == 0) {
 455                u32 regval = readl(sspi->base + SIRFSOC_SPI_CTRL);
 456                switch (value) {
 457                case BITBANG_CS_ACTIVE:
 458                        if (spi->mode & SPI_CS_HIGH)
 459                                regval |= SIRFSOC_SPI_CS_IO_OUT;
 460                        else
 461                                regval &= ~SIRFSOC_SPI_CS_IO_OUT;
 462                        break;
 463                case BITBANG_CS_INACTIVE:
 464                        if (spi->mode & SPI_CS_HIGH)
 465                                regval &= ~SIRFSOC_SPI_CS_IO_OUT;
 466                        else
 467                                regval |= SIRFSOC_SPI_CS_IO_OUT;
 468                        break;
 469                }
 470                writel(regval, sspi->base + SIRFSOC_SPI_CTRL);
 471        } else {
 472                int gpio = sspi->chipselect[spi->chip_select];
 473                switch (value) {
 474                case BITBANG_CS_ACTIVE:
 475                        gpio_direction_output(gpio,
 476                                        spi->mode & SPI_CS_HIGH ? 1 : 0);
 477                        break;
 478                case BITBANG_CS_INACTIVE:
 479                        gpio_direction_output(gpio,
 480                                        spi->mode & SPI_CS_HIGH ? 0 : 1);
 481                        break;
 482                }
 483        }
 484}
 485
 486static int
 487spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
 488{
 489        struct sirfsoc_spi *sspi;
 490        u8 bits_per_word = 0;
 491        int hz = 0;
 492        u32 regval;
 493        u32 txfifo_ctrl, rxfifo_ctrl;
 494        u32 fifo_size = SIRFSOC_SPI_FIFO_SIZE / 4;
 495
 496        sspi = spi_master_get_devdata(spi->master);
 497
 498        bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
 499        hz = t && t->speed_hz ? t->speed_hz : spi->max_speed_hz;
 500
 501        regval = (sspi->ctrl_freq / (2 * hz)) - 1;
 502        if (regval > 0xFFFF || regval < 0) {
 503                dev_err(&spi->dev, "Speed %d not supported\n", hz);
 504                return -EINVAL;
 505        }
 506
 507        switch (bits_per_word) {
 508        case 8:
 509                regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_8;
 510                sspi->rx_word = spi_sirfsoc_rx_word_u8;
 511                sspi->tx_word = spi_sirfsoc_tx_word_u8;
 512                break;
 513        case 12:
 514        case 16:
 515                regval |= (bits_per_word ==  12) ? SIRFSOC_SPI_TRAN_DAT_FORMAT_12 :
 516                        SIRFSOC_SPI_TRAN_DAT_FORMAT_16;
 517                sspi->rx_word = spi_sirfsoc_rx_word_u16;
 518                sspi->tx_word = spi_sirfsoc_tx_word_u16;
 519                break;
 520        case 32:
 521                regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_32;
 522                sspi->rx_word = spi_sirfsoc_rx_word_u32;
 523                sspi->tx_word = spi_sirfsoc_tx_word_u32;
 524                break;
 525        default:
 526                BUG();
 527        }
 528
 529        sspi->word_width = DIV_ROUND_UP(bits_per_word, 8);
 530        txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
 531                                           sspi->word_width;
 532        rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
 533                                           sspi->word_width;
 534
 535        if (!(spi->mode & SPI_CS_HIGH))
 536                regval |= SIRFSOC_SPI_CS_IDLE_STAT;
 537        if (!(spi->mode & SPI_LSB_FIRST))
 538                regval |= SIRFSOC_SPI_TRAN_MSB;
 539        if (spi->mode & SPI_CPOL)
 540                regval |= SIRFSOC_SPI_CLK_IDLE_STAT;
 541
 542        /*
 543         * Data should be driven at least 1/2 cycle before the fetch edge to make
 544         * sure that data gets stable at the fetch edge.
 545         */
 546        if (((spi->mode & SPI_CPOL) && (spi->mode & SPI_CPHA)) ||
 547            (!(spi->mode & SPI_CPOL) && !(spi->mode & SPI_CPHA)))
 548                regval &= ~SIRFSOC_SPI_DRV_POS_EDGE;
 549        else
 550                regval |= SIRFSOC_SPI_DRV_POS_EDGE;
 551
 552        writel(SIRFSOC_SPI_FIFO_SC(fifo_size - 2) |
 553                        SIRFSOC_SPI_FIFO_LC(fifo_size / 2) |
 554                        SIRFSOC_SPI_FIFO_HC(2),
 555                sspi->base + SIRFSOC_SPI_TXFIFO_LEVEL_CHK);
 556        writel(SIRFSOC_SPI_FIFO_SC(2) |
 557                        SIRFSOC_SPI_FIFO_LC(fifo_size / 2) |
 558                        SIRFSOC_SPI_FIFO_HC(fifo_size - 2),
 559                sspi->base + SIRFSOC_SPI_RXFIFO_LEVEL_CHK);
 560        writel(txfifo_ctrl, sspi->base + SIRFSOC_SPI_TXFIFO_CTRL);
 561        writel(rxfifo_ctrl, sspi->base + SIRFSOC_SPI_RXFIFO_CTRL);
 562
 563        if (t && t->tx_buf && !t->rx_buf && (t->len <= SIRFSOC_MAX_CMD_BYTES)) {
 564                regval |= (SIRFSOC_SPI_CMD_BYTE_NUM((t->len - 1)) |
 565                                SIRFSOC_SPI_CMD_MODE);
 566                sspi->tx_by_cmd = true;
 567        } else {
 568                regval &= ~SIRFSOC_SPI_CMD_MODE;
 569                sspi->tx_by_cmd = false;
 570        }
 571        /*
 572         * set spi controller in RISC chipselect mode, we are controlling CS by
 573         * software BITBANG_CS_ACTIVE and BITBANG_CS_INACTIVE.
 574         */
 575        regval |= SIRFSOC_SPI_CS_IO_MODE;
 576        writel(regval, sspi->base + SIRFSOC_SPI_CTRL);
 577
 578        if (IS_DMA_VALID(t)) {
 579                /* Enable DMA mode for RX, TX */
 580                writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_CTRL);
 581                writel(SIRFSOC_SPI_RX_DMA_FLUSH, sspi->base + SIRFSOC_SPI_RX_DMA_IO_CTRL);
 582        } else {
 583                /* Enable IO mode for RX, TX */
 584                writel(SIRFSOC_SPI_IO_MODE_SEL, sspi->base + SIRFSOC_SPI_TX_DMA_IO_CTRL);
 585                writel(SIRFSOC_SPI_IO_MODE_SEL, sspi->base + SIRFSOC_SPI_RX_DMA_IO_CTRL);
 586        }
 587
 588        return 0;
 589}
 590
 591static int spi_sirfsoc_setup(struct spi_device *spi)
 592{
 593        if (!spi->max_speed_hz)
 594                return -EINVAL;
 595
 596        return spi_sirfsoc_setup_transfer(spi, NULL);
 597}
 598
 599static int spi_sirfsoc_probe(struct platform_device *pdev)
 600{
 601        struct sirfsoc_spi *sspi;
 602        struct spi_master *master;
 603        struct resource *mem_res;
 604        int num_cs, cs_gpio, irq;
 605        int i;
 606        int ret;
 607
 608        ret = of_property_read_u32(pdev->dev.of_node,
 609                        "sirf,spi-num-chipselects", &num_cs);
 610        if (ret < 0) {
 611                dev_err(&pdev->dev, "Unable to get chip select number\n");
 612                goto err_cs;
 613        }
 614
 615        master = spi_alloc_master(&pdev->dev, sizeof(*sspi) + sizeof(int) * num_cs);
 616        if (!master) {
 617                dev_err(&pdev->dev, "Unable to allocate SPI master\n");
 618                return -ENOMEM;
 619        }
 620        platform_set_drvdata(pdev, master);
 621        sspi = spi_master_get_devdata(master);
 622
 623        master->num_chipselect = num_cs;
 624
 625        for (i = 0; i < master->num_chipselect; i++) {
 626                cs_gpio = of_get_named_gpio(pdev->dev.of_node, "cs-gpios", i);
 627                if (cs_gpio < 0) {
 628                        dev_err(&pdev->dev, "can't get cs gpio from DT\n");
 629                        ret = -ENODEV;
 630                        goto free_master;
 631                }
 632
 633                sspi->chipselect[i] = cs_gpio;
 634                if (cs_gpio == 0)
 635                        continue; /* use cs from spi controller */
 636
 637                ret = gpio_request(cs_gpio, DRIVER_NAME);
 638                if (ret) {
 639                        while (i > 0) {
 640                                i--;
 641                                if (sspi->chipselect[i] > 0)
 642                                        gpio_free(sspi->chipselect[i]);
 643                        }
 644                        dev_err(&pdev->dev, "fail to request cs gpios\n");
 645                        goto free_master;
 646                }
 647        }
 648
 649        mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 650        sspi->base = devm_ioremap_resource(&pdev->dev, mem_res);
 651        if (IS_ERR(sspi->base)) {
 652                ret = PTR_ERR(sspi->base);
 653                goto free_master;
 654        }
 655
 656        irq = platform_get_irq(pdev, 0);
 657        if (irq < 0) {
 658                ret = -ENXIO;
 659                goto free_master;
 660        }
 661        ret = devm_request_irq(&pdev->dev, irq, spi_sirfsoc_irq, 0,
 662                                DRIVER_NAME, sspi);
 663        if (ret)
 664                goto free_master;
 665
 666        sspi->bitbang.master = master;
 667        sspi->bitbang.chipselect = spi_sirfsoc_chipselect;
 668        sspi->bitbang.setup_transfer = spi_sirfsoc_setup_transfer;
 669        sspi->bitbang.txrx_bufs = spi_sirfsoc_transfer;
 670        sspi->bitbang.master->setup = spi_sirfsoc_setup;
 671        master->bus_num = pdev->id;
 672        master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH;
 673        master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(12) |
 674                                        SPI_BPW_MASK(16) | SPI_BPW_MASK(32);
 675        sspi->bitbang.master->dev.of_node = pdev->dev.of_node;
 676
 677        /* request DMA channels */
 678        sspi->rx_chan = dma_request_slave_channel(&pdev->dev, "rx");
 679        if (!sspi->rx_chan) {
 680                dev_err(&pdev->dev, "can not allocate rx dma channel\n");
 681                ret = -ENODEV;
 682                goto free_master;
 683        }
 684        sspi->tx_chan = dma_request_slave_channel(&pdev->dev, "tx");
 685        if (!sspi->tx_chan) {
 686                dev_err(&pdev->dev, "can not allocate tx dma channel\n");
 687                ret = -ENODEV;
 688                goto free_rx_dma;
 689        }
 690
 691        sspi->clk = clk_get(&pdev->dev, NULL);
 692        if (IS_ERR(sspi->clk)) {
 693                ret = PTR_ERR(sspi->clk);
 694                goto free_tx_dma;
 695        }
 696        clk_prepare_enable(sspi->clk);
 697        sspi->ctrl_freq = clk_get_rate(sspi->clk);
 698
 699        init_completion(&sspi->rx_done);
 700        init_completion(&sspi->tx_done);
 701
 702        writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 703        writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 704        writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 705        writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 706        /* We are not using dummy delay between command and data */
 707        writel(0, sspi->base + SIRFSOC_SPI_DUMMY_DELAY_CTL);
 708
 709        sspi->dummypage = kmalloc(2 * PAGE_SIZE, GFP_KERNEL);
 710        if (!sspi->dummypage) {
 711                ret = -ENOMEM;
 712                goto free_clk;
 713        }
 714
 715        ret = spi_bitbang_start(&sspi->bitbang);
 716        if (ret)
 717                goto free_dummypage;
 718
 719        dev_info(&pdev->dev, "registerred, bus number = %d\n", master->bus_num);
 720
 721        return 0;
 722free_dummypage:
 723        kfree(sspi->dummypage);
 724free_clk:
 725        clk_disable_unprepare(sspi->clk);
 726        clk_put(sspi->clk);
 727free_tx_dma:
 728        dma_release_channel(sspi->tx_chan);
 729free_rx_dma:
 730        dma_release_channel(sspi->rx_chan);
 731free_master:
 732        spi_master_put(master);
 733err_cs:
 734        return ret;
 735}
 736
 737static int  spi_sirfsoc_remove(struct platform_device *pdev)
 738{
 739        struct spi_master *master;
 740        struct sirfsoc_spi *sspi;
 741        int i;
 742
 743        master = platform_get_drvdata(pdev);
 744        sspi = spi_master_get_devdata(master);
 745
 746        spi_bitbang_stop(&sspi->bitbang);
 747        for (i = 0; i < master->num_chipselect; i++) {
 748                if (sspi->chipselect[i] > 0)
 749                        gpio_free(sspi->chipselect[i]);
 750        }
 751        kfree(sspi->dummypage);
 752        clk_disable_unprepare(sspi->clk);
 753        clk_put(sspi->clk);
 754        dma_release_channel(sspi->rx_chan);
 755        dma_release_channel(sspi->tx_chan);
 756        spi_master_put(master);
 757        return 0;
 758}
 759
 760#ifdef CONFIG_PM_SLEEP
 761static int spi_sirfsoc_suspend(struct device *dev)
 762{
 763        struct spi_master *master = dev_get_drvdata(dev);
 764        struct sirfsoc_spi *sspi = spi_master_get_devdata(master);
 765        int ret;
 766
 767        ret = spi_master_suspend(master);
 768        if (ret)
 769                return ret;
 770
 771        clk_disable(sspi->clk);
 772        return 0;
 773}
 774
 775static int spi_sirfsoc_resume(struct device *dev)
 776{
 777        struct spi_master *master = dev_get_drvdata(dev);
 778        struct sirfsoc_spi *sspi = spi_master_get_devdata(master);
 779
 780        clk_enable(sspi->clk);
 781        writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 782        writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 783        writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 784        writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 785
 786        return spi_master_resume(master);
 787}
 788#endif
 789
 790static SIMPLE_DEV_PM_OPS(spi_sirfsoc_pm_ops, spi_sirfsoc_suspend,
 791                         spi_sirfsoc_resume);
 792
 793static const struct of_device_id spi_sirfsoc_of_match[] = {
 794        { .compatible = "sirf,prima2-spi", },
 795        { .compatible = "sirf,marco-spi", },
 796        {}
 797};
 798MODULE_DEVICE_TABLE(of, spi_sirfsoc_of_match);
 799
 800static struct platform_driver spi_sirfsoc_driver = {
 801        .driver = {
 802                .name = DRIVER_NAME,
 803                .owner = THIS_MODULE,
 804                .pm     = &spi_sirfsoc_pm_ops,
 805                .of_match_table = spi_sirfsoc_of_match,
 806        },
 807        .probe = spi_sirfsoc_probe,
 808        .remove = spi_sirfsoc_remove,
 809};
 810module_platform_driver(spi_sirfsoc_driver);
 811
 812MODULE_DESCRIPTION("SiRF SoC SPI master driver");
 813MODULE_AUTHOR("Zhiwu Song <Zhiwu.Song@csr.com>, "
 814                "Barry Song <Baohua.Song@csr.com>");
 815MODULE_LICENSE("GPL v2");
 816