1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21#ifndef R8180_HW
22#define R8180_HW
23
24enum baseband_config {
25 BaseBand_Config_PHY_REG = 0,
26 BaseBand_Config_AGC_TAB = 1,
27};
28
29#define RTL8187_REQT_READ 0xc0
30#define RTL8187_REQT_WRITE 0x40
31#define RTL8187_REQ_GET_REGS 0x05
32#define RTL8187_REQ_SET_REGS 0x05
33
34#define MAX_TX_URB 5
35#define MAX_RX_URB 16
36#define RX_URB_SIZE 9100
37
38#define BB_ANTATTEN_CHAN14 0x0c
39#define BB_ANTENNA_B 0x40
40
41#define BB_HOST_BANG (1<<30)
42#define BB_HOST_BANG_EN (1<<2)
43#define BB_HOST_BANG_CLK (1<<1)
44#define BB_HOST_BANG_RW (1<<3)
45#define BB_HOST_BANG_DATA 1
46
47#define RTL8190_EEPROM_ID 0x8129
48#define EEPROM_VID 0x02
49#define EEPROM_DID 0x04
50#define EEPROM_NODE_ADDRESS_BYTE_0 0x0C
51
52#define EEPROM_TxPowerDiff 0x1F
53
54
55#define EEPROM_PwDiff 0x21
56#define EEPROM_CrystalCap 0x22
57
58
59
60#define EEPROM_TxPwIndex_CCK_V1 0x29
61#define EEPROM_TxPwIndex_OFDM_24G_V1 0x2C
62#define EEPROM_TxPwIndex_Ver 0x27
63
64#define EEPROM_Default_TxPowerDiff 0x0
65#define EEPROM_Default_ThermalMeter 0x77
66#define EEPROM_Default_AntTxPowerDiff 0x0
67#define EEPROM_Default_TxPwDiff_CrystalCap 0x5
68#define EEPROM_Default_PwDiff 0x4
69#define EEPROM_Default_CrystalCap 0x5
70#define EEPROM_Default_TxPower 0x1010
71#define EEPROM_ICVersion_ChannelPlan 0x7C
72#define EEPROM_Customer_ID 0x7B
73#define EEPROM_RFInd_PowerDiff 0x28
74#define EEPROM_ThermalMeter 0x29
75#define EEPROM_TxPwDiff_CrystalCap 0x2A
76#define EEPROM_TxPwIndex_CCK 0x2C
77#define EEPROM_TxPwIndex_OFDM_24G 0x3A
78#define EEPROM_Default_TxPowerLevel 0x10
79#define EEPROM_IC_VER 0x7d
80#define EEPROM_CRC 0x7e
81
82#define EEPROM_CID_DEFAULT 0x0
83#define EEPROM_CID_CAMEO 0x1
84#define EEPROM_CID_RUNTOP 0x2
85#define EEPROM_CID_Senao 0x3
86#define EEPROM_CID_TOSHIBA 0x4
87#define EEPROM_CID_NetCore 0x5
88#define EEPROM_CID_Nettronix 0x6
89#define EEPROM_CID_Pronet 0x7
90#define EEPROM_CID_DLINK 0x8
91#define EEPROM_CID_WHQL 0xFE
92enum _RTL8192Pci_HW {
93 MAC0 = 0x000,
94 MAC1 = 0x001,
95 MAC2 = 0x002,
96 MAC3 = 0x003,
97 MAC4 = 0x004,
98 MAC5 = 0x005,
99 PCIF = 0x009,
100#define MXDMA2_16bytes 0x000
101#define MXDMA2_32bytes 0x001
102#define MXDMA2_64bytes 0x010
103#define MXDMA2_128bytes 0x011
104#define MXDMA2_256bytes 0x100
105#define MXDMA2_512bytes 0x101
106#define MXDMA2_1024bytes 0x110
107#define MXDMA2_NoLimit 0x7
108
109#define MULRW_SHIFT 3
110#define MXDMA2_RX_SHIFT 4
111#define MXDMA2_TX_SHIFT 0
112 PMR = 0x00c,
113 EPROM_CMD = 0x00e,
114#define EPROM_CMD_RESERVED_MASK BIT5
115#define EPROM_CMD_9356SEL BIT4
116#define EPROM_CMD_OPERATING_MODE_SHIFT 6
117#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6))
118#define EPROM_CMD_CONFIG 0x3
119#define EPROM_CMD_NORMAL 0
120#define EPROM_CMD_LOAD 1
121#define EPROM_CMD_PROGRAM 2
122#define EPROM_CS_SHIFT 3
123#define EPROM_CK_SHIFT 2
124#define EPROM_W_SHIFT 1
125#define EPROM_R_SHIFT 0
126
127 AFR = 0x010,
128#define AFR_CardBEn (1<<0)
129#define AFR_CLKRUN_SEL (1<<1)
130#define AFR_FuncRegEn (1<<2)
131
132 ANAPAR = 0x17,
133#define BB_GLOBAL_RESET_BIT 0x1
134 BB_GLOBAL_RESET = 0x020,
135 BSSIDR = 0x02E,
136 CMDR = 0x037,
137#define CR_RST 0x10
138#define CR_RE 0x08
139#define CR_TE 0x04
140#define CR_MulRW 0x01
141 SIFS = 0x03E,
142 TCR = 0x040,
143 RCR = 0x044,
144#define RCR_FILTER_MASK (BIT0 | BIT1 | BIT2 | BIT3 | BIT5 | BIT12 | \
145 BIT18 | BIT19 | BIT20 | BIT21 | BIT22 | BIT23)
146#define RCR_ONLYERLPKT BIT31
147#define RCR_ENCS2 BIT30
148#define RCR_ENCS1 BIT29
149#define RCR_ENMBID BIT27
150#define RCR_ACKTXBW (BIT24|BIT25)
151#define RCR_CBSSID BIT23
152#define RCR_APWRMGT BIT22
153#define RCR_ADD3 BIT21
154#define RCR_AMF BIT20
155#define RCR_ACF BIT19
156#define RCR_ADF BIT18
157#define RCR_RXFTH BIT13
158#define RCR_AICV BIT12
159#define RCR_ACRC32 BIT5
160#define RCR_AB BIT3
161#define RCR_AM BIT2
162#define RCR_APM BIT1
163#define RCR_AAP BIT0
164#define RCR_MXDMA_OFFSET 8
165#define RCR_FIFO_OFFSET 13
166 SLOT_TIME = 0x049,
167 ACK_TIMEOUT = 0x04c,
168 PIFS_TIME = 0x04d,
169 USTIME = 0x04e,
170 EDCAPARA_BE = 0x050,
171 EDCAPARA_BK = 0x054,
172 EDCAPARA_VO = 0x058,
173 EDCAPARA_VI = 0x05C,
174#define AC_PARAM_TXOP_LIMIT_OFFSET 16
175#define AC_PARAM_ECW_MAX_OFFSET 12
176#define AC_PARAM_ECW_MIN_OFFSET 8
177#define AC_PARAM_AIFS_OFFSET 0
178 RFPC = 0x05F,
179 CWRR = 0x060,
180 BCN_TCFG = 0x062,
181#define BCN_TCFG_CW_SHIFT 8
182#define BCN_TCFG_IFS 0
183 BCN_INTERVAL = 0x070,
184 ATIMWND = 0x072,
185 BCN_DRV_EARLY_INT = 0x074,
186#define BCN_DRV_EARLY_INT_SWBCN_SHIFT 8
187#define BCN_DRV_EARLY_INT_TIME_SHIFT 0
188 BCN_DMATIME = 0x076,
189 BCN_ERR_THRESH = 0x078,
190 RWCAM = 0x0A0,
191#define CAM_CM_SecCAMPolling BIT31
192#define CAM_CM_SecCAMClr BIT30
193#define CAM_CM_SecCAMWE BIT16
194#define CAM_VALID BIT15
195#define CAM_NOTVALID 0x0000
196#define CAM_USEDK BIT5
197
198#define CAM_NONE 0x0
199#define CAM_WEP40 0x01
200#define CAM_TKIP 0x02
201#define CAM_AES 0x04
202#define CAM_WEP104 0x05
203
204#define TOTAL_CAM_ENTRY 32
205
206#define CAM_CONFIG_USEDK true
207#define CAM_CONFIG_NO_USEDK false
208#define CAM_WRITE BIT16
209#define CAM_READ 0x00000000
210#define CAM_POLLINIG BIT31
211#define SCR_UseDK 0x01
212 WCAMI = 0x0A4,
213 RCAMO = 0x0A8,
214 SECR = 0x0B0,
215#define SCR_TxUseDK BIT0
216#define SCR_RxUseDK BIT1
217#define SCR_TxEncEnable BIT2
218#define SCR_RxDecEnable BIT3
219#define SCR_SKByA2 BIT4
220#define SCR_NoSKMC BIT5
221 SWREGULATOR = 0x0BD,
222 INTA_MASK = 0x0f4,
223#define IMR8190_DISABLED 0x0
224#define IMR_ATIMEND BIT28
225#define IMR_TBDOK BIT27
226#define IMR_TBDER BIT26
227#define IMR_TXFOVW BIT15
228#define IMR_TIMEOUT0 BIT14
229#define IMR_BcnInt BIT13
230#define IMR_RXFOVW BIT12
231#define IMR_RDU BIT11
232#define IMR_RXCMDOK BIT10
233#define IMR_BDOK BIT9
234#define IMR_HIGHDOK BIT8
235#define IMR_COMDOK BIT7
236#define IMR_MGNTDOK BIT6
237#define IMR_HCCADOK BIT5
238#define IMR_BKDOK BIT4
239#define IMR_BEDOK BIT3
240#define IMR_VIDOK BIT2
241#define IMR_VODOK BIT1
242#define IMR_ROK BIT0
243 ISR = 0x0f8,
244 TPPoll = 0x0fd,
245#define TPPoll_BKQ BIT0
246#define TPPoll_BEQ BIT1
247#define TPPoll_VIQ BIT2
248#define TPPoll_VOQ BIT3
249#define TPPoll_BQ BIT4
250#define TPPoll_CQ BIT5
251#define TPPoll_MQ BIT6
252#define TPPoll_HQ BIT7
253#define TPPoll_HCCAQ BIT8
254#define TPPoll_StopBK BIT9
255#define TPPoll_StopBE BIT10
256#define TPPoll_StopVI BIT11
257#define TPPoll_StopVO BIT12
258#define TPPoll_StopMgt BIT13
259#define TPPoll_StopHigh BIT14
260#define TPPoll_StopHCCA BIT15
261#define TPPoll_SHIFT 8
262
263 PSR = 0x0ff,
264#define PSR_GEN 0x0
265#define PSR_CPU 0x1
266 CPU_GEN = 0x100,
267 BB_RESET = 0x101,
268#define CPU_CCK_LOOPBACK 0x00030000
269#define CPU_GEN_SYSTEM_RESET 0x00000001
270#define CPU_GEN_FIRMWARE_RESET 0x00000008
271#define CPU_GEN_BOOT_RDY 0x00000010
272#define CPU_GEN_FIRM_RDY 0x00000020
273#define CPU_GEN_PUT_CODE_OK 0x00000080
274#define CPU_GEN_BB_RST 0x00000100
275#define CPU_GEN_PWR_STB_CPU 0x00000004
276#define CPU_GEN_NO_LOOPBACK_MSK 0xFFF8FFFF
277#define CPU_GEN_NO_LOOPBACK_SET 0x00080000
278#define CPU_GEN_GPIO_UART 0x00007000
279
280 LED1Cfg = 0x154,
281 LED0Cfg = 0x155,
282
283 AcmAvg = 0x170,
284 AcmHwCtrl = 0x171,
285#define AcmHw_HwEn BIT0
286#define AcmHw_BeqEn BIT1
287#define AcmHw_ViqEn BIT2
288#define AcmHw_VoqEn BIT3
289#define AcmHw_BeqStatus BIT4
290#define AcmHw_ViqStatus BIT5
291#define AcmHw_VoqStatus BIT6
292 AcmFwCtrl = 0x172,
293#define AcmFw_BeqStatus BIT0
294#define AcmFw_ViqStatus BIT1
295#define AcmFw_VoqStatus BIT2
296 VOAdmTime = 0x174,
297 VIAdmTime = 0x178,
298 BEAdmTime = 0x17C,
299 RQPN1 = 0x180,
300 RQPN2 = 0x184,
301 RQPN3 = 0x188,
302 QPRR = 0x1E0,
303 QPNR = 0x1F0,
304 BQDA = 0x200,
305 HQDA = 0x204,
306 CQDA = 0x208,
307 MQDA = 0x20C,
308 HCCAQDA = 0x210,
309 VOQDA = 0x214,
310 VIQDA = 0x218,
311 BEQDA = 0x21C,
312 BKQDA = 0x220,
313 RCQDA = 0x224,
314 RDQDA = 0x228,
315
316 MAR0 = 0x240,
317 MAR4 = 0x244,
318
319 CCX_PERIOD = 0x250,
320 CLM_RESULT = 0x251,
321 NHM_PERIOD = 0x252,
322
323 NHM_THRESHOLD0 = 0x253,
324 NHM_THRESHOLD1 = 0x254,
325 NHM_THRESHOLD2 = 0x255,
326 NHM_THRESHOLD3 = 0x256,
327 NHM_THRESHOLD4 = 0x257,
328 NHM_THRESHOLD5 = 0x258,
329 NHM_THRESHOLD6 = 0x259,
330
331 MCTRL = 0x25A,
332
333 NHM_RPI_COUNTER0 = 0x264,
334 NHM_RPI_COUNTER1 = 0x265,
335 NHM_RPI_COUNTER2 = 0x266,
336 NHM_RPI_COUNTER3 = 0x267,
337 NHM_RPI_COUNTER4 = 0x268,
338 NHM_RPI_COUNTER5 = 0x269,
339 NHM_RPI_COUNTER6 = 0x26A,
340 NHM_RPI_COUNTER7 = 0x26B,
341 WFCRC0 = 0x2f0,
342 WFCRC1 = 0x2f4,
343 WFCRC2 = 0x2f8,
344
345 BW_OPMODE = 0x300,
346#define BW_OPMODE_11J BIT0
347#define BW_OPMODE_5G BIT1
348#define BW_OPMODE_20MHZ BIT2
349 IC_VERRSION = 0x301,
350 MSR = 0x303,
351#define MSR_LINK_MASK ((1<<0)|(1<<1))
352#define MSR_LINK_MANAGED 2
353#define MSR_LINK_NONE 0
354#define MSR_LINK_SHIFT 0
355#define MSR_LINK_ADHOC 1
356#define MSR_LINK_MASTER 3
357#define MSR_LINK_ENEDCA (1<<4)
358
359#define MSR_NOLINK 0x00
360#define MSR_ADHOC 0x01
361#define MSR_INFRA 0x02
362#define MSR_AP 0x03
363
364 RETRY_LIMIT = 0x304,
365#define RETRY_LIMIT_SHORT_SHIFT 8
366#define RETRY_LIMIT_LONG_SHIFT 0
367 TSFR = 0x308,
368 RRSR = 0x310,
369#define RRSR_RSC_OFFSET 21
370#define RRSR_SHORT_OFFSET 23
371#define RRSR_RSC_DUPLICATE 0x600000
372#define RRSR_RSC_UPSUBCHNL 0x400000
373#define RRSR_RSC_LOWSUBCHNL 0x200000
374#define RRSR_SHORT 0x800000
375#define RRSR_1M BIT0
376#define RRSR_2M BIT1
377#define RRSR_5_5M BIT2
378#define RRSR_11M BIT3
379#define RRSR_6M BIT4
380#define RRSR_9M BIT5
381#define RRSR_12M BIT6
382#define RRSR_18M BIT7
383#define RRSR_24M BIT8
384#define RRSR_36M BIT9
385#define RRSR_48M BIT10
386#define RRSR_54M BIT11
387#define RRSR_MCS0 BIT12
388#define RRSR_MCS1 BIT13
389#define RRSR_MCS2 BIT14
390#define RRSR_MCS3 BIT15
391#define RRSR_MCS4 BIT16
392#define RRSR_MCS5 BIT17
393#define RRSR_MCS6 BIT18
394#define RRSR_MCS7 BIT19
395#define BRSR_AckShortPmb BIT23
396 UFWP = 0x318,
397 RATR0 = 0x320,
398#define RATR_1M 0x00000001
399#define RATR_2M 0x00000002
400#define RATR_55M 0x00000004
401#define RATR_11M 0x00000008
402#define RATR_6M 0x00000010
403#define RATR_9M 0x00000020
404#define RATR_12M 0x00000040
405#define RATR_18M 0x00000080
406#define RATR_24M 0x00000100
407#define RATR_36M 0x00000200
408#define RATR_48M 0x00000400
409#define RATR_54M 0x00000800
410#define RATR_MCS0 0x00001000
411#define RATR_MCS1 0x00002000
412#define RATR_MCS2 0x00004000
413#define RATR_MCS3 0x00008000
414#define RATR_MCS4 0x00010000
415#define RATR_MCS5 0x00020000
416#define RATR_MCS6 0x00040000
417#define RATR_MCS7 0x00080000
418#define RATR_MCS8 0x00100000
419#define RATR_MCS9 0x00200000
420#define RATR_MCS10 0x00400000
421#define RATR_MCS11 0x00800000
422#define RATR_MCS12 0x01000000
423#define RATR_MCS13 0x02000000
424#define RATR_MCS14 0x04000000
425#define RATR_MCS15 0x08000000
426#define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M)
427#define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | RATR_18M | \
428 RATR_24M | RATR_36M | RATR_48M | RATR_54M)
429#define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 | \
430 RATR_MCS3 | RATR_MCS4 | RATR_MCS5 | \
431 RATR_MCS6 | RATR_MCS7)
432#define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 | \
433 RATR_MCS11 | RATR_MCS12 | RATR_MCS13 | \
434 RATR_MCS14|RATR_MCS15)
435
436
437 DRIVER_RSSI = 0x32c,
438 MCS_TXAGC = 0x340,
439 CCK_TXAGC = 0x348,
440 MacBlkCtrl = 0x403,
441
442}
443;
444
445#define GPI 0x108
446#define GPO 0x109
447#define GPE 0x10a
448
449#define HWSET_MAX_SIZE_92S 128
450
451#define ANAPAR_FOR_8192PciE 0x17
452
453#endif
454
