1/* 2 saa7115.h - definition for saa7111/3/4/5 inputs and frequency flags 3 4 Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl) 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 2 of the License, or 9 (at your option) any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19*/ 20 21#ifndef _SAA7115_H_ 22#define _SAA7115_H_ 23 24/* s_routing inputs, outputs, and config */ 25 26/* SAA7111/3/4/5 HW inputs */ 27#define SAA7115_COMPOSITE0 0 28#define SAA7115_COMPOSITE1 1 29#define SAA7115_COMPOSITE2 2 30#define SAA7115_COMPOSITE3 3 31#define SAA7115_COMPOSITE4 4 /* not available for the saa7111/3 */ 32#define SAA7115_COMPOSITE5 5 /* not available for the saa7111/3 */ 33#define SAA7115_SVIDEO0 6 34#define SAA7115_SVIDEO1 7 35#define SAA7115_SVIDEO2 8 36#define SAA7115_SVIDEO3 9 37 38/* outputs */ 39#define SAA7115_IPORT_ON 1 40#define SAA7115_IPORT_OFF 0 41 42/* SAA7111 specific outputs. */ 43#define SAA7111_VBI_BYPASS 2 44#define SAA7111_FMT_YUV422 0x00 45#define SAA7111_FMT_RGB 0x40 46#define SAA7111_FMT_CCIR 0x80 47#define SAA7111_FMT_YUV411 0xc0 48 49/* config flags */ 50/* 51 * Register 0x85 should set bit 0 to 0 (it's 1 by default). This bit 52 * controls the IDQ signal polarity which is set to 'inverted' if the bit 53 * it 1 and to 'default' if it is 0. 54 */ 55#define SAA7115_IDQ_IS_DEFAULT (1 << 0) 56 57/* s_crystal_freq values and flags */ 58 59/* SAA7115 v4l2_crystal_freq frequency values */ 60#define SAA7115_FREQ_32_11_MHZ 32110000 /* 32.11 MHz crystal, SAA7114/5 only */ 61#define SAA7115_FREQ_24_576_MHZ 24576000 /* 24.576 MHz crystal */ 62 63/* SAA7115 v4l2_crystal_freq audio clock control flags */ 64#define SAA7115_FREQ_FL_UCGC (1 << 0) /* SA 3A[7], UCGC, SAA7115 only */ 65#define SAA7115_FREQ_FL_CGCDIV (1 << 1) /* SA 3A[6], CGCDIV, SAA7115 only */ 66#define SAA7115_FREQ_FL_APLL (1 << 2) /* SA 3A[3], APLL, SAA7114/5 only */ 67#define SAA7115_FREQ_FL_DOUBLE_ASCLK (1 << 3) /* SA 39, LRDIV, SAA7114/5 only */ 68 69/* ===== SAA7113 Config enums ===== */ 70 71/* Register 0x08 "Horizontal time constant" [Bit 3..4]: 72 * Should be set to "Fast Locking Mode" according to the datasheet, 73 * and that is the default setting in the gm7113c_init table. 74 * saa7113_init sets this value to "VTR Mode". */ 75enum saa7113_r08_htc { 76 SAA7113_HTC_TV_MODE = 0x00, 77 SAA7113_HTC_VTR_MODE, /* Default for saa7113_init */ 78 SAA7113_HTC_FAST_LOCKING_MODE = 0x03 /* Default for gm7113c_init */ 79}; 80 81/* Register 0x10 "Output format selection" [Bit 6..7]: 82 * Defaults to ITU_656 as specified in datasheet. */ 83enum saa7113_r10_ofts { 84 SAA7113_OFTS_ITU_656 = 0x0, /* Default */ 85 SAA7113_OFTS_VFLAG_BY_VREF, 86 SAA7113_OFTS_VFLAG_BY_DATA_TYPE 87}; 88 89/* 90 * Register 0x12 "Output control" [Bit 0..3 Or Bit 4..7]: 91 * This is used to select what data is output on the RTS0 and RTS1 pins. 92 * RTS1 [Bit 4..7] Defaults to DOT_IN. (This value can not be set for RTS0) 93 * RTS0 [Bit 0..3] Defaults to VIPB in gm7113c_init as specified 94 * in the datasheet, but is set to HREF_HS in the saa7113_init table. 95 */ 96enum saa7113_r12_rts { 97 SAA7113_RTS_DOT_IN = 0, /* OBS: Only for RTS1 (Default RTS1) */ 98 SAA7113_RTS_VIPB, /* Default RTS0 For gm7113c_init */ 99 SAA7113_RTS_GPSW, 100 SAA7115_RTS_HL, 101 SAA7113_RTS_VL, 102 SAA7113_RTS_DL, 103 SAA7113_RTS_PLIN, 104 SAA7113_RTS_HREF_HS, /* Default RTS0 For saa7113_init */ 105 SAA7113_RTS_HS, 106 SAA7113_RTS_HQ, 107 SAA7113_RTS_ODD, 108 SAA7113_RTS_VS, 109 SAA7113_RTS_V123, 110 SAA7113_RTS_VGATE, 111 SAA7113_RTS_VREF, 112 SAA7113_RTS_FID 113}; 114 115/** 116 * struct saa7115_platform_data - Allow overriding default initialization 117 * 118 * @saa7113_force_gm7113c_init: Force the use of the gm7113c_init table 119 * instead of saa7113_init table 120 * (saa7113 only) 121 * @saa7113_r08_htc: [R_08 - Bit 3..4] 122 * @saa7113_r10_vrln: [R_10 - Bit 3] 123 * default: Disabled for gm7113c_init 124 * Enabled for saa7113c_init 125 * @saa7113_r10_ofts: [R_10 - Bit 6..7] 126 * @saa7113_r12_rts0: [R_12 - Bit 0..3] 127 * @saa7113_r12_rts1: [R_12 - Bit 4..7] 128 * @saa7113_r13_adlsb: [R_13 - Bit 7] - default: disabled 129 */ 130struct saa7115_platform_data { 131 bool saa7113_force_gm7113c_init; 132 enum saa7113_r08_htc *saa7113_r08_htc; 133 bool *saa7113_r10_vrln; 134 enum saa7113_r10_ofts *saa7113_r10_ofts; 135 enum saa7113_r12_rts *saa7113_r12_rts0; 136 enum saa7113_r12_rts *saa7113_r12_rts1; 137 bool *saa7113_r13_adlsb; 138}; 139 140#endif 141 142