LXR linux/arch/cris/include/arch-v32/mach-fs/mach/hwregs/marb

   1#ifndef __marb_defs_h
   2#define __marb_defs_h
   3
   4/*
   5 * This file is autogenerated from
   6 *   file:           ../../inst/memarb/rtl/guinness/marb_top.r
   7 *     id:           <not found>
   8 *     last modfied: Mon Apr 11 16:12:16 2005
   9 * 
  10 *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r
  11 *      id: $Id: marb_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
  12 * Any changes here will be lost.
  13 *
  14 * -*- buffer-read-only: t -*-
  15 */
  16/* Main access macros */
  17#ifndef REG_RD
  18#define REG_RD( scope, inst, reg ) \
  19  REG_READ( reg_##scope##_##reg, \
  20            (inst) + REG_RD_ADDR_##scope##_##reg )
  21#endif
  22
  23#ifndef REG_WR
  24#define REG_WR( scope, inst, reg, val ) \
  25  REG_WRITE( reg_##scope##_##reg, \
  26             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  27#endif
  28
  29#ifndef REG_RD_VECT
  30#define REG_RD_VECT( scope, inst, reg, index ) \
  31  REG_READ( reg_##scope##_##reg, \
  32            (inst) + REG_RD_ADDR_##scope##_##reg + \
  33            (index) * STRIDE_##scope##_##reg )
  34#endif
  35
  36#ifndef REG_WR_VECT
  37#define REG_WR_VECT( scope, inst, reg, index, val ) \
  38  REG_WRITE( reg_##scope##_##reg, \
  39             (inst) + REG_WR_ADDR_##scope##_##reg + \
  40             (index) * STRIDE_##scope##_##reg, (val) )
  41#endif
  42
  43#ifndef REG_RD_INT
  44#define REG_RD_INT( scope, inst, reg ) \
  45  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
  46#endif
  47
  48#ifndef REG_WR_INT
  49#define REG_WR_INT( scope, inst, reg, val ) \
  50  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  51#endif
  52
  53#ifndef REG_RD_INT_VECT
  54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
  55  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
  56            (index) * STRIDE_##scope##_##reg )
  57#endif
  58
  59#ifndef REG_WR_INT_VECT
  60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
  61  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
  62             (index) * STRIDE_##scope##_##reg, (val) )
  63#endif
  64
  65#ifndef REG_TYPE_CONV
  66#define REG_TYPE_CONV( type, orgtype, val ) \
  67  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
  68#endif
  69
  70#ifndef reg_page_size
  71#define reg_page_size 8192
  72#endif
  73
  74#ifndef REG_ADDR
  75#define REG_ADDR( scope, inst, reg ) \
  76  ( (inst) + REG_RD_ADDR_##scope##_##reg )
  77#endif
  78
  79#ifndef REG_ADDR_VECT
  80#define REG_ADDR_VECT( scope, inst, reg, index ) \
  81  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
  82    (index) * STRIDE_##scope##_##reg )
  83#endif
  84
  85/* C-code for register scope marb */
  86
  87#define STRIDE_marb_rw_int_slots 4
  88/* Register rw_int_slots, scope marb, type rw */
  89typedef struct {
  90  unsigned int owner : 4;
  91  unsigned int dummy1 : 28;
  92} reg_marb_rw_int_slots;
  93#define REG_RD_ADDR_marb_rw_int_slots 0
  94#define REG_WR_ADDR_marb_rw_int_slots 0
  95
  96#define STRIDE_marb_rw_ext_slots 4
  97/* Register rw_ext_slots, scope marb, type rw */
  98typedef struct {
  99  unsigned int owner : 4;
 100  unsigned int dummy1 : 28;
 101} reg_marb_rw_ext_slots;
 102#define REG_RD_ADDR_marb_rw_ext_slots 256
 103#define REG_WR_ADDR_marb_rw_ext_slots 256
 104
 105#define STRIDE_marb_rw_regs_slots 4
 106/* Register rw_regs_slots, scope marb, type rw */
 107typedef struct {
 108  unsigned int owner : 4;
 109  unsigned int dummy1 : 28;
 110} reg_marb_rw_regs_slots;
 111#define REG_RD_ADDR_marb_rw_regs_slots 512
 112#define REG_WR_ADDR_marb_rw_regs_slots 512
 113
 114/* Register rw_intr_mask, scope marb, type rw */
 115typedef struct {
 116  unsigned int bp0 : 1;
 117  unsigned int bp1 : 1;
 118  unsigned int bp2 : 1;
 119  unsigned int bp3 : 1;
 120  unsigned int dummy1 : 28;
 121} reg_marb_rw_intr_mask;
 122#define REG_RD_ADDR_marb_rw_intr_mask 528
 123#define REG_WR_ADDR_marb_rw_intr_mask 528
 124
 125/* Register rw_ack_intr, scope marb, type rw */
 126typedef struct {
 127  unsigned int bp0 : 1;
 128  unsigned int bp1 : 1;
 129  unsigned int bp2 : 1;
 130  unsigned int bp3 : 1;
 131  unsigned int dummy1 : 28;
 132} reg_marb_rw_ack_intr;
 133#define REG_RD_ADDR_marb_rw_ack_intr 532
 134#define REG_WR_ADDR_marb_rw_ack_intr 532
 135
 136/* Register r_intr, scope marb, type r */
 137typedef struct {
 138  unsigned int bp0 : 1;
 139  unsigned int bp1 : 1;
 140  unsigned int bp2 : 1;
 141  unsigned int bp3 : 1;
 142  unsigned int dummy1 : 28;
 143} reg_marb_r_intr;
 144#define REG_RD_ADDR_marb_r_intr 536
 145
 146/* Register r_masked_intr, scope marb, type r */
 147typedef struct {
 148  unsigned int bp0 : 1;
 149  unsigned int bp1 : 1;
 150  unsigned int bp2 : 1;
 151  unsigned int bp3 : 1;
 152  unsigned int dummy1 : 28;
 153} reg_marb_r_masked_intr;
 154#define REG_RD_ADDR_marb_r_masked_intr 540
 155
 156/* Register rw_stop_mask, scope marb, type rw */
 157typedef struct {
 158  unsigned int dma0  : 1;
 159  unsigned int dma1  : 1;
 160  unsigned int dma2  : 1;
 161  unsigned int dma3  : 1;
 162  unsigned int dma4  : 1;
 163  unsigned int dma5  : 1;
 164  unsigned int dma6  : 1;
 165  unsigned int dma7  : 1;
 166  unsigned int dma8  : 1;
 167  unsigned int dma9  : 1;
 168  unsigned int cpui  : 1;
 169  unsigned int cpud  : 1;
 170  unsigned int iop   : 1;
 171  unsigned int slave : 1;
 172  unsigned int dummy1 : 18;
 173} reg_marb_rw_stop_mask;
 174#define REG_RD_ADDR_marb_rw_stop_mask 544
 175#define REG_WR_ADDR_marb_rw_stop_mask 544
 176
 177/* Register r_stopped, scope marb, type r */
 178typedef struct {
 179  unsigned int dma0  : 1;
 180  unsigned int dma1  : 1;
 181  unsigned int dma2  : 1;
 182  unsigned int dma3  : 1;
 183  unsigned int dma4  : 1;
 184  unsigned int dma5  : 1;
 185  unsigned int dma6  : 1;
 186  unsigned int dma7  : 1;
 187  unsigned int dma8  : 1;
 188  unsigned int dma9  : 1;
 189  unsigned int cpui  : 1;
 190  unsigned int cpud  : 1;
 191  unsigned int iop   : 1;
 192  unsigned int slave : 1;
 193  unsigned int dummy1 : 18;
 194} reg_marb_r_stopped;
 195#define REG_RD_ADDR_marb_r_stopped 548
 196
 197/* Register rw_no_snoop, scope marb, type rw */
 198typedef struct {
 199  unsigned int dma0  : 1;
 200  unsigned int dma1  : 1;
 201  unsigned int dma2  : 1;
 202  unsigned int dma3  : 1;
 203  unsigned int dma4  : 1;
 204  unsigned int dma5  : 1;
 205  unsigned int dma6  : 1;
 206  unsigned int dma7  : 1;
 207  unsigned int dma8  : 1;
 208  unsigned int dma9  : 1;
 209  unsigned int cpui  : 1;
 210  unsigned int cpud  : 1;
 211  unsigned int iop   : 1;
 212  unsigned int slave : 1;
 213  unsigned int dummy1 : 18;
 214} reg_marb_rw_no_snoop;
 215#define REG_RD_ADDR_marb_rw_no_snoop 832
 216#define REG_WR_ADDR_marb_rw_no_snoop 832
 217
 218/* Register rw_no_snoop_rq, scope marb, type rw */
 219typedef struct {
 220  unsigned int dummy1 : 10;
 221  unsigned int cpui : 1;
 222  unsigned int cpud : 1;
 223  unsigned int dummy2 : 20;
 224} reg_marb_rw_no_snoop_rq;
 225#define REG_RD_ADDR_marb_rw_no_snoop_rq 836
 226#define REG_WR_ADDR_marb_rw_no_snoop_rq 836
 227
 228
 229/* Constants */
 230enum {
 231  regk_marb_cpud                           = 0x0000000b,
 232  regk_marb_cpui                           = 0x0000000a,
 233  regk_marb_dma0                           = 0x00000000,
 234  regk_marb_dma1                           = 0x00000001,
 235  regk_marb_dma2                           = 0x00000002,
 236  regk_marb_dma3                           = 0x00000003,
 237  regk_marb_dma4                           = 0x00000004,
 238  regk_marb_dma5                           = 0x00000005,
 239  regk_marb_dma6                           = 0x00000006,
 240  regk_marb_dma7                           = 0x00000007,
 241  regk_marb_dma8                           = 0x00000008,
 242  regk_marb_dma9                           = 0x00000009,
 243  regk_marb_iop                            = 0x0000000c,
 244  regk_marb_no                             = 0x00000000,
 245  regk_marb_r_stopped_default              = 0x00000000,
 246  regk_marb_rw_ext_slots_default           = 0x00000000,
 247  regk_marb_rw_ext_slots_size              = 0x00000040,
 248  regk_marb_rw_int_slots_default           = 0x00000000,
 249  regk_marb_rw_int_slots_size              = 0x00000040,
 250  regk_marb_rw_intr_mask_default           = 0x00000000,
 251  regk_marb_rw_no_snoop_default            = 0x00000000,
 252  regk_marb_rw_no_snoop_rq_default         = 0x00000000,
 253  regk_marb_rw_regs_slots_default          = 0x00000000,
 254  regk_marb_rw_regs_slots_size             = 0x00000004,
 255  regk_marb_rw_stop_mask_default           = 0x00000000,
 256  regk_marb_slave                          = 0x0000000d,
 257  regk_marb_yes                            = 0x00000001
 258};
 259#endif /* __marb_defs_h */
 260#ifndef __marb_bp_defs_h
 261#define __marb_bp_defs_h
 262
 263/*
 264 * This file is autogenerated from
 265 *   file:           ../../inst/memarb/rtl/guinness/marb_top.r
 266 *     id:           <not found>
 267 *     last modfied: Mon Apr 11 16:12:16 2005
 268 * 
 269 *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r
 270 *      id: $Id: marb_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
 271 * Any changes here will be lost.
 272 *
 273 * -*- buffer-read-only: t -*-
 274 */
 275/* Main access macros */
 276#ifndef REG_RD
 277#define REG_RD( scope, inst, reg ) \
 278  REG_READ( reg_##scope##_##reg, \
 279            (inst) + REG_RD_ADDR_##scope##_##reg )
 280#endif
 281
 282#ifndef REG_WR
 283#define REG_WR( scope, inst, reg, val ) \
 284  REG_WRITE( reg_##scope##_##reg, \
 285             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
 286#endif
 287
 288#ifndef REG_RD_VECT
 289#define REG_RD_VECT( scope, inst, reg, index ) \
 290  REG_READ( reg_##scope##_##reg, \
 291            (inst) + REG_RD_ADDR_##scope##_##reg + \
 292            (index) * STRIDE_##scope##_##reg )
 293#endif
 294
 295#ifndef REG_WR_VECT
 296#define REG_WR_VECT( scope, inst, reg, index, val ) \
 297  REG_WRITE( reg_##scope##_##reg, \
 298             (inst) + REG_WR_ADDR_##scope##_##reg + \
 299             (index) * STRIDE_##scope##_##reg, (val) )
 300#endif
 301
 302#ifndef REG_RD_INT
 303#define REG_RD_INT( scope, inst, reg ) \
 304  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
 305#endif
 306
 307#ifndef REG_WR_INT
 308#define REG_WR_INT( scope, inst, reg, val ) \
 309  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
 310#endif
 311
 312#ifndef REG_RD_INT_VECT
 313#define REG_RD_INT_VECT( scope, inst, reg, index ) \
 314  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
 315            (index) * STRIDE_##scope##_##reg )
 316#endif
 317
 318#ifndef REG_WR_INT_VECT
 319#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
 320  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
 321             (index) * STRIDE_##scope##_##reg, (val) )
 322#endif
 323
 324#ifndef REG_TYPE_CONV
 325#define REG_TYPE_CONV( type, orgtype, val ) \
 326  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
 327#endif
 328
 329#ifndef reg_page_size
 330#define reg_page_size 8192
 331#endif
 332
 333#ifndef REG_ADDR
 334#define REG_ADDR( scope, inst, reg ) \
 335  ( (inst) + REG_RD_ADDR_##scope##_##reg )
 336#endif
 337
 338#ifndef REG_ADDR_VECT
 339#define REG_ADDR_VECT( scope, inst, reg, index ) \
 340  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
 341    (index) * STRIDE_##scope##_##reg )
 342#endif
 343
 344/* C-code for register scope marb_bp */
 345
 346/* Register rw_first_addr, scope marb_bp, type rw */
 347typedef unsigned int reg_marb_bp_rw_first_addr;
 348#define REG_RD_ADDR_marb_bp_rw_first_addr 0
 349#define REG_WR_ADDR_marb_bp_rw_first_addr 0
 350
 351/* Register rw_last_addr, scope marb_bp, type rw */
 352typedef unsigned int reg_marb_bp_rw_last_addr;
 353#define REG_RD_ADDR_marb_bp_rw_last_addr 4
 354#define REG_WR_ADDR_marb_bp_rw_last_addr 4
 355
 356/* Register rw_op, scope marb_bp, type rw */
 357typedef struct {
 358  unsigned int rd         : 1;
 359  unsigned int wr         : 1;
 360  unsigned int rd_excl    : 1;
 361  unsigned int pri_wr     : 1;
 362  unsigned int us_rd      : 1;
 363  unsigned int us_wr      : 1;
 364  unsigned int us_rd_excl : 1;
 365  unsigned int us_pri_wr  : 1;
 366  unsigned int dummy1     : 24;
 367} reg_marb_bp_rw_op;
 368#define REG_RD_ADDR_marb_bp_rw_op 8
 369#define REG_WR_ADDR_marb_bp_rw_op 8
 370
 371/* Register rw_clients, scope marb_bp, type rw */
 372typedef struct {
 373  unsigned int dma0  : 1;
 374  unsigned int dma1  : 1;
 375  unsigned int dma2  : 1;
 376  unsigned int dma3  : 1;
 377  unsigned int dma4  : 1;
 378  unsigned int dma5  : 1;
 379  unsigned int dma6  : 1;
 380  unsigned int dma7  : 1;
 381  unsigned int dma8  : 1;
 382  unsigned int dma9  : 1;
 383  unsigned int cpui  : 1;
 384  unsigned int cpud  : 1;
 385  unsigned int iop   : 1;
 386  unsigned int slave : 1;
 387  unsigned int dummy1 : 18;
 388} reg_marb_bp_rw_clients;
 389#define REG_RD_ADDR_marb_bp_rw_clients 12
 390#define REG_WR_ADDR_marb_bp_rw_clients 12
 391
 392/* Register rw_options, scope marb_bp, type rw */
 393typedef struct {
 394  unsigned int wrap : 1;
 395  unsigned int dummy1 : 31;
 396} reg_marb_bp_rw_options;
 397#define REG_RD_ADDR_marb_bp_rw_options 16
 398#define REG_WR_ADDR_marb_bp_rw_options 16
 399
 400/* Register r_brk_addr, scope marb_bp, type r */
 401typedef unsigned int reg_marb_bp_r_brk_addr;
 402#define REG_RD_ADDR_marb_bp_r_brk_addr 20
 403
 404/* Register r_brk_op, scope marb_bp, type r */
 405typedef struct {
 406  unsigned int rd         : 1;
 407  unsigned int wr         : 1;
 408  unsigned int rd_excl    : 1;
 409  unsigned int pri_wr     : 1;
 410  unsigned int us_rd      : 1;
 411  unsigned int us_wr      : 1;
 412  unsigned int us_rd_excl : 1;
 413  unsigned int us_pri_wr  : 1;
 414  unsigned int dummy1     : 24;
 415} reg_marb_bp_r_brk_op;
 416#define REG_RD_ADDR_marb_bp_r_brk_op 24
 417
 418/* Register r_brk_clients, scope marb_bp, type r */
 419typedef struct {
 420  unsigned int dma0  : 1;
 421  unsigned int dma1  : 1;
 422  unsigned int dma2  : 1;
 423  unsigned int dma3  : 1;
 424  unsigned int dma4  : 1;
 425  unsigned int dma5  : 1;
 426  unsigned int dma6  : 1;
 427  unsigned int dma7  : 1;
 428  unsigned int dma8  : 1;
 429  unsigned int dma9  : 1;
 430  unsigned int cpui  : 1;
 431  unsigned int cpud  : 1;
 432  unsigned int iop   : 1;
 433  unsigned int slave : 1;
 434  unsigned int dummy1 : 18;
 435} reg_marb_bp_r_brk_clients;
 436#define REG_RD_ADDR_marb_bp_r_brk_clients 28
 437
 438/* Register r_brk_first_client, scope marb_bp, type r */
 439typedef struct {
 440  unsigned int dma0  : 1;
 441  unsigned int dma1  : 1;
 442  unsigned int dma2  : 1;
 443  unsigned int dma3  : 1;
 444  unsigned int dma4  : 1;
 445  unsigned int dma5  : 1;
 446  unsigned int dma6  : 1;
 447  unsigned int dma7  : 1;
 448  unsigned int dma8  : 1;
 449  unsigned int dma9  : 1;
 450  unsigned int cpui  : 1;
 451  unsigned int cpud  : 1;
 452  unsigned int iop   : 1;
 453  unsigned int slave : 1;
 454  unsigned int dummy1 : 18;
 455} reg_marb_bp_r_brk_first_client;
 456#define REG_RD_ADDR_marb_bp_r_brk_first_client 32
 457
 458/* Register r_brk_size, scope marb_bp, type r */
 459typedef unsigned int reg_marb_bp_r_brk_size;
 460#define REG_RD_ADDR_marb_bp_r_brk_size 36
 461
 462/* Register rw_ack, scope marb_bp, type rw */
 463typedef unsigned int reg_marb_bp_rw_ack;
 464#define REG_RD_ADDR_marb_bp_rw_ack 40
 465#define REG_WR_ADDR_marb_bp_rw_ack 40
 466
 467
 468/* Constants */
 469enum {
 470  regk_marb_bp_no                          = 0x00000000,
 471  regk_marb_bp_rw_op_default               = 0x00000000,
 472  regk_marb_bp_rw_options_default          = 0x00000000,
 473  regk_marb_bp_yes                         = 0x00000001
 474};
 475#endif /* __marb_bp_defs_h */
 476