LXR linux/arch/mips/txx9/generic/pci.c

   1/*
   2 * linux/arch/mips/txx9/pci.c
   3 *
   4 * Based on linux/arch/mips/txx9/rbtx4927/setup.c,
   5 *          linux/arch/mips/txx9/rbtx4938/setup.c,
   6 *          and RBTX49xx patch from CELF patch archive.
   7 *
   8 * Copyright 2001-2005 MontaVista Software Inc.
   9 * Copyright (C) 1996, 97, 2001, 04  Ralf Baechle (ralf@linux-mips.org)
  10 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
  11 *
  12 * This file is subject to the terms and conditions of the GNU General Public
  13 * License.  See the file "COPYING" in the main directory of this archive
  14 * for more details.
  15 */
  16#include <linux/delay.h>
  17#include <linux/jiffies.h>
  18#include <linux/io.h>
  19#include <asm/txx9/generic.h>
  20#include <asm/txx9/pci.h>
  21#ifdef CONFIG_TOSHIBA_FPCIB0
  22#include <linux/interrupt.h>
  23#include <linux/slab.h>
  24#include <asm/i8259.h>
  25#include <asm/txx9/smsc_fdc37m81x.h>
  26#endif
  27
  28static int __init
  29early_read_config_word(struct pci_controller *hose,
  30                       int top_bus, int bus, int devfn, int offset, u16 *value)
  31{
  32        struct pci_dev fake_dev;
  33        struct pci_bus fake_bus;
  34
  35        fake_dev.bus = &fake_bus;
  36        fake_dev.sysdata = hose;
  37        fake_dev.devfn = devfn;
  38        fake_bus.number = bus;
  39        fake_bus.sysdata = hose;
  40        fake_bus.ops = hose->pci_ops;
  41
  42        if (bus != top_bus)
  43                /* Fake a parent bus structure. */
  44                fake_bus.parent = &fake_bus;
  45        else
  46                fake_bus.parent = NULL;
  47
  48        return pci_read_config_word(&fake_dev, offset, value);
  49}
  50
  51int __init txx9_pci66_check(struct pci_controller *hose, int top_bus,
  52                            int current_bus)
  53{
  54        u32 pci_devfn;
  55        unsigned short vid;
  56        int cap66 = -1;
  57        u16 stat;
  58
  59        /* It seems SLC90E66 needs some time after PCI reset... */
  60        mdelay(80);
  61
  62        printk(KERN_INFO "PCI: Checking 66MHz capabilities...\n");
  63
  64        for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) {
  65                if (PCI_FUNC(pci_devfn))
  66                        continue;
  67                if (early_read_config_word(hose, top_bus, current_bus,
  68                                           pci_devfn, PCI_VENDOR_ID, &vid) !=
  69                    PCIBIOS_SUCCESSFUL)
  70                        continue;
  71                if (vid == 0xffff)
  72                        continue;
  73
  74                /* check 66MHz capability */
  75                if (cap66 < 0)
  76                        cap66 = 1;
  77                if (cap66) {
  78                        early_read_config_word(hose, top_bus, current_bus,
  79                                               pci_devfn, PCI_STATUS, &stat);
  80                        if (!(stat & PCI_STATUS_66MHZ)) {
  81                                printk(KERN_DEBUG
  82                                       "PCI: %02x:%02x not 66MHz capable.\n",
  83                                       current_bus, pci_devfn);
  84                                cap66 = 0;
  85                                break;
  86                        }
  87                }
  88        }
  89        return cap66 > 0;
  90}
  91
  92static struct resource primary_pci_mem_res[2] = {
  93        { .name = "PCI MEM" },
  94        { .name = "PCI MMIO" },
  95};
  96static struct resource primary_pci_io_res = { .name = "PCI IO" };
  97struct pci_controller txx9_primary_pcic = {
  98        .mem_resource = &primary_pci_mem_res[0],
  99        .io_resource = &primary_pci_io_res,
 100};
 101
 102#ifdef CONFIG_64BIT
 103int txx9_pci_mem_high __initdata = 1;
 104#else
 105int txx9_pci_mem_high __initdata;
 106#endif
 107
 108/*
 109 * allocate pci_controller and resources.
 110 * mem_base, io_base: physical address.  0 for auto assignment.
 111 * mem_size and io_size means max size on auto assignment.
 112 * pcic must be &txx9_primary_pcic or NULL.
 113 */
 114struct pci_controller *__init
 115txx9_alloc_pci_controller(struct pci_controller *pcic,
 116                          unsigned long mem_base, unsigned long mem_size,
 117                          unsigned long io_base, unsigned long io_size)
 118{
 119        struct pcic {
 120                struct pci_controller c;
 121                struct resource r_mem[2];
 122                struct resource r_io;
 123        } *new = NULL;
 124        int min_size = 0x10000;
 125
 126        if (!pcic) {
 127                new = kzalloc(sizeof(*new), GFP_KERNEL);
 128                if (!new)
 129                        return NULL;
 130                new->r_mem[0].name = "PCI mem";
 131                new->r_mem[1].name = "PCI mmio";
 132                new->r_io.name = "PCI io";
 133                new->c.mem_resource = new->r_mem;
 134                new->c.io_resource = &new->r_io;
 135                pcic = &new->c;
 136        } else
 137                BUG_ON(pcic != &txx9_primary_pcic);
 138        pcic->io_resource->flags = IORESOURCE_IO;
 139
 140        /*
 141         * for auto assignment, first search a (big) region for PCI
 142         * MEM, then search a region for PCI IO.
 143         */
 144        if (mem_base) {
 145                pcic->mem_resource[0].start = mem_base;
 146                pcic->mem_resource[0].end = mem_base + mem_size - 1;
 147                if (request_resource(&iomem_resource, &pcic->mem_resource[0]))
 148                        goto free_and_exit;
 149        } else {
 150                unsigned long min = 0, max = 0x20000000; /* low 512MB */
 151                if (!mem_size) {
 152                        /* default size for auto assignment */
 153                        if (txx9_pci_mem_high)
 154                                mem_size = 0x20000000;  /* mem:512M(max) */
 155                        else
 156                                mem_size = 0x08000000;  /* mem:128M(max) */
 157                }
 158                if (txx9_pci_mem_high) {
 159                        min = 0x20000000;
 160                        max = 0xe0000000;
 161                }
 162                /* search free region for PCI MEM */
 163                for (; mem_size >= min_size; mem_size /= 2) {
 164                        if (allocate_resource(&iomem_resource,
 165                                              &pcic->mem_resource[0],
 166                                              mem_size, min, max,
 167                                              mem_size, NULL, NULL) == 0)
 168                                break;
 169                }
 170                if (mem_size < min_size)
 171                        goto free_and_exit;
 172        }
 173
 174        pcic->mem_resource[1].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
 175        if (io_base) {
 176                pcic->mem_resource[1].start = io_base;
 177                pcic->mem_resource[1].end = io_base + io_size - 1;
 178                if (request_resource(&iomem_resource, &pcic->mem_resource[1]))
 179                        goto release_and_exit;
 180        } else {
 181                if (!io_size)
 182                        /* default size for auto assignment */
 183                        io_size = 0x01000000;   /* io:16M(max) */
 184                /* search free region for PCI IO in low 512MB */
 185                for (; io_size >= min_size; io_size /= 2) {
 186                        if (allocate_resource(&iomem_resource,
 187                                              &pcic->mem_resource[1],
 188                                              io_size, 0, 0x20000000,
 189                                              io_size, NULL, NULL) == 0)
 190                                break;
 191                }
 192                if (io_size < min_size)
 193                        goto release_and_exit;
 194                io_base = pcic->mem_resource[1].start;
 195        }
 196
 197        pcic->mem_resource[0].flags = IORESOURCE_MEM;
 198        if (pcic == &txx9_primary_pcic &&
 199            mips_io_port_base == (unsigned long)-1) {
 200                /* map ioport 0 to PCI I/O space address 0 */
 201                set_io_port_base(IO_BASE + pcic->mem_resource[1].start);
 202                pcic->io_resource->start = 0;
 203                pcic->io_offset = 0;    /* busaddr == ioaddr */
 204                pcic->io_map_base = IO_BASE + pcic->mem_resource[1].start;
 205        } else {
 206                /* physaddr to ioaddr */
 207                pcic->io_resource->start =
 208                        io_base - (mips_io_port_base - IO_BASE);
 209                pcic->io_offset = io_base - (mips_io_port_base - IO_BASE);
 210                pcic->io_map_base = mips_io_port_base;
 211        }
 212        pcic->io_resource->end = pcic->io_resource->start + io_size - 1;
 213
 214        pcic->mem_offset = 0;   /* busaddr == physaddr */
 215
 216        printk(KERN_INFO "PCI: IO %pR MEM %pR\n",
 217               &pcic->mem_resource[1], &pcic->mem_resource[0]);
 218
 219        /* register_pci_controller() will request MEM resource */
 220        release_resource(&pcic->mem_resource[0]);
 221        return pcic;
 222 release_and_exit:
 223        release_resource(&pcic->mem_resource[0]);
 224 free_and_exit:
 225        kfree(new);
 226        printk(KERN_ERR "PCI: Failed to allocate resources.\n");
 227        return NULL;
 228}
 229
 230static int __init
 231txx9_arch_pci_init(void)
 232{
 233        PCIBIOS_MIN_IO = 0x8000;        /* reseve legacy I/O space */
 234        return 0;
 235}
 236arch_initcall(txx9_arch_pci_init);
 237
 238/* IRQ/IDSEL mapping */
 239int txx9_pci_option =
 240#ifdef CONFIG_PICMG_PCI_BACKPLANE_DEFAULT
 241        TXX9_PCI_OPT_PICMG |
 242#endif
 243        TXX9_PCI_OPT_CLK_AUTO;
 244
 245enum txx9_pci_err_action txx9_pci_err_action = TXX9_PCI_ERR_REPORT;
 246
 247#ifdef CONFIG_TOSHIBA_FPCIB0
 248static irqreturn_t i8259_interrupt(int irq, void *dev_id)
 249{
 250        int isairq;
 251
 252        isairq = i8259_irq();
 253        if (unlikely(isairq <= I8259A_IRQ_BASE))
 254                return IRQ_NONE;
 255        generic_handle_irq(isairq);
 256        return IRQ_HANDLED;
 257}
 258
 259static int txx9_i8259_irq_setup(int irq)
 260{
 261        int err;
 262
 263        init_i8259_irqs();
 264        err = request_irq(irq, &i8259_interrupt, IRQF_SHARED,
 265                          "cascade(i8259)", (void *)(long)irq);
 266        if (!err)
 267                printk(KERN_INFO "PCI-ISA bridge PIC (irq %d)\n", irq);
 268        return err;
 269}
 270
 271static void quirk_slc90e66_bridge(struct pci_dev *dev)
 272{
 273        int irq;        /* PCI/ISA Bridge interrupt */
 274        u8 reg_64;
 275        u32 reg_b0;
 276        u8 reg_e1;
 277        irq = pcibios_map_irq(dev, PCI_SLOT(dev->devfn), 1); /* INTA */
 278        if (!irq)
 279                return;
 280        txx9_i8259_irq_setup(irq);
 281        pci_read_config_byte(dev, 0x64, &reg_64);
 282        pci_read_config_dword(dev, 0xb0, &reg_b0);
 283        pci_read_config_byte(dev, 0xe1, &reg_e1);
 284        /* serial irq control */
 285        reg_64 = 0xd0;
 286        /* serial irq pin */
 287        reg_b0 |= 0x00010000;
 288        /* ide irq on isa14 */
 289        reg_e1 &= 0xf0;
 290        reg_e1 |= 0x0d;
 291        pci_write_config_byte(dev, 0x64, reg_64);
 292        pci_write_config_dword(dev, 0xb0, reg_b0);
 293        pci_write_config_byte(dev, 0xe1, reg_e1);
 294
 295        smsc_fdc37m81x_init(0x3f0);
 296        smsc_fdc37m81x_config_beg();
 297        smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM,
 298                                  SMSC_FDC37M81X_KBD);
 299        smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1);
 300        smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12);
 301        smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE,
 302                                  1);
 303        smsc_fdc37m81x_config_end();
 304}
 305
 306static void quirk_slc90e66_ide(struct pci_dev *dev)
 307{
 308        unsigned char dat;
 309        int regs[2] = {0x41, 0x43};
 310        int i;
 311
 312        /* SMSC SLC90E66 IDE uses irq 14, 15 (default) */
 313        pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 14);
 314        pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &dat);
 315        printk(KERN_INFO "PCI: %s: IRQ %02x", pci_name(dev), dat);
 316        /* enable SMSC SLC90E66 IDE */
 317        for (i = 0; i < ARRAY_SIZE(regs); i++) {
 318                pci_read_config_byte(dev, regs[i], &dat);
 319                pci_write_config_byte(dev, regs[i], dat | 0x80);
 320                pci_read_config_byte(dev, regs[i], &dat);
 321                printk(KERN_CONT " IDETIM%d %02x", i, dat);
 322        }
 323        pci_read_config_byte(dev, 0x5c, &dat);
 324        /*
 325         * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
 326         *
 327         * This line of code is intended to provide the user with a work
 328         * around solution to the anomalies cited in SMSC's anomaly sheet
 329         * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"".
 330         *
 331         * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
 332         */
 333        dat |= 0x01;
 334        pci_write_config_byte(dev, regs[i], dat);
 335        pci_read_config_byte(dev, 0x5c, &dat);
 336        printk(KERN_CONT " REG5C %02x", dat);
 337        printk(KERN_CONT "\n");
 338}
 339#endif /* CONFIG_TOSHIBA_FPCIB0 */
 340
 341static void tc35815_fixup(struct pci_dev *dev)
 342{
 343        /* This device may have PM registers but not they are not supported. */
 344        if (dev->pm_cap) {
 345                dev_info(&dev->dev, "PM disabled\n");
 346                dev->pm_cap = 0;
 347        }
 348}
 349
 350static void final_fixup(struct pci_dev *dev)
 351{
 352        unsigned char bist;
 353
 354        /* Do build-in self test */
 355        if (pci_read_config_byte(dev, PCI_BIST, &bist) == PCIBIOS_SUCCESSFUL &&
 356            (bist & PCI_BIST_CAPABLE)) {
 357                unsigned long timeout;
 358                pci_set_power_state(dev, PCI_D0);
 359                printk(KERN_INFO "PCI: %s BIST...", pci_name(dev));
 360                pci_write_config_byte(dev, PCI_BIST, PCI_BIST_START);
 361                timeout = jiffies + HZ * 2;     /* timeout after 2 sec */
 362                do {
 363                        pci_read_config_byte(dev, PCI_BIST, &bist);
 364                        if (time_after(jiffies, timeout))
 365                                break;
 366                } while (bist & PCI_BIST_START);
 367                if (bist & (PCI_BIST_CODE_MASK | PCI_BIST_START))
 368                        printk(KERN_CONT "failed. (0x%x)\n", bist);
 369                else
 370                        printk(KERN_CONT "OK.\n");
 371        }
 372}
 373
 374#ifdef CONFIG_TOSHIBA_FPCIB0
 375#define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460
 376DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_0,
 377        quirk_slc90e66_bridge);
 378DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1,
 379        quirk_slc90e66_ide);
 380DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1,
 381        quirk_slc90e66_ide);
 382#endif
 383DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TOSHIBA_2,
 384                        PCI_DEVICE_ID_TOSHIBA_TC35815_NWU, tc35815_fixup);
 385DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TOSHIBA_2,
 386                        PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939, tc35815_fixup);
 387DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, final_fixup);
 388DECLARE_PCI_FIXUP_RESUME(PCI_ANY_ID, PCI_ANY_ID, final_fixup);
 389
 390int pcibios_plat_dev_init(struct pci_dev *dev)
 391{
 392        return 0;
 393}
 394
 395int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 396{
 397        return txx9_board_vec->pci_map_irq(dev, slot, pin);
 398}
 399
 400char * (*txx9_board_pcibios_setup)(char *str) __initdata;
 401
 402char *__init txx9_pcibios_setup(char *str)
 403{
 404        if (txx9_board_pcibios_setup && !txx9_board_pcibios_setup(str))
 405                return NULL;
 406        if (!strcmp(str, "picmg")) {
 407                /* PICMG compliant backplane (TOSHIBA JMB-PICMG-ATX
 408                   (5V or 3.3V), JMB-PICMG-L2 (5V only), etc.) */
 409                txx9_pci_option |= TXX9_PCI_OPT_PICMG;
 410                return NULL;
 411        } else if (!strcmp(str, "nopicmg")) {
 412                /* non-PICMG compliant backplane (TOSHIBA
 413                   RBHBK4100,RBHBK4200, Interface PCM-PCM05, etc.) */
 414                txx9_pci_option &= ~TXX9_PCI_OPT_PICMG;
 415                return NULL;
 416        } else if (!strncmp(str, "clk=", 4)) {
 417                char *val = str + 4;
 418                txx9_pci_option &= ~TXX9_PCI_OPT_CLK_MASK;
 419                if (strcmp(val, "33") == 0)
 420                        txx9_pci_option |= TXX9_PCI_OPT_CLK_33;
 421                else if (strcmp(val, "66") == 0)
 422                        txx9_pci_option |= TXX9_PCI_OPT_CLK_66;
 423                else /* "auto" */
 424                        txx9_pci_option |= TXX9_PCI_OPT_CLK_AUTO;
 425                return NULL;
 426        } else if (!strncmp(str, "err=", 4)) {
 427                if (!strcmp(str + 4, "panic"))
 428                        txx9_pci_err_action = TXX9_PCI_ERR_PANIC;
 429                else if (!strcmp(str + 4, "ignore"))
 430                        txx9_pci_err_action = TXX9_PCI_ERR_IGNORE;
 431                return NULL;
 432        }
 433        return str;
 434}
 435