LXR linux/arch/powerpc/include/asm/mmu-hash64.h

   1#ifndef _ASM_POWERPC_MMU_HASH64_H_
   2#define _ASM_POWERPC_MMU_HASH64_H_
   3/*
   4 * PowerPC64 memory management structures
   5 *
   6 * Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com>
   7 *   PPC64 rework.
   8 *
   9 * This program is free software; you can redistribute it and/or
  10 * modify it under the terms of the GNU General Public License
  11 * as published by the Free Software Foundation; either version
  12 * 2 of the License, or (at your option) any later version.
  13 */
  14
  15#include <asm/asm-compat.h>
  16#include <asm/page.h>
  17
  18/*
  19 * This is necessary to get the definition of PGTABLE_RANGE which we
  20 * need for various slices related matters. Note that this isn't the
  21 * complete pgtable.h but only a portion of it.
  22 */
  23#include <asm/pgtable-ppc64.h>
  24#include <asm/bug.h>
  25#include <asm/processor.h>
  26
  27/*
  28 * Segment table
  29 */
  30
  31#define STE_ESID_V      0x80
  32#define STE_ESID_KS     0x20
  33#define STE_ESID_KP     0x10
  34#define STE_ESID_N      0x08
  35
  36#define STE_VSID_SHIFT  12
  37
  38/* Location of cpu0's segment table */
  39#define STAB0_PAGE      0x8
  40#define STAB0_OFFSET    (STAB0_PAGE << 12)
  41#define STAB0_PHYS_ADDR (STAB0_OFFSET + PHYSICAL_START)
  42
  43#ifndef __ASSEMBLY__
  44extern char initial_stab[];
  45#endif /* ! __ASSEMBLY */
  46
  47/*
  48 * SLB
  49 */
  50
  51#define SLB_NUM_BOLTED          3
  52#define SLB_CACHE_ENTRIES       8
  53#define SLB_MIN_SIZE            32
  54
  55/* Bits in the SLB ESID word */
  56#define SLB_ESID_V              ASM_CONST(0x0000000008000000) /* valid */
  57
  58/* Bits in the SLB VSID word */
  59#define SLB_VSID_SHIFT          12
  60#define SLB_VSID_SHIFT_1T       24
  61#define SLB_VSID_SSIZE_SHIFT    62
  62#define SLB_VSID_B              ASM_CONST(0xc000000000000000)
  63#define SLB_VSID_B_256M         ASM_CONST(0x0000000000000000)
  64#define SLB_VSID_B_1T           ASM_CONST(0x4000000000000000)
  65#define SLB_VSID_KS             ASM_CONST(0x0000000000000800)
  66#define SLB_VSID_KP             ASM_CONST(0x0000000000000400)
  67#define SLB_VSID_N              ASM_CONST(0x0000000000000200) /* no-execute */
  68#define SLB_VSID_L              ASM_CONST(0x0000000000000100)
  69#define SLB_VSID_C              ASM_CONST(0x0000000000000080) /* class */
  70#define SLB_VSID_LP             ASM_CONST(0x0000000000000030)
  71#define SLB_VSID_LP_00          ASM_CONST(0x0000000000000000)
  72#define SLB_VSID_LP_01          ASM_CONST(0x0000000000000010)
  73#define SLB_VSID_LP_10          ASM_CONST(0x0000000000000020)
  74#define SLB_VSID_LP_11          ASM_CONST(0x0000000000000030)
  75#define SLB_VSID_LLP            (SLB_VSID_L|SLB_VSID_LP)
  76
  77#define SLB_VSID_KERNEL         (SLB_VSID_KP)
  78#define SLB_VSID_USER           (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C)
  79
  80#define SLBIE_C                 (0x08000000)
  81#define SLBIE_SSIZE_SHIFT       25
  82
  83/*
  84 * Hash table
  85 */
  86
  87#define HPTES_PER_GROUP 8
  88
  89#define HPTE_V_SSIZE_SHIFT      62
  90#define HPTE_V_AVPN_SHIFT       7
  91#define HPTE_V_AVPN             ASM_CONST(0x3fffffffffffff80)
  92#define HPTE_V_AVPN_VAL(x)      (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
  93#define HPTE_V_COMPARE(x,y)     (!(((x) ^ (y)) & 0xffffffffffffff80UL))
  94#define HPTE_V_BOLTED           ASM_CONST(0x0000000000000010)
  95#define HPTE_V_LOCK             ASM_CONST(0x0000000000000008)
  96#define HPTE_V_LARGE            ASM_CONST(0x0000000000000004)
  97#define HPTE_V_SECONDARY        ASM_CONST(0x0000000000000002)
  98#define HPTE_V_VALID            ASM_CONST(0x0000000000000001)
  99
 100#define HPTE_R_PP0              ASM_CONST(0x8000000000000000)
 101#define HPTE_R_TS               ASM_CONST(0x4000000000000000)
 102#define HPTE_R_KEY_HI           ASM_CONST(0x3000000000000000)
 103#define HPTE_R_RPN_SHIFT        12
 104#define HPTE_R_RPN              ASM_CONST(0x0ffffffffffff000)
 105#define HPTE_R_PP               ASM_CONST(0x0000000000000003)
 106#define HPTE_R_N                ASM_CONST(0x0000000000000004)
 107#define HPTE_R_G                ASM_CONST(0x0000000000000008)
 108#define HPTE_R_M                ASM_CONST(0x0000000000000010)
 109#define HPTE_R_I                ASM_CONST(0x0000000000000020)
 110#define HPTE_R_W                ASM_CONST(0x0000000000000040)
 111#define HPTE_R_WIMG             ASM_CONST(0x0000000000000078)
 112#define HPTE_R_C                ASM_CONST(0x0000000000000080)
 113#define HPTE_R_R                ASM_CONST(0x0000000000000100)
 114#define HPTE_R_KEY_LO           ASM_CONST(0x0000000000000e00)
 115
 116#define HPTE_V_1TB_SEG          ASM_CONST(0x4000000000000000)
 117#define HPTE_V_VRMA_MASK        ASM_CONST(0x4001ffffff000000)
 118
 119/* Values for PP (assumes Ks=0, Kp=1) */
 120#define PP_RWXX 0       /* Supervisor read/write, User none */
 121#define PP_RWRX 1       /* Supervisor read/write, User read */
 122#define PP_RWRW 2       /* Supervisor read/write, User read/write */
 123#define PP_RXRX 3       /* Supervisor read,       User read */
 124#define PP_RXXX (HPTE_R_PP0 | 2)        /* Supervisor read, user none */
 125
 126/* Fields for tlbiel instruction in architecture 2.06 */
 127#define TLBIEL_INVAL_SEL_MASK   0xc00   /* invalidation selector */
 128#define  TLBIEL_INVAL_PAGE      0x000   /* invalidate a single page */
 129#define  TLBIEL_INVAL_SET_LPID  0x800   /* invalidate a set for current LPID */
 130#define  TLBIEL_INVAL_SET       0xc00   /* invalidate a set for all LPIDs */
 131#define TLBIEL_INVAL_SET_MASK   0xfff000        /* set number to inval. */
 132#define TLBIEL_INVAL_SET_SHIFT  12
 133
 134#define POWER7_TLB_SETS         128     /* # sets in POWER7 TLB */
 135
 136#ifndef __ASSEMBLY__
 137
 138struct hash_pte {
 139        __be64 v;
 140        __be64 r;
 141};
 142
 143extern struct hash_pte *htab_address;
 144extern unsigned long htab_size_bytes;
 145extern unsigned long htab_hash_mask;
 146
 147/*
 148 * Page size definition
 149 *
 150 *    shift : is the "PAGE_SHIFT" value for that page size
 151 *    sllp  : is a bit mask with the value of SLB L || LP to be or'ed
 152 *            directly to a slbmte "vsid" value
 153 *    penc  : is the HPTE encoding mask for the "LP" field:
 154 *
 155 */
 156struct mmu_psize_def
 157{
 158        unsigned int    shift;  /* number of bits */
 159        int             penc[MMU_PAGE_COUNT];   /* HPTE encoding */
 160        unsigned int    tlbiel; /* tlbiel supported for that page size */
 161        unsigned long   avpnm;  /* bits to mask out in AVPN in the HPTE */
 162        unsigned long   sllp;   /* SLB L||LP (exact mask to use in slbmte) */
 163};
 164extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
 165
 166static inline int shift_to_mmu_psize(unsigned int shift)
 167{
 168        int psize;
 169
 170        for (psize = 0; psize < MMU_PAGE_COUNT; ++psize)
 171                if (mmu_psize_defs[psize].shift == shift)
 172                        return psize;
 173        return -1;
 174}
 175
 176static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize)
 177{
 178        if (mmu_psize_defs[mmu_psize].shift)
 179                return mmu_psize_defs[mmu_psize].shift;
 180        BUG();
 181}
 182
 183#endif /* __ASSEMBLY__ */
 184
 185/*
 186 * Segment sizes.
 187 * These are the values used by hardware in the B field of
 188 * SLB entries and the first dword of MMU hashtable entries.
 189 * The B field is 2 bits; the values 2 and 3 are unused and reserved.
 190 */
 191#define MMU_SEGSIZE_256M        0
 192#define MMU_SEGSIZE_1T          1
 193
 194/*
 195 * encode page number shift.
 196 * in order to fit the 78 bit va in a 64 bit variable we shift the va by
 197 * 12 bits. This enable us to address upto 76 bit va.
 198 * For hpt hash from a va we can ignore the page size bits of va and for
 199 * hpte encoding we ignore up to 23 bits of va. So ignoring lower 12 bits ensure
 200 * we work in all cases including 4k page size.
 201 */
 202#define VPN_SHIFT       12
 203
 204/*
 205 * HPTE Large Page (LP) details
 206 */
 207#define LP_SHIFT        12
 208#define LP_BITS         8
 209#define LP_MASK(i)      ((0xFF >> (i)) << LP_SHIFT)
 210
 211#ifndef __ASSEMBLY__
 212
 213static inline int segment_shift(int ssize)
 214{
 215        if (ssize == MMU_SEGSIZE_256M)
 216                return SID_SHIFT;
 217        return SID_SHIFT_1T;
 218}
 219
 220/*
 221 * The current system page and segment sizes
 222 */
 223extern int mmu_linear_psize;
 224extern int mmu_virtual_psize;
 225extern int mmu_vmalloc_psize;
 226extern int mmu_vmemmap_psize;
 227extern int mmu_io_psize;
 228extern int mmu_kernel_ssize;
 229extern int mmu_highuser_ssize;
 230extern u16 mmu_slb_size;
 231extern unsigned long tce_alloc_start, tce_alloc_end;
 232
 233/*
 234 * If the processor supports 64k normal pages but not 64k cache
 235 * inhibited pages, we have to be prepared to switch processes
 236 * to use 4k pages when they create cache-inhibited mappings.
 237 * If this is the case, mmu_ci_restrictions will be set to 1.
 238 */
 239extern int mmu_ci_restrictions;
 240
 241/*
 242 * This computes the AVPN and B fields of the first dword of a HPTE,
 243 * for use when we want to match an existing PTE.  The bottom 7 bits
 244 * of the returned value are zero.
 245 */
 246static inline unsigned long hpte_encode_avpn(unsigned long vpn, int psize,
 247                                             int ssize)
 248{
 249        unsigned long v;
 250        /*
 251         * The AVA field omits the low-order 23 bits of the 78 bits VA.
 252         * These bits are not needed in the PTE, because the
 253         * low-order b of these bits are part of the byte offset
 254         * into the virtual page and, if b < 23, the high-order
 255         * 23-b of these bits are always used in selecting the
 256         * PTEGs to be searched
 257         */
 258        v = (vpn >> (23 - VPN_SHIFT)) & ~(mmu_psize_defs[psize].avpnm);
 259        v <<= HPTE_V_AVPN_SHIFT;
 260        v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;
 261        return v;
 262}
 263
 264/*
 265 * This function sets the AVPN and L fields of the HPTE  appropriately
 266 * using the base page size and actual page size.
 267 */
 268static inline unsigned long hpte_encode_v(unsigned long vpn, int base_psize,
 269                                          int actual_psize, int ssize)
 270{
 271        unsigned long v;
 272        v = hpte_encode_avpn(vpn, base_psize, ssize);
 273        if (actual_psize != MMU_PAGE_4K)
 274                v |= HPTE_V_LARGE;
 275        return v;
 276}
 277
 278/*
 279 * This function sets the ARPN, and LP fields of the HPTE appropriately
 280 * for the page size. We assume the pa is already "clean" that is properly
 281 * aligned for the requested page size
 282 */
 283static inline unsigned long hpte_encode_r(unsigned long pa, int base_psize,
 284                                          int actual_psize)
 285{
 286        /* A 4K page needs no special encoding */
 287        if (actual_psize == MMU_PAGE_4K)
 288                return pa & HPTE_R_RPN;
 289        else {
 290                unsigned int penc = mmu_psize_defs[base_psize].penc[actual_psize];
 291                unsigned int shift = mmu_psize_defs[actual_psize].shift;
 292                return (pa & ~((1ul << shift) - 1)) | (penc << LP_SHIFT);
 293        }
 294}
 295
 296/*
 297 * Build a VPN_SHIFT bit shifted va given VSID, EA and segment size.
 298 */
 299static inline unsigned long hpt_vpn(unsigned long ea,
 300                                    unsigned long vsid, int ssize)
 301{
 302        unsigned long mask;
 303        int s_shift = segment_shift(ssize);
 304
 305        mask = (1ul << (s_shift - VPN_SHIFT)) - 1;
 306        return (vsid << (s_shift - VPN_SHIFT)) | ((ea >> VPN_SHIFT) & mask);
 307}
 308
 309/*
 310 * This hashes a virtual address
 311 */
 312static inline unsigned long hpt_hash(unsigned long vpn,
 313                                     unsigned int shift, int ssize)
 314{
 315        int mask;
 316        unsigned long hash, vsid;
 317
 318        /* VPN_SHIFT can be atmost 12 */
 319        if (ssize == MMU_SEGSIZE_256M) {
 320                mask = (1ul << (SID_SHIFT - VPN_SHIFT)) - 1;
 321                hash = (vpn >> (SID_SHIFT - VPN_SHIFT)) ^
 322                        ((vpn & mask) >> (shift - VPN_SHIFT));
 323        } else {
 324                mask = (1ul << (SID_SHIFT_1T - VPN_SHIFT)) - 1;
 325                vsid = vpn >> (SID_SHIFT_1T - VPN_SHIFT);
 326                hash = vsid ^ (vsid << 25) ^
 327                        ((vpn & mask) >> (shift - VPN_SHIFT)) ;
 328        }
 329        return hash & 0x7fffffffffUL;
 330}
 331
 332extern int __hash_page_4K(unsigned long ea, unsigned long access,
 333                          unsigned long vsid, pte_t *ptep, unsigned long trap,
 334                          unsigned int local, int ssize, int subpage_prot);
 335extern int __hash_page_64K(unsigned long ea, unsigned long access,
 336                           unsigned long vsid, pte_t *ptep, unsigned long trap,
 337                           unsigned int local, int ssize);
 338struct mm_struct;
 339unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap);
 340extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap);
 341int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
 342                     pte_t *ptep, unsigned long trap, int local, int ssize,
 343                     unsigned int shift, unsigned int mmu_psize);
 344#ifdef CONFIG_TRANSPARENT_HUGEPAGE
 345extern int __hash_page_thp(unsigned long ea, unsigned long access,
 346                           unsigned long vsid, pmd_t *pmdp, unsigned long trap,
 347                           int local, int ssize, unsigned int psize);
 348#else
 349static inline int __hash_page_thp(unsigned long ea, unsigned long access,
 350                                  unsigned long vsid, pmd_t *pmdp,
 351                                  unsigned long trap, int local,
 352                                  int ssize, unsigned int psize)
 353{
 354        BUG();
 355        return -1;
 356}
 357#endif
 358extern void hash_failure_debug(unsigned long ea, unsigned long access,
 359                               unsigned long vsid, unsigned long trap,
 360                               int ssize, int psize, int lpsize,
 361                               unsigned long pte);
 362extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
 363                             unsigned long pstart, unsigned long prot,
 364                             int psize, int ssize);
 365extern void add_gpage(u64 addr, u64 page_size, unsigned long number_of_pages);
 366extern void demote_segment_4k(struct mm_struct *mm, unsigned long addr);
 367
 368extern void hpte_init_native(void);
 369extern void hpte_init_lpar(void);
 370extern void hpte_init_beat(void);
 371extern void hpte_init_beat_v3(void);
 372
 373extern void stabs_alloc(void);
 374extern void slb_initialize(void);
 375extern void slb_flush_and_rebolt(void);
 376extern void stab_initialize(unsigned long stab);
 377
 378extern void slb_vmalloc_update(void);
 379extern void slb_set_size(u16 size);
 380#endif /* __ASSEMBLY__ */
 381
 382/*
 383 * VSID allocation (256MB segment)
 384 *
 385 * We first generate a 37-bit "proto-VSID". Proto-VSIDs are generated
 386 * from mmu context id and effective segment id of the address.
 387 *
 388 * For user processes max context id is limited to ((1ul << 19) - 5)
 389 * for kernel space, we use the top 4 context ids to map address as below
 390 * NOTE: each context only support 64TB now.
 391 * 0x7fffc -  [ 0xc000000000000000 - 0xc0003fffffffffff ]
 392 * 0x7fffd -  [ 0xd000000000000000 - 0xd0003fffffffffff ]
 393 * 0x7fffe -  [ 0xe000000000000000 - 0xe0003fffffffffff ]
 394 * 0x7ffff -  [ 0xf000000000000000 - 0xf0003fffffffffff ]
 395 *
 396 * The proto-VSIDs are then scrambled into real VSIDs with the
 397 * multiplicative hash:
 398 *
 399 *      VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
 400 *
 401 * VSID_MULTIPLIER is prime, so in particular it is
 402 * co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
 403 * Because the modulus is 2^n-1 we can compute it efficiently without
 404 * a divide or extra multiply (see below). The scramble function gives
 405 * robust scattering in the hash table (at least based on some initial
 406 * results).
 407 *
 408 * We also consider VSID 0 special. We use VSID 0 for slb entries mapping
 409 * bad address. This enables us to consolidate bad address handling in
 410 * hash_page.
 411 *
 412 * We also need to avoid the last segment of the last context, because that
 413 * would give a protovsid of 0x1fffffffff. That will result in a VSID 0
 414 * because of the modulo operation in vsid scramble. But the vmemmap
 415 * (which is what uses region 0xf) will never be close to 64TB in size
 416 * (it's 56 bytes per page of system memory).
 417 */
 418
 419#define CONTEXT_BITS            19
 420#define ESID_BITS               18
 421#define ESID_BITS_1T            6
 422
 423/*
 424 * 256MB segment
 425 * The proto-VSID space has 2^(CONTEX_BITS + ESID_BITS) - 1 segments
 426 * available for user + kernel mapping. The top 4 contexts are used for
 427 * kernel mapping. Each segment contains 2^28 bytes. Each
 428 * context maps 2^46 bytes (64TB) so we can support 2^19-1 contexts
 429 * (19 == 37 + 28 - 46).
 430 */
 431#define MAX_USER_CONTEXT        ((ASM_CONST(1) << CONTEXT_BITS) - 5)
 432
 433/*
 434 * This should be computed such that protovosid * vsid_mulitplier
 435 * doesn't overflow 64 bits. It should also be co-prime to vsid_modulus
 436 */
 437#define VSID_MULTIPLIER_256M    ASM_CONST(12538073)     /* 24-bit prime */
 438#define VSID_BITS_256M          (CONTEXT_BITS + ESID_BITS)
 439#define VSID_MODULUS_256M       ((1UL<<VSID_BITS_256M)-1)
 440
 441#define VSID_MULTIPLIER_1T      ASM_CONST(12538073)     /* 24-bit prime */
 442#define VSID_BITS_1T            (CONTEXT_BITS + ESID_BITS_1T)
 443#define VSID_MODULUS_1T         ((1UL<<VSID_BITS_1T)-1)
 444
 445
 446#define USER_VSID_RANGE (1UL << (ESID_BITS + SID_SHIFT))
 447
 448/*
 449 * This macro generates asm code to compute the VSID scramble
 450 * function.  Used in slb_allocate() and do_stab_bolted.  The function
 451 * computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS
 452 *
 453 *      rt = register continaing the proto-VSID and into which the
 454 *              VSID will be stored
 455 *      rx = scratch register (clobbered)
 456 *
 457 *      - rt and rx must be different registers
 458 *      - The answer will end up in the low VSID_BITS bits of rt.  The higher
 459 *        bits may contain other garbage, so you may need to mask the
 460 *        result.
 461 */
 462#define ASM_VSID_SCRAMBLE(rt, rx, size)                                 \
 463        lis     rx,VSID_MULTIPLIER_##size@h;                            \
 464        ori     rx,rx,VSID_MULTIPLIER_##size@l;                         \
 465        mulld   rt,rt,rx;               /* rt = rt * MULTIPLIER */      \
 466                                                                        \
 467        srdi    rx,rt,VSID_BITS_##size;                                 \
 468        clrldi  rt,rt,(64-VSID_BITS_##size);                            \
 469        add     rt,rt,rx;               /* add high and low bits */     \
 470        /* NOTE: explanation based on VSID_BITS_##size = 36             \
 471         * Now, r3 == VSID (mod 2^36-1), and lies between 0 and         \
 472         * 2^36-1+2^28-1.  That in particular means that if r3 >=       \
 473         * 2^36-1, then r3+1 has the 2^36 bit set.  So, if r3+1 has     \
 474         * the bit clear, r3 already has the answer we want, if it      \
 475         * doesn't, the answer is the low 36 bits of r3+1.  So in all   \
 476         * cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\
 477        addi    rx,rt,1;                                                \
 478        srdi    rx,rx,VSID_BITS_##size; /* extract 2^VSID_BITS bit */   \
 479        add     rt,rt,rx
 480
 481/* 4 bits per slice and we have one slice per 1TB */
 482#define SLICE_ARRAY_SIZE  (PGTABLE_RANGE >> 41)
 483
 484#ifndef __ASSEMBLY__
 485
 486#ifdef CONFIG_PPC_SUBPAGE_PROT
 487/*
 488 * For the sub-page protection option, we extend the PGD with one of
 489 * these.  Basically we have a 3-level tree, with the top level being
 490 * the protptrs array.  To optimize speed and memory consumption when
 491 * only addresses < 4GB are being protected, pointers to the first
 492 * four pages of sub-page protection words are stored in the low_prot
 493 * array.
 494 * Each page of sub-page protection words protects 1GB (4 bytes
 495 * protects 64k).  For the 3-level tree, each page of pointers then
 496 * protects 8TB.
 497 */
 498struct subpage_prot_table {
 499        unsigned long maxaddr;  /* only addresses < this are protected */
 500        unsigned int **protptrs[(TASK_SIZE_USER64 >> 43)];
 501        unsigned int *low_prot[4];
 502};
 503
 504#define SBP_L1_BITS             (PAGE_SHIFT - 2)
 505#define SBP_L2_BITS             (PAGE_SHIFT - 3)
 506#define SBP_L1_COUNT            (1 << SBP_L1_BITS)
 507#define SBP_L2_COUNT            (1 << SBP_L2_BITS)
 508#define SBP_L2_SHIFT            (PAGE_SHIFT + SBP_L1_BITS)
 509#define SBP_L3_SHIFT            (SBP_L2_SHIFT + SBP_L2_BITS)
 510
 511extern void subpage_prot_free(struct mm_struct *mm);
 512extern void subpage_prot_init_new_context(struct mm_struct *mm);
 513#else
 514static inline void subpage_prot_free(struct mm_struct *mm) {}
 515static inline void subpage_prot_init_new_context(struct mm_struct *mm) { }
 516#endif /* CONFIG_PPC_SUBPAGE_PROT */
 517
 518typedef unsigned long mm_context_id_t;
 519struct spinlock;
 520
 521typedef struct {
 522        mm_context_id_t id;
 523        u16 user_psize;         /* page size index */
 524
 525#ifdef CONFIG_PPC_MM_SLICES
 526        u64 low_slices_psize;   /* SLB page size encodings */
 527        unsigned char high_slices_psize[SLICE_ARRAY_SIZE];
 528#else
 529        u16 sllp;               /* SLB page size encoding */
 530#endif
 531        unsigned long vdso_base;
 532#ifdef CONFIG_PPC_SUBPAGE_PROT
 533        struct subpage_prot_table spt;
 534#endif /* CONFIG_PPC_SUBPAGE_PROT */
 535#ifdef CONFIG_PPC_ICSWX
 536        struct spinlock *cop_lockp; /* guard acop and cop_pid */
 537        unsigned long acop;     /* mask of enabled coprocessor types */
 538        unsigned int cop_pid;   /* pid value used with coprocessors */
 539#endif /* CONFIG_PPC_ICSWX */
 540#ifdef CONFIG_PPC_64K_PAGES
 541        /* for 4K PTE fragment support */
 542        void *pte_frag;
 543#endif
 544} mm_context_t;
 545
 546
 547#if 0
 548/*
 549 * The code below is equivalent to this function for arguments
 550 * < 2^VSID_BITS, which is all this should ever be called
 551 * with.  However gcc is not clever enough to compute the
 552 * modulus (2^n-1) without a second multiply.
 553 */
 554#define vsid_scramble(protovsid, size) \
 555        ((((protovsid) * VSID_MULTIPLIER_##size) % VSID_MODULUS_##size))
 556
 557#else /* 1 */
 558#define vsid_scramble(protovsid, size) \
 559        ({                                                               \
 560                unsigned long x;                                         \
 561                x = (protovsid) * VSID_MULTIPLIER_##size;                \
 562                x = (x >> VSID_BITS_##size) + (x & VSID_MODULUS_##size); \
 563                (x + ((x+1) >> VSID_BITS_##size)) & VSID_MODULUS_##size; \
 564        })
 565#endif /* 1 */
 566
 567/* Returns the segment size indicator for a user address */
 568static inline int user_segment_size(unsigned long addr)
 569{
 570        /* Use 1T segments if possible for addresses >= 1T */
 571        if (addr >= (1UL << SID_SHIFT_1T))
 572                return mmu_highuser_ssize;
 573        return MMU_SEGSIZE_256M;
 574}
 575
 576static inline unsigned long get_vsid(unsigned long context, unsigned long ea,
 577                                     int ssize)
 578{
 579        /*
 580         * Bad address. We return VSID 0 for that
 581         */
 582        if ((ea & ~REGION_MASK) >= PGTABLE_RANGE)
 583                return 0;
 584
 585        if (ssize == MMU_SEGSIZE_256M)
 586                return vsid_scramble((context << ESID_BITS)
 587                                     | (ea >> SID_SHIFT), 256M);
 588        return vsid_scramble((context << ESID_BITS_1T)
 589                             | (ea >> SID_SHIFT_1T), 1T);
 590}
 591
 592/*
 593 * This is only valid for addresses >= PAGE_OFFSET
 594 *
 595 * For kernel space, we use the top 4 context ids to map address as below
 596 * 0x7fffc -  [ 0xc000000000000000 - 0xc0003fffffffffff ]
 597 * 0x7fffd -  [ 0xd000000000000000 - 0xd0003fffffffffff ]
 598 * 0x7fffe -  [ 0xe000000000000000 - 0xe0003fffffffffff ]
 599 * 0x7ffff -  [ 0xf000000000000000 - 0xf0003fffffffffff ]
 600 */
 601static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize)
 602{
 603        unsigned long context;
 604
 605        /*
 606         * kernel take the top 4 context from the available range
 607         */
 608        context = (MAX_USER_CONTEXT) + ((ea >> 60) - 0xc) + 1;
 609        return get_vsid(context, ea, ssize);
 610}
 611#endif /* __ASSEMBLY__ */
 612
 613#endif /* _ASM_POWERPC_MMU_HASH64_H_ */
 614