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28#include <linux/atomic.h>
29#include <linux/delay.h>
30#include <linux/export.h>
31#include <linux/init.h>
32#include <linux/list.h>
33#include <linux/of.h>
34#include <linux/pci.h>
35#include <linux/proc_fs.h>
36#include <linux/rbtree.h>
37#include <linux/sched.h>
38#include <linux/seq_file.h>
39#include <linux/spinlock.h>
40
41#include <asm/eeh.h>
42#include <asm/eeh_event.h>
43#include <asm/io.h>
44#include <asm/machdep.h>
45#include <asm/ppc-pci.h>
46#include <asm/rtas.h>
47
48
49static int ibm_set_eeh_option;
50static int ibm_set_slot_reset;
51static int ibm_read_slot_reset_state;
52static int ibm_read_slot_reset_state2;
53static int ibm_slot_error_detail;
54static int ibm_get_config_addr_info;
55static int ibm_get_config_addr_info2;
56static int ibm_configure_bridge;
57static int ibm_configure_pe;
58
59
60
61
62
63
64static unsigned char slot_errbuf[RTAS_ERROR_LOG_MAX];
65static DEFINE_SPINLOCK(slot_errbuf_lock);
66static int eeh_error_buf_size;
67
68
69
70
71
72
73static int pseries_eeh_init(void)
74{
75
76 ibm_set_eeh_option = rtas_token("ibm,set-eeh-option");
77 ibm_set_slot_reset = rtas_token("ibm,set-slot-reset");
78 ibm_read_slot_reset_state2 = rtas_token("ibm,read-slot-reset-state2");
79 ibm_read_slot_reset_state = rtas_token("ibm,read-slot-reset-state");
80 ibm_slot_error_detail = rtas_token("ibm,slot-error-detail");
81 ibm_get_config_addr_info2 = rtas_token("ibm,get-config-addr-info2");
82 ibm_get_config_addr_info = rtas_token("ibm,get-config-addr-info");
83 ibm_configure_pe = rtas_token("ibm,configure-pe");
84 ibm_configure_bridge = rtas_token("ibm,configure-bridge");
85
86
87
88
89
90
91 if (ibm_set_eeh_option == RTAS_UNKNOWN_SERVICE) {
92 pr_warning("%s: RTAS service <ibm,set-eeh-option> invalid\n",
93 __func__);
94 return -EINVAL;
95 } else if (ibm_set_slot_reset == RTAS_UNKNOWN_SERVICE) {
96 pr_warning("%s: RTAS service <ibm,set-slot-reset> invalid\n",
97 __func__);
98 return -EINVAL;
99 } else if (ibm_read_slot_reset_state2 == RTAS_UNKNOWN_SERVICE &&
100 ibm_read_slot_reset_state == RTAS_UNKNOWN_SERVICE) {
101 pr_warning("%s: RTAS service <ibm,read-slot-reset-state2> and "
102 "<ibm,read-slot-reset-state> invalid\n",
103 __func__);
104 return -EINVAL;
105 } else if (ibm_slot_error_detail == RTAS_UNKNOWN_SERVICE) {
106 pr_warning("%s: RTAS service <ibm,slot-error-detail> invalid\n",
107 __func__);
108 return -EINVAL;
109 } else if (ibm_configure_pe == RTAS_UNKNOWN_SERVICE &&
110 ibm_configure_bridge == RTAS_UNKNOWN_SERVICE) {
111 pr_warning("%s: RTAS service <ibm,configure-pe> and "
112 "<ibm,configure-bridge> invalid\n",
113 __func__);
114 return -EINVAL;
115 }
116
117
118 spin_lock_init(&slot_errbuf_lock);
119 eeh_error_buf_size = rtas_token("rtas-error-log-max");
120 if (eeh_error_buf_size == RTAS_UNKNOWN_SERVICE) {
121 pr_warning("%s: unknown EEH error log size\n",
122 __func__);
123 eeh_error_buf_size = 1024;
124 } else if (eeh_error_buf_size > RTAS_ERROR_LOG_MAX) {
125 pr_warning("%s: EEH error log size %d exceeds the maximal %d\n",
126 __func__, eeh_error_buf_size, RTAS_ERROR_LOG_MAX);
127 eeh_error_buf_size = RTAS_ERROR_LOG_MAX;
128 }
129
130
131 eeh_probe_mode_set(EEH_PROBE_MODE_DEVTREE);
132
133 return 0;
134}
135
136static int pseries_eeh_cap_start(struct device_node *dn)
137{
138 struct pci_dn *pdn = PCI_DN(dn);
139 u32 status;
140
141 if (!pdn)
142 return 0;
143
144 rtas_read_config(pdn, PCI_STATUS, 2, &status);
145 if (!(status & PCI_STATUS_CAP_LIST))
146 return 0;
147
148 return PCI_CAPABILITY_LIST;
149}
150
151
152static int pseries_eeh_find_cap(struct device_node *dn, int cap)
153{
154 struct pci_dn *pdn = PCI_DN(dn);
155 int pos = pseries_eeh_cap_start(dn);
156 int cnt = 48;
157 u32 id;
158
159 if (!pos)
160 return 0;
161
162 while (cnt--) {
163 rtas_read_config(pdn, pos, 1, &pos);
164 if (pos < 0x40)
165 break;
166 pos &= ~3;
167 rtas_read_config(pdn, pos + PCI_CAP_LIST_ID, 1, &id);
168 if (id == 0xff)
169 break;
170 if (id == cap)
171 return pos;
172 pos += PCI_CAP_LIST_NEXT;
173 }
174
175 return 0;
176}
177
178static int pseries_eeh_find_ecap(struct device_node *dn, int cap)
179{
180 struct pci_dn *pdn = PCI_DN(dn);
181 struct eeh_dev *edev = of_node_to_eeh_dev(dn);
182 u32 header;
183 int pos = 256;
184 int ttl = (4096 - 256) / 8;
185
186 if (!edev || !edev->pcie_cap)
187 return 0;
188 if (rtas_read_config(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
189 return 0;
190 else if (!header)
191 return 0;
192
193 while (ttl-- > 0) {
194 if (PCI_EXT_CAP_ID(header) == cap && pos)
195 return pos;
196
197 pos = PCI_EXT_CAP_NEXT(header);
198 if (pos < 256)
199 break;
200
201 if (rtas_read_config(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
202 break;
203 }
204
205 return 0;
206}
207
208
209
210
211
212
213
214
215
216
217static void *pseries_eeh_of_probe(struct device_node *dn, void *flag)
218{
219 struct eeh_dev *edev;
220 struct eeh_pe pe;
221 struct pci_dn *pdn = PCI_DN(dn);
222 const __be32 *classp, *vendorp, *devicep;
223 u32 class_code;
224 const __be32 *regs;
225 u32 pcie_flags;
226 int enable = 0;
227 int ret;
228
229
230 edev = of_node_to_eeh_dev(dn);
231 if (edev->pe || !of_device_is_available(dn))
232 return NULL;
233
234
235 classp = of_get_property(dn, "class-code", NULL);
236 vendorp = of_get_property(dn, "vendor-id", NULL);
237 devicep = of_get_property(dn, "device-id", NULL);
238
239
240 if (!classp || !vendorp || !devicep)
241 return NULL;
242 if (dn->type && !strcmp(dn->type, "isa"))
243 return NULL;
244
245 class_code = of_read_number(classp, 1);
246
247
248
249
250
251
252 edev->class_code = class_code;
253 edev->pcix_cap = pseries_eeh_find_cap(dn, PCI_CAP_ID_PCIX);
254 edev->pcie_cap = pseries_eeh_find_cap(dn, PCI_CAP_ID_EXP);
255 edev->aer_cap = pseries_eeh_find_ecap(dn, PCI_EXT_CAP_ID_ERR);
256 edev->mode &= 0xFFFFFF00;
257 if ((edev->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) {
258 edev->mode |= EEH_DEV_BRIDGE;
259 if (edev->pcie_cap) {
260 rtas_read_config(pdn, edev->pcie_cap + PCI_EXP_FLAGS,
261 2, &pcie_flags);
262 pcie_flags = (pcie_flags & PCI_EXP_FLAGS_TYPE) >> 4;
263 if (pcie_flags == PCI_EXP_TYPE_ROOT_PORT)
264 edev->mode |= EEH_DEV_ROOT_PORT;
265 else if (pcie_flags == PCI_EXP_TYPE_DOWNSTREAM)
266 edev->mode |= EEH_DEV_DS_PORT;
267 }
268 }
269
270
271 regs = of_get_property(dn, "reg", NULL);
272 if (!regs) {
273 pr_warning("%s: OF node property %s::reg not found\n",
274 __func__, dn->full_name);
275 return NULL;
276 }
277
278
279 memset(&pe, 0, sizeof(struct eeh_pe));
280 pe.phb = edev->phb;
281 pe.config_addr = of_read_number(regs, 1);
282
283
284 ret = eeh_ops->set_option(&pe, EEH_OPT_ENABLE);
285 if (!ret) {
286 edev->config_addr = of_read_number(regs, 1);
287
288 edev->pe_config_addr = eeh_ops->get_pe_addr(&pe);
289 pe.addr = edev->pe_config_addr;
290
291
292
293
294
295 ret = eeh_ops->get_state(&pe, NULL);
296 if (ret > 0 && ret != EEH_STATE_NOT_SUPPORT)
297 enable = 1;
298
299 if (enable) {
300 eeh_set_enable(true);
301 eeh_add_to_parent_pe(edev);
302
303 pr_debug("%s: EEH enabled on %s PHB#%d-PE#%x, config addr#%x\n",
304 __func__, dn->full_name, pe.phb->global_number,
305 pe.addr, pe.config_addr);
306 } else if (dn->parent && of_node_to_eeh_dev(dn->parent) &&
307 (of_node_to_eeh_dev(dn->parent))->pe) {
308
309
310
311 edev->config_addr = of_node_to_eeh_dev(dn->parent)->config_addr;
312 edev->pe_config_addr = of_node_to_eeh_dev(dn->parent)->pe_config_addr;
313 eeh_add_to_parent_pe(edev);
314 }
315 }
316
317
318 eeh_save_bars(edev);
319
320 return NULL;
321}
322
323
324
325
326
327
328
329
330
331
332static int pseries_eeh_set_option(struct eeh_pe *pe, int option)
333{
334 int ret = 0;
335 int config_addr;
336
337
338
339
340
341
342
343 switch (option) {
344 case EEH_OPT_DISABLE:
345 case EEH_OPT_ENABLE:
346 case EEH_OPT_THAW_MMIO:
347 case EEH_OPT_THAW_DMA:
348 config_addr = pe->config_addr;
349 if (pe->addr)
350 config_addr = pe->addr;
351 break;
352
353 default:
354 pr_err("%s: Invalid option %d\n",
355 __func__, option);
356 return -EINVAL;
357 }
358
359 ret = rtas_call(ibm_set_eeh_option, 4, 1, NULL,
360 config_addr, BUID_HI(pe->phb->buid),
361 BUID_LO(pe->phb->buid), option);
362
363 return ret;
364}
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379static int pseries_eeh_get_pe_addr(struct eeh_pe *pe)
380{
381 int ret = 0;
382 int rets[3];
383
384 if (ibm_get_config_addr_info2 != RTAS_UNKNOWN_SERVICE) {
385
386
387
388
389
390 ret = rtas_call(ibm_get_config_addr_info2, 4, 2, rets,
391 pe->config_addr, BUID_HI(pe->phb->buid),
392 BUID_LO(pe->phb->buid), 1);
393 if (ret || (rets[0] == 0))
394 return 0;
395
396
397 ret = rtas_call(ibm_get_config_addr_info2, 4, 2, rets,
398 pe->config_addr, BUID_HI(pe->phb->buid),
399 BUID_LO(pe->phb->buid), 0);
400 if (ret) {
401 pr_warning("%s: Failed to get address for PHB#%d-PE#%x\n",
402 __func__, pe->phb->global_number, pe->config_addr);
403 return 0;
404 }
405
406 return rets[0];
407 }
408
409 if (ibm_get_config_addr_info != RTAS_UNKNOWN_SERVICE) {
410 ret = rtas_call(ibm_get_config_addr_info, 4, 2, rets,
411 pe->config_addr, BUID_HI(pe->phb->buid),
412 BUID_LO(pe->phb->buid), 0);
413 if (ret) {
414 pr_warning("%s: Failed to get address for PHB#%d-PE#%x\n",
415 __func__, pe->phb->global_number, pe->config_addr);
416 return 0;
417 }
418
419 return rets[0];
420 }
421
422 return ret;
423}
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438static int pseries_eeh_get_state(struct eeh_pe *pe, int *state)
439{
440 int config_addr;
441 int ret;
442 int rets[4];
443 int result;
444
445
446 config_addr = pe->config_addr;
447 if (pe->addr)
448 config_addr = pe->addr;
449
450 if (ibm_read_slot_reset_state2 != RTAS_UNKNOWN_SERVICE) {
451 ret = rtas_call(ibm_read_slot_reset_state2, 3, 4, rets,
452 config_addr, BUID_HI(pe->phb->buid),
453 BUID_LO(pe->phb->buid));
454 } else if (ibm_read_slot_reset_state != RTAS_UNKNOWN_SERVICE) {
455
456 rets[2] = 0;
457 ret = rtas_call(ibm_read_slot_reset_state, 3, 3, rets,
458 config_addr, BUID_HI(pe->phb->buid),
459 BUID_LO(pe->phb->buid));
460 } else {
461 return EEH_STATE_NOT_SUPPORT;
462 }
463
464 if (ret)
465 return ret;
466
467
468 result = 0;
469 if (rets[1]) {
470 switch(rets[0]) {
471 case 0:
472 result &= ~EEH_STATE_RESET_ACTIVE;
473 result |= EEH_STATE_MMIO_ACTIVE;
474 result |= EEH_STATE_DMA_ACTIVE;
475 break;
476 case 1:
477 result |= EEH_STATE_RESET_ACTIVE;
478 result |= EEH_STATE_MMIO_ACTIVE;
479 result |= EEH_STATE_DMA_ACTIVE;
480 break;
481 case 2:
482 result &= ~EEH_STATE_RESET_ACTIVE;
483 result &= ~EEH_STATE_MMIO_ACTIVE;
484 result &= ~EEH_STATE_DMA_ACTIVE;
485 break;
486 case 4:
487 result &= ~EEH_STATE_RESET_ACTIVE;
488 result &= ~EEH_STATE_MMIO_ACTIVE;
489 result &= ~EEH_STATE_DMA_ACTIVE;
490 result |= EEH_STATE_MMIO_ENABLED;
491 break;
492 case 5:
493 if (rets[2]) {
494 if (state) *state = rets[2];
495 result = EEH_STATE_UNAVAILABLE;
496 } else {
497 result = EEH_STATE_NOT_SUPPORT;
498 }
499 break;
500 default:
501 result = EEH_STATE_NOT_SUPPORT;
502 }
503 } else {
504 result = EEH_STATE_NOT_SUPPORT;
505 }
506
507 return result;
508}
509
510
511
512
513
514
515
516
517static int pseries_eeh_reset(struct eeh_pe *pe, int option)
518{
519 int config_addr;
520 int ret;
521
522
523 config_addr = pe->config_addr;
524 if (pe->addr)
525 config_addr = pe->addr;
526
527
528 ret = rtas_call(ibm_set_slot_reset, 4, 1, NULL,
529 config_addr, BUID_HI(pe->phb->buid),
530 BUID_LO(pe->phb->buid), option);
531
532
533 if (option == EEH_RESET_FUNDAMENTAL &&
534 ret == -8) {
535 option = EEH_RESET_HOT;
536 ret = rtas_call(ibm_set_slot_reset, 4, 1, NULL,
537 config_addr, BUID_HI(pe->phb->buid),
538 BUID_LO(pe->phb->buid), option);
539 }
540
541
542 if (option == EEH_RESET_FUNDAMENTAL ||
543 option == EEH_RESET_HOT)
544 msleep(EEH_PE_RST_HOLD_TIME);
545 else
546 msleep(EEH_PE_RST_SETTLE_TIME);
547
548 return ret;
549}
550
551
552
553
554
555
556
557
558
559static int pseries_eeh_wait_state(struct eeh_pe *pe, int max_wait)
560{
561 int ret;
562 int mwait;
563
564
565
566
567
568
569
570
571
572#define EEH_STATE_MIN_WAIT_TIME (1000)
573#define EEH_STATE_MAX_WAIT_TIME (300 * 1000)
574
575 while (1) {
576 ret = pseries_eeh_get_state(pe, &mwait);
577
578
579
580
581
582
583 if (ret != EEH_STATE_UNAVAILABLE)
584 return ret;
585
586 if (max_wait <= 0) {
587 pr_warning("%s: Timeout when getting PE's state (%d)\n",
588 __func__, max_wait);
589 return EEH_STATE_NOT_SUPPORT;
590 }
591
592 if (mwait <= 0) {
593 pr_warning("%s: Firmware returned bad wait value %d\n",
594 __func__, mwait);
595 mwait = EEH_STATE_MIN_WAIT_TIME;
596 } else if (mwait > EEH_STATE_MAX_WAIT_TIME) {
597 pr_warning("%s: Firmware returned too long wait value %d\n",
598 __func__, mwait);
599 mwait = EEH_STATE_MAX_WAIT_TIME;
600 }
601
602 max_wait -= mwait;
603 msleep(mwait);
604 }
605
606 return EEH_STATE_NOT_SUPPORT;
607}
608
609
610
611
612
613
614
615
616
617
618
619
620static int pseries_eeh_get_log(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len)
621{
622 int config_addr;
623 unsigned long flags;
624 int ret;
625
626 spin_lock_irqsave(&slot_errbuf_lock, flags);
627 memset(slot_errbuf, 0, eeh_error_buf_size);
628
629
630 config_addr = pe->config_addr;
631 if (pe->addr)
632 config_addr = pe->addr;
633
634 ret = rtas_call(ibm_slot_error_detail, 8, 1, NULL, config_addr,
635 BUID_HI(pe->phb->buid), BUID_LO(pe->phb->buid),
636 virt_to_phys(drv_log), len,
637 virt_to_phys(slot_errbuf), eeh_error_buf_size,
638 severity);
639 if (!ret)
640 log_error(slot_errbuf, ERR_TYPE_RTAS_LOG, 0);
641 spin_unlock_irqrestore(&slot_errbuf_lock, flags);
642
643 return ret;
644}
645
646
647
648
649
650
651
652
653
654static int pseries_eeh_configure_bridge(struct eeh_pe *pe)
655{
656 int config_addr;
657 int ret;
658
659
660 config_addr = pe->config_addr;
661 if (pe->addr)
662 config_addr = pe->addr;
663
664
665 if (ibm_configure_pe != RTAS_UNKNOWN_SERVICE) {
666 ret = rtas_call(ibm_configure_pe, 3, 1, NULL,
667 config_addr, BUID_HI(pe->phb->buid),
668 BUID_LO(pe->phb->buid));
669 } else if (ibm_configure_bridge != RTAS_UNKNOWN_SERVICE) {
670 ret = rtas_call(ibm_configure_bridge, 3, 1, NULL,
671 config_addr, BUID_HI(pe->phb->buid),
672 BUID_LO(pe->phb->buid));
673 } else {
674 return -EFAULT;
675 }
676
677 if (ret)
678 pr_warning("%s: Unable to configure bridge PHB#%d-PE#%x (%d)\n",
679 __func__, pe->phb->global_number, pe->addr, ret);
680
681 return ret;
682}
683
684
685
686
687
688
689
690
691
692
693static int pseries_eeh_read_config(struct device_node *dn, int where, int size, u32 *val)
694{
695 struct pci_dn *pdn;
696
697 pdn = PCI_DN(dn);
698
699 return rtas_read_config(pdn, where, size, val);
700}
701
702
703
704
705
706
707
708
709
710
711static int pseries_eeh_write_config(struct device_node *dn, int where, int size, u32 val)
712{
713 struct pci_dn *pdn;
714
715 pdn = PCI_DN(dn);
716
717 return rtas_write_config(pdn, where, size, val);
718}
719
720static struct eeh_ops pseries_eeh_ops = {
721 .name = "pseries",
722 .init = pseries_eeh_init,
723 .of_probe = pseries_eeh_of_probe,
724 .dev_probe = NULL,
725 .set_option = pseries_eeh_set_option,
726 .get_pe_addr = pseries_eeh_get_pe_addr,
727 .get_state = pseries_eeh_get_state,
728 .reset = pseries_eeh_reset,
729 .wait_state = pseries_eeh_wait_state,
730 .get_log = pseries_eeh_get_log,
731 .configure_bridge = pseries_eeh_configure_bridge,
732 .read_config = pseries_eeh_read_config,
733 .write_config = pseries_eeh_write_config,
734 .next_error = NULL,
735 .restore_config = NULL
736};
737
738
739
740
741
742
743
744static int __init eeh_pseries_init(void)
745{
746 int ret = -EINVAL;
747
748 if (!machine_is(pseries))
749 return ret;
750
751 ret = eeh_ops_register(&pseries_eeh_ops);
752 if (!ret)
753 pr_info("EEH: pSeries platform initialized\n");
754 else
755 pr_info("EEH: pSeries platform initialization failure (%d)\n",
756 ret);
757
758 return ret;
759}
760
761early_initcall(eeh_pseries_init);
762