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5#include <linux/delay.h>
6#include <linux/dmi.h>
7#include <linux/pci.h>
8#include <linux/vgaarb.h>
9#include <asm/hpet.h>
10#include <asm/pci_x86.h>
11
12static void pci_fixup_i450nx(struct pci_dev *d)
13{
14
15
16
17 int pxb, reg;
18 u8 busno, suba, subb;
19
20 dev_warn(&d->dev, "Searching for i450NX host bridges\n");
21 reg = 0xd0;
22 for(pxb = 0; pxb < 2; pxb++) {
23 pci_read_config_byte(d, reg++, &busno);
24 pci_read_config_byte(d, reg++, &suba);
25 pci_read_config_byte(d, reg++, &subb);
26 dev_dbg(&d->dev, "i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno,
27 suba, subb);
28 if (busno)
29 pcibios_scan_root(busno);
30 if (suba < subb)
31 pcibios_scan_root(suba+1);
32 }
33 pcibios_last_bus = -1;
34}
35DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx);
36
37static void pci_fixup_i450gx(struct pci_dev *d)
38{
39
40
41
42
43 u8 busno;
44 pci_read_config_byte(d, 0x4a, &busno);
45 dev_info(&d->dev, "i440KX/GX host bridge; secondary bus %02x\n", busno);
46 pcibios_scan_root(busno);
47 pcibios_last_bus = -1;
48}
49DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454GX, pci_fixup_i450gx);
50
51static void pci_fixup_umc_ide(struct pci_dev *d)
52{
53
54
55
56
57 int i;
58
59 dev_warn(&d->dev, "Fixing base address flags\n");
60 for(i = 0; i < 4; i++)
61 d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
62}
63DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide);
64
65static void pci_fixup_ncr53c810(struct pci_dev *d)
66{
67
68
69
70
71 if (!d->class) {
72 dev_warn(&d->dev, "Fixing NCR 53C810 class code\n");
73 d->class = PCI_CLASS_STORAGE_SCSI << 8;
74 }
75}
76DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, pci_fixup_ncr53c810);
77
78static void pci_fixup_latency(struct pci_dev *d)
79{
80
81
82
83
84 dev_dbg(&d->dev, "Setting max latency to 32\n");
85 pcibios_max_latency = 32;
86}
87DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency);
88DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency);
89
90static void pci_fixup_piix4_acpi(struct pci_dev *d)
91{
92
93
94
95 d->irq = 9;
96}
97DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, pci_fixup_piix4_acpi);
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115
116#define VIA_8363_KL133_REVISION_ID 0x81
117#define VIA_8363_KM133_REVISION_ID 0x84
118
119static void pci_fixup_via_northbridge_bug(struct pci_dev *d)
120{
121 u8 v;
122 int where = 0x55;
123 int mask = 0x1f;
124
125 if (d->device == PCI_DEVICE_ID_VIA_8367_0) {
126
127
128
129 pci_write_config_byte(d, PCI_LATENCY_TIMER, 0);
130
131 where = 0x95;
132
133 } else if (d->device == PCI_DEVICE_ID_VIA_8363_0 &&
134 (d->revision == VIA_8363_KL133_REVISION_ID ||
135 d->revision == VIA_8363_KM133_REVISION_ID)) {
136 mask = 0x3f;
137
138 }
139
140 pci_read_config_byte(d, where, &v);
141 if (v & ~mask) {
142 dev_warn(&d->dev, "Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x -> %02x\n", \
143 d->device, d->revision, where, v, mask, v & mask);
144 v &= mask;
145 pci_write_config_byte(d, where, v);
146 }
147}
148DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug);
149DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug);
150DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug);
151DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug);
152DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug);
153DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug);
154DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug);
155DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug);
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165
166static void pci_fixup_transparent_bridge(struct pci_dev *dev)
167{
168 if ((dev->device & 0xff00) == 0x2400)
169 dev->transparent = 1;
170}
171DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
172 PCI_CLASS_BRIDGE_PCI, 8, pci_fixup_transparent_bridge);
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185
186static void pci_fixup_nforce2(struct pci_dev *dev)
187{
188 u32 val;
189
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197
198 pci_read_config_dword(dev, 0x6c, &val);
199
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203 if ((val & 0x00FF0000) != 0x00010000) {
204 dev_warn(&dev->dev, "nForce2 C1 Halt Disconnect fixup\n");
205 pci_write_config_dword(dev, 0x6c, (val & 0xFF00FFFF) | 0x00010000);
206 }
207}
208DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);
209DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);
210
211
212#define MAX_PCIEROOT 6
213static int quirk_aspm_offset[MAX_PCIEROOT << 3];
214
215#define GET_INDEX(a, b) ((((a) - PCI_DEVICE_ID_INTEL_MCH_PA) << 3) + ((b) & 7))
216
217static int quirk_pcie_aspm_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
218{
219 return raw_pci_read(pci_domain_nr(bus), bus->number,
220 devfn, where, size, value);
221}
222
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225
226
227static int quirk_pcie_aspm_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
228{
229 u8 offset;
230
231 offset = quirk_aspm_offset[GET_INDEX(bus->self->device, devfn)];
232
233 if ((offset) && (where == offset))
234 value = value & ~PCI_EXP_LNKCTL_ASPMC;
235
236 return raw_pci_write(pci_domain_nr(bus), bus->number,
237 devfn, where, size, value);
238}
239
240static struct pci_ops quirk_pcie_aspm_ops = {
241 .read = quirk_pcie_aspm_read,
242 .write = quirk_pcie_aspm_write,
243};
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252
253static void pcie_rootport_aspm_quirk(struct pci_dev *pdev)
254{
255 int i;
256 struct pci_bus *pbus;
257 struct pci_dev *dev;
258
259 if ((pbus = pdev->subordinate) == NULL)
260 return;
261
262
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265
266
267 if ((pdev->device < PCI_DEVICE_ID_INTEL_MCH_PA) ||
268 (pdev->device > PCI_DEVICE_ID_INTEL_MCH_PC1))
269 return;
270
271 if (list_empty(&pbus->devices)) {
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278 for (i = GET_INDEX(pdev->device, 0); i <= GET_INDEX(pdev->device, 7); ++i)
279 quirk_aspm_offset[i] = 0;
280
281 pci_bus_set_ops(pbus, pbus->parent->ops);
282 } else {
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289 list_for_each_entry(dev, &pbus->devices, bus_list)
290
291 quirk_aspm_offset[GET_INDEX(pdev->device, dev->devfn)] =
292 dev->pcie_cap + PCI_EXP_LNKCTL;
293
294 pci_bus_set_ops(pbus, &quirk_pcie_aspm_ops);
295 dev_info(&pbus->dev, "writes to ASPM control bits will be ignored\n");
296 }
297
298}
299DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PA, pcie_rootport_aspm_quirk);
300DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PA1, pcie_rootport_aspm_quirk);
301DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PB, pcie_rootport_aspm_quirk);
302DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PB1, pcie_rootport_aspm_quirk);
303DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PC, pcie_rootport_aspm_quirk);
304DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PC1, pcie_rootport_aspm_quirk);
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322
323static void pci_fixup_video(struct pci_dev *pdev)
324{
325 struct pci_dev *bridge;
326 struct pci_bus *bus;
327 u16 config;
328
329
330 bus = pdev->bus;
331 while (bus) {
332 bridge = bus->self;
333
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338
339
340
341 if (bridge && (pci_is_bridge(bridge))) {
342 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
343 &config);
344 if (!(config & PCI_BRIDGE_CTL_VGA))
345 return;
346 }
347 bus = bus->parent;
348 }
349 if (!vga_default_device() || pdev == vga_default_device()) {
350 pci_read_config_word(pdev, PCI_COMMAND, &config);
351 if (config & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
352 pdev->resource[PCI_ROM_RESOURCE].flags |= IORESOURCE_ROM_SHADOW;
353 dev_printk(KERN_DEBUG, &pdev->dev, "Boot video device\n");
354 vga_set_default_device(pdev);
355 }
356 }
357}
358DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
359 PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_video);
360
361
362static const struct dmi_system_id msi_k8t_dmi_table[] = {
363 {
364 .ident = "MSI-K8T-Neo2Fir",
365 .matches = {
366 DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
367 DMI_MATCH(DMI_PRODUCT_NAME, "MS-6702E"),
368 },
369 },
370 {}
371};
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383static void pci_fixup_msi_k8t_onboard_sound(struct pci_dev *dev)
384{
385 unsigned char val;
386 if (!dmi_check_system(msi_k8t_dmi_table))
387 return;
388
389 pci_read_config_byte(dev, 0x50, &val);
390 if (val & 0x40) {
391 pci_write_config_byte(dev, 0x50, val & (~0x40));
392
393
394 pci_read_config_byte(dev, 0x50, &val);
395 if (val & 0x40)
396 dev_info(&dev->dev, "Detected MSI K8T Neo2-FIR; "
397 "can't enable onboard soundcard!\n");
398 else
399 dev_info(&dev->dev, "Detected MSI K8T Neo2-FIR; "
400 "enabled onboard soundcard\n");
401 }
402}
403DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
404 pci_fixup_msi_k8t_onboard_sound);
405DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
406 pci_fixup_msi_k8t_onboard_sound);
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416
417static u16 toshiba_line_size;
418
419static const struct dmi_system_id toshiba_ohci1394_dmi_table[] = {
420 {
421 .ident = "Toshiba PS5 based laptop",
422 .matches = {
423 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
424 DMI_MATCH(DMI_PRODUCT_VERSION, "PS5"),
425 },
426 },
427 {
428 .ident = "Toshiba PSM4 based laptop",
429 .matches = {
430 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
431 DMI_MATCH(DMI_PRODUCT_VERSION, "PSM4"),
432 },
433 },
434 {
435 .ident = "Toshiba A40 based laptop",
436 .matches = {
437 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
438 DMI_MATCH(DMI_PRODUCT_VERSION, "PSA40U"),
439 },
440 },
441 { }
442};
443
444static void pci_pre_fixup_toshiba_ohci1394(struct pci_dev *dev)
445{
446 if (!dmi_check_system(toshiba_ohci1394_dmi_table))
447 return;
448
449 dev->current_state = PCI_D3cold;
450 pci_read_config_word(dev, PCI_CACHE_LINE_SIZE, &toshiba_line_size);
451}
452DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0x8032,
453 pci_pre_fixup_toshiba_ohci1394);
454
455static void pci_post_fixup_toshiba_ohci1394(struct pci_dev *dev)
456{
457 if (!dmi_check_system(toshiba_ohci1394_dmi_table))
458 return;
459
460
461 pci_write_config_word(dev, PCI_CACHE_LINE_SIZE, toshiba_line_size);
462 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, (u8 *)&dev->irq);
463 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
464 pci_resource_start(dev, 0));
465 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
466 pci_resource_start(dev, 1));
467}
468DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_TI, 0x8032,
469 pci_post_fixup_toshiba_ohci1394);
470
471
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473
474
475
476static void pci_early_fixup_cyrix_5530(struct pci_dev *dev)
477{
478 u8 r;
479
480 pci_read_config_byte(dev, 0x42, &r);
481 r &= 0xfd;
482 pci_write_config_byte(dev, 0x42, r);
483}
484DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY,
485 pci_early_fixup_cyrix_5530);
486DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY,
487 pci_early_fixup_cyrix_5530);
488
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492
493static void pci_siemens_interrupt_controller(struct pci_dev *dev)
494{
495 dev->resource[0].flags |= IORESOURCE_PCI_FIXED;
496}
497DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SIEMENS, 0x0015,
498 pci_siemens_interrupt_controller);
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503
504static void sb600_disable_hpet_bar(struct pci_dev *dev)
505{
506 u8 val;
507
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514
515 pci_read_config_byte(dev, 0x08, &val);
516
517 if (val < 0x2F) {
518 outb(0x55, 0xCD6);
519 val = inb(0xCD7);
520
521
522 outb(0x55, 0xCD6);
523 outb(val | 0x80, 0xCD7);
524 }
525}
526DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x4385, sb600_disable_hpet_bar);
527
528#ifdef CONFIG_HPET_TIMER
529static void sb600_hpet_quirk(struct pci_dev *dev)
530{
531 struct resource *r = &dev->resource[1];
532
533 if (r->flags & IORESOURCE_MEM && r->start == hpet_address) {
534 r->flags |= IORESOURCE_PCI_FIXED;
535 dev_info(&dev->dev, "reg 0x14 contains HPET; making it immovable\n");
536 }
537}
538DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x4385, sb600_hpet_quirk);
539#endif
540
541
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547
548
549static void twinhead_reserve_killing_zone(struct pci_dev *dev)
550{
551 if (dev->subsystem_vendor == 0x14FF && dev->subsystem_device == 0xA003) {
552 pr_info("Reserving memory on Twinhead H12Y\n");
553 request_mem_region(0xFFB00000, 0x100000, "twinhead");
554 }
555}
556DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x27B9, twinhead_reserve_killing_zone);
557