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21#ifndef __MTIP32XX_H__
22#define __MTIP32XX_H__
23
24#include <linux/spinlock.h>
25#include <linux/rwsem.h>
26#include <linux/ata.h>
27#include <linux/interrupt.h>
28#include <linux/genhd.h>
29
30
31#define PCI_SUBSYSTEM_DEVICEID 0x2E
32
33
34#define PCIE_CONFIG_EXT_DEVICE_CONTROL_OFFSET 0x48
35
36
37#define MTIP_SEC_ERASE_MODE 0x2
38
39
40#define MTIP_MAX_RETRIES 2
41
42
43#define MTIP_NCQ_CMD_TIMEOUT_MS 15000
44#define MTIP_IOCTL_CMD_TIMEOUT_MS 5000
45#define MTIP_INT_CMD_TIMEOUT_MS 5000
46#define MTIP_QUIESCE_IO_TIMEOUT_MS (MTIP_NCQ_CMD_TIMEOUT_MS * \
47 (MTIP_MAX_RETRIES + 1))
48
49
50#define MTIP_TIMEOUT_CHECK_PERIOD 500
51
52
53#define MTIP_FTL_REBUILD_OFFSET 142
54#define MTIP_FTL_REBUILD_MAGIC 0xED51
55#define MTIP_FTL_REBUILD_TIMEOUT_MS 2400000
56
57
58#define MTIP_MAX_UNALIGNED_SLOTS 2
59
60
61#define MTIP_TAG_BIT(tag) (tag & 0x1F)
62
63
64
65
66
67
68#define MTIP_TAG_INDEX(tag) (tag >> 5)
69
70
71
72
73
74#define MTIP_MAX_SG 504
75
76
77
78
79
80#define MTIP_MAX_SLOT_GROUPS 8
81
82
83#define MTIP_TAG_INTERNAL 0
84
85
86#define PCI_VENDOR_ID_MICRON 0x1344
87#define P320H_DEVICE_ID 0x5150
88#define P320M_DEVICE_ID 0x5151
89#define P320S_DEVICE_ID 0x5152
90#define P325M_DEVICE_ID 0x5153
91#define P420H_DEVICE_ID 0x5160
92#define P420M_DEVICE_ID 0x5161
93#define P425M_DEVICE_ID 0x5163
94
95
96#define MTIP_DRV_NAME "mtip32xx"
97#define MTIP_DRV_VERSION "1.3.1"
98
99
100#define MTIP_MAX_MINORS 16
101
102
103#define MTIP_MAX_COMMAND_SLOTS (MTIP_MAX_SLOT_GROUPS * 32)
104
105
106
107
108
109
110
111
112
113#define U32_PER_LONG (sizeof(long) / sizeof(u32))
114#define SLOTBITS_IN_LONGS ((MTIP_MAX_SLOT_GROUPS + \
115 (U32_PER_LONG-1))/U32_PER_LONG)
116
117
118#define MTIP_ABAR 5
119
120#ifdef DEBUG
121 #define dbg_printk(format, arg...) \
122 printk(pr_fmt(format), ##arg);
123#else
124 #define dbg_printk(format, arg...)
125#endif
126
127#define MTIP_DFS_MAX_BUF_SIZE 1024
128
129#define __force_bit2int (unsigned int __force)
130
131enum {
132
133 MTIP_PF_IC_ACTIVE_BIT = 0,
134 MTIP_PF_EH_ACTIVE_BIT = 1,
135 MTIP_PF_SE_ACTIVE_BIT = 2,
136 MTIP_PF_DM_ACTIVE_BIT = 3,
137 MTIP_PF_PAUSE_IO = ((1 << MTIP_PF_IC_ACTIVE_BIT) |
138 (1 << MTIP_PF_EH_ACTIVE_BIT) |
139 (1 << MTIP_PF_SE_ACTIVE_BIT) |
140 (1 << MTIP_PF_DM_ACTIVE_BIT)),
141
142 MTIP_PF_SVC_THD_ACTIVE_BIT = 4,
143 MTIP_PF_ISSUE_CMDS_BIT = 5,
144 MTIP_PF_REBUILD_BIT = 6,
145 MTIP_PF_SR_CLEANUP_BIT = 7,
146 MTIP_PF_SVC_THD_STOP_BIT = 8,
147
148
149 MTIP_DDF_SEC_LOCK_BIT = 0,
150 MTIP_DDF_REMOVE_PENDING_BIT = 1,
151 MTIP_DDF_OVER_TEMP_BIT = 2,
152 MTIP_DDF_WRITE_PROTECT_BIT = 3,
153 MTIP_DDF_REMOVE_DONE_BIT = 4,
154 MTIP_DDF_CLEANUP_BIT = 5,
155 MTIP_DDF_RESUME_BIT = 6,
156 MTIP_DDF_INIT_DONE_BIT = 7,
157 MTIP_DDF_REBUILD_FAILED_BIT = 8,
158
159 MTIP_DDF_STOP_IO = ((1 << MTIP_DDF_REMOVE_PENDING_BIT) |
160 (1 << MTIP_DDF_SEC_LOCK_BIT) |
161 (1 << MTIP_DDF_OVER_TEMP_BIT) |
162 (1 << MTIP_DDF_WRITE_PROTECT_BIT) |
163 (1 << MTIP_DDF_REBUILD_FAILED_BIT)),
164
165};
166
167struct smart_attr {
168 u8 attr_id;
169 u16 flags;
170 u8 cur;
171 u8 worst;
172 u32 data;
173 u8 res[3];
174} __packed;
175
176struct mtip_work {
177 struct work_struct work;
178 void *port;
179 int cpu_binding;
180 u32 completed;
181} ____cacheline_aligned_in_smp;
182
183#define DEFINE_HANDLER(group) \
184 void mtip_workq_sdbf##group(struct work_struct *work) \
185 { \
186 struct mtip_work *w = (struct mtip_work *) work; \
187 mtip_workq_sdbfx(w->port, group, w->completed); \
188 }
189
190#define MTIP_TRIM_TIMEOUT_MS 240000
191#define MTIP_MAX_TRIM_ENTRIES 8
192#define MTIP_MAX_TRIM_ENTRY_LEN 0xfff8
193
194struct mtip_trim_entry {
195 u32 lba;
196 u16 rsvd;
197 u16 range;
198} __packed;
199
200struct mtip_trim {
201
202 struct mtip_trim_entry entry[MTIP_MAX_TRIM_ENTRIES];
203} __packed;
204
205
206struct host_to_dev_fis {
207
208
209
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211
212
213
214
215
216
217
218 unsigned char type;
219 unsigned char opts;
220 unsigned char command;
221 unsigned char features;
222
223 union {
224 unsigned char lba_low;
225 unsigned char sector;
226 };
227 union {
228 unsigned char lba_mid;
229 unsigned char cyl_low;
230 };
231 union {
232 unsigned char lba_hi;
233 unsigned char cyl_hi;
234 };
235 union {
236 unsigned char device;
237 unsigned char head;
238 };
239
240 union {
241 unsigned char lba_low_ex;
242 unsigned char sector_ex;
243 };
244 union {
245 unsigned char lba_mid_ex;
246 unsigned char cyl_low_ex;
247 };
248 union {
249 unsigned char lba_hi_ex;
250 unsigned char cyl_hi_ex;
251 };
252 unsigned char features_ex;
253
254 unsigned char sect_count;
255 unsigned char sect_cnt_ex;
256 unsigned char res2;
257 unsigned char control;
258
259 unsigned int res3;
260};
261
262
263struct mtip_cmd_hdr {
264
265
266
267
268
269
270
271
272
273 unsigned int opts;
274
275 union {
276 unsigned int byte_count;
277 unsigned int status;
278 };
279
280
281
282
283 unsigned int ctba;
284
285
286
287
288 unsigned int ctbau;
289
290 unsigned int res[4];
291};
292
293
294struct mtip_cmd_sg {
295
296
297
298
299
300 unsigned int dba;
301
302
303
304
305 unsigned int dba_upper;
306
307 unsigned int reserved;
308
309
310
311
312
313
314 unsigned int info;
315};
316struct mtip_port;
317
318
319struct mtip_cmd {
320
321 struct mtip_cmd_hdr *command_header;
322
323 dma_addr_t command_header_dma;
324
325 void *command;
326
327 dma_addr_t command_dma;
328
329 void *comp_data;
330
331
332
333
334 void (*comp_func)(struct mtip_port *port,
335 int tag,
336 struct mtip_cmd *cmd,
337 int status);
338
339 int scatter_ents;
340
341 int unaligned;
342
343 struct scatterlist sg[MTIP_MAX_SG];
344
345 int retries;
346
347 int direction;
348};
349
350
351struct mtip_port {
352
353 struct driver_data *dd;
354
355
356
357
358 unsigned long identify_valid;
359
360 void __iomem *mmio;
361
362 void __iomem *s_active[MTIP_MAX_SLOT_GROUPS];
363
364 void __iomem *completed[MTIP_MAX_SLOT_GROUPS];
365
366 void __iomem *cmd_issue[MTIP_MAX_SLOT_GROUPS];
367
368
369
370
371 void *command_list;
372
373
374
375
376 dma_addr_t command_list_dma;
377
378
379
380
381 void *rxfis;
382
383
384
385
386 dma_addr_t rxfis_dma;
387
388
389
390 void *block1;
391
392
393
394 dma_addr_t block1_dma;
395
396
397
398
399 u16 *identify;
400
401
402
403
404 dma_addr_t identify_dma;
405
406
407
408
409 u16 *sector_buffer;
410
411
412
413
414 dma_addr_t sector_buffer_dma;
415
416
417
418
419
420
421 u16 *log_buf;
422 dma_addr_t log_buf_dma;
423
424 u8 *smart_buf;
425 dma_addr_t smart_buf_dma;
426
427 unsigned long allocated[SLOTBITS_IN_LONGS];
428
429
430
431
432 unsigned long cmds_to_issue[SLOTBITS_IN_LONGS];
433
434 wait_queue_head_t svc_wait;
435
436
437
438
439 unsigned long flags;
440
441
442
443 unsigned long ic_pause_timer;
444
445
446 struct semaphore cmd_slot_unal;
447
448
449 spinlock_t cmd_issue_lock[MTIP_MAX_SLOT_GROUPS];
450};
451
452
453
454
455
456
457struct driver_data {
458 void __iomem *mmio;
459
460 int major;
461
462 int instance;
463
464 struct gendisk *disk;
465
466 struct pci_dev *pdev;
467
468 struct request_queue *queue;
469
470 struct blk_mq_tag_set tags;
471
472 struct mtip_port *port;
473
474 unsigned product_type;
475
476 unsigned slot_groups;
477
478 unsigned long index;
479
480 unsigned long dd_flag;
481
482 struct task_struct *mtip_svc_handler;
483
484 struct dentry *dfs_node;
485
486 bool trim_supp;
487
488 bool sr;
489
490 int numa_node;
491
492 char workq_name[32];
493
494 struct workqueue_struct *isr_workq;
495
496 atomic_t irq_workers_active;
497
498 struct mtip_work work[MTIP_MAX_SLOT_GROUPS];
499
500 int isr_binding;
501
502 struct block_device *bdev;
503
504 struct list_head online_list;
505
506 struct list_head remove_list;
507
508 int unal_qdepth;
509};
510
511#endif
512