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22#include <linux/platform_device.h>
23#include <linux/slab.h>
24#include "tpm.h"
25
26
27enum tpm_nsc_addr{
28 TPM_NSC_IRQ = 0x07,
29 TPM_NSC_BASE0_HI = 0x60,
30 TPM_NSC_BASE0_LO = 0x61,
31 TPM_NSC_BASE1_HI = 0x62,
32 TPM_NSC_BASE1_LO = 0x63
33};
34
35enum tpm_nsc_index {
36 NSC_LDN_INDEX = 0x07,
37 NSC_SID_INDEX = 0x20,
38 NSC_LDC_INDEX = 0x30,
39 NSC_DIO_INDEX = 0x60,
40 NSC_CIO_INDEX = 0x62,
41 NSC_IRQ_INDEX = 0x70,
42 NSC_ITS_INDEX = 0x71
43};
44
45enum tpm_nsc_status_loc {
46 NSC_STATUS = 0x01,
47 NSC_COMMAND = 0x01,
48 NSC_DATA = 0x00
49};
50
51
52enum tpm_nsc_status {
53 NSC_STATUS_OBF = 0x01,
54 NSC_STATUS_IBF = 0x02,
55 NSC_STATUS_F0 = 0x04,
56 NSC_STATUS_A2 = 0x08,
57 NSC_STATUS_RDY = 0x10,
58 NSC_STATUS_IBR = 0x20
59};
60
61
62enum tpm_nsc_cmd_mode {
63 NSC_COMMAND_NORMAL = 0x01,
64 NSC_COMMAND_EOC = 0x03,
65 NSC_COMMAND_CANCEL = 0x22
66};
67
68
69
70static int wait_for_stat(struct tpm_chip *chip, u8 mask, u8 val, u8 * data)
71{
72 unsigned long stop;
73
74
75 *data = inb(chip->vendor.base + NSC_STATUS);
76 if ((*data & mask) == val)
77 return 0;
78
79
80 stop = jiffies + 10 * HZ;
81 do {
82 msleep(TPM_TIMEOUT);
83 *data = inb(chip->vendor.base + 1);
84 if ((*data & mask) == val)
85 return 0;
86 }
87 while (time_before(jiffies, stop));
88
89 return -EBUSY;
90}
91
92static int nsc_wait_for_ready(struct tpm_chip *chip)
93{
94 int status;
95 unsigned long stop;
96
97
98 status = inb(chip->vendor.base + NSC_STATUS);
99 if (status & NSC_STATUS_OBF)
100 status = inb(chip->vendor.base + NSC_DATA);
101 if (status & NSC_STATUS_RDY)
102 return 0;
103
104
105 stop = jiffies + 100;
106 do {
107 msleep(TPM_TIMEOUT);
108 status = inb(chip->vendor.base + NSC_STATUS);
109 if (status & NSC_STATUS_OBF)
110 status = inb(chip->vendor.base + NSC_DATA);
111 if (status & NSC_STATUS_RDY)
112 return 0;
113 }
114 while (time_before(jiffies, stop));
115
116 dev_info(chip->dev, "wait for ready failed\n");
117 return -EBUSY;
118}
119
120
121static int tpm_nsc_recv(struct tpm_chip *chip, u8 * buf, size_t count)
122{
123 u8 *buffer = buf;
124 u8 data, *p;
125 u32 size;
126 __be32 *native_size;
127
128 if (count < 6)
129 return -EIO;
130
131 if (wait_for_stat(chip, NSC_STATUS_F0, NSC_STATUS_F0, &data) < 0) {
132 dev_err(chip->dev, "F0 timeout\n");
133 return -EIO;
134 }
135 if ((data =
136 inb(chip->vendor.base + NSC_DATA)) != NSC_COMMAND_NORMAL) {
137 dev_err(chip->dev, "not in normal mode (0x%x)\n",
138 data);
139 return -EIO;
140 }
141
142
143 for (p = buffer; p < &buffer[count]; p++) {
144 if (wait_for_stat
145 (chip, NSC_STATUS_OBF, NSC_STATUS_OBF, &data) < 0) {
146 dev_err(chip->dev,
147 "OBF timeout (while reading data)\n");
148 return -EIO;
149 }
150 if (data & NSC_STATUS_F0)
151 break;
152 *p = inb(chip->vendor.base + NSC_DATA);
153 }
154
155 if ((data & NSC_STATUS_F0) == 0 &&
156 (wait_for_stat(chip, NSC_STATUS_F0, NSC_STATUS_F0, &data) < 0)) {
157 dev_err(chip->dev, "F0 not set\n");
158 return -EIO;
159 }
160 if ((data = inb(chip->vendor.base + NSC_DATA)) != NSC_COMMAND_EOC) {
161 dev_err(chip->dev,
162 "expected end of command(0x%x)\n", data);
163 return -EIO;
164 }
165
166 native_size = (__force __be32 *) (buf + 2);
167 size = be32_to_cpu(*native_size);
168
169 if (count < size)
170 return -EIO;
171
172 return size;
173}
174
175static int tpm_nsc_send(struct tpm_chip *chip, u8 * buf, size_t count)
176{
177 u8 data;
178 int i;
179
180
181
182
183
184
185
186 outb(NSC_COMMAND_CANCEL, chip->vendor.base + NSC_COMMAND);
187
188 if (nsc_wait_for_ready(chip) != 0)
189 return -EIO;
190
191 if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
192 dev_err(chip->dev, "IBF timeout\n");
193 return -EIO;
194 }
195
196 outb(NSC_COMMAND_NORMAL, chip->vendor.base + NSC_COMMAND);
197 if (wait_for_stat(chip, NSC_STATUS_IBR, NSC_STATUS_IBR, &data) < 0) {
198 dev_err(chip->dev, "IBR timeout\n");
199 return -EIO;
200 }
201
202 for (i = 0; i < count; i++) {
203 if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
204 dev_err(chip->dev,
205 "IBF timeout (while writing data)\n");
206 return -EIO;
207 }
208 outb(buf[i], chip->vendor.base + NSC_DATA);
209 }
210
211 if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
212 dev_err(chip->dev, "IBF timeout\n");
213 return -EIO;
214 }
215 outb(NSC_COMMAND_EOC, chip->vendor.base + NSC_COMMAND);
216
217 return count;
218}
219
220static void tpm_nsc_cancel(struct tpm_chip *chip)
221{
222 outb(NSC_COMMAND_CANCEL, chip->vendor.base + NSC_COMMAND);
223}
224
225static u8 tpm_nsc_status(struct tpm_chip *chip)
226{
227 return inb(chip->vendor.base + NSC_STATUS);
228}
229
230static bool tpm_nsc_req_canceled(struct tpm_chip *chip, u8 status)
231{
232 return (status == NSC_STATUS_RDY);
233}
234
235static const struct tpm_class_ops tpm_nsc = {
236 .recv = tpm_nsc_recv,
237 .send = tpm_nsc_send,
238 .cancel = tpm_nsc_cancel,
239 .status = tpm_nsc_status,
240 .req_complete_mask = NSC_STATUS_OBF,
241 .req_complete_val = NSC_STATUS_OBF,
242 .req_canceled = tpm_nsc_req_canceled,
243};
244
245static struct platform_device *pdev = NULL;
246
247static void tpm_nsc_remove(struct device *dev)
248{
249 struct tpm_chip *chip = dev_get_drvdata(dev);
250 if ( chip ) {
251 release_region(chip->vendor.base, 2);
252 tpm_remove_hardware(chip->dev);
253 }
254}
255
256static SIMPLE_DEV_PM_OPS(tpm_nsc_pm, tpm_pm_suspend, tpm_pm_resume);
257
258static struct platform_driver nsc_drv = {
259 .driver = {
260 .name = "tpm_nsc",
261 .owner = THIS_MODULE,
262 .pm = &tpm_nsc_pm,
263 },
264};
265
266static int __init init_nsc(void)
267{
268 int rc = 0;
269 int lo, hi, err;
270 int nscAddrBase = TPM_ADDR;
271 struct tpm_chip *chip;
272 unsigned long base;
273
274
275 if (tpm_read_index(TPM_ADDR, NSC_SID_INDEX) != 0xEF) {
276 nscAddrBase = (tpm_read_index(TPM_SUPERIO_ADDR, 0x2C)<<8)|
277 (tpm_read_index(TPM_SUPERIO_ADDR, 0x2B)&0xFE);
278 if (tpm_read_index(nscAddrBase, NSC_SID_INDEX) != 0xF6)
279 return -ENODEV;
280 }
281
282 err = platform_driver_register(&nsc_drv);
283 if (err)
284 return err;
285
286 hi = tpm_read_index(nscAddrBase, TPM_NSC_BASE0_HI);
287 lo = tpm_read_index(nscAddrBase, TPM_NSC_BASE0_LO);
288 base = (hi<<8) | lo;
289
290
291 tpm_write_index(nscAddrBase, NSC_LDC_INDEX, 0x01);
292
293 pdev = platform_device_alloc("tpm_nscl0", -1);
294 if (!pdev) {
295 rc = -ENOMEM;
296 goto err_unreg_drv;
297 }
298
299 pdev->num_resources = 0;
300 pdev->dev.driver = &nsc_drv.driver;
301 pdev->dev.release = tpm_nsc_remove;
302
303 if ((rc = platform_device_add(pdev)) < 0)
304 goto err_put_dev;
305
306 if (request_region(base, 2, "tpm_nsc0") == NULL ) {
307 rc = -EBUSY;
308 goto err_del_dev;
309 }
310
311 if (!(chip = tpm_register_hardware(&pdev->dev, &tpm_nsc))) {
312 rc = -ENODEV;
313 goto err_rel_reg;
314 }
315
316 dev_dbg(&pdev->dev, "NSC TPM detected\n");
317 dev_dbg(&pdev->dev,
318 "NSC LDN 0x%x, SID 0x%x, SRID 0x%x\n",
319 tpm_read_index(nscAddrBase,0x07), tpm_read_index(nscAddrBase,0x20),
320 tpm_read_index(nscAddrBase,0x27));
321 dev_dbg(&pdev->dev,
322 "NSC SIOCF1 0x%x SIOCF5 0x%x SIOCF6 0x%x SIOCF8 0x%x\n",
323 tpm_read_index(nscAddrBase,0x21), tpm_read_index(nscAddrBase,0x25),
324 tpm_read_index(nscAddrBase,0x26), tpm_read_index(nscAddrBase,0x28));
325 dev_dbg(&pdev->dev, "NSC IO Base0 0x%x\n",
326 (tpm_read_index(nscAddrBase,0x60) << 8) | tpm_read_index(nscAddrBase,0x61));
327 dev_dbg(&pdev->dev, "NSC IO Base1 0x%x\n",
328 (tpm_read_index(nscAddrBase,0x62) << 8) | tpm_read_index(nscAddrBase,0x63));
329 dev_dbg(&pdev->dev, "NSC Interrupt number and wakeup 0x%x\n",
330 tpm_read_index(nscAddrBase,0x70));
331 dev_dbg(&pdev->dev, "NSC IRQ type select 0x%x\n",
332 tpm_read_index(nscAddrBase,0x71));
333 dev_dbg(&pdev->dev,
334 "NSC DMA channel select0 0x%x, select1 0x%x\n",
335 tpm_read_index(nscAddrBase,0x74), tpm_read_index(nscAddrBase,0x75));
336 dev_dbg(&pdev->dev,
337 "NSC Config "
338 "0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
339 tpm_read_index(nscAddrBase,0xF0), tpm_read_index(nscAddrBase,0xF1),
340 tpm_read_index(nscAddrBase,0xF2), tpm_read_index(nscAddrBase,0xF3),
341 tpm_read_index(nscAddrBase,0xF4), tpm_read_index(nscAddrBase,0xF5),
342 tpm_read_index(nscAddrBase,0xF6), tpm_read_index(nscAddrBase,0xF7),
343 tpm_read_index(nscAddrBase,0xF8), tpm_read_index(nscAddrBase,0xF9));
344
345 dev_info(&pdev->dev,
346 "NSC TPM revision %d\n",
347 tpm_read_index(nscAddrBase, 0x27) & 0x1F);
348
349 chip->vendor.base = base;
350
351 return 0;
352
353err_rel_reg:
354 release_region(base, 2);
355err_del_dev:
356 platform_device_del(pdev);
357err_put_dev:
358 platform_device_put(pdev);
359err_unreg_drv:
360 platform_driver_unregister(&nsc_drv);
361 return rc;
362}
363
364static void __exit cleanup_nsc(void)
365{
366 if (pdev) {
367 tpm_nsc_remove(&pdev->dev);
368 platform_device_unregister(pdev);
369 }
370
371 platform_driver_unregister(&nsc_drv);
372}
373
374module_init(init_nsc);
375module_exit(cleanup_nsc);
376
377MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)");
378MODULE_DESCRIPTION("TPM Driver");
379MODULE_VERSION("2.0");
380MODULE_LICENSE("GPL");
381
