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16#include <linux/clk.h>
17#include <linux/clockchips.h>
18#include <linux/clocksource.h>
19#include <linux/delay.h>
20#include <linux/err.h>
21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/io.h>
24#include <linux/ioport.h>
25#include <linux/irq.h>
26#include <linux/module.h>
27#include <linux/platform_device.h>
28#include <linux/pm_domain.h>
29#include <linux/pm_runtime.h>
30#include <linux/sh_timer.h>
31#include <linux/slab.h>
32#include <linux/spinlock.h>
33
34struct sh_cmt_device;
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64
65enum sh_cmt_model {
66 SH_CMT_16BIT,
67 SH_CMT_32BIT,
68 SH_CMT_32BIT_FAST,
69 SH_CMT_48BIT,
70 SH_CMT_48BIT_GEN2,
71};
72
73struct sh_cmt_info {
74 enum sh_cmt_model model;
75
76 unsigned long width;
77 unsigned long overflow_bit;
78 unsigned long clear_bits;
79
80
81 unsigned long (*read_control)(void __iomem *base, unsigned long offs);
82 void (*write_control)(void __iomem *base, unsigned long offs,
83 unsigned long value);
84
85
86 unsigned long (*read_count)(void __iomem *base, unsigned long offs);
87 void (*write_count)(void __iomem *base, unsigned long offs,
88 unsigned long value);
89};
90
91struct sh_cmt_channel {
92 struct sh_cmt_device *cmt;
93
94 unsigned int index;
95 unsigned int hwidx;
96
97 void __iomem *iostart;
98 void __iomem *ioctrl;
99
100 unsigned int timer_bit;
101 unsigned long flags;
102 unsigned long match_value;
103 unsigned long next_match_value;
104 unsigned long max_match_value;
105 unsigned long rate;
106 raw_spinlock_t lock;
107 struct clock_event_device ced;
108 struct clocksource cs;
109 unsigned long total_cycles;
110 bool cs_enabled;
111};
112
113struct sh_cmt_device {
114 struct platform_device *pdev;
115
116 const struct sh_cmt_info *info;
117 bool legacy;
118
119 void __iomem *mapbase_ch;
120 void __iomem *mapbase;
121 struct clk *clk;
122
123 struct sh_cmt_channel *channels;
124 unsigned int num_channels;
125
126 bool has_clockevent;
127 bool has_clocksource;
128};
129
130#define SH_CMT16_CMCSR_CMF (1 << 7)
131#define SH_CMT16_CMCSR_CMIE (1 << 6)
132#define SH_CMT16_CMCSR_CKS8 (0 << 0)
133#define SH_CMT16_CMCSR_CKS32 (1 << 0)
134#define SH_CMT16_CMCSR_CKS128 (2 << 0)
135#define SH_CMT16_CMCSR_CKS512 (3 << 0)
136#define SH_CMT16_CMCSR_CKS_MASK (3 << 0)
137
138#define SH_CMT32_CMCSR_CMF (1 << 15)
139#define SH_CMT32_CMCSR_OVF (1 << 14)
140#define SH_CMT32_CMCSR_WRFLG (1 << 13)
141#define SH_CMT32_CMCSR_STTF (1 << 12)
142#define SH_CMT32_CMCSR_STPF (1 << 11)
143#define SH_CMT32_CMCSR_SSIE (1 << 10)
144#define SH_CMT32_CMCSR_CMS (1 << 9)
145#define SH_CMT32_CMCSR_CMM (1 << 8)
146#define SH_CMT32_CMCSR_CMTOUT_IE (1 << 7)
147#define SH_CMT32_CMCSR_CMR_NONE (0 << 4)
148#define SH_CMT32_CMCSR_CMR_DMA (1 << 4)
149#define SH_CMT32_CMCSR_CMR_IRQ (2 << 4)
150#define SH_CMT32_CMCSR_CMR_MASK (3 << 4)
151#define SH_CMT32_CMCSR_DBGIVD (1 << 3)
152#define SH_CMT32_CMCSR_CKS_RCLK8 (4 << 0)
153#define SH_CMT32_CMCSR_CKS_RCLK32 (5 << 0)
154#define SH_CMT32_CMCSR_CKS_RCLK128 (6 << 0)
155#define SH_CMT32_CMCSR_CKS_RCLK1 (7 << 0)
156#define SH_CMT32_CMCSR_CKS_MASK (7 << 0)
157
158static unsigned long sh_cmt_read16(void __iomem *base, unsigned long offs)
159{
160 return ioread16(base + (offs << 1));
161}
162
163static unsigned long sh_cmt_read32(void __iomem *base, unsigned long offs)
164{
165 return ioread32(base + (offs << 2));
166}
167
168static void sh_cmt_write16(void __iomem *base, unsigned long offs,
169 unsigned long value)
170{
171 iowrite16(value, base + (offs << 1));
172}
173
174static void sh_cmt_write32(void __iomem *base, unsigned long offs,
175 unsigned long value)
176{
177 iowrite32(value, base + (offs << 2));
178}
179
180static const struct sh_cmt_info sh_cmt_info[] = {
181 [SH_CMT_16BIT] = {
182 .model = SH_CMT_16BIT,
183 .width = 16,
184 .overflow_bit = SH_CMT16_CMCSR_CMF,
185 .clear_bits = ~SH_CMT16_CMCSR_CMF,
186 .read_control = sh_cmt_read16,
187 .write_control = sh_cmt_write16,
188 .read_count = sh_cmt_read16,
189 .write_count = sh_cmt_write16,
190 },
191 [SH_CMT_32BIT] = {
192 .model = SH_CMT_32BIT,
193 .width = 32,
194 .overflow_bit = SH_CMT32_CMCSR_CMF,
195 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
196 .read_control = sh_cmt_read16,
197 .write_control = sh_cmt_write16,
198 .read_count = sh_cmt_read32,
199 .write_count = sh_cmt_write32,
200 },
201 [SH_CMT_32BIT_FAST] = {
202 .model = SH_CMT_32BIT_FAST,
203 .width = 32,
204 .overflow_bit = SH_CMT32_CMCSR_CMF,
205 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
206 .read_control = sh_cmt_read16,
207 .write_control = sh_cmt_write16,
208 .read_count = sh_cmt_read32,
209 .write_count = sh_cmt_write32,
210 },
211 [SH_CMT_48BIT] = {
212 .model = SH_CMT_48BIT,
213 .width = 32,
214 .overflow_bit = SH_CMT32_CMCSR_CMF,
215 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
216 .read_control = sh_cmt_read32,
217 .write_control = sh_cmt_write32,
218 .read_count = sh_cmt_read32,
219 .write_count = sh_cmt_write32,
220 },
221 [SH_CMT_48BIT_GEN2] = {
222 .model = SH_CMT_48BIT_GEN2,
223 .width = 32,
224 .overflow_bit = SH_CMT32_CMCSR_CMF,
225 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
226 .read_control = sh_cmt_read32,
227 .write_control = sh_cmt_write32,
228 .read_count = sh_cmt_read32,
229 .write_count = sh_cmt_write32,
230 },
231};
232
233#define CMCSR 0
234#define CMCNT 1
235#define CMCOR 2
236
237static inline unsigned long sh_cmt_read_cmstr(struct sh_cmt_channel *ch)
238{
239 if (ch->iostart)
240 return ch->cmt->info->read_control(ch->iostart, 0);
241 else
242 return ch->cmt->info->read_control(ch->cmt->mapbase, 0);
243}
244
245static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch,
246 unsigned long value)
247{
248 if (ch->iostart)
249 ch->cmt->info->write_control(ch->iostart, 0, value);
250 else
251 ch->cmt->info->write_control(ch->cmt->mapbase, 0, value);
252}
253
254static inline unsigned long sh_cmt_read_cmcsr(struct sh_cmt_channel *ch)
255{
256 return ch->cmt->info->read_control(ch->ioctrl, CMCSR);
257}
258
259static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch,
260 unsigned long value)
261{
262 ch->cmt->info->write_control(ch->ioctrl, CMCSR, value);
263}
264
265static inline unsigned long sh_cmt_read_cmcnt(struct sh_cmt_channel *ch)
266{
267 return ch->cmt->info->read_count(ch->ioctrl, CMCNT);
268}
269
270static inline void sh_cmt_write_cmcnt(struct sh_cmt_channel *ch,
271 unsigned long value)
272{
273 ch->cmt->info->write_count(ch->ioctrl, CMCNT, value);
274}
275
276static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch,
277 unsigned long value)
278{
279 ch->cmt->info->write_count(ch->ioctrl, CMCOR, value);
280}
281
282static unsigned long sh_cmt_get_counter(struct sh_cmt_channel *ch,
283 int *has_wrapped)
284{
285 unsigned long v1, v2, v3;
286 int o1, o2;
287
288 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
289
290
291 do {
292 o2 = o1;
293 v1 = sh_cmt_read_cmcnt(ch);
294 v2 = sh_cmt_read_cmcnt(ch);
295 v3 = sh_cmt_read_cmcnt(ch);
296 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
297 } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
298 || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));
299
300 *has_wrapped = o1;
301 return v2;
302}
303
304static DEFINE_RAW_SPINLOCK(sh_cmt_lock);
305
306static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start)
307{
308 unsigned long flags, value;
309
310
311 raw_spin_lock_irqsave(&sh_cmt_lock, flags);
312 value = sh_cmt_read_cmstr(ch);
313
314 if (start)
315 value |= 1 << ch->timer_bit;
316 else
317 value &= ~(1 << ch->timer_bit);
318
319 sh_cmt_write_cmstr(ch, value);
320 raw_spin_unlock_irqrestore(&sh_cmt_lock, flags);
321}
322
323static int sh_cmt_enable(struct sh_cmt_channel *ch, unsigned long *rate)
324{
325 int k, ret;
326
327 pm_runtime_get_sync(&ch->cmt->pdev->dev);
328 dev_pm_syscore_device(&ch->cmt->pdev->dev, true);
329
330
331 ret = clk_enable(ch->cmt->clk);
332 if (ret) {
333 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n",
334 ch->index);
335 goto err0;
336 }
337
338
339 sh_cmt_start_stop_ch(ch, 0);
340
341
342 if (ch->cmt->info->width == 16) {
343 *rate = clk_get_rate(ch->cmt->clk) / 512;
344 sh_cmt_write_cmcsr(ch, SH_CMT16_CMCSR_CMIE |
345 SH_CMT16_CMCSR_CKS512);
346 } else {
347 *rate = clk_get_rate(ch->cmt->clk) / 8;
348 sh_cmt_write_cmcsr(ch, SH_CMT32_CMCSR_CMM |
349 SH_CMT32_CMCSR_CMTOUT_IE |
350 SH_CMT32_CMCSR_CMR_IRQ |
351 SH_CMT32_CMCSR_CKS_RCLK8);
352 }
353
354 sh_cmt_write_cmcor(ch, 0xffffffff);
355 sh_cmt_write_cmcnt(ch, 0);
356
357
358
359
360
361
362
363
364
365
366
367
368 for (k = 0; k < 100; k++) {
369 if (!sh_cmt_read_cmcnt(ch))
370 break;
371 udelay(1);
372 }
373
374 if (sh_cmt_read_cmcnt(ch)) {
375 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n",
376 ch->index);
377 ret = -ETIMEDOUT;
378 goto err1;
379 }
380
381
382 sh_cmt_start_stop_ch(ch, 1);
383 return 0;
384 err1:
385
386 clk_disable(ch->cmt->clk);
387
388 err0:
389 return ret;
390}
391
392static void sh_cmt_disable(struct sh_cmt_channel *ch)
393{
394
395 sh_cmt_start_stop_ch(ch, 0);
396
397
398 sh_cmt_write_cmcsr(ch, 0);
399
400
401 clk_disable(ch->cmt->clk);
402
403 dev_pm_syscore_device(&ch->cmt->pdev->dev, false);
404 pm_runtime_put(&ch->cmt->pdev->dev);
405}
406
407
408#define FLAG_CLOCKEVENT (1 << 0)
409#define FLAG_CLOCKSOURCE (1 << 1)
410#define FLAG_REPROGRAM (1 << 2)
411#define FLAG_SKIPEVENT (1 << 3)
412#define FLAG_IRQCONTEXT (1 << 4)
413
414static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch,
415 int absolute)
416{
417 unsigned long new_match;
418 unsigned long value = ch->next_match_value;
419 unsigned long delay = 0;
420 unsigned long now = 0;
421 int has_wrapped;
422
423 now = sh_cmt_get_counter(ch, &has_wrapped);
424 ch->flags |= FLAG_REPROGRAM;
425
426 if (has_wrapped) {
427
428
429
430
431 ch->flags |= FLAG_SKIPEVENT;
432 return;
433 }
434
435 if (absolute)
436 now = 0;
437
438 do {
439
440
441
442 new_match = now + value + delay;
443 if (new_match > ch->max_match_value)
444 new_match = ch->max_match_value;
445
446 sh_cmt_write_cmcor(ch, new_match);
447
448 now = sh_cmt_get_counter(ch, &has_wrapped);
449 if (has_wrapped && (new_match > ch->match_value)) {
450
451
452
453
454
455
456 ch->flags |= FLAG_SKIPEVENT;
457 break;
458 }
459
460 if (has_wrapped) {
461
462
463
464
465
466
467 ch->match_value = new_match;
468 break;
469 }
470
471
472 if (now < new_match) {
473
474
475
476
477
478 ch->match_value = new_match;
479 break;
480 }
481
482
483
484
485
486
487
488 if (delay)
489 delay <<= 1;
490 else
491 delay = 1;
492
493 if (!delay)
494 dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n",
495 ch->index);
496
497 } while (delay);
498}
499
500static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
501{
502 if (delta > ch->max_match_value)
503 dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n",
504 ch->index);
505
506 ch->next_match_value = delta;
507 sh_cmt_clock_event_program_verify(ch, 0);
508}
509
510static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
511{
512 unsigned long flags;
513
514 raw_spin_lock_irqsave(&ch->lock, flags);
515 __sh_cmt_set_next(ch, delta);
516 raw_spin_unlock_irqrestore(&ch->lock, flags);
517}
518
519static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id)
520{
521 struct sh_cmt_channel *ch = dev_id;
522
523
524 sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) &
525 ch->cmt->info->clear_bits);
526
527
528
529
530
531 if (ch->flags & FLAG_CLOCKSOURCE)
532 ch->total_cycles += ch->match_value + 1;
533
534 if (!(ch->flags & FLAG_REPROGRAM))
535 ch->next_match_value = ch->max_match_value;
536
537 ch->flags |= FLAG_IRQCONTEXT;
538
539 if (ch->flags & FLAG_CLOCKEVENT) {
540 if (!(ch->flags & FLAG_SKIPEVENT)) {
541 if (ch->ced.mode == CLOCK_EVT_MODE_ONESHOT) {
542 ch->next_match_value = ch->max_match_value;
543 ch->flags |= FLAG_REPROGRAM;
544 }
545
546 ch->ced.event_handler(&ch->ced);
547 }
548 }
549
550 ch->flags &= ~FLAG_SKIPEVENT;
551
552 if (ch->flags & FLAG_REPROGRAM) {
553 ch->flags &= ~FLAG_REPROGRAM;
554 sh_cmt_clock_event_program_verify(ch, 1);
555
556 if (ch->flags & FLAG_CLOCKEVENT)
557 if ((ch->ced.mode == CLOCK_EVT_MODE_SHUTDOWN)
558 || (ch->match_value == ch->next_match_value))
559 ch->flags &= ~FLAG_REPROGRAM;
560 }
561
562 ch->flags &= ~FLAG_IRQCONTEXT;
563
564 return IRQ_HANDLED;
565}
566
567static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag)
568{
569 int ret = 0;
570 unsigned long flags;
571
572 raw_spin_lock_irqsave(&ch->lock, flags);
573
574 if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
575 ret = sh_cmt_enable(ch, &ch->rate);
576
577 if (ret)
578 goto out;
579 ch->flags |= flag;
580
581
582 if ((flag == FLAG_CLOCKSOURCE) && (!(ch->flags & FLAG_CLOCKEVENT)))
583 __sh_cmt_set_next(ch, ch->max_match_value);
584 out:
585 raw_spin_unlock_irqrestore(&ch->lock, flags);
586
587 return ret;
588}
589
590static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag)
591{
592 unsigned long flags;
593 unsigned long f;
594
595 raw_spin_lock_irqsave(&ch->lock, flags);
596
597 f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE);
598 ch->flags &= ~flag;
599
600 if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
601 sh_cmt_disable(ch);
602
603
604 if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE))
605 __sh_cmt_set_next(ch, ch->max_match_value);
606
607 raw_spin_unlock_irqrestore(&ch->lock, flags);
608}
609
610static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs)
611{
612 return container_of(cs, struct sh_cmt_channel, cs);
613}
614
615static cycle_t sh_cmt_clocksource_read(struct clocksource *cs)
616{
617 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
618 unsigned long flags, raw;
619 unsigned long value;
620 int has_wrapped;
621
622 raw_spin_lock_irqsave(&ch->lock, flags);
623 value = ch->total_cycles;
624 raw = sh_cmt_get_counter(ch, &has_wrapped);
625
626 if (unlikely(has_wrapped))
627 raw += ch->match_value + 1;
628 raw_spin_unlock_irqrestore(&ch->lock, flags);
629
630 return value + raw;
631}
632
633static int sh_cmt_clocksource_enable(struct clocksource *cs)
634{
635 int ret;
636 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
637
638 WARN_ON(ch->cs_enabled);
639
640 ch->total_cycles = 0;
641
642 ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE);
643 if (!ret) {
644 __clocksource_updatefreq_hz(cs, ch->rate);
645 ch->cs_enabled = true;
646 }
647 return ret;
648}
649
650static void sh_cmt_clocksource_disable(struct clocksource *cs)
651{
652 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
653
654 WARN_ON(!ch->cs_enabled);
655
656 sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
657 ch->cs_enabled = false;
658}
659
660static void sh_cmt_clocksource_suspend(struct clocksource *cs)
661{
662 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
663
664 sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
665 pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev);
666}
667
668static void sh_cmt_clocksource_resume(struct clocksource *cs)
669{
670 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
671
672 pm_genpd_syscore_poweron(&ch->cmt->pdev->dev);
673 sh_cmt_start(ch, FLAG_CLOCKSOURCE);
674}
675
676static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch,
677 const char *name)
678{
679 struct clocksource *cs = &ch->cs;
680
681 cs->name = name;
682 cs->rating = 125;
683 cs->read = sh_cmt_clocksource_read;
684 cs->enable = sh_cmt_clocksource_enable;
685 cs->disable = sh_cmt_clocksource_disable;
686 cs->suspend = sh_cmt_clocksource_suspend;
687 cs->resume = sh_cmt_clocksource_resume;
688 cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
689 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
690
691 dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n",
692 ch->index);
693
694
695 clocksource_register_hz(cs, 1);
696 return 0;
697}
698
699static struct sh_cmt_channel *ced_to_sh_cmt(struct clock_event_device *ced)
700{
701 return container_of(ced, struct sh_cmt_channel, ced);
702}
703
704static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic)
705{
706 struct clock_event_device *ced = &ch->ced;
707
708 sh_cmt_start(ch, FLAG_CLOCKEVENT);
709
710
711
712 ced->shift = 32;
713 ced->mult = div_sc(ch->rate, NSEC_PER_SEC, ced->shift);
714 ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced);
715 ced->min_delta_ns = clockevent_delta2ns(0x1f, ced);
716
717 if (periodic)
718 sh_cmt_set_next(ch, ((ch->rate + HZ/2) / HZ) - 1);
719 else
720 sh_cmt_set_next(ch, ch->max_match_value);
721}
722
723static void sh_cmt_clock_event_mode(enum clock_event_mode mode,
724 struct clock_event_device *ced)
725{
726 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
727
728
729 switch (ced->mode) {
730 case CLOCK_EVT_MODE_PERIODIC:
731 case CLOCK_EVT_MODE_ONESHOT:
732 sh_cmt_stop(ch, FLAG_CLOCKEVENT);
733 break;
734 default:
735 break;
736 }
737
738 switch (mode) {
739 case CLOCK_EVT_MODE_PERIODIC:
740 dev_info(&ch->cmt->pdev->dev,
741 "ch%u: used for periodic clock events\n", ch->index);
742 sh_cmt_clock_event_start(ch, 1);
743 break;
744 case CLOCK_EVT_MODE_ONESHOT:
745 dev_info(&ch->cmt->pdev->dev,
746 "ch%u: used for oneshot clock events\n", ch->index);
747 sh_cmt_clock_event_start(ch, 0);
748 break;
749 case CLOCK_EVT_MODE_SHUTDOWN:
750 case CLOCK_EVT_MODE_UNUSED:
751 sh_cmt_stop(ch, FLAG_CLOCKEVENT);
752 break;
753 default:
754 break;
755 }
756}
757
758static int sh_cmt_clock_event_next(unsigned long delta,
759 struct clock_event_device *ced)
760{
761 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
762
763 BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
764 if (likely(ch->flags & FLAG_IRQCONTEXT))
765 ch->next_match_value = delta - 1;
766 else
767 sh_cmt_set_next(ch, delta - 1);
768
769 return 0;
770}
771
772static void sh_cmt_clock_event_suspend(struct clock_event_device *ced)
773{
774 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
775
776 pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev);
777 clk_unprepare(ch->cmt->clk);
778}
779
780static void sh_cmt_clock_event_resume(struct clock_event_device *ced)
781{
782 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
783
784 clk_prepare(ch->cmt->clk);
785 pm_genpd_syscore_poweron(&ch->cmt->pdev->dev);
786}
787
788static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch,
789 const char *name)
790{
791 struct clock_event_device *ced = &ch->ced;
792 int irq;
793 int ret;
794
795 irq = platform_get_irq(ch->cmt->pdev, ch->cmt->legacy ? 0 : ch->index);
796 if (irq < 0) {
797 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to get irq\n",
798 ch->index);
799 return irq;
800 }
801
802 ret = request_irq(irq, sh_cmt_interrupt,
803 IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
804 dev_name(&ch->cmt->pdev->dev), ch);
805 if (ret) {
806 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n",
807 ch->index, irq);
808 return ret;
809 }
810
811 ced->name = name;
812 ced->features = CLOCK_EVT_FEAT_PERIODIC;
813 ced->features |= CLOCK_EVT_FEAT_ONESHOT;
814 ced->rating = 125;
815 ced->cpumask = cpu_possible_mask;
816 ced->set_next_event = sh_cmt_clock_event_next;
817 ced->set_mode = sh_cmt_clock_event_mode;
818 ced->suspend = sh_cmt_clock_event_suspend;
819 ced->resume = sh_cmt_clock_event_resume;
820
821 dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n",
822 ch->index);
823 clockevents_register_device(ced);
824
825 return 0;
826}
827
828static int sh_cmt_register(struct sh_cmt_channel *ch, const char *name,
829 bool clockevent, bool clocksource)
830{
831 int ret;
832
833 if (clockevent) {
834 ch->cmt->has_clockevent = true;
835 ret = sh_cmt_register_clockevent(ch, name);
836 if (ret < 0)
837 return ret;
838 }
839
840 if (clocksource) {
841 ch->cmt->has_clocksource = true;
842 sh_cmt_register_clocksource(ch, name);
843 }
844
845 return 0;
846}
847
848static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index,
849 unsigned int hwidx, bool clockevent,
850 bool clocksource, struct sh_cmt_device *cmt)
851{
852 int ret;
853
854
855 if (!clockevent && !clocksource)
856 return 0;
857
858 ch->cmt = cmt;
859 ch->index = index;
860 ch->hwidx = hwidx;
861
862
863
864
865
866
867
868
869 if (cmt->legacy) {
870 ch->ioctrl = cmt->mapbase_ch;
871 } else {
872 switch (cmt->info->model) {
873 case SH_CMT_16BIT:
874 ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6;
875 break;
876 case SH_CMT_32BIT:
877 case SH_CMT_48BIT:
878 ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10;
879 break;
880 case SH_CMT_32BIT_FAST:
881
882
883
884
885
886 ch->ioctrl = cmt->mapbase + 0x40;
887 break;
888 case SH_CMT_48BIT_GEN2:
889 ch->iostart = cmt->mapbase + ch->hwidx * 0x100;
890 ch->ioctrl = ch->iostart + 0x10;
891 break;
892 }
893 }
894
895 if (cmt->info->width == (sizeof(ch->max_match_value) * 8))
896 ch->max_match_value = ~0;
897 else
898 ch->max_match_value = (1 << cmt->info->width) - 1;
899
900 ch->match_value = ch->max_match_value;
901 raw_spin_lock_init(&ch->lock);
902
903 if (cmt->legacy) {
904 ch->timer_bit = ch->hwidx;
905 } else {
906 ch->timer_bit = cmt->info->model == SH_CMT_48BIT_GEN2
907 ? 0 : ch->hwidx;
908 }
909
910 ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev),
911 clockevent, clocksource);
912 if (ret) {
913 dev_err(&cmt->pdev->dev, "ch%u: registration failed\n",
914 ch->index);
915 return ret;
916 }
917 ch->cs_enabled = false;
918
919 return 0;
920}
921
922static int sh_cmt_map_memory(struct sh_cmt_device *cmt)
923{
924 struct resource *mem;
925
926 mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0);
927 if (!mem) {
928 dev_err(&cmt->pdev->dev, "failed to get I/O memory\n");
929 return -ENXIO;
930 }
931
932 cmt->mapbase = ioremap_nocache(mem->start, resource_size(mem));
933 if (cmt->mapbase == NULL) {
934 dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n");
935 return -ENXIO;
936 }
937
938 return 0;
939}
940
941static int sh_cmt_map_memory_legacy(struct sh_cmt_device *cmt)
942{
943 struct sh_timer_config *cfg = cmt->pdev->dev.platform_data;
944 struct resource *res, *res2;
945
946
947 res = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0);
948 if (!res) {
949 dev_err(&cmt->pdev->dev, "failed to get I/O memory\n");
950 return -ENXIO;
951 }
952
953 cmt->mapbase_ch = ioremap_nocache(res->start, resource_size(res));
954 if (cmt->mapbase_ch == NULL) {
955 dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n");
956 return -ENXIO;
957 }
958
959
960 res2 = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 1);
961
962
963 cmt->mapbase = ioremap_nocache(res2 ? res2->start :
964 res->start - cfg->channel_offset,
965 res2 ? resource_size(res2) : 2);
966 if (cmt->mapbase == NULL) {
967 dev_err(&cmt->pdev->dev, "failed to remap I/O second memory\n");
968 iounmap(cmt->mapbase_ch);
969 return -ENXIO;
970 }
971
972
973 if (resource_size(res) == 6)
974 cmt->info = &sh_cmt_info[SH_CMT_16BIT];
975 else if (res2 && (resource_size(res2) == 4))
976 cmt->info = &sh_cmt_info[SH_CMT_48BIT_GEN2];
977 else
978 cmt->info = &sh_cmt_info[SH_CMT_32BIT];
979
980 return 0;
981}
982
983static void sh_cmt_unmap_memory(struct sh_cmt_device *cmt)
984{
985 iounmap(cmt->mapbase);
986 if (cmt->mapbase_ch)
987 iounmap(cmt->mapbase_ch);
988}
989
990static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
991{
992 struct sh_timer_config *cfg = pdev->dev.platform_data;
993 const struct platform_device_id *id = pdev->id_entry;
994 unsigned int hw_channels;
995 int ret;
996
997 memset(cmt, 0, sizeof(*cmt));
998 cmt->pdev = pdev;
999
1000 if (!cfg) {
1001 dev_err(&cmt->pdev->dev, "missing platform data\n");
1002 return -ENXIO;
1003 }
1004
1005 cmt->info = (const struct sh_cmt_info *)id->driver_data;
1006 cmt->legacy = cmt->info ? false : true;
1007
1008
1009 cmt->clk = clk_get(&cmt->pdev->dev, cmt->legacy ? "cmt_fck" : "fck");
1010 if (IS_ERR(cmt->clk)) {
1011 dev_err(&cmt->pdev->dev, "cannot get clock\n");
1012 return PTR_ERR(cmt->clk);
1013 }
1014
1015 ret = clk_prepare(cmt->clk);
1016 if (ret < 0)
1017 goto err_clk_put;
1018
1019
1020
1021
1022
1023
1024 if (cmt->legacy)
1025 ret = sh_cmt_map_memory_legacy(cmt);
1026 else
1027 ret = sh_cmt_map_memory(cmt);
1028
1029 if (ret < 0)
1030 goto err_clk_unprepare;
1031
1032
1033 if (cmt->legacy) {
1034 cmt->num_channels = 1;
1035 hw_channels = 0;
1036 } else {
1037 cmt->num_channels = hweight8(cfg->channels_mask);
1038 hw_channels = cfg->channels_mask;
1039 }
1040
1041 cmt->channels = kzalloc(cmt->num_channels * sizeof(*cmt->channels),
1042 GFP_KERNEL);
1043 if (cmt->channels == NULL) {
1044 ret = -ENOMEM;
1045 goto err_unmap;
1046 }
1047
1048 if (cmt->legacy) {
1049 ret = sh_cmt_setup_channel(&cmt->channels[0],
1050 cfg->timer_bit, cfg->timer_bit,
1051 cfg->clockevent_rating != 0,
1052 cfg->clocksource_rating != 0, cmt);
1053 if (ret < 0)
1054 goto err_unmap;
1055 } else {
1056 unsigned int mask = hw_channels;
1057 unsigned int i;
1058
1059
1060
1061
1062
1063
1064 for (i = 0; i < cmt->num_channels; ++i) {
1065 unsigned int hwidx = ffs(mask) - 1;
1066 bool clocksource = i == 1 || cmt->num_channels == 1;
1067 bool clockevent = i == 0;
1068
1069 ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx,
1070 clockevent, clocksource,
1071 cmt);
1072 if (ret < 0)
1073 goto err_unmap;
1074
1075 mask &= ~(1 << hwidx);
1076 }
1077 }
1078
1079 platform_set_drvdata(pdev, cmt);
1080
1081 return 0;
1082
1083err_unmap:
1084 kfree(cmt->channels);
1085 sh_cmt_unmap_memory(cmt);
1086err_clk_unprepare:
1087 clk_unprepare(cmt->clk);
1088err_clk_put:
1089 clk_put(cmt->clk);
1090 return ret;
1091}
1092
1093static int sh_cmt_probe(struct platform_device *pdev)
1094{
1095 struct sh_cmt_device *cmt = platform_get_drvdata(pdev);
1096 int ret;
1097
1098 if (!is_early_platform_device(pdev)) {
1099 pm_runtime_set_active(&pdev->dev);
1100 pm_runtime_enable(&pdev->dev);
1101 }
1102
1103 if (cmt) {
1104 dev_info(&pdev->dev, "kept as earlytimer\n");
1105 goto out;
1106 }
1107
1108 cmt = kzalloc(sizeof(*cmt), GFP_KERNEL);
1109 if (cmt == NULL)
1110 return -ENOMEM;
1111
1112 ret = sh_cmt_setup(cmt, pdev);
1113 if (ret) {
1114 kfree(cmt);
1115 pm_runtime_idle(&pdev->dev);
1116 return ret;
1117 }
1118 if (is_early_platform_device(pdev))
1119 return 0;
1120
1121 out:
1122 if (cmt->has_clockevent || cmt->has_clocksource)
1123 pm_runtime_irq_safe(&pdev->dev);
1124 else
1125 pm_runtime_idle(&pdev->dev);
1126
1127 return 0;
1128}
1129
1130static int sh_cmt_remove(struct platform_device *pdev)
1131{
1132 return -EBUSY;
1133}
1134
1135static const struct platform_device_id sh_cmt_id_table[] = {
1136 { "sh_cmt", 0 },
1137 { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] },
1138 { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] },
1139 { "sh-cmt-32-fast", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT_FAST] },
1140 { "sh-cmt-48", (kernel_ulong_t)&sh_cmt_info[SH_CMT_48BIT] },
1141 { "sh-cmt-48-gen2", (kernel_ulong_t)&sh_cmt_info[SH_CMT_48BIT_GEN2] },
1142 { }
1143};
1144MODULE_DEVICE_TABLE(platform, sh_cmt_id_table);
1145
1146static struct platform_driver sh_cmt_device_driver = {
1147 .probe = sh_cmt_probe,
1148 .remove = sh_cmt_remove,
1149 .driver = {
1150 .name = "sh_cmt",
1151 },
1152 .id_table = sh_cmt_id_table,
1153};
1154
1155static int __init sh_cmt_init(void)
1156{
1157 return platform_driver_register(&sh_cmt_device_driver);
1158}
1159
1160static void __exit sh_cmt_exit(void)
1161{
1162 platform_driver_unregister(&sh_cmt_device_driver);
1163}
1164
1165early_platform_init("earlytimer", &sh_cmt_device_driver);
1166subsys_initcall(sh_cmt_init);
1167module_exit(sh_cmt_exit);
1168
1169MODULE_AUTHOR("Magnus Damm");
1170MODULE_DESCRIPTION("SuperH CMT Timer Driver");
1171MODULE_LICENSE("GPL v2");
1172