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25#include <core/os.h>
26#include <core/class.h>
27#include <core/client.h>
28#include <core/handle.h>
29#include <core/engctx.h>
30#include <core/enum.h>
31
32#include <subdev/fb.h>
33#include <subdev/vm.h>
34#include <subdev/timer.h>
35
36#include <engine/fifo.h>
37#include <engine/graph.h>
38
39#include "nv50.h"
40
41struct nv50_graph_priv {
42 struct nouveau_graph base;
43 spinlock_t lock;
44 u32 size;
45};
46
47struct nv50_graph_chan {
48 struct nouveau_graph_chan base;
49};
50
51static u64
52nv50_graph_units(struct nouveau_graph *graph)
53{
54 struct nv50_graph_priv *priv = (void *)graph;
55
56 return nv_rd32(priv, 0x1540);
57}
58
59
60
61
62
63static int
64nv50_graph_object_ctor(struct nouveau_object *parent,
65 struct nouveau_object *engine,
66 struct nouveau_oclass *oclass, void *data, u32 size,
67 struct nouveau_object **pobject)
68{
69 struct nouveau_gpuobj *obj;
70 int ret;
71
72 ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent,
73 16, 16, 0, &obj);
74 *pobject = nv_object(obj);
75 if (ret)
76 return ret;
77
78 nv_wo32(obj, 0x00, nv_mclass(obj));
79 nv_wo32(obj, 0x04, 0x00000000);
80 nv_wo32(obj, 0x08, 0x00000000);
81 nv_wo32(obj, 0x0c, 0x00000000);
82 return 0;
83}
84
85static struct nouveau_ofuncs
86nv50_graph_ofuncs = {
87 .ctor = nv50_graph_object_ctor,
88 .dtor = _nouveau_gpuobj_dtor,
89 .init = _nouveau_gpuobj_init,
90 .fini = _nouveau_gpuobj_fini,
91 .rd32 = _nouveau_gpuobj_rd32,
92 .wr32 = _nouveau_gpuobj_wr32,
93};
94
95static struct nouveau_oclass
96nv50_graph_sclass[] = {
97 { 0x0030, &nv50_graph_ofuncs },
98 { 0x502d, &nv50_graph_ofuncs },
99 { 0x5039, &nv50_graph_ofuncs },
100 { 0x5097, &nv50_graph_ofuncs },
101 { 0x50c0, &nv50_graph_ofuncs },
102 {}
103};
104
105static struct nouveau_oclass
106nv84_graph_sclass[] = {
107 { 0x0030, &nv50_graph_ofuncs },
108 { 0x502d, &nv50_graph_ofuncs },
109 { 0x5039, &nv50_graph_ofuncs },
110 { 0x50c0, &nv50_graph_ofuncs },
111 { 0x8297, &nv50_graph_ofuncs },
112 {}
113};
114
115static struct nouveau_oclass
116nva0_graph_sclass[] = {
117 { 0x0030, &nv50_graph_ofuncs },
118 { 0x502d, &nv50_graph_ofuncs },
119 { 0x5039, &nv50_graph_ofuncs },
120 { 0x50c0, &nv50_graph_ofuncs },
121 { 0x8397, &nv50_graph_ofuncs },
122 {}
123};
124
125static struct nouveau_oclass
126nva3_graph_sclass[] = {
127 { 0x0030, &nv50_graph_ofuncs },
128 { 0x502d, &nv50_graph_ofuncs },
129 { 0x5039, &nv50_graph_ofuncs },
130 { 0x50c0, &nv50_graph_ofuncs },
131 { 0x8597, &nv50_graph_ofuncs },
132 { 0x85c0, &nv50_graph_ofuncs },
133 {}
134};
135
136static struct nouveau_oclass
137nvaf_graph_sclass[] = {
138 { 0x0030, &nv50_graph_ofuncs },
139 { 0x502d, &nv50_graph_ofuncs },
140 { 0x5039, &nv50_graph_ofuncs },
141 { 0x50c0, &nv50_graph_ofuncs },
142 { 0x85c0, &nv50_graph_ofuncs },
143 { 0x8697, &nv50_graph_ofuncs },
144 {}
145};
146
147
148
149
150
151static int
152nv50_graph_context_ctor(struct nouveau_object *parent,
153 struct nouveau_object *engine,
154 struct nouveau_oclass *oclass, void *data, u32 size,
155 struct nouveau_object **pobject)
156{
157 struct nv50_graph_priv *priv = (void *)engine;
158 struct nv50_graph_chan *chan;
159 int ret;
160
161 ret = nouveau_graph_context_create(parent, engine, oclass, NULL,
162 priv->size, 0,
163 NVOBJ_FLAG_ZERO_ALLOC, &chan);
164 *pobject = nv_object(chan);
165 if (ret)
166 return ret;
167
168 nv50_grctx_fill(nv_device(priv), nv_gpuobj(chan));
169 return 0;
170}
171
172static struct nouveau_oclass
173nv50_graph_cclass = {
174 .handle = NV_ENGCTX(GR, 0x50),
175 .ofuncs = &(struct nouveau_ofuncs) {
176 .ctor = nv50_graph_context_ctor,
177 .dtor = _nouveau_graph_context_dtor,
178 .init = _nouveau_graph_context_init,
179 .fini = _nouveau_graph_context_fini,
180 .rd32 = _nouveau_graph_context_rd32,
181 .wr32 = _nouveau_graph_context_wr32,
182 },
183};
184
185
186
187
188
189static const struct nouveau_bitfield nv50_pgraph_status[] = {
190 { 0x00000001, "BUSY" },
191 { 0x00000002, "DISPATCH" },
192 { 0x00000004, "UNK2" },
193 { 0x00000008, "UNK3" },
194 { 0x00000010, "UNK4" },
195 { 0x00000020, "UNK5" },
196 { 0x00000040, "M2MF" },
197 { 0x00000080, "UNK7" },
198 { 0x00000100, "CTXPROG" },
199 { 0x00000200, "VFETCH" },
200 { 0x00000400, "CCACHE_PREGEOM" },
201 { 0x00000800, "STRMOUT_VATTR_POSTGEOM" },
202 { 0x00001000, "VCLIP" },
203 { 0x00002000, "RATTR_APLANE" },
204 { 0x00004000, "TRAST" },
205 { 0x00008000, "CLIPID" },
206 { 0x00010000, "ZCULL" },
207 { 0x00020000, "ENG2D" },
208 { 0x00040000, "RMASK" },
209 { 0x00080000, "TPC_RAST" },
210 { 0x00100000, "TPC_PROP" },
211 { 0x00200000, "TPC_TEX" },
212 { 0x00400000, "TPC_GEOM" },
213 { 0x00800000, "TPC_MP" },
214 { 0x01000000, "ROP" },
215 {}
216};
217
218static const char *const nv50_pgraph_vstatus_0[] = {
219 "VFETCH", "CCACHE", "PREGEOM", "POSTGEOM", "VATTR", "STRMOUT", "VCLIP",
220 NULL
221};
222
223static const char *const nv50_pgraph_vstatus_1[] = {
224 "TPC_RAST", "TPC_PROP", "TPC_TEX", "TPC_GEOM", "TPC_MP", NULL
225};
226
227static const char *const nv50_pgraph_vstatus_2[] = {
228 "RATTR", "APLANE", "TRAST", "CLIPID", "ZCULL", "ENG2D", "RMASK",
229 "ROP", NULL
230};
231
232static void nouveau_pgraph_vstatus_print(struct nv50_graph_priv *priv, int r,
233 const char *const units[], u32 status)
234{
235 int i;
236
237 nv_error(priv, "PGRAPH_VSTATUS%d: 0x%08x", r, status);
238
239 for (i = 0; units[i] && status; i++) {
240 if ((status & 7) == 1)
241 pr_cont(" %s", units[i]);
242 status >>= 3;
243 }
244 if (status)
245 pr_cont(" (invalid: 0x%x)", status);
246 pr_cont("\n");
247}
248
249static int
250nv84_graph_tlb_flush(struct nouveau_engine *engine)
251{
252 struct nouveau_timer *ptimer = nouveau_timer(engine);
253 struct nv50_graph_priv *priv = (void *)engine;
254 bool idle, timeout = false;
255 unsigned long flags;
256 u64 start;
257 u32 tmp;
258
259 spin_lock_irqsave(&priv->lock, flags);
260 nv_mask(priv, 0x400500, 0x00000001, 0x00000000);
261
262 start = ptimer->read(ptimer);
263 do {
264 idle = true;
265
266 for (tmp = nv_rd32(priv, 0x400380); tmp && idle; tmp >>= 3) {
267 if ((tmp & 7) == 1)
268 idle = false;
269 }
270
271 for (tmp = nv_rd32(priv, 0x400384); tmp && idle; tmp >>= 3) {
272 if ((tmp & 7) == 1)
273 idle = false;
274 }
275
276 for (tmp = nv_rd32(priv, 0x400388); tmp && idle; tmp >>= 3) {
277 if ((tmp & 7) == 1)
278 idle = false;
279 }
280 } while (!idle &&
281 !(timeout = ptimer->read(ptimer) - start > 2000000000));
282
283 if (timeout) {
284 nv_error(priv, "PGRAPH TLB flush idle timeout fail\n");
285
286 tmp = nv_rd32(priv, 0x400700);
287 nv_error(priv, "PGRAPH_STATUS : 0x%08x", tmp);
288 nouveau_bitfield_print(nv50_pgraph_status, tmp);
289 pr_cont("\n");
290
291 nouveau_pgraph_vstatus_print(priv, 0, nv50_pgraph_vstatus_0,
292 nv_rd32(priv, 0x400380));
293 nouveau_pgraph_vstatus_print(priv, 1, nv50_pgraph_vstatus_1,
294 nv_rd32(priv, 0x400384));
295 nouveau_pgraph_vstatus_print(priv, 2, nv50_pgraph_vstatus_2,
296 nv_rd32(priv, 0x400388));
297 }
298
299
300 nv_wr32(priv, 0x100c80, 0x00000001);
301 if (!nv_wait(priv, 0x100c80, 0x00000001, 0x00000000))
302 nv_error(priv, "vm flush timeout\n");
303 nv_mask(priv, 0x400500, 0x00000001, 0x00000001);
304 spin_unlock_irqrestore(&priv->lock, flags);
305 return timeout ? -EBUSY : 0;
306}
307
308static const struct nouveau_bitfield nv50_mp_exec_errors[] = {
309 { 0x01, "STACK_UNDERFLOW" },
310 { 0x02, "STACK_MISMATCH" },
311 { 0x04, "QUADON_ACTIVE" },
312 { 0x08, "TIMEOUT" },
313 { 0x10, "INVALID_OPCODE" },
314 { 0x20, "PM_OVERFLOW" },
315 { 0x40, "BREAKPOINT" },
316 {}
317};
318
319static const struct nouveau_bitfield nv50_mpc_traps[] = {
320 { 0x0000001, "LOCAL_LIMIT_READ" },
321 { 0x0000010, "LOCAL_LIMIT_WRITE" },
322 { 0x0000040, "STACK_LIMIT" },
323 { 0x0000100, "GLOBAL_LIMIT_READ" },
324 { 0x0001000, "GLOBAL_LIMIT_WRITE" },
325 { 0x0010000, "MP0" },
326 { 0x0020000, "MP1" },
327 { 0x0040000, "GLOBAL_LIMIT_RED" },
328 { 0x0400000, "GLOBAL_LIMIT_ATOM" },
329 { 0x4000000, "MP2" },
330 {}
331};
332
333static const struct nouveau_bitfield nv50_tex_traps[] = {
334 { 0x00000001, "" },
335 { 0x00000002, "FAULT" },
336 { 0x00000004, "STORAGE_TYPE_MISMATCH" },
337 { 0x00000008, "LINEAR_MISMATCH" },
338 { 0x00000020, "WRONG_MEMTYPE" },
339 {}
340};
341
342static const struct nouveau_bitfield nv50_graph_trap_m2mf[] = {
343 { 0x00000001, "NOTIFY" },
344 { 0x00000002, "IN" },
345 { 0x00000004, "OUT" },
346 {}
347};
348
349static const struct nouveau_bitfield nv50_graph_trap_vfetch[] = {
350 { 0x00000001, "FAULT" },
351 {}
352};
353
354static const struct nouveau_bitfield nv50_graph_trap_strmout[] = {
355 { 0x00000001, "FAULT" },
356 {}
357};
358
359static const struct nouveau_bitfield nv50_graph_trap_ccache[] = {
360 { 0x00000001, "FAULT" },
361 {}
362};
363
364
365const struct nouveau_enum nv50_data_error_names[] = {
366 { 0x00000003, "INVALID_OPERATION", NULL },
367 { 0x00000004, "INVALID_VALUE", NULL },
368 { 0x00000005, "INVALID_ENUM", NULL },
369 { 0x00000008, "INVALID_OBJECT", NULL },
370 { 0x00000009, "READ_ONLY_OBJECT", NULL },
371 { 0x0000000a, "SUPERVISOR_OBJECT", NULL },
372 { 0x0000000b, "INVALID_ADDRESS_ALIGNMENT", NULL },
373 { 0x0000000c, "INVALID_BITFIELD", NULL },
374 { 0x0000000d, "BEGIN_END_ACTIVE", NULL },
375 { 0x0000000e, "SEMANTIC_COLOR_BACK_OVER_LIMIT", NULL },
376 { 0x0000000f, "VIEWPORT_ID_NEEDS_GP", NULL },
377 { 0x00000010, "RT_DOUBLE_BIND", NULL },
378 { 0x00000011, "RT_TYPES_MISMATCH", NULL },
379 { 0x00000012, "RT_LINEAR_WITH_ZETA", NULL },
380 { 0x00000015, "FP_TOO_FEW_REGS", NULL },
381 { 0x00000016, "ZETA_FORMAT_CSAA_MISMATCH", NULL },
382 { 0x00000017, "RT_LINEAR_WITH_MSAA", NULL },
383 { 0x00000018, "FP_INTERPOLANT_START_OVER_LIMIT", NULL },
384 { 0x00000019, "SEMANTIC_LAYER_OVER_LIMIT", NULL },
385 { 0x0000001a, "RT_INVALID_ALIGNMENT", NULL },
386 { 0x0000001b, "SAMPLER_OVER_LIMIT", NULL },
387 { 0x0000001c, "TEXTURE_OVER_LIMIT", NULL },
388 { 0x0000001e, "GP_TOO_MANY_OUTPUTS", NULL },
389 { 0x0000001f, "RT_BPP128_WITH_MS8", NULL },
390 { 0x00000021, "Z_OUT_OF_BOUNDS", NULL },
391 { 0x00000023, "XY_OUT_OF_BOUNDS", NULL },
392 { 0x00000024, "VP_ZERO_INPUTS", NULL },
393 { 0x00000027, "CP_MORE_PARAMS_THAN_SHARED", NULL },
394 { 0x00000028, "CP_NO_REG_SPACE_STRIPED", NULL },
395 { 0x00000029, "CP_NO_REG_SPACE_PACKED", NULL },
396 { 0x0000002a, "CP_NOT_ENOUGH_WARPS", NULL },
397 { 0x0000002b, "CP_BLOCK_SIZE_MISMATCH", NULL },
398 { 0x0000002c, "CP_NOT_ENOUGH_LOCAL_WARPS", NULL },
399 { 0x0000002d, "CP_NOT_ENOUGH_STACK_WARPS", NULL },
400 { 0x0000002e, "CP_NO_BLOCKDIM_LATCH", NULL },
401 { 0x00000031, "ENG2D_FORMAT_MISMATCH", NULL },
402 { 0x0000003f, "PRIMITIVE_ID_NEEDS_GP", NULL },
403 { 0x00000044, "SEMANTIC_VIEWPORT_OVER_LIMIT", NULL },
404 { 0x00000045, "SEMANTIC_COLOR_FRONT_OVER_LIMIT", NULL },
405 { 0x00000046, "LAYER_ID_NEEDS_GP", NULL },
406 { 0x00000047, "SEMANTIC_CLIP_OVER_LIMIT", NULL },
407 { 0x00000048, "SEMANTIC_PTSZ_OVER_LIMIT", NULL },
408 {}
409};
410
411static const struct nouveau_bitfield nv50_graph_intr_name[] = {
412 { 0x00000001, "NOTIFY" },
413 { 0x00000002, "COMPUTE_QUERY" },
414 { 0x00000010, "ILLEGAL_MTHD" },
415 { 0x00000020, "ILLEGAL_CLASS" },
416 { 0x00000040, "DOUBLE_NOTIFY" },
417 { 0x00001000, "CONTEXT_SWITCH" },
418 { 0x00010000, "BUFFER_NOTIFY" },
419 { 0x00100000, "DATA_ERROR" },
420 { 0x00200000, "TRAP" },
421 { 0x01000000, "SINGLE_STEP" },
422 {}
423};
424
425static const struct nouveau_bitfield nv50_graph_trap_prop[] = {
426 { 0x00000004, "SURF_WIDTH_OVERRUN" },
427 { 0x00000008, "SURF_HEIGHT_OVERRUN" },
428 { 0x00000010, "DST2D_FAULT" },
429 { 0x00000020, "ZETA_FAULT" },
430 { 0x00000040, "RT_FAULT" },
431 { 0x00000080, "CUDA_FAULT" },
432 { 0x00000100, "DST2D_STORAGE_TYPE_MISMATCH" },
433 { 0x00000200, "ZETA_STORAGE_TYPE_MISMATCH" },
434 { 0x00000400, "RT_STORAGE_TYPE_MISMATCH" },
435 { 0x00000800, "DST2D_LINEAR_MISMATCH" },
436 { 0x00001000, "RT_LINEAR_MISMATCH" },
437 {}
438};
439
440static void
441nv50_priv_prop_trap(struct nv50_graph_priv *priv,
442 u32 ustatus_addr, u32 ustatus, u32 tp)
443{
444 u32 e0c = nv_rd32(priv, ustatus_addr + 0x04);
445 u32 e10 = nv_rd32(priv, ustatus_addr + 0x08);
446 u32 e14 = nv_rd32(priv, ustatus_addr + 0x0c);
447 u32 e18 = nv_rd32(priv, ustatus_addr + 0x10);
448 u32 e1c = nv_rd32(priv, ustatus_addr + 0x14);
449 u32 e20 = nv_rd32(priv, ustatus_addr + 0x18);
450 u32 e24 = nv_rd32(priv, ustatus_addr + 0x1c);
451
452
453 if (ustatus & 0x00000080) {
454 if (e18 & 0x80000000) {
455
456 nv_error(priv, "TRAP_PROP - TP %d - CUDA_FAULT - Global read fault at address %02x%08x\n",
457 tp, e14, e10 | ((e18 >> 24) & 0x1f));
458 e18 &= ~0x1f000000;
459 } else if (e18 & 0xc) {
460
461 nv_error(priv, "TRAP_PROP - TP %d - CUDA_FAULT - Global write fault at address %02x%08x\n",
462 tp, e14, e10 | ((e18 >> 7) & 0x1f));
463 e18 &= ~0x00000f80;
464 } else {
465 nv_error(priv, "TRAP_PROP - TP %d - Unknown CUDA fault at address %02x%08x\n",
466 tp, e14, e10);
467 }
468 ustatus &= ~0x00000080;
469 }
470 if (ustatus) {
471 nv_error(priv, "TRAP_PROP - TP %d -", tp);
472 nouveau_bitfield_print(nv50_graph_trap_prop, ustatus);
473 pr_cont(" - Address %02x%08x\n", e14, e10);
474 }
475 nv_error(priv, "TRAP_PROP - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
476 tp, e0c, e18, e1c, e20, e24);
477}
478
479static void
480nv50_priv_mp_trap(struct nv50_graph_priv *priv, int tpid, int display)
481{
482 u32 units = nv_rd32(priv, 0x1540);
483 u32 addr, mp10, status, pc, oplow, ophigh;
484 int i;
485 int mps = 0;
486 for (i = 0; i < 4; i++) {
487 if (!(units & 1 << (i+24)))
488 continue;
489 if (nv_device(priv)->chipset < 0xa0)
490 addr = 0x408200 + (tpid << 12) + (i << 7);
491 else
492 addr = 0x408100 + (tpid << 11) + (i << 7);
493 mp10 = nv_rd32(priv, addr + 0x10);
494 status = nv_rd32(priv, addr + 0x14);
495 if (!status)
496 continue;
497 if (display) {
498 nv_rd32(priv, addr + 0x20);
499 pc = nv_rd32(priv, addr + 0x24);
500 oplow = nv_rd32(priv, addr + 0x70);
501 ophigh = nv_rd32(priv, addr + 0x74);
502 nv_error(priv, "TRAP_MP_EXEC - "
503 "TP %d MP %d:", tpid, i);
504 nouveau_bitfield_print(nv50_mp_exec_errors, status);
505 pr_cont(" at %06x warp %d, opcode %08x %08x\n",
506 pc&0xffffff, pc >> 24,
507 oplow, ophigh);
508 }
509 nv_wr32(priv, addr + 0x10, mp10);
510 nv_wr32(priv, addr + 0x14, 0);
511 mps++;
512 }
513 if (!mps && display)
514 nv_error(priv, "TRAP_MP_EXEC - TP %d: "
515 "No MPs claiming errors?\n", tpid);
516}
517
518static void
519nv50_priv_tp_trap(struct nv50_graph_priv *priv, int type, u32 ustatus_old,
520 u32 ustatus_new, int display, const char *name)
521{
522 int tps = 0;
523 u32 units = nv_rd32(priv, 0x1540);
524 int i, r;
525 u32 ustatus_addr, ustatus;
526 for (i = 0; i < 16; i++) {
527 if (!(units & (1 << i)))
528 continue;
529 if (nv_device(priv)->chipset < 0xa0)
530 ustatus_addr = ustatus_old + (i << 12);
531 else
532 ustatus_addr = ustatus_new + (i << 11);
533 ustatus = nv_rd32(priv, ustatus_addr) & 0x7fffffff;
534 if (!ustatus)
535 continue;
536 tps++;
537 switch (type) {
538 case 6:
539 if (display) {
540 nv_error(priv, "magic set %d:\n", i);
541 for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4)
542 nv_error(priv, "\t0x%08x: 0x%08x\n", r,
543 nv_rd32(priv, r));
544 if (ustatus) {
545 nv_error(priv, "%s - TP%d:", name, i);
546 nouveau_bitfield_print(nv50_tex_traps,
547 ustatus);
548 pr_cont("\n");
549 ustatus = 0;
550 }
551 }
552 break;
553 case 7:
554 if (ustatus & 0x04030000) {
555 nv50_priv_mp_trap(priv, i, display);
556 ustatus &= ~0x04030000;
557 }
558 if (ustatus && display) {
559 nv_error(priv, "%s - TP%d:", name, i);
560 nouveau_bitfield_print(nv50_mpc_traps, ustatus);
561 pr_cont("\n");
562 ustatus = 0;
563 }
564 break;
565 case 8:
566 if (display)
567 nv50_priv_prop_trap(
568 priv, ustatus_addr, ustatus, i);
569 ustatus = 0;
570 break;
571 }
572 if (ustatus) {
573 if (display)
574 nv_error(priv, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus);
575 }
576 nv_wr32(priv, ustatus_addr, 0xc0000000);
577 }
578
579 if (!tps && display)
580 nv_warn(priv, "%s - No TPs claiming errors?\n", name);
581}
582
583static int
584nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display,
585 int chid, u64 inst, struct nouveau_object *engctx)
586{
587 u32 status = nv_rd32(priv, 0x400108);
588 u32 ustatus;
589
590 if (!status && display) {
591 nv_error(priv, "TRAP: no units reporting traps?\n");
592 return 1;
593 }
594
595
596
597
598 if (status & 0x001) {
599 ustatus = nv_rd32(priv, 0x400804) & 0x7fffffff;
600 if (!ustatus && display) {
601 nv_error(priv, "TRAP_DISPATCH - no ustatus?\n");
602 }
603
604 nv_wr32(priv, 0x400500, 0x00000000);
605
606
607 if (ustatus & 0x00000001) {
608 u32 addr = nv_rd32(priv, 0x400808);
609 u32 subc = (addr & 0x00070000) >> 16;
610 u32 mthd = (addr & 0x00001ffc);
611 u32 datal = nv_rd32(priv, 0x40080c);
612 u32 datah = nv_rd32(priv, 0x400810);
613 u32 class = nv_rd32(priv, 0x400814);
614 u32 r848 = nv_rd32(priv, 0x400848);
615
616 nv_error(priv, "TRAP DISPATCH_FAULT\n");
617 if (display && (addr & 0x80000000)) {
618 nv_error(priv,
619 "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x%08x 400808 0x%08x 400848 0x%08x\n",
620 chid, inst,
621 nouveau_client_name(engctx), subc,
622 class, mthd, datah, datal, addr, r848);
623 } else
624 if (display) {
625 nv_error(priv, "no stuck command?\n");
626 }
627
628 nv_wr32(priv, 0x400808, 0);
629 nv_wr32(priv, 0x4008e8, nv_rd32(priv, 0x4008e8) & 3);
630 nv_wr32(priv, 0x400848, 0);
631 ustatus &= ~0x00000001;
632 }
633
634 if (ustatus & 0x00000002) {
635 u32 addr = nv_rd32(priv, 0x40084c);
636 u32 subc = (addr & 0x00070000) >> 16;
637 u32 mthd = (addr & 0x00001ffc);
638 u32 data = nv_rd32(priv, 0x40085c);
639 u32 class = nv_rd32(priv, 0x400814);
640
641 nv_error(priv, "TRAP DISPATCH_QUERY\n");
642 if (display && (addr & 0x80000000)) {
643 nv_error(priv,
644 "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x 40084c 0x%08x\n",
645 chid, inst,
646 nouveau_client_name(engctx), subc,
647 class, mthd, data, addr);
648 } else
649 if (display) {
650 nv_error(priv, "no stuck command?\n");
651 }
652
653 nv_wr32(priv, 0x40084c, 0);
654 ustatus &= ~0x00000002;
655 }
656
657 if (ustatus && display) {
658 nv_error(priv, "TRAP_DISPATCH (unknown "
659 "0x%08x)\n", ustatus);
660 }
661
662 nv_wr32(priv, 0x400804, 0xc0000000);
663 nv_wr32(priv, 0x400108, 0x001);
664 status &= ~0x001;
665 if (!status)
666 return 0;
667 }
668
669
670 if (status & 0x002) {
671 u32 ustatus = nv_rd32(priv, 0x406800) & 0x7fffffff;
672 if (display) {
673 nv_error(priv, "TRAP_M2MF");
674 nouveau_bitfield_print(nv50_graph_trap_m2mf, ustatus);
675 pr_cont("\n");
676 nv_error(priv, "TRAP_M2MF %08x %08x %08x %08x\n",
677 nv_rd32(priv, 0x406804), nv_rd32(priv, 0x406808),
678 nv_rd32(priv, 0x40680c), nv_rd32(priv, 0x406810));
679
680 }
681
682
683 nv_wr32(priv, 0x400040, 2);
684 nv_wr32(priv, 0x400040, 0);
685 nv_wr32(priv, 0x406800, 0xc0000000);
686 nv_wr32(priv, 0x400108, 0x002);
687 status &= ~0x002;
688 }
689
690
691 if (status & 0x004) {
692 u32 ustatus = nv_rd32(priv, 0x400c04) & 0x7fffffff;
693 if (display) {
694 nv_error(priv, "TRAP_VFETCH");
695 nouveau_bitfield_print(nv50_graph_trap_vfetch, ustatus);
696 pr_cont("\n");
697 nv_error(priv, "TRAP_VFETCH %08x %08x %08x %08x\n",
698 nv_rd32(priv, 0x400c00), nv_rd32(priv, 0x400c08),
699 nv_rd32(priv, 0x400c0c), nv_rd32(priv, 0x400c10));
700 }
701
702 nv_wr32(priv, 0x400c04, 0xc0000000);
703 nv_wr32(priv, 0x400108, 0x004);
704 status &= ~0x004;
705 }
706
707
708 if (status & 0x008) {
709 ustatus = nv_rd32(priv, 0x401800) & 0x7fffffff;
710 if (display) {
711 nv_error(priv, "TRAP_STRMOUT");
712 nouveau_bitfield_print(nv50_graph_trap_strmout, ustatus);
713 pr_cont("\n");
714 nv_error(priv, "TRAP_STRMOUT %08x %08x %08x %08x\n",
715 nv_rd32(priv, 0x401804), nv_rd32(priv, 0x401808),
716 nv_rd32(priv, 0x40180c), nv_rd32(priv, 0x401810));
717
718 }
719
720
721 nv_wr32(priv, 0x400040, 0x80);
722 nv_wr32(priv, 0x400040, 0);
723 nv_wr32(priv, 0x401800, 0xc0000000);
724 nv_wr32(priv, 0x400108, 0x008);
725 status &= ~0x008;
726 }
727
728
729 if (status & 0x010) {
730 ustatus = nv_rd32(priv, 0x405018) & 0x7fffffff;
731 if (display) {
732 nv_error(priv, "TRAP_CCACHE");
733 nouveau_bitfield_print(nv50_graph_trap_ccache, ustatus);
734 pr_cont("\n");
735 nv_error(priv, "TRAP_CCACHE %08x %08x %08x %08x"
736 " %08x %08x %08x\n",
737 nv_rd32(priv, 0x405000), nv_rd32(priv, 0x405004),
738 nv_rd32(priv, 0x405008), nv_rd32(priv, 0x40500c),
739 nv_rd32(priv, 0x405010), nv_rd32(priv, 0x405014),
740 nv_rd32(priv, 0x40501c));
741
742 }
743
744 nv_wr32(priv, 0x405018, 0xc0000000);
745 nv_wr32(priv, 0x400108, 0x010);
746 status &= ~0x010;
747 }
748
749
750
751
752 if (status & 0x20) {
753 ustatus = nv_rd32(priv, 0x402000) & 0x7fffffff;
754 if (display)
755 nv_error(priv, "TRAP_UNKC04 0x%08x\n", ustatus);
756 nv_wr32(priv, 0x402000, 0xc0000000);
757
758 }
759
760
761 if (status & 0x040) {
762 nv50_priv_tp_trap(priv, 6, 0x408900, 0x408600, display,
763 "TRAP_TEXTURE");
764 nv_wr32(priv, 0x400108, 0x040);
765 status &= ~0x040;
766 }
767
768
769 if (status & 0x080) {
770 nv50_priv_tp_trap(priv, 7, 0x408314, 0x40831c, display,
771 "TRAP_MP");
772 nv_wr32(priv, 0x400108, 0x080);
773 status &= ~0x080;
774 }
775
776
777
778 if (status & 0x100) {
779 nv50_priv_tp_trap(priv, 8, 0x408e08, 0x408708, display,
780 "TRAP_PROP");
781 nv_wr32(priv, 0x400108, 0x100);
782 status &= ~0x100;
783 }
784
785 if (status) {
786 if (display)
787 nv_error(priv, "TRAP: unknown 0x%08x\n", status);
788 nv_wr32(priv, 0x400108, status);
789 }
790
791 return 1;
792}
793
794static void
795nv50_graph_intr(struct nouveau_subdev *subdev)
796{
797 struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
798 struct nouveau_engine *engine = nv_engine(subdev);
799 struct nouveau_object *engctx;
800 struct nouveau_handle *handle = NULL;
801 struct nv50_graph_priv *priv = (void *)subdev;
802 u32 stat = nv_rd32(priv, 0x400100);
803 u32 inst = nv_rd32(priv, 0x40032c) & 0x0fffffff;
804 u32 addr = nv_rd32(priv, 0x400704);
805 u32 subc = (addr & 0x00070000) >> 16;
806 u32 mthd = (addr & 0x00001ffc);
807 u32 data = nv_rd32(priv, 0x400708);
808 u32 class = nv_rd32(priv, 0x400814);
809 u32 show = stat, show_bitfield = stat;
810 int chid;
811
812 engctx = nouveau_engctx_get(engine, inst);
813 chid = pfifo->chid(pfifo, engctx);
814
815 if (stat & 0x00000010) {
816 handle = nouveau_handle_get_class(engctx, class);
817 if (handle && !nv_call(handle->object, mthd, data))
818 show &= ~0x00000010;
819 nouveau_handle_put(handle);
820 }
821
822 if (show & 0x00100000) {
823 u32 ecode = nv_rd32(priv, 0x400110);
824 nv_error(priv, "DATA_ERROR ");
825 nouveau_enum_print(nv50_data_error_names, ecode);
826 pr_cont("\n");
827 show_bitfield &= ~0x00100000;
828 }
829
830 if (stat & 0x00200000) {
831 if (!nv50_graph_trap_handler(priv, show, chid, (u64)inst << 12,
832 engctx))
833 show &= ~0x00200000;
834 show_bitfield &= ~0x00200000;
835 }
836
837 nv_wr32(priv, 0x400100, stat);
838 nv_wr32(priv, 0x400500, 0x00010001);
839
840 if (show) {
841 show &= show_bitfield;
842 if (show) {
843 nv_error(priv, "%s", "");
844 nouveau_bitfield_print(nv50_graph_intr_name, show);
845 pr_cont("\n");
846 }
847 nv_error(priv,
848 "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
849 chid, (u64)inst << 12, nouveau_client_name(engctx),
850 subc, class, mthd, data);
851 }
852
853 if (nv_rd32(priv, 0x400824) & (1 << 31))
854 nv_wr32(priv, 0x400824, nv_rd32(priv, 0x400824) & ~(1 << 31));
855
856 nouveau_engctx_put(engctx);
857}
858
859static int
860nv50_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
861 struct nouveau_oclass *oclass, void *data, u32 size,
862 struct nouveau_object **pobject)
863{
864 struct nv50_graph_priv *priv;
865 int ret;
866
867 ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
868 *pobject = nv_object(priv);
869 if (ret)
870 return ret;
871
872 nv_subdev(priv)->unit = 0x00201000;
873 nv_subdev(priv)->intr = nv50_graph_intr;
874 nv_engine(priv)->cclass = &nv50_graph_cclass;
875
876 priv->base.units = nv50_graph_units;
877
878 switch (nv_device(priv)->chipset) {
879 case 0x50:
880 nv_engine(priv)->sclass = nv50_graph_sclass;
881 break;
882 case 0x84:
883 case 0x86:
884 case 0x92:
885 case 0x94:
886 case 0x96:
887 case 0x98:
888 nv_engine(priv)->sclass = nv84_graph_sclass;
889 break;
890 case 0xa0:
891 case 0xaa:
892 case 0xac:
893 nv_engine(priv)->sclass = nva0_graph_sclass;
894 break;
895 case 0xa3:
896 case 0xa5:
897 case 0xa8:
898 nv_engine(priv)->sclass = nva3_graph_sclass;
899 break;
900 case 0xaf:
901 nv_engine(priv)->sclass = nvaf_graph_sclass;
902 break;
903
904 }
905
906
907 if (nv_device(priv)->chipset != 0x50 &&
908 nv_device(priv)->chipset != 0xac)
909 nv_engine(priv)->tlb_flush = nv84_graph_tlb_flush;
910
911 spin_lock_init(&priv->lock);
912 return 0;
913}
914
915static int
916nv50_graph_init(struct nouveau_object *object)
917{
918 struct nv50_graph_priv *priv = (void *)object;
919 int ret, units, i;
920
921 ret = nouveau_graph_init(&priv->base);
922 if (ret)
923 return ret;
924
925
926 nv_wr32(priv, 0x40008c, 0x00000004);
927
928
929 nv_wr32(priv, 0x400804, 0xc0000000);
930 nv_wr32(priv, 0x406800, 0xc0000000);
931 nv_wr32(priv, 0x400c04, 0xc0000000);
932 nv_wr32(priv, 0x401800, 0xc0000000);
933 nv_wr32(priv, 0x405018, 0xc0000000);
934 nv_wr32(priv, 0x402000, 0xc0000000);
935
936 units = nv_rd32(priv, 0x001540);
937 for (i = 0; i < 16; i++) {
938 if (!(units & (1 << i)))
939 continue;
940
941 if (nv_device(priv)->chipset < 0xa0) {
942 nv_wr32(priv, 0x408900 + (i << 12), 0xc0000000);
943 nv_wr32(priv, 0x408e08 + (i << 12), 0xc0000000);
944 nv_wr32(priv, 0x408314 + (i << 12), 0xc0000000);
945 } else {
946 nv_wr32(priv, 0x408600 + (i << 11), 0xc0000000);
947 nv_wr32(priv, 0x408708 + (i << 11), 0xc0000000);
948 nv_wr32(priv, 0x40831c + (i << 11), 0xc0000000);
949 }
950 }
951
952 nv_wr32(priv, 0x400108, 0xffffffff);
953 nv_wr32(priv, 0x400138, 0xffffffff);
954 nv_wr32(priv, 0x400100, 0xffffffff);
955 nv_wr32(priv, 0x40013c, 0xffffffff);
956 nv_wr32(priv, 0x400500, 0x00010001);
957
958
959 ret = nv50_grctx_init(nv_device(priv), &priv->size);
960 if (ret)
961 return ret;
962
963 nv_wr32(priv, 0x400824, 0x00000000);
964 nv_wr32(priv, 0x400828, 0x00000000);
965 nv_wr32(priv, 0x40082c, 0x00000000);
966 nv_wr32(priv, 0x400830, 0x00000000);
967 nv_wr32(priv, 0x40032c, 0x00000000);
968 nv_wr32(priv, 0x400330, 0x00000000);
969
970
971 switch (nv_device(priv)->chipset & 0xf0) {
972 case 0x50:
973 case 0x80:
974 case 0x90:
975 nv_wr32(priv, 0x402ca8, 0x00000800);
976 break;
977 case 0xa0:
978 default:
979 if (nv_device(priv)->chipset == 0xa0 ||
980 nv_device(priv)->chipset == 0xaa ||
981 nv_device(priv)->chipset == 0xac) {
982 nv_wr32(priv, 0x402ca8, 0x00000802);
983 } else {
984 nv_wr32(priv, 0x402cc0, 0x00000000);
985 nv_wr32(priv, 0x402ca8, 0x00000002);
986 }
987
988 break;
989 }
990
991
992 for (i = 0; i < 8; i++) {
993 nv_wr32(priv, 0x402c20 + (i * 0x10), 0x00000000);
994 nv_wr32(priv, 0x402c24 + (i * 0x10), 0x00000000);
995 nv_wr32(priv, 0x402c28 + (i * 0x10), 0x00000000);
996 nv_wr32(priv, 0x402c2c + (i * 0x10), 0x00000000);
997 }
998 return 0;
999}
1000
1001struct nouveau_oclass
1002nv50_graph_oclass = {
1003 .handle = NV_ENGINE(GR, 0x50),
1004 .ofuncs = &(struct nouveau_ofuncs) {
1005 .ctor = nv50_graph_ctor,
1006 .dtor = _nouveau_graph_dtor,
1007 .init = nv50_graph_init,
1008 .fini = _nouveau_graph_fini,
1009 },
1010};
1011
