LXR linux/drivers/gpu/drm/nouveau/nvc0

   1/*
   2 * Copyright 2012 Red Hat Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: Ben Skeggs
  23 */
  24
  25#include <core/object.h>
  26#include <core/client.h>
  27#include <core/class.h>
  28
  29#include <engine/fifo.h>
  30
  31#include "nouveau_drm.h"
  32#include "nouveau_dma.h"
  33#include "nouveau_fence.h"
  34
  35#include "nv50_display.h"
  36
  37static int
  38nvc0_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
  39{
  40        int ret = RING_SPACE(chan, 6);
  41        if (ret == 0) {
  42                BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 5);
  43                OUT_RING  (chan, upper_32_bits(virtual));
  44                OUT_RING  (chan, lower_32_bits(virtual));
  45                OUT_RING  (chan, sequence);
  46                OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
  47                OUT_RING  (chan, 0x00000000);
  48                FIRE_RING (chan);
  49        }
  50        return ret;
  51}
  52
  53static int
  54nvc0_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
  55{
  56        int ret = RING_SPACE(chan, 5);
  57        if (ret == 0) {
  58                BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
  59                OUT_RING  (chan, upper_32_bits(virtual));
  60                OUT_RING  (chan, lower_32_bits(virtual));
  61                OUT_RING  (chan, sequence);
  62                OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL |
  63                                 NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
  64                FIRE_RING (chan);
  65        }
  66        return ret;
  67}
  68
  69static int
  70nvc0_fence_context_new(struct nouveau_channel *chan)
  71{
  72        int ret = nv84_fence_context_new(chan);
  73        if (ret == 0) {
  74                struct nv84_fence_chan *fctx = chan->fence;
  75                fctx->base.emit32 = nvc0_fence_emit32;
  76                fctx->base.sync32 = nvc0_fence_sync32;
  77        }
  78        return ret;
  79}
  80
  81int
  82nvc0_fence_create(struct nouveau_drm *drm)
  83{
  84        int ret = nv84_fence_create(drm);
  85        if (ret == 0) {
  86                struct nv84_fence_priv *priv = drm->fence;
  87                priv->base.context_new = nvc0_fence_context_new;
  88        }
  89        return ret;
  90}
  91