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31#ifndef __ALTERA_TSE_H__
32#define __ALTERA_TSE_H__
33
34#define ALTERA_TSE_RESOURCE_NAME "altera_tse"
35
36#include <linux/bitops.h>
37#include <linux/if_vlan.h>
38#include <linux/list.h>
39#include <linux/netdevice.h>
40#include <linux/phy.h>
41
42#define ALTERA_TSE_SW_RESET_WATCHDOG_CNTR 10000
43#define ALTERA_TSE_MAC_FIFO_WIDTH 4
44
45
46
47#define ALTERA_TSE_RX_SECTION_EMPTY 16
48#define ALTERA_TSE_RX_SECTION_FULL 0
49#define ALTERA_TSE_RX_ALMOST_EMPTY 8
50#define ALTERA_TSE_RX_ALMOST_FULL 8
51
52
53#define ALTERA_TSE_TX_SECTION_EMPTY 16
54#define ALTERA_TSE_TX_SECTION_FULL 0
55#define ALTERA_TSE_TX_ALMOST_EMPTY 8
56#define ALTERA_TSE_TX_ALMOST_FULL 3
57
58
59#define ALTERA_TSE_TX_IPG_LENGTH 12
60
61#define ALTERA_TSE_PAUSE_QUANTA 0xffff
62
63#define GET_BIT_VALUE(v, bit) (((v) >> (bit)) & 0x1)
64
65
66
67#define MAC_CMDCFG_TX_ENA BIT(0)
68#define MAC_CMDCFG_RX_ENA BIT(1)
69#define MAC_CMDCFG_XON_GEN BIT(2)
70#define MAC_CMDCFG_ETH_SPEED BIT(3)
71#define MAC_CMDCFG_PROMIS_EN BIT(4)
72#define MAC_CMDCFG_PAD_EN BIT(5)
73#define MAC_CMDCFG_CRC_FWD BIT(6)
74#define MAC_CMDCFG_PAUSE_FWD BIT(7)
75#define MAC_CMDCFG_PAUSE_IGNORE BIT(8)
76#define MAC_CMDCFG_TX_ADDR_INS BIT(9)
77#define MAC_CMDCFG_HD_ENA BIT(10)
78#define MAC_CMDCFG_EXCESS_COL BIT(11)
79#define MAC_CMDCFG_LATE_COL BIT(12)
80#define MAC_CMDCFG_SW_RESET BIT(13)
81#define MAC_CMDCFG_MHASH_SEL BIT(14)
82#define MAC_CMDCFG_LOOP_ENA BIT(15)
83#define MAC_CMDCFG_TX_ADDR_SEL(v) (((v) & 0x7) << 16)
84#define MAC_CMDCFG_MAGIC_ENA BIT(19)
85#define MAC_CMDCFG_SLEEP BIT(20)
86#define MAC_CMDCFG_WAKEUP BIT(21)
87#define MAC_CMDCFG_XOFF_GEN BIT(22)
88#define MAC_CMDCFG_CNTL_FRM_ENA BIT(23)
89#define MAC_CMDCFG_NO_LGTH_CHECK BIT(24)
90#define MAC_CMDCFG_ENA_10 BIT(25)
91#define MAC_CMDCFG_RX_ERR_DISC BIT(26)
92#define MAC_CMDCFG_DISABLE_READ_TIMEOUT BIT(27)
93#define MAC_CMDCFG_CNT_RESET BIT(31)
94
95#define MAC_CMDCFG_TX_ENA_GET(v) GET_BIT_VALUE(v, 0)
96#define MAC_CMDCFG_RX_ENA_GET(v) GET_BIT_VALUE(v, 1)
97#define MAC_CMDCFG_XON_GEN_GET(v) GET_BIT_VALUE(v, 2)
98#define MAC_CMDCFG_ETH_SPEED_GET(v) GET_BIT_VALUE(v, 3)
99#define MAC_CMDCFG_PROMIS_EN_GET(v) GET_BIT_VALUE(v, 4)
100#define MAC_CMDCFG_PAD_EN_GET(v) GET_BIT_VALUE(v, 5)
101#define MAC_CMDCFG_CRC_FWD_GET(v) GET_BIT_VALUE(v, 6)
102#define MAC_CMDCFG_PAUSE_FWD_GET(v) GET_BIT_VALUE(v, 7)
103#define MAC_CMDCFG_PAUSE_IGNORE_GET(v) GET_BIT_VALUE(v, 8)
104#define MAC_CMDCFG_TX_ADDR_INS_GET(v) GET_BIT_VALUE(v, 9)
105#define MAC_CMDCFG_HD_ENA_GET(v) GET_BIT_VALUE(v, 10)
106#define MAC_CMDCFG_EXCESS_COL_GET(v) GET_BIT_VALUE(v, 11)
107#define MAC_CMDCFG_LATE_COL_GET(v) GET_BIT_VALUE(v, 12)
108#define MAC_CMDCFG_SW_RESET_GET(v) GET_BIT_VALUE(v, 13)
109#define MAC_CMDCFG_MHASH_SEL_GET(v) GET_BIT_VALUE(v, 14)
110#define MAC_CMDCFG_LOOP_ENA_GET(v) GET_BIT_VALUE(v, 15)
111#define MAC_CMDCFG_TX_ADDR_SEL_GET(v) (((v) >> 16) & 0x7)
112#define MAC_CMDCFG_MAGIC_ENA_GET(v) GET_BIT_VALUE(v, 19)
113#define MAC_CMDCFG_SLEEP_GET(v) GET_BIT_VALUE(v, 20)
114#define MAC_CMDCFG_WAKEUP_GET(v) GET_BIT_VALUE(v, 21)
115#define MAC_CMDCFG_XOFF_GEN_GET(v) GET_BIT_VALUE(v, 22)
116#define MAC_CMDCFG_CNTL_FRM_ENA_GET(v) GET_BIT_VALUE(v, 23)
117#define MAC_CMDCFG_NO_LGTH_CHECK_GET(v) GET_BIT_VALUE(v, 24)
118#define MAC_CMDCFG_ENA_10_GET(v) GET_BIT_VALUE(v, 25)
119#define MAC_CMDCFG_RX_ERR_DISC_GET(v) GET_BIT_VALUE(v, 26)
120#define MAC_CMDCFG_DISABLE_READ_TIMEOUT_GET(v) GET_BIT_VALUE(v, 27)
121#define MAC_CMDCFG_CNT_RESET_GET(v) GET_BIT_VALUE(v, 31)
122
123
124
125struct altera_tse_mdio {
126 u32 control;
127 u32 status;
128 u32 phy_id1;
129 u32 phy_id2;
130 u32 auto_negotiation_advertisement;
131
132
133
134 u32 remote_partner_base_page_ability;
135
136 u32 reg6;
137 u32 reg7;
138 u32 reg8;
139 u32 reg9;
140 u32 rega;
141 u32 regb;
142 u32 regc;
143 u32 regd;
144 u32 rege;
145 u32 regf;
146 u32 reg10;
147 u32 reg11;
148 u32 reg12;
149 u32 reg13;
150 u32 reg14;
151 u32 reg15;
152 u32 reg16;
153 u32 reg17;
154 u32 reg18;
155 u32 reg19;
156 u32 reg1a;
157 u32 reg1b;
158 u32 reg1c;
159 u32 reg1d;
160 u32 reg1e;
161 u32 reg1f;
162};
163
164
165
166
167
168
169struct altera_tse_mac {
170
171
172
173 u32 megacore_revision;
174
175
176
177 u32 scratch_pad;
178
179
180
181 u32 command_config;
182
183
184
185 u32 mac_addr_0;
186
187
188
189 u32 mac_addr_1;
190
191 u32 frm_length;
192
193
194
195 u32 pause_quanta;
196
197 u32 rx_section_empty;
198
199 u32 rx_section_full;
200
201 u32 tx_section_empty;
202
203 u32 tx_section_full;
204
205 u32 rx_almost_empty;
206
207 u32 rx_almost_full;
208
209 u32 tx_almost_empty;
210
211 u32 tx_almost_full;
212
213 u32 mdio_phy0_addr;
214
215 u32 mdio_phy1_addr;
216
217
218 u32 holdoff_quant;
219
220
221 u32 reserved1[5];
222
223
224 u32 tx_ipg_length;
225
226
227
228
229 u32 mac_id_1;
230 u32 mac_id_2;
231
232
233 u32 frames_transmitted_ok;
234
235 u32 frames_received_ok;
236
237 u32 frames_check_sequence_errors;
238
239 u32 alignment_errors;
240
241
242
243 u32 octets_transmitted_ok;
244
245 u32 octets_received_ok;
246
247
248
249
250 u32 tx_pause_mac_ctrl_frames;
251
252 u32 rx_pause_mac_ctrl_frames;
253
254
255
256
257 u32 if_in_errors;
258
259 u32 if_out_errors;
260
261 u32 if_in_ucast_pkts;
262
263 u32 if_in_multicast_pkts;
264
265 u32 if_in_broadcast_pkts;
266 u32 if_out_discards;
267
268 u32 if_out_ucast_pkts;
269
270
271
272 u32 if_out_multicast_pkts;
273 u32 if_out_broadcast_pkts;
274
275
276
277
278
279
280 u32 ether_stats_drop_events;
281
282 u32 ether_stats_octets;
283
284 u32 ether_stats_pkts;
285
286 u32 ether_stats_undersize_pkts;
287
288
289
290 u32 ether_stats_oversize_pkts;
291
292 u32 ether_stats_pkts_64_octets;
293
294 u32 ether_stats_pkts_65to127_octets;
295
296 u32 ether_stats_pkts_128to255_octets;
297
298 u32 ether_stats_pkts_256to511_octets;
299
300 u32 ether_stats_pkts_512to1023_octets;
301
302 u32 ether_stats_pkts_1024to1518_octets;
303
304
305
306
307 u32 ether_stats_pkts_1519tox_octets;
308
309 u32 ether_stats_jabbers;
310
311 u32 ether_stats_fragments;
312
313 u32 reserved2;
314
315
316 u32 tx_cmd_stat;
317 u32 rx_cmd_stat;
318
319
320 u32 msb_octets_transmitted_ok;
321 u32 msb_octets_received_ok;
322 u32 msb_ether_stats_octets;
323
324 u32 reserved3;
325
326
327
328
329 u32 hash_table[64];
330
331
332
333
334 struct altera_tse_mdio mdio_phy0;
335 struct altera_tse_mdio mdio_phy1;
336
337
338 u32 supp_mac_addr_0_0;
339 u32 supp_mac_addr_0_1;
340 u32 supp_mac_addr_1_0;
341 u32 supp_mac_addr_1_1;
342 u32 supp_mac_addr_2_0;
343 u32 supp_mac_addr_2_1;
344 u32 supp_mac_addr_3_0;
345 u32 supp_mac_addr_3_1;
346
347 u32 reserved4[8];
348
349
350 u32 tx_period;
351 u32 tx_adjust_fns;
352 u32 tx_adjust_ns;
353 u32 rx_period;
354 u32 rx_adjust_fns;
355 u32 rx_adjust_ns;
356
357 u32 reserved5[42];
358};
359
360#define tse_csroffs(a) (offsetof(struct altera_tse_mac, a))
361
362
363
364#define ALTERA_TSE_TX_CMD_STAT_OMIT_CRC BIT(17)
365#define ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 BIT(18)
366#define ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16 BIT(25)
367
368
369
370
371struct tse_buffer {
372 struct list_head lh;
373 struct sk_buff *skb;
374 dma_addr_t dma_addr;
375 u32 len;
376 int mapped_as_page;
377};
378
379struct altera_tse_private;
380
381#define ALTERA_DTYPE_SGDMA 1
382#define ALTERA_DTYPE_MSGDMA 2
383
384
385struct altera_dmaops {
386 int altera_dtype;
387 int dmamask;
388 void (*reset_dma)(struct altera_tse_private *);
389 void (*enable_txirq)(struct altera_tse_private *);
390 void (*enable_rxirq)(struct altera_tse_private *);
391 void (*disable_txirq)(struct altera_tse_private *);
392 void (*disable_rxirq)(struct altera_tse_private *);
393 void (*clear_txirq)(struct altera_tse_private *);
394 void (*clear_rxirq)(struct altera_tse_private *);
395 int (*tx_buffer)(struct altera_tse_private *, struct tse_buffer *);
396 u32 (*tx_completions)(struct altera_tse_private *);
397 void (*add_rx_desc)(struct altera_tse_private *, struct tse_buffer *);
398 u32 (*get_rx_status)(struct altera_tse_private *);
399 int (*init_dma)(struct altera_tse_private *);
400 void (*uninit_dma)(struct altera_tse_private *);
401 void (*start_rxdma)(struct altera_tse_private *);
402};
403
404
405
406struct altera_tse_private {
407 struct net_device *dev;
408 struct device *device;
409 struct napi_struct napi;
410
411
412 struct altera_tse_mac __iomem *mac_dev;
413
414
415 u32 revision;
416
417
418 void __iomem *rx_dma_csr;
419 void __iomem *rx_dma_desc;
420 void __iomem *rx_dma_resp;
421
422
423 void __iomem *tx_dma_csr;
424 void __iomem *tx_dma_desc;
425
426
427 struct tse_buffer *rx_ring;
428 u32 rx_cons;
429 u32 rx_prod;
430 u32 rx_ring_size;
431 u32 rx_dma_buf_sz;
432
433
434 struct tse_buffer *tx_ring;
435 u32 tx_prod;
436 u32 tx_cons;
437 u32 tx_ring_size;
438
439
440 u32 tx_irq;
441 u32 rx_irq;
442
443
444 u32 tx_fifo_depth;
445 u32 rx_fifo_depth;
446 u32 max_mtu;
447
448
449 u32 hash_filter;
450 u32 added_unicast;
451
452
453 u32 txdescmem;
454 u32 rxdescmem;
455 dma_addr_t rxdescmem_busaddr;
456 dma_addr_t txdescmem_busaddr;
457 u32 txctrlreg;
458 u32 rxctrlreg;
459 dma_addr_t rxdescphys;
460 dma_addr_t txdescphys;
461 size_t sgdmadesclen;
462
463 struct list_head txlisthd;
464 struct list_head rxlisthd;
465
466
467 spinlock_t mac_cfg_lock;
468
469 spinlock_t tx_lock;
470
471 spinlock_t rxdma_irq_lock;
472
473
474 int phy_addr;
475 phy_interface_t phy_iface;
476 struct mii_bus *mdio;
477 struct phy_device *phydev;
478 int oldspeed;
479 int oldduplex;
480 int oldlink;
481
482
483 u32 msg_enable;
484
485 struct altera_dmaops *dmaops;
486};
487
488
489
490void altera_tse_set_ethtool_ops(struct net_device *);
491
492static inline
493u32 csrrd32(void __iomem *mac, size_t offs)
494{
495 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
496 return readl(paddr);
497}
498
499static inline
500u16 csrrd16(void __iomem *mac, size_t offs)
501{
502 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
503 return readw(paddr);
504}
505
506static inline
507u8 csrrd8(void __iomem *mac, size_t offs)
508{
509 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
510 return readb(paddr);
511}
512
513static inline
514void csrwr32(u32 val, void __iomem *mac, size_t offs)
515{
516 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
517
518 writel(val, paddr);
519}
520
521static inline
522void csrwr16(u16 val, void __iomem *mac, size_t offs)
523{
524 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
525
526 writew(val, paddr);
527}
528
529static inline
530void csrwr8(u8 val, void __iomem *mac, size_t offs)
531{
532 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
533
534 writeb(val, paddr);
535}
536
537#endif
538