LXR linux/drivers/pinctrl/pinctrl-lantiq.h

   1/*
   2 *  linux/drivers/pinctrl/pinctrl-lantiq.h
   3 *  based on linux/drivers/pinctrl/pinctrl-pxa3xx.h
   4 *
   5 *  This program is free software; you can redistribute it and/or modify
   6 *  it under the terms of the GNU General Public License version 2 as
   7 *  publishhed by the Free Software Foundation.
   8 *
   9 *  Copyright (C) 2012 John Crispin <blogic@openwrt.org>
  10 */
  11
  12#ifndef __PINCTRL_LANTIQ_H
  13#define __PINCTRL_LANTIQ_H
  14
  15#include <linux/clkdev.h>
  16#include <linux/pinctrl/pinctrl.h>
  17#include <linux/pinctrl/pinconf.h>
  18#include <linux/pinctrl/pinmux.h>
  19#include <linux/pinctrl/consumer.h>
  20#include <linux/pinctrl/machine.h>
  21
  22#include "core.h"
  23
  24#define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
  25
  26#define LTQ_MAX_MUX             4
  27#define MFPR_FUNC_MASK          0x3
  28
  29#define LTQ_PINCONF_PACK(param, arg)            ((param) << 16 | (arg))
  30#define LTQ_PINCONF_UNPACK_PARAM(conf)          ((conf) >> 16)
  31#define LTQ_PINCONF_UNPACK_ARG(conf)            ((conf) & 0xffff)
  32
  33enum ltq_pinconf_param {
  34        LTQ_PINCONF_PARAM_PULL,
  35        LTQ_PINCONF_PARAM_OPEN_DRAIN,
  36        LTQ_PINCONF_PARAM_DRIVE_CURRENT,
  37        LTQ_PINCONF_PARAM_SLEW_RATE,
  38        LTQ_PINCONF_PARAM_OUTPUT,
  39};
  40
  41struct ltq_cfg_param {
  42        const char *property;
  43        enum ltq_pinconf_param param;
  44};
  45
  46struct ltq_mfp_pin {
  47        const char *name;
  48        const unsigned int pin;
  49        const unsigned short func[LTQ_MAX_MUX];
  50};
  51
  52struct ltq_pin_group {
  53        const char *name;
  54        const unsigned mux;
  55        const unsigned *pins;
  56        const unsigned npins;
  57};
  58
  59struct ltq_pmx_func {
  60        const char *name;
  61        const char * const *groups;
  62        const unsigned num_groups;
  63};
  64
  65struct ltq_pinmux_info {
  66        struct device *dev;
  67        struct pinctrl_dev *pctrl;
  68
  69        /* we need to manage up to 5 pad controllers */
  70        void __iomem *membase[5];
  71
  72        /* the descriptor for the subsystem */
  73        struct pinctrl_desc *desc;
  74
  75        /* we expose our pads to the subsystem */
  76        struct pinctrl_pin_desc *pads;
  77
  78        /* the number of pads. this varies between socs */
  79        unsigned int num_pads;
  80
  81        /* these are our multifunction pins */
  82        const struct ltq_mfp_pin *mfp;
  83        unsigned int num_mfp;
  84
  85        /* a number of multifunction pins can be grouped together */
  86        const struct ltq_pin_group *grps;
  87        unsigned int num_grps;
  88
  89        /* a mapping between function string and id */
  90        const struct ltq_pmx_func *funcs;
  91        unsigned int num_funcs;
  92
  93        /* the pinconf options that we are able to read from the DT */
  94        const struct ltq_cfg_param *params;
  95        unsigned int num_params;
  96
  97        /* the pad controller can have a irq mapping  */
  98        const unsigned *exin;
  99        unsigned int num_exin;
 100
 101        /* we need 5 clocks max */
 102        struct clk *clk[5];
 103
 104        /* soc specific callback used to apply muxing */
 105        int (*apply_mux)(struct pinctrl_dev *pctrldev, int pin, int mux);
 106};
 107
 108enum ltq_pin {
 109        GPIO0 = 0,
 110        GPIO1,
 111        GPIO2,
 112        GPIO3,
 113        GPIO4,
 114        GPIO5,
 115        GPIO6,
 116        GPIO7,
 117        GPIO8,
 118        GPIO9,
 119        GPIO10, /* 10 */
 120        GPIO11,
 121        GPIO12,
 122        GPIO13,
 123        GPIO14,
 124        GPIO15,
 125        GPIO16,
 126        GPIO17,
 127        GPIO18,
 128        GPIO19,
 129        GPIO20, /* 20 */
 130        GPIO21,
 131        GPIO22,
 132        GPIO23,
 133        GPIO24,
 134        GPIO25,
 135        GPIO26,
 136        GPIO27,
 137        GPIO28,
 138        GPIO29,
 139        GPIO30, /* 30 */
 140        GPIO31,
 141        GPIO32,
 142        GPIO33,
 143        GPIO34,
 144        GPIO35,
 145        GPIO36,
 146        GPIO37,
 147        GPIO38,
 148        GPIO39,
 149        GPIO40, /* 40 */
 150        GPIO41,
 151        GPIO42,
 152        GPIO43,
 153        GPIO44,
 154        GPIO45,
 155        GPIO46,
 156        GPIO47,
 157        GPIO48,
 158        GPIO49,
 159        GPIO50, /* 50 */
 160        GPIO51,
 161        GPIO52,
 162        GPIO53,
 163        GPIO54,
 164        GPIO55,
 165
 166        GPIO64,
 167        GPIO65,
 168        GPIO66,
 169        GPIO67,
 170        GPIO68,
 171        GPIO69,
 172        GPIO70,
 173        GPIO71,
 174        GPIO72,
 175        GPIO73,
 176        GPIO74,
 177        GPIO75,
 178        GPIO76,
 179        GPIO77,
 180        GPIO78,
 181        GPIO79,
 182        GPIO80,
 183        GPIO81,
 184        GPIO82,
 185        GPIO83,
 186        GPIO84,
 187        GPIO85,
 188        GPIO86,
 189        GPIO87,
 190        GPIO88,
 191};
 192
 193extern int ltq_pinctrl_register(struct platform_device *pdev,
 194                                   struct ltq_pinmux_info *info);
 195extern int ltq_pinctrl_unregister(struct platform_device *pdev);
 196#endif  /* __PINCTRL_PXA3XX_H */
 197