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18#ifndef __BFA_DEFS_H__
19#define __BFA_DEFS_H__
20
21#include "bfa_fc.h"
22#include "bfad_drv.h"
23
24#define BFA_MFG_SERIALNUM_SIZE 11
25#define STRSZ(_n) (((_n) + 4) & ~3)
26
27
28
29
30enum {
31 BFA_MFG_TYPE_CB_MAX = 825,
32 BFA_MFG_TYPE_FC8P2 = 825,
33 BFA_MFG_TYPE_FC8P1 = 815,
34 BFA_MFG_TYPE_FC4P2 = 425,
35 BFA_MFG_TYPE_FC4P1 = 415,
36 BFA_MFG_TYPE_CNA10P2 = 1020,
37 BFA_MFG_TYPE_CNA10P1 = 1010,
38 BFA_MFG_TYPE_JAYHAWK = 804,
39 BFA_MFG_TYPE_WANCHESE = 1007,
40 BFA_MFG_TYPE_ASTRA = 807,
41 BFA_MFG_TYPE_LIGHTNING_P0 = 902,
42 BFA_MFG_TYPE_LIGHTNING = 1741,
43 BFA_MFG_TYPE_PROWLER_F = 1560,
44 BFA_MFG_TYPE_PROWLER_N = 1410,
45 BFA_MFG_TYPE_PROWLER_C = 1710,
46 BFA_MFG_TYPE_PROWLER_D = 1860,
47 BFA_MFG_TYPE_CHINOOK = 1867,
48 BFA_MFG_TYPE_CHINOOK2 = 1869,
49 BFA_MFG_TYPE_INVALID = 0,
50};
51
52#pragma pack(1)
53
54
55
56
57#define bfa_mfg_is_mezz(type) (( \
58 (type) == BFA_MFG_TYPE_JAYHAWK || \
59 (type) == BFA_MFG_TYPE_WANCHESE || \
60 (type) == BFA_MFG_TYPE_ASTRA || \
61 (type) == BFA_MFG_TYPE_LIGHTNING_P0 || \
62 (type) == BFA_MFG_TYPE_LIGHTNING || \
63 (type) == BFA_MFG_TYPE_CHINOOK || \
64 (type) == BFA_MFG_TYPE_CHINOOK2))
65
66
67
68
69#define bfa_mfg_is_old_wwn_mac_model(type) (( \
70 (type) == BFA_MFG_TYPE_FC8P2 || \
71 (type) == BFA_MFG_TYPE_FC8P1 || \
72 (type) == BFA_MFG_TYPE_FC4P2 || \
73 (type) == BFA_MFG_TYPE_FC4P1 || \
74 (type) == BFA_MFG_TYPE_CNA10P2 || \
75 (type) == BFA_MFG_TYPE_CNA10P1 || \
76 (type) == BFA_MFG_TYPE_JAYHAWK || \
77 (type) == BFA_MFG_TYPE_WANCHESE))
78
79#define bfa_mfg_increment_wwn_mac(m, i) \
80do { \
81 u32 t = ((u32)(m)[0] << 16) | ((u32)(m)[1] << 8) | \
82 (u32)(m)[2]; \
83 t += (i); \
84 (m)[0] = (t >> 16) & 0xFF; \
85 (m)[1] = (t >> 8) & 0xFF; \
86 (m)[2] = t & 0xFF; \
87} while (0)
88
89
90
91
92#define BFA_MFG_VPD_LEN 512
93
94
95
96
97enum {
98 BFA_MFG_VPD_UNKNOWN = 0,
99 BFA_MFG_VPD_IBM = 1,
100 BFA_MFG_VPD_HP = 2,
101 BFA_MFG_VPD_DELL = 3,
102 BFA_MFG_VPD_PCI_IBM = 0x08,
103 BFA_MFG_VPD_PCI_HP = 0x10,
104 BFA_MFG_VPD_PCI_DELL = 0x20,
105 BFA_MFG_VPD_PCI_BRCD = 0xf8,
106};
107
108
109
110
111struct bfa_mfg_vpd_s {
112 u8 version;
113 u8 vpd_sig[3];
114 u8 chksum;
115 u8 vendor;
116 u8 len;
117 u8 rsv;
118 u8 data[BFA_MFG_VPD_LEN];
119};
120
121#pragma pack()
122
123
124
125
126enum bfa_status {
127 BFA_STATUS_OK = 0,
128 BFA_STATUS_FAILED = 1,
129 BFA_STATUS_EINVAL = 2,
130
131 BFA_STATUS_ENOMEM = 3,
132 BFA_STATUS_ETIMER = 5,
133
134 BFA_STATUS_EPROTOCOL = 6,
135 BFA_STATUS_BADFLASH = 9,
136 BFA_STATUS_SFP_UNSUPP = 10,
137 BFA_STATUS_UNKNOWN_VFID = 11,
138 BFA_STATUS_DATACORRUPTED = 12,
139 BFA_STATUS_DEVBUSY = 13,
140 BFA_STATUS_HDMA_FAILED = 16,
141 BFA_STATUS_FLASH_BAD_LEN = 17,
142 BFA_STATUS_UNKNOWN_LWWN = 18,
143 BFA_STATUS_UNKNOWN_RWWN = 19,
144 BFA_STATUS_VPORT_EXISTS = 21,
145 BFA_STATUS_VPORT_MAX = 22,
146 BFA_STATUS_UNSUPP_SPEED = 23,
147 BFA_STATUS_INVLD_DFSZ = 24,
148 BFA_STATUS_CMD_NOTSUPP = 26,
149 BFA_STATUS_FABRIC_RJT = 29,
150 BFA_STATUS_UNKNOWN_VWWN = 30,
151 BFA_STATUS_PORT_OFFLINE = 34,
152 BFA_STATUS_VPORT_WWN_BP = 46,
153 BFA_STATUS_PORT_NOT_DISABLED = 47,
154 BFA_STATUS_NO_FCPIM_NEXUS = 52,
155 BFA_STATUS_IOC_FAILURE = 56,
156
157 BFA_STATUS_INVALID_WWN = 57,
158 BFA_STATUS_ADAPTER_ENABLED = 60,
159 BFA_STATUS_IOC_NON_OP = 61,
160 BFA_STATUS_VERSION_FAIL = 70,
161 BFA_STATUS_DIAG_BUSY = 71,
162 BFA_STATUS_BEACON_ON = 72,
163 BFA_STATUS_ENOFSAVE = 78,
164 BFA_STATUS_IOC_DISABLED = 82,
165 BFA_STATUS_ERROR_TRL_ENABLED = 87,
166 BFA_STATUS_ERROR_QOS_ENABLED = 88,
167 BFA_STATUS_NO_SFP_DEV = 89,
168 BFA_STATUS_MEMTEST_FAILED = 90,
169 BFA_STATUS_LEDTEST_OP = 109,
170 BFA_STATUS_INVALID_MAC = 134,
171 BFA_STATUS_CMD_NOTSUPP_CNA = 146,
172 BFA_STATUS_PBC = 154,
173
174 BFA_STATUS_BAD_FWCFG = 156,
175 BFA_STATUS_INVALID_VENDOR = 158,
176 BFA_STATUS_SFP_NOT_READY = 159,
177 BFA_STATUS_TRUNK_ENABLED = 164,
178
179 BFA_STATUS_TRUNK_DISABLED = 165,
180
181 BFA_STATUS_IOPROFILE_OFF = 175,
182 BFA_STATUS_PHY_NOT_PRESENT = 183,
183 BFA_STATUS_FEATURE_NOT_SUPPORTED = 192,
184 BFA_STATUS_ENTRY_EXISTS = 193,
185 BFA_STATUS_ENTRY_NOT_EXISTS = 194,
186 BFA_STATUS_NO_CHANGE = 195,
187 BFA_STATUS_FAA_ENABLED = 197,
188 BFA_STATUS_FAA_DISABLED = 198,
189 BFA_STATUS_FAA_ACQUIRED = 199,
190 BFA_STATUS_FAA_ACQ_ADDR = 200,
191 BFA_STATUS_BBCR_FC_ONLY = 201,
192
193 BFA_STATUS_ERROR_TRUNK_ENABLED = 203,
194 BFA_STATUS_MAX_ENTRY_REACHED = 212,
195 BFA_STATUS_TOPOLOGY_LOOP = 230,
196 BFA_STATUS_LOOP_UNSUPP_MEZZ = 231,
197
198 BFA_STATUS_INVALID_BW = 233,
199 BFA_STATUS_QOS_BW_INVALID = 234,
200
201 BFA_STATUS_DPORT_ENABLED = 235,
202 BFA_STATUS_DPORT_DISABLED = 236,
203 BFA_STATUS_CMD_NOTSUPP_MEZZ = 239,
204 BFA_STATUS_FRU_NOT_PRESENT = 240,
205 BFA_STATUS_DPORT_NO_SFP = 243,
206
207
208 BFA_STATUS_DPORT_ERR = 245,
209 BFA_STATUS_DPORT_ENOSYS = 254,
210 BFA_STATUS_DPORT_CANT_PERF = 255,
211
212 BFA_STATUS_DPORT_LOGICALERR = 256,
213 BFA_STATUS_DPORT_SWBUSY = 257,
214 BFA_STATUS_ERR_BBCR_SPEED_UNSUPPORT = 258,
215
216 BFA_STATUS_ERROR_BBCR_ENABLED = 259,
217
218 BFA_STATUS_INVALID_BBSCN = 260,
219
220 BFA_STATUS_DDPORT_ERR = 261,
221
222
223 BFA_STATUS_DPORT_SFPWRAP_ERR = 262,
224
225 BFA_STATUS_BBCR_CFG_NO_CHANGE = 265,
226
227 BFA_STATUS_DPORT_SW_NOTREADY = 268,
228
229
230 BFA_STATUS_DPORT_INV_SFP = 271,
231 BFA_STATUS_DPORT_CMD_NOTSUPP = 273,
232
233 BFA_STATUS_MAX_VAL
234};
235#define bfa_status_t enum bfa_status
236
237enum bfa_eproto_status {
238 BFA_EPROTO_BAD_ACCEPT = 0,
239 BFA_EPROTO_UNKNOWN_RSP = 1
240};
241#define bfa_eproto_status_t enum bfa_eproto_status
242
243enum bfa_boolean {
244 BFA_FALSE = 0,
245 BFA_TRUE = 1
246};
247#define bfa_boolean_t enum bfa_boolean
248
249#define BFA_STRING_32 32
250#define BFA_VERSION_LEN 64
251
252
253
254
255
256
257
258
259enum {
260 BFA_ADAPTER_SERIAL_NUM_LEN = STRSZ(BFA_MFG_SERIALNUM_SIZE),
261
262
263
264 BFA_ADAPTER_MODEL_NAME_LEN = 16,
265 BFA_ADAPTER_MODEL_DESCR_LEN = 128,
266 BFA_ADAPTER_MFG_NAME_LEN = 8,
267 BFA_ADAPTER_SYM_NAME_LEN = 64,
268 BFA_ADAPTER_OS_TYPE_LEN = 64,
269 BFA_ADAPTER_UUID_LEN = 16,
270};
271
272struct bfa_adapter_attr_s {
273 char manufacturer[BFA_ADAPTER_MFG_NAME_LEN];
274 char serial_num[BFA_ADAPTER_SERIAL_NUM_LEN];
275 u32 card_type;
276 char model[BFA_ADAPTER_MODEL_NAME_LEN];
277 char model_descr[BFA_ADAPTER_MODEL_DESCR_LEN];
278 wwn_t pwwn;
279 char node_symname[FC_SYMNAME_MAX];
280 char hw_ver[BFA_VERSION_LEN];
281 char fw_ver[BFA_VERSION_LEN];
282 char optrom_ver[BFA_VERSION_LEN];
283 char os_type[BFA_ADAPTER_OS_TYPE_LEN];
284 struct bfa_mfg_vpd_s vpd;
285 struct mac_s mac;
286
287 u8 nports;
288 u8 max_speed;
289 u8 prototype;
290 char asic_rev;
291
292 u8 pcie_gen;
293 u8 pcie_lanes_orig;
294 u8 pcie_lanes;
295 u8 cna_capable;
296
297 u8 is_mezz;
298 u8 trunk_capable;
299 u8 mfg_day;
300 u8 mfg_month;
301 u16 mfg_year;
302 u16 rsvd;
303 u8 uuid[BFA_ADAPTER_UUID_LEN];
304};
305
306
307
308
309
310enum {
311 BFA_IOC_DRIVER_LEN = 16,
312 BFA_IOC_CHIP_REV_LEN = 8,
313};
314
315
316
317
318struct bfa_ioc_driver_attr_s {
319 char driver[BFA_IOC_DRIVER_LEN];
320 char driver_ver[BFA_VERSION_LEN];
321 char fw_ver[BFA_VERSION_LEN];
322 char bios_ver[BFA_VERSION_LEN];
323 char efi_ver[BFA_VERSION_LEN];
324 char ob_ver[BFA_VERSION_LEN];
325};
326
327
328
329
330struct bfa_ioc_pci_attr_s {
331 u16 vendor_id;
332 u16 device_id;
333 u16 ssid;
334 u16 ssvid;
335 u32 pcifn;
336 u32 rsvd;
337 char chip_rev[BFA_IOC_CHIP_REV_LEN];
338};
339
340
341
342
343enum bfa_ioc_state {
344 BFA_IOC_UNINIT = 1,
345 BFA_IOC_RESET = 2,
346 BFA_IOC_SEMWAIT = 3,
347 BFA_IOC_HWINIT = 4,
348 BFA_IOC_GETATTR = 5,
349 BFA_IOC_OPERATIONAL = 6,
350 BFA_IOC_INITFAIL = 7,
351 BFA_IOC_FAIL = 8,
352 BFA_IOC_DISABLING = 9,
353 BFA_IOC_DISABLED = 10,
354 BFA_IOC_FWMISMATCH = 11,
355 BFA_IOC_ENABLING = 12,
356 BFA_IOC_HWFAIL = 13,
357 BFA_IOC_ACQ_ADDR = 14,
358};
359
360
361
362
363struct bfa_fw_ioc_stats_s {
364 u32 enable_reqs;
365 u32 disable_reqs;
366 u32 get_attr_reqs;
367 u32 dbg_sync;
368 u32 dbg_dump;
369 u32 unknown_reqs;
370};
371
372
373
374
375struct bfa_ioc_drv_stats_s {
376 u32 ioc_isrs;
377 u32 ioc_enables;
378 u32 ioc_disables;
379 u32 ioc_hbfails;
380 u32 ioc_boots;
381 u32 stats_tmos;
382 u32 hb_count;
383 u32 disable_reqs;
384 u32 enable_reqs;
385 u32 disable_replies;
386 u32 enable_replies;
387 u32 rsvd;
388};
389
390
391
392
393struct bfa_ioc_stats_s {
394 struct bfa_ioc_drv_stats_s drv_stats;
395 struct bfa_fw_ioc_stats_s fw_stats;
396};
397
398enum bfa_ioc_type_e {
399 BFA_IOC_TYPE_FC = 1,
400 BFA_IOC_TYPE_FCoE = 2,
401 BFA_IOC_TYPE_LL = 3,
402};
403
404
405
406
407struct bfa_ioc_attr_s {
408 enum bfa_ioc_type_e ioc_type;
409 enum bfa_ioc_state state;
410 struct bfa_adapter_attr_s adapter_attr;
411 struct bfa_ioc_driver_attr_s driver_attr;
412 struct bfa_ioc_pci_attr_s pci_attr;
413 u8 port_id;
414 u8 port_mode;
415 u8 cap_bm;
416 u8 port_mode_cfg;
417 u8 def_fn;
418 u8 rsvd[3];
419};
420
421
422
423
424enum bfa_aen_category {
425 BFA_AEN_CAT_ADAPTER = 1,
426 BFA_AEN_CAT_PORT = 2,
427 BFA_AEN_CAT_LPORT = 3,
428 BFA_AEN_CAT_RPORT = 4,
429 BFA_AEN_CAT_ITNIM = 5,
430 BFA_AEN_CAT_AUDIT = 8,
431 BFA_AEN_CAT_IOC = 9,
432};
433
434
435enum bfa_adapter_aen_event {
436 BFA_ADAPTER_AEN_ADD = 1,
437 BFA_ADAPTER_AEN_REMOVE = 2,
438};
439
440struct bfa_adapter_aen_data_s {
441 char serial_num[BFA_ADAPTER_SERIAL_NUM_LEN];
442 u32 nports;
443 wwn_t pwwn;
444};
445
446
447enum bfa_port_aen_event {
448 BFA_PORT_AEN_ONLINE = 1,
449 BFA_PORT_AEN_OFFLINE = 2,
450 BFA_PORT_AEN_RLIR = 3,
451 BFA_PORT_AEN_SFP_INSERT = 4,
452 BFA_PORT_AEN_SFP_REMOVE = 5,
453 BFA_PORT_AEN_SFP_POM = 6,
454 BFA_PORT_AEN_ENABLE = 7,
455 BFA_PORT_AEN_DISABLE = 8,
456 BFA_PORT_AEN_AUTH_ON = 9,
457 BFA_PORT_AEN_AUTH_OFF = 10,
458 BFA_PORT_AEN_DISCONNECT = 11,
459 BFA_PORT_AEN_QOS_NEG = 12,
460 BFA_PORT_AEN_FABRIC_NAME_CHANGE = 13,
461 BFA_PORT_AEN_SFP_ACCESS_ERROR = 14,
462 BFA_PORT_AEN_SFP_UNSUPPORT = 15,
463};
464
465enum bfa_port_aen_sfp_pom {
466 BFA_PORT_AEN_SFP_POM_GREEN = 1,
467 BFA_PORT_AEN_SFP_POM_AMBER = 2,
468 BFA_PORT_AEN_SFP_POM_RED = 3,
469 BFA_PORT_AEN_SFP_POM_MAX = BFA_PORT_AEN_SFP_POM_RED
470};
471
472struct bfa_port_aen_data_s {
473 wwn_t pwwn;
474 wwn_t fwwn;
475 u32 phy_port_num;
476 u16 ioc_type;
477 u16 level;
478 mac_t mac;
479 u16 rsvd;
480};
481
482
483enum bfa_lport_aen_event {
484 BFA_LPORT_AEN_NEW = 1,
485 BFA_LPORT_AEN_DELETE = 2,
486 BFA_LPORT_AEN_ONLINE = 3,
487 BFA_LPORT_AEN_OFFLINE = 4,
488 BFA_LPORT_AEN_DISCONNECT = 5,
489 BFA_LPORT_AEN_NEW_PROP = 6,
490 BFA_LPORT_AEN_DELETE_PROP = 7,
491 BFA_LPORT_AEN_NEW_STANDARD = 8,
492 BFA_LPORT_AEN_DELETE_STANDARD = 9,
493 BFA_LPORT_AEN_NPIV_DUP_WWN = 10,
494 BFA_LPORT_AEN_NPIV_FABRIC_MAX = 11,
495 BFA_LPORT_AEN_NPIV_UNKNOWN = 12,
496};
497
498struct bfa_lport_aen_data_s {
499 u16 vf_id;
500 u16 roles;
501 u32 rsvd;
502 wwn_t ppwwn;
503 wwn_t lpwwn;
504};
505
506
507enum bfa_itnim_aen_event {
508 BFA_ITNIM_AEN_ONLINE = 1,
509 BFA_ITNIM_AEN_OFFLINE = 2,
510 BFA_ITNIM_AEN_DISCONNECT = 3,
511};
512
513struct bfa_itnim_aen_data_s {
514 u16 vf_id;
515 u16 rsvd[3];
516 wwn_t ppwwn;
517 wwn_t lpwwn;
518 wwn_t rpwwn;
519};
520
521
522enum bfa_audit_aen_event {
523 BFA_AUDIT_AEN_AUTH_ENABLE = 1,
524 BFA_AUDIT_AEN_AUTH_DISABLE = 2,
525 BFA_AUDIT_AEN_FLASH_ERASE = 3,
526 BFA_AUDIT_AEN_FLASH_UPDATE = 4,
527};
528
529struct bfa_audit_aen_data_s {
530 wwn_t pwwn;
531 int partition_inst;
532 int partition_type;
533};
534
535
536enum bfa_ioc_aen_event {
537 BFA_IOC_AEN_HBGOOD = 1,
538 BFA_IOC_AEN_HBFAIL = 2,
539 BFA_IOC_AEN_ENABLE = 3,
540 BFA_IOC_AEN_DISABLE = 4,
541 BFA_IOC_AEN_FWMISMATCH = 5,
542 BFA_IOC_AEN_FWCFG_ERROR = 6,
543 BFA_IOC_AEN_INVALID_VENDOR = 7,
544 BFA_IOC_AEN_INVALID_NWWN = 8,
545 BFA_IOC_AEN_INVALID_PWWN = 9
546};
547
548struct bfa_ioc_aen_data_s {
549 wwn_t pwwn;
550 u16 ioc_type;
551 mac_t mac;
552};
553
554
555
556
557
558
559
560
561#define BFA_MFG_CHKSUM_SIZE 16
562
563#define BFA_MFG_PARTNUM_SIZE 14
564#define BFA_MFG_SUPPLIER_ID_SIZE 10
565#define BFA_MFG_SUPPLIER_PARTNUM_SIZE 20
566#define BFA_MFG_SUPPLIER_SERIALNUM_SIZE 20
567#define BFA_MFG_SUPPLIER_REVISION_SIZE 4
568
569
570
571#define BFA_MFG_IC_FC 0x01
572#define BFA_MFG_IC_ETH 0x02
573
574
575
576
577#define BFA_CM_HBA 0x01
578#define BFA_CM_CNA 0x02
579#define BFA_CM_NIC 0x04
580#define BFA_CM_FC16G 0x08
581#define BFA_CM_SRIOV 0x10
582#define BFA_CM_MEZZ 0x20
583
584#pragma pack(1)
585
586
587
588
589struct bfa_mfg_block_s {
590 u8 version;
591 u8 mfg_sig[3];
592 u16 mfgsize;
593 u16 u16_chksum;
594 char brcd_serialnum[STRSZ(BFA_MFG_SERIALNUM_SIZE)];
595 char brcd_partnum[STRSZ(BFA_MFG_PARTNUM_SIZE)];
596 u8 mfg_day;
597 u8 mfg_month;
598 u16 mfg_year;
599 wwn_t mfg_wwn;
600 u8 num_wwn;
601 u8 mfg_speeds;
602 u8 rsv[2];
603 char supplier_id[STRSZ(BFA_MFG_SUPPLIER_ID_SIZE)];
604 char supplier_partnum[STRSZ(BFA_MFG_SUPPLIER_PARTNUM_SIZE)];
605 char supplier_serialnum[STRSZ(BFA_MFG_SUPPLIER_SERIALNUM_SIZE)];
606 char supplier_revision[STRSZ(BFA_MFG_SUPPLIER_REVISION_SIZE)];
607 mac_t mfg_mac;
608 u8 num_mac;
609 u8 rsv2;
610 u32 card_type;
611 char cap_nic;
612 char cap_cna;
613 char cap_hba;
614 char cap_fc16g;
615 char cap_sriov;
616 char cap_mezz;
617 u8 rsv3;
618 u8 mfg_nports;
619 char media[8];
620 char initial_mode[8];
621 u8 rsv4[84];
622 u8 md5_chksum[BFA_MFG_CHKSUM_SIZE];
623};
624
625#pragma pack()
626
627
628
629
630
631
632
633
634enum {
635 BFA_PCI_VENDOR_ID_BROCADE = 0x1657,
636 BFA_PCI_DEVICE_ID_FC_8G2P = 0x13,
637 BFA_PCI_DEVICE_ID_FC_8G1P = 0x17,
638 BFA_PCI_DEVICE_ID_CT = 0x14,
639 BFA_PCI_DEVICE_ID_CT_FC = 0x21,
640 BFA_PCI_DEVICE_ID_CT2 = 0x22,
641 BFA_PCI_DEVICE_ID_CT2_QUAD = 0x23,
642};
643
644#define bfa_asic_id_cb(__d) \
645 ((__d) == BFA_PCI_DEVICE_ID_FC_8G2P || \
646 (__d) == BFA_PCI_DEVICE_ID_FC_8G1P)
647#define bfa_asic_id_ct(__d) \
648 ((__d) == BFA_PCI_DEVICE_ID_CT || \
649 (__d) == BFA_PCI_DEVICE_ID_CT_FC)
650#define bfa_asic_id_ct2(__d) \
651 ((__d) == BFA_PCI_DEVICE_ID_CT2 || \
652 (__d) == BFA_PCI_DEVICE_ID_CT2_QUAD)
653#define bfa_asic_id_ctc(__d) \
654 (bfa_asic_id_ct(__d) || bfa_asic_id_ct2(__d))
655
656
657
658
659enum {
660 BFA_PCI_FCOE_SSDEVICE_ID = 0x14,
661 BFA_PCI_CT2_SSID_FCoE = 0x22,
662 BFA_PCI_CT2_SSID_ETH = 0x23,
663 BFA_PCI_CT2_SSID_FC = 0x24,
664};
665
666
667
668
669#define BFA_PCI_ACCESS_RANGES 1
670
671
672
673
674
675enum bfa_port_speed {
676 BFA_PORT_SPEED_UNKNOWN = 0,
677 BFA_PORT_SPEED_1GBPS = 1,
678 BFA_PORT_SPEED_2GBPS = 2,
679 BFA_PORT_SPEED_4GBPS = 4,
680 BFA_PORT_SPEED_8GBPS = 8,
681 BFA_PORT_SPEED_10GBPS = 10,
682 BFA_PORT_SPEED_16GBPS = 16,
683 BFA_PORT_SPEED_AUTO = 0xf,
684};
685#define bfa_port_speed_t enum bfa_port_speed
686
687enum {
688 BFA_BOOT_BOOTLUN_MAX = 4,
689 BFA_PREBOOT_BOOTLUN_MAX = 8,
690};
691
692#define BOOT_CFG_REV1 1
693#define BOOT_CFG_VLAN 1
694
695
696
697
698
699enum bfa_boot_bootopt {
700 BFA_BOOT_AUTO_DISCOVER = 0,
701 BFA_BOOT_STORED_BLUN = 1,
702 BFA_BOOT_FIRST_LUN = 2,
703 BFA_BOOT_PBC = 3,
704};
705
706#pragma pack(1)
707
708
709
710struct bfa_boot_bootlun_s {
711 wwn_t pwwn;
712 struct scsi_lun lun;
713};
714#pragma pack()
715
716
717
718
719struct bfa_boot_cfg_s {
720 u8 version;
721 u8 rsvd1;
722 u16 chksum;
723 u8 enable;
724 u8 speed;
725 u8 topology;
726 u8 bootopt;
727 u32 nbluns;
728 u32 rsvd2;
729 struct bfa_boot_bootlun_s blun[BFA_BOOT_BOOTLUN_MAX];
730 struct bfa_boot_bootlun_s blun_disc[BFA_BOOT_BOOTLUN_MAX];
731};
732
733struct bfa_boot_pbc_s {
734 u8 enable;
735 u8 speed;
736 u8 topology;
737 u8 rsvd1;
738 u32 nbluns;
739 struct bfa_boot_bootlun_s pblun[BFA_PREBOOT_BOOTLUN_MAX];
740};
741
742struct bfa_ethboot_cfg_s {
743 u8 version;
744 u8 rsvd1;
745 u16 chksum;
746 u8 enable;
747 u8 rsvd2;
748 u16 vlan;
749};
750
751
752
753
754#define BFA_ABLK_MAX_PORTS 2
755#define BFA_ABLK_MAX_PFS 16
756#define BFA_ABLK_MAX 2
757
758#pragma pack(1)
759enum bfa_mode_s {
760 BFA_MODE_HBA = 1,
761 BFA_MODE_CNA = 2,
762 BFA_MODE_NIC = 3
763};
764
765struct bfa_adapter_cfg_mode_s {
766 u16 max_pf;
767 u16 max_vf;
768 enum bfa_mode_s mode;
769};
770
771struct bfa_ablk_cfg_pf_s {
772 u16 pers;
773 u8 port_id;
774 u8 optrom;
775 u8 valid;
776 u8 sriov;
777 u8 max_vfs;
778 u8 rsvd[1];
779 u16 num_qpairs;
780 u16 num_vectors;
781 u16 bw_min;
782 u16 bw_max;
783};
784
785struct bfa_ablk_cfg_port_s {
786 u8 mode;
787 u8 type;
788 u8 max_pfs;
789 u8 rsvd[5];
790};
791
792struct bfa_ablk_cfg_inst_s {
793 u8 nports;
794 u8 max_pfs;
795 u8 rsvd[6];
796 struct bfa_ablk_cfg_pf_s pf_cfg[BFA_ABLK_MAX_PFS];
797 struct bfa_ablk_cfg_port_s port_cfg[BFA_ABLK_MAX_PORTS];
798};
799
800struct bfa_ablk_cfg_s {
801 struct bfa_ablk_cfg_inst_s inst[BFA_ABLK_MAX];
802};
803
804
805
806
807
808#define SFP_DIAGMON_SIZE 10
809
810
811#define BFA_SFP_SCN_REMOVED 0
812#define BFA_SFP_SCN_INSERTED 1
813#define BFA_SFP_SCN_POM 2
814#define BFA_SFP_SCN_FAILED 3
815#define BFA_SFP_SCN_UNSUPPORT 4
816#define BFA_SFP_SCN_VALID 5
817
818enum bfa_defs_sfp_media_e {
819 BFA_SFP_MEDIA_UNKNOWN = 0x00,
820 BFA_SFP_MEDIA_CU = 0x01,
821 BFA_SFP_MEDIA_LW = 0x02,
822 BFA_SFP_MEDIA_SW = 0x03,
823 BFA_SFP_MEDIA_EL = 0x04,
824 BFA_SFP_MEDIA_UNSUPPORT = 0x05,
825};
826
827
828
829
830enum {
831 SFP_XMTR_TECH_CU = (1 << 0),
832 SFP_XMTR_TECH_CP = (1 << 1),
833 SFP_XMTR_TECH_CA = (1 << 2),
834 SFP_XMTR_TECH_LL = (1 << 3),
835 SFP_XMTR_TECH_SL = (1 << 4),
836 SFP_XMTR_TECH_SN = (1 << 5),
837 SFP_XMTR_TECH_EL_INTRA = (1 << 6),
838 SFP_XMTR_TECH_EL_INTER = (1 << 7),
839 SFP_XMTR_TECH_LC = (1 << 8),
840 SFP_XMTR_TECH_SA = (1 << 9)
841};
842
843
844
845
846
847struct sfp_srlid_base_s {
848 u8 id;
849 u8 extid;
850 u8 connector;
851 u8 xcvr[8];
852 u8 encoding;
853 u8 br_norm;
854 u8 rate_id;
855 u8 len_km;
856 u8 len_100m;
857 u8 len_om2;
858 u8 len_om1;
859 u8 len_cu;
860 u8 len_om3;
861 u8 vendor_name[16];
862 u8 unalloc1;
863 u8 vendor_oui[3];
864 u8 vendor_pn[16];
865 u8 vendor_rev[4];
866 u8 wavelen[2];
867 u8 unalloc2;
868 u8 cc_base;
869};
870
871
872
873
874
875struct sfp_srlid_ext_s {
876 u8 options[2];
877 u8 br_max;
878 u8 br_min;
879 u8 vendor_sn[16];
880 u8 date_code[8];
881 u8 diag_mon_type;
882 u8 en_options;
883 u8 sff_8472;
884 u8 cc_ext;
885};
886
887
888
889
890
891struct sfp_diag_base_s {
892
893
894
895 u8 temp_high_alarm[2];
896 u8 temp_low_alarm[2];
897 u8 temp_high_warning[2];
898 u8 temp_low_warning[2];
899
900 u8 volt_high_alarm[2];
901 u8 volt_low_alarm[2];
902 u8 volt_high_warning[2];
903 u8 volt_low_warning[2];
904
905 u8 bias_high_alarm[2];
906 u8 bias_low_alarm[2];
907 u8 bias_high_warning[2];
908 u8 bias_low_warning[2];
909
910 u8 tx_pwr_high_alarm[2];
911 u8 tx_pwr_low_alarm[2];
912 u8 tx_pwr_high_warning[2];
913 u8 tx_pwr_low_warning[2];
914
915 u8 rx_pwr_high_alarm[2];
916 u8 rx_pwr_low_alarm[2];
917 u8 rx_pwr_high_warning[2];
918 u8 rx_pwr_low_warning[2];
919
920 u8 unallocate_1[16];
921
922
923
924
925 u8 rx_pwr[20];
926 u8 tx_i[4];
927 u8 tx_pwr[4];
928 u8 temp[4];
929 u8 volt[4];
930 u8 unallocate_2[3];
931 u8 cc_dmi;
932};
933
934
935
936
937
938struct sfp_diag_ext_s {
939 u8 diag[SFP_DIAGMON_SIZE];
940 u8 unalloc1[4];
941 u8 status_ctl;
942 u8 rsvd;
943 u8 alarm_flags[2];
944 u8 unalloc2[2];
945 u8 warning_flags[2];
946 u8 ext_status_ctl[2];
947};
948
949
950
951
952
953
954struct sfp_usr_eeprom_s {
955 u8 rsvd1[2];
956 u8 ewrap;
957 u8 rsvd2[2];
958 u8 owrap;
959 u8 rsvd3[2];
960 u8 prbs;
961 u8 rsvd4[2];
962 u8 tx_eqz_16;
963 u8 tx_eqz_8;
964 u8 rsvd5[2];
965 u8 rx_emp_16;
966 u8 rx_emp_8;
967 u8 rsvd6[2];
968 u8 tx_eye_adj;
969 u8 rsvd7[3];
970 u8 tx_eye_qctl;
971 u8 tx_eye_qres;
972 u8 rsvd8[2];
973 u8 poh[3];
974 u8 rsvd9[2];
975};
976
977struct sfp_mem_s {
978 struct sfp_srlid_base_s srlid_base;
979 struct sfp_srlid_ext_s srlid_ext;
980 struct sfp_diag_base_s diag_base;
981 struct sfp_diag_ext_s diag_ext;
982 struct sfp_usr_eeprom_s usr_eeprom;
983};
984
985
986
987
988union sfp_xcvr_e10g_code_u {
989 u8 b;
990 struct {
991#ifdef __BIG_ENDIAN
992 u8 e10g_unall:1;
993 u8 e10g_lrm:1;
994 u8 e10g_lr:1;
995 u8 e10g_sr:1;
996 u8 ib_sx:1;
997 u8 ib_lx:1;
998 u8 ib_cu_a:1;
999 u8 ib_cu_p:1;
1000#else
1001 u8 ib_cu_p:1;
1002 u8 ib_cu_a:1;
1003 u8 ib_lx:1;
1004 u8 ib_sx:1;
1005 u8 e10g_sr:1;
1006 u8 e10g_lr:1;
1007 u8 e10g_lrm:1;
1008 u8 e10g_unall:1;
1009#endif
1010 } r;
1011};
1012
1013union sfp_xcvr_so1_code_u {
1014 u8 b;
1015 struct {
1016 u8 escon:2;
1017 u8 oc192_reach:1;
1018 u8 so_reach:2;
1019 u8 oc48_reach:3;
1020 } r;
1021};
1022
1023union sfp_xcvr_so2_code_u {
1024 u8 b;
1025 struct {
1026 u8 reserved:1;
1027 u8 oc12_reach:3;
1028 u8 reserved1:1;
1029 u8 oc3_reach:3;
1030 } r;
1031};
1032
1033union sfp_xcvr_eth_code_u {
1034 u8 b;
1035 struct {
1036 u8 base_px:1;
1037 u8 base_bx10:1;
1038 u8 e100base_fx:1;
1039 u8 e100base_lx:1;
1040 u8 e1000base_t:1;
1041 u8 e1000base_cx:1;
1042 u8 e1000base_lx:1;
1043 u8 e1000base_sx:1;
1044 } r;
1045};
1046
1047struct sfp_xcvr_fc1_code_s {
1048 u8 link_len:5;
1049 u8 xmtr_tech2:3;
1050 u8 xmtr_tech1:7;
1051 u8 reserved1:1;
1052};
1053
1054union sfp_xcvr_fc2_code_u {
1055 u8 b;
1056 struct {
1057 u8 tw_media:1;
1058 u8 tp_media:1;
1059 u8 mi_media:1;
1060 u8 tv_media:1;
1061 u8 m6_media:1;
1062 u8 m5_media:1;
1063 u8 reserved:1;
1064 u8 sm_media:1;
1065 } r;
1066};
1067
1068union sfp_xcvr_fc3_code_u {
1069 u8 b;
1070 struct {
1071#ifdef __BIG_ENDIAN
1072 u8 rsv4:1;
1073 u8 mb800:1;
1074 u8 mb1600:1;
1075 u8 mb400:1;
1076 u8 rsv2:1;
1077 u8 mb200:1;
1078 u8 rsv1:1;
1079 u8 mb100:1;
1080#else
1081 u8 mb100:1;
1082 u8 rsv1:1;
1083 u8 mb200:1;
1084 u8 rsv2:1;
1085 u8 mb400:1;
1086 u8 mb1600:1;
1087 u8 mb800:1;
1088 u8 rsv4:1;
1089#endif
1090 } r;
1091};
1092
1093struct sfp_xcvr_s {
1094 union sfp_xcvr_e10g_code_u e10g;
1095 union sfp_xcvr_so1_code_u so1;
1096 union sfp_xcvr_so2_code_u so2;
1097 union sfp_xcvr_eth_code_u eth;
1098 struct sfp_xcvr_fc1_code_s fc1;
1099 union sfp_xcvr_fc2_code_u fc2;
1100 union sfp_xcvr_fc3_code_u fc3;
1101};
1102
1103
1104
1105
1106#define BFA_FLASH_PART_ENTRY_SIZE 32
1107#define BFA_FLASH_PART_MAX 32
1108
1109enum bfa_flash_part_type {
1110 BFA_FLASH_PART_OPTROM = 1,
1111 BFA_FLASH_PART_FWIMG = 2,
1112 BFA_FLASH_PART_FWCFG = 3,
1113 BFA_FLASH_PART_DRV = 4,
1114 BFA_FLASH_PART_BOOT = 5,
1115 BFA_FLASH_PART_ASIC = 6,
1116 BFA_FLASH_PART_MFG = 7,
1117 BFA_FLASH_PART_OPTROM2 = 8,
1118 BFA_FLASH_PART_VPD = 9,
1119 BFA_FLASH_PART_PBC = 10,
1120 BFA_FLASH_PART_BOOTOVL = 11,
1121 BFA_FLASH_PART_LOG = 12,
1122 BFA_FLASH_PART_PXECFG = 13,
1123 BFA_FLASH_PART_PXEOVL = 14,
1124 BFA_FLASH_PART_PORTCFG = 15,
1125 BFA_FLASH_PART_ASICBK = 16,
1126};
1127
1128
1129
1130
1131struct bfa_flash_part_attr_s {
1132 u32 part_type;
1133 u32 part_instance;
1134 u32 part_off;
1135 u32 part_size;
1136 u32 part_len;
1137 u32 part_status;
1138 char rsv[BFA_FLASH_PART_ENTRY_SIZE - 24];
1139};
1140
1141
1142
1143
1144struct bfa_flash_attr_s {
1145 u32 status;
1146 u32 npart;
1147 struct bfa_flash_part_attr_s part[BFA_FLASH_PART_MAX];
1148};
1149
1150
1151
1152
1153#define LB_PATTERN_DEFAULT 0xB5B5B5B5
1154#define QTEST_CNT_DEFAULT 10
1155#define QTEST_PAT_DEFAULT LB_PATTERN_DEFAULT
1156#define DPORT_ENABLE_LOOPCNT_DEFAULT (1024 * 1024)
1157
1158struct bfa_diag_memtest_s {
1159 u8 algo;
1160 u8 rsvd[7];
1161};
1162
1163struct bfa_diag_memtest_result {
1164 u32 status;
1165 u32 addr;
1166 u32 exp;
1167 u32 act;
1168 u32 err_status;
1169 u32 err_status1;
1170 u32 err_addr;
1171 u8 algo;
1172 u8 rsv[3];
1173};
1174
1175struct bfa_diag_loopback_result_s {
1176 u32 numtxmfrm;
1177 u32 numosffrm;
1178 u32 numrcvfrm;
1179 u32 badfrminf;
1180 u32 badfrmnum;
1181 u8 status;
1182 u8 rsvd[3];
1183};
1184
1185enum bfa_diag_dport_test_status {
1186 DPORT_TEST_ST_IDLE = 0,
1187 DPORT_TEST_ST_FINAL = 1,
1188 DPORT_TEST_ST_SKIP = 2,
1189 DPORT_TEST_ST_FAIL = 3,
1190 DPORT_TEST_ST_INPRG = 4,
1191 DPORT_TEST_ST_RESPONDER = 5,
1192 DPORT_TEST_ST_STOPPED = 6,
1193 DPORT_TEST_ST_MAX
1194};
1195
1196enum bfa_diag_dport_test_type {
1197 DPORT_TEST_ELOOP = 0,
1198 DPORT_TEST_OLOOP = 1,
1199 DPORT_TEST_ROLOOP = 2,
1200 DPORT_TEST_LINK = 3,
1201 DPORT_TEST_MAX
1202};
1203
1204enum bfa_diag_dport_test_opmode {
1205 BFA_DPORT_OPMODE_AUTO = 0,
1206 BFA_DPORT_OPMODE_MANU = 1,
1207};
1208
1209struct bfa_diag_dport_subtest_result_s {
1210 u8 status;
1211 u8 rsvd[7];
1212 u64 start_time;
1213};
1214
1215struct bfa_diag_dport_result_s {
1216 wwn_t rp_pwwn;
1217 wwn_t rp_nwwn;
1218 u64 start_time;
1219 u64 end_time;
1220 u8 status;
1221 u8 mode;
1222 u8 rsvd;
1223 u8 speed;
1224 u16 buffer_required;
1225 u16 frmsz;
1226 u32 lpcnt;
1227 u32 pat;
1228 u32 roundtrip_latency;
1229 u32 est_cable_distance;
1230 struct bfa_diag_dport_subtest_result_s subtest[DPORT_TEST_MAX];
1231};
1232
1233struct bfa_diag_ledtest_s {
1234 u32 cmd;
1235 u32 color;
1236 u16 freq;
1237 u8 led;
1238 u8 rsvd[5];
1239};
1240
1241struct bfa_diag_loopback_s {
1242 u32 loopcnt;
1243 u32 pattern;
1244 u8 lb_mode;
1245 u8 speed;
1246 u8 rsvd[2];
1247};
1248
1249
1250
1251
1252enum bfa_phy_status_e {
1253 BFA_PHY_STATUS_GOOD = 0,
1254 BFA_PHY_STATUS_NOT_PRESENT = 1,
1255 BFA_PHY_STATUS_BAD = 2,
1256};
1257
1258
1259
1260
1261struct bfa_phy_attr_s {
1262 u32 status;
1263 u32 length;
1264 u32 fw_ver;
1265 u32 an_status;
1266 u32 pma_pmd_status;
1267 u32 pma_pmd_signal;
1268 u32 pcs_status;
1269};
1270
1271
1272
1273
1274struct bfa_phy_stats_s {
1275 u32 status;
1276 u32 link_breaks;
1277 u32 pma_pmd_fault;
1278 u32 pcs_fault;
1279 u32 speed_neg;
1280 u32 tx_eq_training;
1281 u32 tx_eq_timeout;
1282 u32 crc_error;
1283};
1284
1285#pragma pack()
1286
1287#endif
1288