1
2
3
4
5
6
7#include "qla_def.h"
8#include "qla_gbl.h"
9
10#include <linux/delay.h>
11#include <linux/slab.h>
12#include <linux/vmalloc.h>
13
14#include "qla_devtbl.h"
15
16#ifdef CONFIG_SPARC
17#include <asm/prom.h>
18#endif
19
20#include <target/target_core_base.h>
21#include "qla_target.h"
22
23
24
25
26static int qla2x00_isp_firmware(scsi_qla_host_t *);
27static int qla2x00_setup_chip(scsi_qla_host_t *);
28static int qla2x00_fw_ready(scsi_qla_host_t *);
29static int qla2x00_configure_hba(scsi_qla_host_t *);
30static int qla2x00_configure_loop(scsi_qla_host_t *);
31static int qla2x00_configure_local_loop(scsi_qla_host_t *);
32static int qla2x00_configure_fabric(scsi_qla_host_t *);
33static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *, struct list_head *);
34static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *,
35 uint16_t *);
36
37static int qla2x00_restart_isp(scsi_qla_host_t *);
38
39static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
40static int qla84xx_init_chip(scsi_qla_host_t *);
41static int qla25xx_init_queues(struct qla_hw_data *);
42
43
44
45void
46qla2x00_sp_timeout(unsigned long __data)
47{
48 srb_t *sp = (srb_t *)__data;
49 struct srb_iocb *iocb;
50 fc_port_t *fcport = sp->fcport;
51 struct qla_hw_data *ha = fcport->vha->hw;
52 struct req_que *req;
53 unsigned long flags;
54
55 spin_lock_irqsave(&ha->hardware_lock, flags);
56 req = ha->req_q_map[0];
57 req->outstanding_cmds[sp->handle] = NULL;
58 iocb = &sp->u.iocb_cmd;
59 iocb->timeout(sp);
60 sp->free(fcport->vha, sp);
61 spin_unlock_irqrestore(&ha->hardware_lock, flags);
62}
63
64void
65qla2x00_sp_free(void *data, void *ptr)
66{
67 srb_t *sp = (srb_t *)ptr;
68 struct srb_iocb *iocb = &sp->u.iocb_cmd;
69 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
70
71 del_timer(&iocb->timer);
72 qla2x00_rel_sp(vha, sp);
73}
74
75
76
77unsigned long
78qla2x00_get_async_timeout(struct scsi_qla_host *vha)
79{
80 unsigned long tmo;
81 struct qla_hw_data *ha = vha->hw;
82
83
84 tmo = ha->r_a_tov / 10 * 2;
85 if (IS_QLAFX00(ha)) {
86 tmo = FX00_DEF_RATOV * 2;
87 } else if (!IS_FWI2_CAPABLE(ha)) {
88
89
90
91
92 tmo = ha->login_timeout;
93 }
94 return tmo;
95}
96
97static void
98qla2x00_async_iocb_timeout(void *data)
99{
100 srb_t *sp = (srb_t *)data;
101 fc_port_t *fcport = sp->fcport;
102
103 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
104 "Async-%s timeout - hdl=%x portid=%02x%02x%02x.\n",
105 sp->name, sp->handle, fcport->d_id.b.domain, fcport->d_id.b.area,
106 fcport->d_id.b.al_pa);
107
108 fcport->flags &= ~FCF_ASYNC_SENT;
109 if (sp->type == SRB_LOGIN_CMD) {
110 struct srb_iocb *lio = &sp->u.iocb_cmd;
111 qla2x00_post_async_logout_work(fcport->vha, fcport, NULL);
112
113 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
114 lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
115 QLA_LOGIO_LOGIN_RETRIED : 0;
116 qla2x00_post_async_login_done_work(fcport->vha, fcport,
117 lio->u.logio.data);
118 }
119}
120
121static void
122qla2x00_async_login_sp_done(void *data, void *ptr, int res)
123{
124 srb_t *sp = (srb_t *)ptr;
125 struct srb_iocb *lio = &sp->u.iocb_cmd;
126 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
127
128 if (!test_bit(UNLOADING, &vha->dpc_flags))
129 qla2x00_post_async_login_done_work(sp->fcport->vha, sp->fcport,
130 lio->u.logio.data);
131 sp->free(sp->fcport->vha, sp);
132}
133
134int
135qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
136 uint16_t *data)
137{
138 srb_t *sp;
139 struct srb_iocb *lio;
140 int rval;
141
142 rval = QLA_FUNCTION_FAILED;
143 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
144 if (!sp)
145 goto done;
146
147 sp->type = SRB_LOGIN_CMD;
148 sp->name = "login";
149 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
150
151 lio = &sp->u.iocb_cmd;
152 lio->timeout = qla2x00_async_iocb_timeout;
153 sp->done = qla2x00_async_login_sp_done;
154 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
155 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
156 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
157 rval = qla2x00_start_sp(sp);
158 if (rval != QLA_SUCCESS)
159 goto done_free_sp;
160
161 ql_dbg(ql_dbg_disc, vha, 0x2072,
162 "Async-login - hdl=%x, loopid=%x portid=%02x%02x%02x "
163 "retries=%d.\n", sp->handle, fcport->loop_id,
164 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
165 fcport->login_retry);
166 return rval;
167
168done_free_sp:
169 sp->free(fcport->vha, sp);
170done:
171 return rval;
172}
173
174static void
175qla2x00_async_logout_sp_done(void *data, void *ptr, int res)
176{
177 srb_t *sp = (srb_t *)ptr;
178 struct srb_iocb *lio = &sp->u.iocb_cmd;
179 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
180
181 if (!test_bit(UNLOADING, &vha->dpc_flags))
182 qla2x00_post_async_logout_done_work(sp->fcport->vha, sp->fcport,
183 lio->u.logio.data);
184 sp->free(sp->fcport->vha, sp);
185}
186
187int
188qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
189{
190 srb_t *sp;
191 struct srb_iocb *lio;
192 int rval;
193
194 rval = QLA_FUNCTION_FAILED;
195 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
196 if (!sp)
197 goto done;
198
199 sp->type = SRB_LOGOUT_CMD;
200 sp->name = "logout";
201 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
202
203 lio = &sp->u.iocb_cmd;
204 lio->timeout = qla2x00_async_iocb_timeout;
205 sp->done = qla2x00_async_logout_sp_done;
206 rval = qla2x00_start_sp(sp);
207 if (rval != QLA_SUCCESS)
208 goto done_free_sp;
209
210 ql_dbg(ql_dbg_disc, vha, 0x2070,
211 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
212 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
213 fcport->d_id.b.area, fcport->d_id.b.al_pa);
214 return rval;
215
216done_free_sp:
217 sp->free(fcport->vha, sp);
218done:
219 return rval;
220}
221
222static void
223qla2x00_async_adisc_sp_done(void *data, void *ptr, int res)
224{
225 srb_t *sp = (srb_t *)ptr;
226 struct srb_iocb *lio = &sp->u.iocb_cmd;
227 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
228
229 if (!test_bit(UNLOADING, &vha->dpc_flags))
230 qla2x00_post_async_adisc_done_work(sp->fcport->vha, sp->fcport,
231 lio->u.logio.data);
232 sp->free(sp->fcport->vha, sp);
233}
234
235int
236qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
237 uint16_t *data)
238{
239 srb_t *sp;
240 struct srb_iocb *lio;
241 int rval;
242
243 rval = QLA_FUNCTION_FAILED;
244 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
245 if (!sp)
246 goto done;
247
248 sp->type = SRB_ADISC_CMD;
249 sp->name = "adisc";
250 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
251
252 lio = &sp->u.iocb_cmd;
253 lio->timeout = qla2x00_async_iocb_timeout;
254 sp->done = qla2x00_async_adisc_sp_done;
255 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
256 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
257 rval = qla2x00_start_sp(sp);
258 if (rval != QLA_SUCCESS)
259 goto done_free_sp;
260
261 ql_dbg(ql_dbg_disc, vha, 0x206f,
262 "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n",
263 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
264 fcport->d_id.b.area, fcport->d_id.b.al_pa);
265 return rval;
266
267done_free_sp:
268 sp->free(fcport->vha, sp);
269done:
270 return rval;
271}
272
273static void
274qla2x00_tmf_iocb_timeout(void *data)
275{
276 srb_t *sp = (srb_t *)data;
277 struct srb_iocb *tmf = &sp->u.iocb_cmd;
278
279 tmf->u.tmf.comp_status = CS_TIMEOUT;
280 complete(&tmf->u.tmf.comp);
281}
282
283static void
284qla2x00_tmf_sp_done(void *data, void *ptr, int res)
285{
286 srb_t *sp = (srb_t *)ptr;
287 struct srb_iocb *tmf = &sp->u.iocb_cmd;
288 complete(&tmf->u.tmf.comp);
289}
290
291int
292qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun,
293 uint32_t tag)
294{
295 struct scsi_qla_host *vha = fcport->vha;
296 struct srb_iocb *tm_iocb;
297 srb_t *sp;
298 int rval = QLA_FUNCTION_FAILED;
299
300 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
301 if (!sp)
302 goto done;
303
304 tm_iocb = &sp->u.iocb_cmd;
305 sp->type = SRB_TM_CMD;
306 sp->name = "tmf";
307 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
308 tm_iocb->u.tmf.flags = flags;
309 tm_iocb->u.tmf.lun = lun;
310 tm_iocb->u.tmf.data = tag;
311 sp->done = qla2x00_tmf_sp_done;
312 tm_iocb->timeout = qla2x00_tmf_iocb_timeout;
313 init_completion(&tm_iocb->u.tmf.comp);
314
315 rval = qla2x00_start_sp(sp);
316 if (rval != QLA_SUCCESS)
317 goto done_free_sp;
318
319 ql_dbg(ql_dbg_taskm, vha, 0x802f,
320 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
321 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
322 fcport->d_id.b.area, fcport->d_id.b.al_pa);
323
324 wait_for_completion(&tm_iocb->u.tmf.comp);
325
326 rval = tm_iocb->u.tmf.comp_status == CS_COMPLETE ?
327 QLA_SUCCESS : QLA_FUNCTION_FAILED;
328
329 if ((rval != QLA_SUCCESS) || tm_iocb->u.tmf.data) {
330 ql_dbg(ql_dbg_taskm, vha, 0x8030,
331 "TM IOCB failed (%x).\n", rval);
332 }
333
334 if (!test_bit(UNLOADING, &vha->dpc_flags) && !IS_QLAFX00(vha->hw)) {
335 flags = tm_iocb->u.tmf.flags;
336 lun = (uint16_t)tm_iocb->u.tmf.lun;
337
338
339 qla2x00_marker(vha, vha->hw->req_q_map[0],
340 vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
341 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
342 }
343
344done_free_sp:
345 sp->free(vha, sp);
346done:
347 return rval;
348}
349
350static void
351qla24xx_abort_iocb_timeout(void *data)
352{
353 srb_t *sp = (srb_t *)data;
354 struct srb_iocb *abt = &sp->u.iocb_cmd;
355
356 abt->u.abt.comp_status = CS_TIMEOUT;
357 complete(&abt->u.abt.comp);
358}
359
360static void
361qla24xx_abort_sp_done(void *data, void *ptr, int res)
362{
363 srb_t *sp = (srb_t *)ptr;
364 struct srb_iocb *abt = &sp->u.iocb_cmd;
365
366 complete(&abt->u.abt.comp);
367}
368
369static int
370qla24xx_async_abort_cmd(srb_t *cmd_sp)
371{
372 scsi_qla_host_t *vha = cmd_sp->fcport->vha;
373 fc_port_t *fcport = cmd_sp->fcport;
374 struct srb_iocb *abt_iocb;
375 srb_t *sp;
376 int rval = QLA_FUNCTION_FAILED;
377
378 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
379 if (!sp)
380 goto done;
381
382 abt_iocb = &sp->u.iocb_cmd;
383 sp->type = SRB_ABT_CMD;
384 sp->name = "abort";
385 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
386 abt_iocb->u.abt.cmd_hndl = cmd_sp->handle;
387 sp->done = qla24xx_abort_sp_done;
388 abt_iocb->timeout = qla24xx_abort_iocb_timeout;
389 init_completion(&abt_iocb->u.abt.comp);
390
391 rval = qla2x00_start_sp(sp);
392 if (rval != QLA_SUCCESS)
393 goto done_free_sp;
394
395 ql_dbg(ql_dbg_async, vha, 0x507c,
396 "Abort command issued - hdl=%x, target_id=%x\n",
397 cmd_sp->handle, fcport->tgt_id);
398
399 wait_for_completion(&abt_iocb->u.abt.comp);
400
401 rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ?
402 QLA_SUCCESS : QLA_FUNCTION_FAILED;
403
404done_free_sp:
405 sp->free(vha, sp);
406done:
407 return rval;
408}
409
410int
411qla24xx_async_abort_command(srb_t *sp)
412{
413 unsigned long flags = 0;
414
415 uint32_t handle;
416 fc_port_t *fcport = sp->fcport;
417 struct scsi_qla_host *vha = fcport->vha;
418 struct qla_hw_data *ha = vha->hw;
419 struct req_que *req = vha->req;
420
421 spin_lock_irqsave(&ha->hardware_lock, flags);
422 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
423 if (req->outstanding_cmds[handle] == sp)
424 break;
425 }
426 spin_unlock_irqrestore(&ha->hardware_lock, flags);
427 if (handle == req->num_outstanding_cmds) {
428
429 return QLA_FUNCTION_FAILED;
430 }
431 if (sp->type == SRB_FXIOCB_DCMD)
432 return qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
433 FXDISC_ABORT_IOCTL);
434
435 return qla24xx_async_abort_cmd(sp);
436}
437
438void
439qla2x00_async_login_done(struct scsi_qla_host *vha, fc_port_t *fcport,
440 uint16_t *data)
441{
442 int rval;
443
444 switch (data[0]) {
445 case MBS_COMMAND_COMPLETE:
446
447
448
449
450
451 rval = qla2x00_get_port_database(vha, fcport, 0);
452 if (rval == QLA_NOT_LOGGED_IN) {
453 fcport->flags &= ~FCF_ASYNC_SENT;
454 fcport->flags |= FCF_LOGIN_NEEDED;
455 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
456 break;
457 }
458
459 if (rval != QLA_SUCCESS) {
460 qla2x00_post_async_logout_work(vha, fcport, NULL);
461 qla2x00_post_async_login_work(vha, fcport, NULL);
462 break;
463 }
464 if (fcport->flags & FCF_FCP2_DEVICE) {
465 qla2x00_post_async_adisc_work(vha, fcport, data);
466 break;
467 }
468 qla2x00_update_fcport(vha, fcport);
469 break;
470 case MBS_COMMAND_ERROR:
471 fcport->flags &= ~FCF_ASYNC_SENT;
472 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
473 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
474 else
475 qla2x00_mark_device_lost(vha, fcport, 1, 0);
476 break;
477 case MBS_PORT_ID_USED:
478 fcport->loop_id = data[1];
479 qla2x00_post_async_logout_work(vha, fcport, NULL);
480 qla2x00_post_async_login_work(vha, fcport, NULL);
481 break;
482 case MBS_LOOP_ID_USED:
483 fcport->loop_id++;
484 rval = qla2x00_find_new_loop_id(vha, fcport);
485 if (rval != QLA_SUCCESS) {
486 fcport->flags &= ~FCF_ASYNC_SENT;
487 qla2x00_mark_device_lost(vha, fcport, 1, 0);
488 break;
489 }
490 qla2x00_post_async_login_work(vha, fcport, NULL);
491 break;
492 }
493 return;
494}
495
496void
497qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
498 uint16_t *data)
499{
500 qla2x00_mark_device_lost(vha, fcport, 1, 0);
501 return;
502}
503
504void
505qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
506 uint16_t *data)
507{
508 if (data[0] == MBS_COMMAND_COMPLETE) {
509 qla2x00_update_fcport(vha, fcport);
510
511 return;
512 }
513
514
515 fcport->flags &= ~FCF_ASYNC_SENT;
516 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
517 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
518 else
519 qla2x00_mark_device_lost(vha, fcport, 1, 0);
520
521 return;
522}
523
524
525
526
527
528static int
529qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
530{
531 int rval = QLA_SUCCESS;
532 struct qla_hw_data *ha = vha->hw;
533 uint32_t idc_major_ver, idc_minor_ver;
534 uint16_t config[4];
535
536 qla83xx_idc_lock(vha, 0);
537
538
539
540
541 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
542 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
543
544
545 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
546 ql_dbg(ql_dbg_p3p, vha, 0xb077,
547 "Error while setting DRV-Presence.\n");
548 rval = QLA_FUNCTION_FAILED;
549 goto exit;
550 }
551
552
553 qla83xx_reset_ownership(vha);
554
555
556
557
558
559
560
561 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
562 if (ha->flags.nic_core_reset_owner) {
563
564 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
565 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
566
567
568 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
569 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
570
571
572
573
574 ql_log(ql_log_warn, vha, 0xb07d,
575 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
576 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
577 __qla83xx_clear_drv_presence(vha);
578 rval = QLA_FUNCTION_FAILED;
579 goto exit;
580 }
581
582 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
583 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
584 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
585
586 if (ha->flags.nic_core_reset_owner) {
587 memset(config, 0, sizeof(config));
588 if (!qla81xx_get_port_config(vha, config))
589 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
590 QLA8XXX_DEV_READY);
591 }
592
593 rval = qla83xx_idc_state_handler(vha);
594
595exit:
596 qla83xx_idc_unlock(vha, 0);
597
598 return rval;
599}
600
601
602
603
604
605
606
607
608
609
610
611int
612qla2x00_initialize_adapter(scsi_qla_host_t *vha)
613{
614 int rval;
615 struct qla_hw_data *ha = vha->hw;
616 struct req_que *req = ha->req_q_map[0];
617
618
619 vha->flags.online = 0;
620 ha->flags.chip_reset_done = 0;
621 vha->flags.reset_active = 0;
622 ha->flags.pci_channel_io_perm_failure = 0;
623 ha->flags.eeh_busy = 0;
624 vha->qla_stats.jiffies_at_last_reset = get_jiffies_64();
625 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
626 atomic_set(&vha->loop_state, LOOP_DOWN);
627 vha->device_flags = DFLG_NO_CABLE;
628 vha->dpc_flags = 0;
629 vha->flags.management_server_logged_in = 0;
630 vha->marker_needed = 0;
631 ha->isp_abort_cnt = 0;
632 ha->beacon_blink_led = 0;
633
634 set_bit(0, ha->req_qid_map);
635 set_bit(0, ha->rsp_qid_map);
636
637 ql_dbg(ql_dbg_init, vha, 0x0040,
638 "Configuring PCI space...\n");
639 rval = ha->isp_ops->pci_config(vha);
640 if (rval) {
641 ql_log(ql_log_warn, vha, 0x0044,
642 "Unable to configure PCI space.\n");
643 return (rval);
644 }
645
646 ha->isp_ops->reset_chip(vha);
647
648 rval = qla2xxx_get_flash_info(vha);
649 if (rval) {
650 ql_log(ql_log_fatal, vha, 0x004f,
651 "Unable to validate FLASH data.\n");
652 return rval;
653 }
654
655 if (IS_QLA8044(ha)) {
656 qla8044_read_reset_template(vha);
657
658
659
660
661
662 if (ql2xdontresethba == 1)
663 qla8044_set_idc_dontreset(vha);
664 }
665
666 ha->isp_ops->get_flash_version(vha, req->ring);
667 ql_dbg(ql_dbg_init, vha, 0x0061,
668 "Configure NVRAM parameters...\n");
669
670 ha->isp_ops->nvram_config(vha);
671
672 if (ha->flags.disable_serdes) {
673
674 ql_log(ql_log_info, vha, 0x0077,
675 "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name);
676 return QLA_FUNCTION_FAILED;
677 }
678
679 ql_dbg(ql_dbg_init, vha, 0x0078,
680 "Verifying loaded RISC code...\n");
681
682 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
683 rval = ha->isp_ops->chip_diag(vha);
684 if (rval)
685 return (rval);
686 rval = qla2x00_setup_chip(vha);
687 if (rval)
688 return (rval);
689 }
690
691 if (IS_QLA84XX(ha)) {
692 ha->cs84xx = qla84xx_get_chip(vha);
693 if (!ha->cs84xx) {
694 ql_log(ql_log_warn, vha, 0x00d0,
695 "Unable to configure ISP84XX.\n");
696 return QLA_FUNCTION_FAILED;
697 }
698 }
699
700 if (qla_ini_mode_enabled(vha))
701 rval = qla2x00_init_rings(vha);
702
703 ha->flags.chip_reset_done = 1;
704
705 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
706
707 rval = qla84xx_init_chip(vha);
708 if (rval != QLA_SUCCESS) {
709 ql_log(ql_log_warn, vha, 0x00d4,
710 "Unable to initialize ISP84XX.\n");
711 qla84xx_put_chip(vha);
712 }
713 }
714
715
716 if (IS_QLA8031(ha)) {
717 rval = qla83xx_nic_core_fw_load(vha);
718 if (rval)
719 ql_log(ql_log_warn, vha, 0x0124,
720 "Error in initializing NIC Core f/w.\n");
721 }
722
723 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
724 qla24xx_read_fcp_prio_cfg(vha);
725
726 if (IS_P3P_TYPE(ha))
727 qla82xx_set_driver_version(vha, QLA2XXX_VERSION);
728 else
729 qla25xx_set_driver_version(vha, QLA2XXX_VERSION);
730
731 return (rval);
732}
733
734
735
736
737
738
739
740int
741qla2100_pci_config(scsi_qla_host_t *vha)
742{
743 uint16_t w;
744 unsigned long flags;
745 struct qla_hw_data *ha = vha->hw;
746 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
747
748 pci_set_master(ha->pdev);
749 pci_try_set_mwi(ha->pdev);
750
751 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
752 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
753 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
754
755 pci_disable_rom(ha->pdev);
756
757
758 spin_lock_irqsave(&ha->hardware_lock, flags);
759 ha->pci_attr = RD_REG_WORD(®->ctrl_status);
760 spin_unlock_irqrestore(&ha->hardware_lock, flags);
761
762 return QLA_SUCCESS;
763}
764
765
766
767
768
769
770
771int
772qla2300_pci_config(scsi_qla_host_t *vha)
773{
774 uint16_t w;
775 unsigned long flags = 0;
776 uint32_t cnt;
777 struct qla_hw_data *ha = vha->hw;
778 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
779
780 pci_set_master(ha->pdev);
781 pci_try_set_mwi(ha->pdev);
782
783 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
784 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
785
786 if (IS_QLA2322(ha) || IS_QLA6322(ha))
787 w &= ~PCI_COMMAND_INTX_DISABLE;
788 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
789
790
791
792
793
794
795
796
797 if (IS_QLA2300(ha)) {
798 spin_lock_irqsave(&ha->hardware_lock, flags);
799
800
801 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC);
802 for (cnt = 0; cnt < 30000; cnt++) {
803 if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) != 0)
804 break;
805
806 udelay(10);
807 }
808
809
810 WRT_REG_WORD(®->ctrl_status, 0x20);
811 RD_REG_WORD(®->ctrl_status);
812
813
814 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
815
816 if (ha->fb_rev == FPM_2300)
817 pci_clear_mwi(ha->pdev);
818
819
820 WRT_REG_WORD(®->ctrl_status, 0x0);
821 RD_REG_WORD(®->ctrl_status);
822
823
824 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC);
825 for (cnt = 0; cnt < 30000; cnt++) {
826 if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0)
827 break;
828
829 udelay(10);
830 }
831
832 spin_unlock_irqrestore(&ha->hardware_lock, flags);
833 }
834
835 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
836
837 pci_disable_rom(ha->pdev);
838
839
840 spin_lock_irqsave(&ha->hardware_lock, flags);
841 ha->pci_attr = RD_REG_WORD(®->ctrl_status);
842 spin_unlock_irqrestore(&ha->hardware_lock, flags);
843
844 return QLA_SUCCESS;
845}
846
847
848
849
850
851
852
853int
854qla24xx_pci_config(scsi_qla_host_t *vha)
855{
856 uint16_t w;
857 unsigned long flags = 0;
858 struct qla_hw_data *ha = vha->hw;
859 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
860
861 pci_set_master(ha->pdev);
862 pci_try_set_mwi(ha->pdev);
863
864 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
865 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
866 w &= ~PCI_COMMAND_INTX_DISABLE;
867 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
868
869 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
870
871
872 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
873 pcix_set_mmrbc(ha->pdev, 2048);
874
875
876 if (pci_is_pcie(ha->pdev))
877 pcie_set_readrq(ha->pdev, 4096);
878
879 pci_disable_rom(ha->pdev);
880
881 ha->chip_revision = ha->pdev->revision;
882
883
884 spin_lock_irqsave(&ha->hardware_lock, flags);
885 ha->pci_attr = RD_REG_DWORD(®->ctrl_status);
886 spin_unlock_irqrestore(&ha->hardware_lock, flags);
887
888 return QLA_SUCCESS;
889}
890
891
892
893
894
895
896
897int
898qla25xx_pci_config(scsi_qla_host_t *vha)
899{
900 uint16_t w;
901 struct qla_hw_data *ha = vha->hw;
902
903 pci_set_master(ha->pdev);
904 pci_try_set_mwi(ha->pdev);
905
906 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
907 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
908 w &= ~PCI_COMMAND_INTX_DISABLE;
909 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
910
911
912 if (pci_is_pcie(ha->pdev))
913 pcie_set_readrq(ha->pdev, 4096);
914
915 pci_disable_rom(ha->pdev);
916
917 ha->chip_revision = ha->pdev->revision;
918
919 return QLA_SUCCESS;
920}
921
922
923
924
925
926
927
928static int
929qla2x00_isp_firmware(scsi_qla_host_t *vha)
930{
931 int rval;
932 uint16_t loop_id, topo, sw_cap;
933 uint8_t domain, area, al_pa;
934 struct qla_hw_data *ha = vha->hw;
935
936
937 rval = QLA_FUNCTION_FAILED;
938
939 if (ha->flags.disable_risc_code_load) {
940 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
941
942
943 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
944 if (rval == QLA_SUCCESS) {
945
946 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
947 &area, &domain, &topo, &sw_cap);
948 }
949 }
950
951 if (rval)
952 ql_dbg(ql_dbg_init, vha, 0x007a,
953 "**** Load RISC code ****.\n");
954
955 return (rval);
956}
957
958
959
960
961
962
963
964void
965qla2x00_reset_chip(scsi_qla_host_t *vha)
966{
967 unsigned long flags = 0;
968 struct qla_hw_data *ha = vha->hw;
969 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
970 uint32_t cnt;
971 uint16_t cmd;
972
973 if (unlikely(pci_channel_offline(ha->pdev)))
974 return;
975
976 ha->isp_ops->disable_intrs(ha);
977
978 spin_lock_irqsave(&ha->hardware_lock, flags);
979
980
981 cmd = 0;
982 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
983 cmd &= ~PCI_COMMAND_MASTER;
984 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
985
986 if (!IS_QLA2100(ha)) {
987
988 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC);
989 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
990 for (cnt = 0; cnt < 30000; cnt++) {
991 if ((RD_REG_WORD(®->hccr) &
992 HCCR_RISC_PAUSE) != 0)
993 break;
994 udelay(100);
995 }
996 } else {
997 RD_REG_WORD(®->hccr);
998 udelay(10);
999 }
1000
1001
1002 WRT_REG_WORD(®->ctrl_status, 0x20);
1003 RD_REG_WORD(®->ctrl_status);
1004
1005
1006 WRT_REG_WORD(®->fpm_diag_config, 0x100);
1007 RD_REG_WORD(®->fpm_diag_config);
1008
1009
1010 if (!IS_QLA2200(ha)) {
1011 WRT_REG_WORD(®->fpm_diag_config, 0x0);
1012 RD_REG_WORD(®->fpm_diag_config);
1013 }
1014
1015
1016 WRT_REG_WORD(®->ctrl_status, 0x10);
1017 RD_REG_WORD(®->ctrl_status);
1018
1019
1020 if (IS_QLA2200(ha)) {
1021 WRT_FB_CMD_REG(ha, reg, 0xa000);
1022 RD_FB_CMD_REG(ha, reg);
1023 } else {
1024 WRT_FB_CMD_REG(ha, reg, 0x00fc);
1025
1026
1027 for (cnt = 0; cnt < 3000; cnt++) {
1028 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
1029 break;
1030 udelay(100);
1031 }
1032 }
1033
1034
1035 WRT_REG_WORD(®->ctrl_status, 0);
1036 RD_REG_WORD(®->ctrl_status);
1037
1038
1039 WRT_REG_WORD(®->hccr, HCCR_RESET_RISC);
1040 RD_REG_WORD(®->hccr);
1041
1042
1043 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC);
1044 RD_REG_WORD(®->hccr);
1045 }
1046
1047 WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT);
1048 WRT_REG_WORD(®->hccr, HCCR_CLR_HOST_INT);
1049
1050
1051 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET);
1052
1053
1054 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1055
1056
1057
1058
1059
1060 udelay(20);
1061 for (cnt = 30000; cnt; cnt--) {
1062 if ((RD_REG_WORD(®->ctrl_status) &
1063 CSR_ISP_SOFT_RESET) == 0)
1064 break;
1065 udelay(100);
1066 }
1067 } else
1068 udelay(10);
1069
1070
1071 WRT_REG_WORD(®->hccr, HCCR_RESET_RISC);
1072
1073 WRT_REG_WORD(®->semaphore, 0);
1074
1075
1076 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC);
1077 RD_REG_WORD(®->hccr);
1078
1079 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1080 for (cnt = 0; cnt < 30000; cnt++) {
1081 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
1082 break;
1083
1084 udelay(100);
1085 }
1086 } else
1087 udelay(100);
1088
1089
1090 cmd |= PCI_COMMAND_MASTER;
1091 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
1092
1093
1094 if (!IS_QLA2100(ha)) {
1095 WRT_REG_WORD(®->hccr, HCCR_DISABLE_PARITY_PAUSE);
1096 RD_REG_WORD(®->hccr);
1097 }
1098
1099 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1100}
1101
1102
1103
1104
1105
1106
1107static int
1108qla81xx_reset_mpi(scsi_qla_host_t *vha)
1109{
1110 uint16_t mb[4] = {0x1010, 0, 1, 0};
1111
1112 if (!IS_QLA81XX(vha->hw))
1113 return QLA_SUCCESS;
1114
1115 return qla81xx_write_mpi_register(vha, mb);
1116}
1117
1118
1119
1120
1121
1122
1123
1124static inline void
1125qla24xx_reset_risc(scsi_qla_host_t *vha)
1126{
1127 unsigned long flags = 0;
1128 struct qla_hw_data *ha = vha->hw;
1129 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1130 uint32_t cnt, d2;
1131 uint16_t wd;
1132 static int abts_cnt;
1133
1134 spin_lock_irqsave(&ha->hardware_lock, flags);
1135
1136
1137 WRT_REG_DWORD(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1138 for (cnt = 0; cnt < 30000; cnt++) {
1139 if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
1140 break;
1141
1142 udelay(10);
1143 }
1144
1145 WRT_REG_DWORD(®->ctrl_status,
1146 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1147 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
1148
1149 udelay(100);
1150
1151 d2 = (uint32_t) RD_REG_WORD(®->mailbox0);
1152 for (cnt = 10000 ; cnt && d2; cnt--) {
1153 udelay(5);
1154 d2 = (uint32_t) RD_REG_WORD(®->mailbox0);
1155 barrier();
1156 }
1157
1158
1159 d2 = RD_REG_DWORD(®->ctrl_status);
1160 for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) {
1161 udelay(5);
1162 d2 = RD_REG_DWORD(®->ctrl_status);
1163 barrier();
1164 }
1165
1166
1167 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
1168 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
1169 if (++abts_cnt < 5) {
1170 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1171 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
1172 } else {
1173
1174
1175
1176
1177 abts_cnt = 0;
1178 vha->flags.online = 0;
1179 }
1180 }
1181 }
1182
1183 WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET);
1184 RD_REG_DWORD(®->hccr);
1185
1186 WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE);
1187 RD_REG_DWORD(®->hccr);
1188
1189 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET);
1190 RD_REG_DWORD(®->hccr);
1191
1192 d2 = (uint32_t) RD_REG_WORD(®->mailbox0);
1193 for (cnt = 6000000 ; cnt && d2; cnt--) {
1194 udelay(5);
1195 d2 = (uint32_t) RD_REG_WORD(®->mailbox0);
1196 barrier();
1197 }
1198
1199 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1200
1201 if (IS_NOPOLLING_TYPE(ha))
1202 ha->isp_ops->enable_intrs(ha);
1203}
1204
1205static void
1206qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data)
1207{
1208 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1209
1210 WRT_REG_DWORD(®->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1211 *data = RD_REG_DWORD(®->iobase_window + RISC_REGISTER_WINDOW_OFFET);
1212
1213}
1214
1215static void
1216qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data)
1217{
1218 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1219
1220 WRT_REG_DWORD(®->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1221 WRT_REG_DWORD(®->iobase_window + RISC_REGISTER_WINDOW_OFFET, data);
1222}
1223
1224static void
1225qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha)
1226{
1227 struct qla_hw_data *ha = vha->hw;
1228 uint32_t wd32 = 0;
1229 uint delta_msec = 100;
1230 uint elapsed_msec = 0;
1231 uint timeout_msec;
1232 ulong n;
1233
1234 if (!IS_QLA25XX(ha) && !IS_QLA2031(ha))
1235 return;
1236
1237attempt:
1238 timeout_msec = TIMEOUT_SEMAPHORE;
1239 n = timeout_msec / delta_msec;
1240 while (n--) {
1241 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET);
1242 qla25xx_read_risc_sema_reg(vha, &wd32);
1243 if (wd32 & RISC_SEMAPHORE)
1244 break;
1245 msleep(delta_msec);
1246 elapsed_msec += delta_msec;
1247 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1248 goto force;
1249 }
1250
1251 if (!(wd32 & RISC_SEMAPHORE))
1252 goto force;
1253
1254 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1255 goto acquired;
1256
1257 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR);
1258 timeout_msec = TIMEOUT_SEMAPHORE_FORCE;
1259 n = timeout_msec / delta_msec;
1260 while (n--) {
1261 qla25xx_read_risc_sema_reg(vha, &wd32);
1262 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1263 break;
1264 msleep(delta_msec);
1265 elapsed_msec += delta_msec;
1266 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1267 goto force;
1268 }
1269
1270 if (wd32 & RISC_SEMAPHORE_FORCE)
1271 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR);
1272
1273 goto attempt;
1274
1275force:
1276 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET);
1277
1278acquired:
1279 return;
1280}
1281
1282
1283
1284
1285
1286
1287
1288void
1289qla24xx_reset_chip(scsi_qla_host_t *vha)
1290{
1291 struct qla_hw_data *ha = vha->hw;
1292
1293 if (pci_channel_offline(ha->pdev) &&
1294 ha->flags.pci_channel_io_perm_failure) {
1295 return;
1296 }
1297
1298 ha->isp_ops->disable_intrs(ha);
1299
1300 qla25xx_manipulate_risc_semaphore(vha);
1301
1302
1303 qla24xx_reset_risc(vha);
1304}
1305
1306
1307
1308
1309
1310
1311
1312int
1313qla2x00_chip_diag(scsi_qla_host_t *vha)
1314{
1315 int rval;
1316 struct qla_hw_data *ha = vha->hw;
1317 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1318 unsigned long flags = 0;
1319 uint16_t data;
1320 uint32_t cnt;
1321 uint16_t mb[5];
1322 struct req_que *req = ha->req_q_map[0];
1323
1324
1325 rval = QLA_FUNCTION_FAILED;
1326
1327 ql_dbg(ql_dbg_init, vha, 0x007b,
1328 "Testing device at %lx.\n", (u_long)®->flash_address);
1329
1330 spin_lock_irqsave(&ha->hardware_lock, flags);
1331
1332
1333 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET);
1334
1335
1336
1337
1338
1339 udelay(20);
1340 data = qla2x00_debounce_register(®->ctrl_status);
1341 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
1342 udelay(5);
1343 data = RD_REG_WORD(®->ctrl_status);
1344 barrier();
1345 }
1346
1347 if (!cnt)
1348 goto chip_diag_failed;
1349
1350 ql_dbg(ql_dbg_init, vha, 0x007c,
1351 "Reset register cleared by chip reset.\n");
1352
1353
1354 WRT_REG_WORD(®->hccr, HCCR_RESET_RISC);
1355 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC);
1356
1357
1358 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1359 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
1360 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
1361 udelay(5);
1362 data = RD_MAILBOX_REG(ha, reg, 0);
1363 barrier();
1364 }
1365 } else
1366 udelay(10);
1367
1368 if (!cnt)
1369 goto chip_diag_failed;
1370
1371
1372 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n");
1373
1374 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
1375 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
1376 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
1377 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
1378 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
1379 mb[3] != PROD_ID_3) {
1380 ql_log(ql_log_warn, vha, 0x0062,
1381 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
1382 mb[1], mb[2], mb[3]);
1383
1384 goto chip_diag_failed;
1385 }
1386 ha->product_id[0] = mb[1];
1387 ha->product_id[1] = mb[2];
1388 ha->product_id[2] = mb[3];
1389 ha->product_id[3] = mb[4];
1390
1391
1392 if (req->length > 1024)
1393 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
1394 else
1395 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
1396 req->length;
1397
1398 if (IS_QLA2200(ha) &&
1399 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
1400
1401 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
1402
1403 ha->device_type |= DT_ISP2200A;
1404 ha->fw_transfer_size = 128;
1405 }
1406
1407
1408 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1409
1410 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
1411 rval = qla2x00_mbx_reg_test(vha);
1412 if (rval)
1413 ql_log(ql_log_warn, vha, 0x0080,
1414 "Failed mailbox send register test.\n");
1415 else
1416
1417 rval = QLA_SUCCESS;
1418 spin_lock_irqsave(&ha->hardware_lock, flags);
1419
1420chip_diag_failed:
1421 if (rval)
1422 ql_log(ql_log_info, vha, 0x0081,
1423 "Chip diagnostics **** FAILED ****.\n");
1424
1425 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1426
1427 return (rval);
1428}
1429
1430
1431
1432
1433
1434
1435
1436int
1437qla24xx_chip_diag(scsi_qla_host_t *vha)
1438{
1439 int rval;
1440 struct qla_hw_data *ha = vha->hw;
1441 struct req_que *req = ha->req_q_map[0];
1442
1443 if (IS_P3P_TYPE(ha))
1444 return QLA_SUCCESS;
1445
1446 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
1447
1448 rval = qla2x00_mbx_reg_test(vha);
1449 if (rval) {
1450 ql_log(ql_log_warn, vha, 0x0082,
1451 "Failed mailbox send register test.\n");
1452 } else {
1453
1454 rval = QLA_SUCCESS;
1455 }
1456
1457 return rval;
1458}
1459
1460void
1461qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
1462{
1463 int rval;
1464 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
1465 eft_size, fce_size, mq_size;
1466 dma_addr_t tc_dma;
1467 void *tc;
1468 struct qla_hw_data *ha = vha->hw;
1469 struct req_que *req = ha->req_q_map[0];
1470 struct rsp_que *rsp = ha->rsp_q_map[0];
1471
1472 if (ha->fw_dump) {
1473 ql_dbg(ql_dbg_init, vha, 0x00bd,
1474 "Firmware dump already allocated.\n");
1475 return;
1476 }
1477
1478 ha->fw_dumped = 0;
1479 ha->fw_dump_cap_flags = 0;
1480 dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
1481 req_q_size = rsp_q_size = 0;
1482
1483 if (IS_QLA27XX(ha))
1484 goto try_fce;
1485
1486 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
1487 fixed_size = sizeof(struct qla2100_fw_dump);
1488 } else if (IS_QLA23XX(ha)) {
1489 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
1490 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
1491 sizeof(uint16_t);
1492 } else if (IS_FWI2_CAPABLE(ha)) {
1493 if (IS_QLA83XX(ha))
1494 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
1495 else if (IS_QLA81XX(ha))
1496 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
1497 else if (IS_QLA25XX(ha))
1498 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
1499 else
1500 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
1501
1502 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
1503 sizeof(uint32_t);
1504 if (ha->mqenable) {
1505 if (!IS_QLA83XX(ha))
1506 mq_size = sizeof(struct qla2xxx_mq_chain);
1507
1508
1509
1510
1511 mq_size += ha->max_req_queues *
1512 (req->length * sizeof(request_t));
1513 mq_size += ha->max_rsp_queues *
1514 (rsp->length * sizeof(response_t));
1515 }
1516 if (ha->tgt.atio_ring)
1517 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
1518
1519 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
1520 !IS_QLA27XX(ha))
1521 goto try_eft;
1522
1523try_fce:
1524 if (ha->fce)
1525 dma_free_coherent(&ha->pdev->dev,
1526 FCE_SIZE, ha->fce, ha->fce_dma);
1527
1528
1529 tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
1530 GFP_KERNEL);
1531 if (!tc) {
1532 ql_log(ql_log_warn, vha, 0x00be,
1533 "Unable to allocate (%d KB) for FCE.\n",
1534 FCE_SIZE / 1024);
1535 goto try_eft;
1536 }
1537
1538 memset(tc, 0, FCE_SIZE);
1539 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
1540 ha->fce_mb, &ha->fce_bufs);
1541 if (rval) {
1542 ql_log(ql_log_warn, vha, 0x00bf,
1543 "Unable to initialize FCE (%d).\n", rval);
1544 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
1545 tc_dma);
1546 ha->flags.fce_enabled = 0;
1547 goto try_eft;
1548 }
1549 ql_dbg(ql_dbg_init, vha, 0x00c0,
1550 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
1551
1552 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
1553 ha->flags.fce_enabled = 1;
1554 ha->fce_dma = tc_dma;
1555 ha->fce = tc;
1556
1557try_eft:
1558 if (ha->eft)
1559 dma_free_coherent(&ha->pdev->dev,
1560 EFT_SIZE, ha->eft, ha->eft_dma);
1561
1562
1563 tc = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
1564 GFP_KERNEL);
1565 if (!tc) {
1566 ql_log(ql_log_warn, vha, 0x00c1,
1567 "Unable to allocate (%d KB) for EFT.\n",
1568 EFT_SIZE / 1024);
1569 goto cont_alloc;
1570 }
1571
1572 memset(tc, 0, EFT_SIZE);
1573 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
1574 if (rval) {
1575 ql_log(ql_log_warn, vha, 0x00c2,
1576 "Unable to initialize EFT (%d).\n", rval);
1577 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
1578 tc_dma);
1579 goto cont_alloc;
1580 }
1581 ql_dbg(ql_dbg_init, vha, 0x00c3,
1582 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
1583
1584 eft_size = EFT_SIZE;
1585 ha->eft_dma = tc_dma;
1586 ha->eft = tc;
1587 }
1588
1589cont_alloc:
1590 if (IS_QLA27XX(ha)) {
1591 if (!ha->fw_dump_template) {
1592 ql_log(ql_log_warn, vha, 0x00ba,
1593 "Failed missing fwdump template\n");
1594 return;
1595 }
1596 dump_size = qla27xx_fwdt_calculate_dump_size(vha);
1597 ql_dbg(ql_dbg_init, vha, 0x00fa,
1598 "-> allocating fwdump (%x bytes)...\n", dump_size);
1599 goto allocate;
1600 }
1601
1602 req_q_size = req->length * sizeof(request_t);
1603 rsp_q_size = rsp->length * sizeof(response_t);
1604 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
1605 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
1606 ha->chain_offset = dump_size;
1607 dump_size += mq_size + fce_size;
1608
1609allocate:
1610 ha->fw_dump = vmalloc(dump_size);
1611 if (!ha->fw_dump) {
1612 ql_log(ql_log_warn, vha, 0x00c4,
1613 "Unable to allocate (%d KB) for firmware dump.\n",
1614 dump_size / 1024);
1615
1616 if (ha->fce) {
1617 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
1618 ha->fce_dma);
1619 ha->fce = NULL;
1620 ha->fce_dma = 0;
1621 }
1622
1623 if (ha->eft) {
1624 dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
1625 ha->eft_dma);
1626 ha->eft = NULL;
1627 ha->eft_dma = 0;
1628 }
1629 return;
1630 }
1631 ha->fw_dump_len = dump_size;
1632 ql_dbg(ql_dbg_init, vha, 0x00c5,
1633 "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
1634
1635 if (IS_QLA27XX(ha))
1636 return;
1637
1638 ha->fw_dump->signature[0] = 'Q';
1639 ha->fw_dump->signature[1] = 'L';
1640 ha->fw_dump->signature[2] = 'G';
1641 ha->fw_dump->signature[3] = 'C';
1642 ha->fw_dump->version = __constant_htonl(1);
1643
1644 ha->fw_dump->fixed_size = htonl(fixed_size);
1645 ha->fw_dump->mem_size = htonl(mem_size);
1646 ha->fw_dump->req_q_size = htonl(req_q_size);
1647 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
1648
1649 ha->fw_dump->eft_size = htonl(eft_size);
1650 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
1651 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
1652
1653 ha->fw_dump->header_size =
1654 htonl(offsetof(struct qla2xxx_fw_dump, isp));
1655}
1656
1657static int
1658qla81xx_mpi_sync(scsi_qla_host_t *vha)
1659{
1660#define MPS_MASK 0xe0
1661 int rval;
1662 uint16_t dc;
1663 uint32_t dw;
1664
1665 if (!IS_QLA81XX(vha->hw))
1666 return QLA_SUCCESS;
1667
1668 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
1669 if (rval != QLA_SUCCESS) {
1670 ql_log(ql_log_warn, vha, 0x0105,
1671 "Unable to acquire semaphore.\n");
1672 goto done;
1673 }
1674
1675 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
1676 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
1677 if (rval != QLA_SUCCESS) {
1678 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
1679 goto done_release;
1680 }
1681
1682 dc &= MPS_MASK;
1683 if (dc == (dw & MPS_MASK))
1684 goto done_release;
1685
1686 dw &= ~MPS_MASK;
1687 dw |= dc;
1688 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
1689 if (rval != QLA_SUCCESS) {
1690 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
1691 }
1692
1693done_release:
1694 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
1695 if (rval != QLA_SUCCESS) {
1696 ql_log(ql_log_warn, vha, 0x006d,
1697 "Unable to release semaphore.\n");
1698 }
1699
1700done:
1701 return rval;
1702}
1703
1704int
1705qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req)
1706{
1707
1708 if (req->outstanding_cmds)
1709 return QLA_SUCCESS;
1710
1711 if (!IS_FWI2_CAPABLE(ha) || (ha->mqiobase &&
1712 (ql2xmultique_tag || ql2xmaxqueues > 1)))
1713 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS;
1714 else {
1715 if (ha->fw_xcb_count <= ha->fw_iocb_count)
1716 req->num_outstanding_cmds = ha->fw_xcb_count;
1717 else
1718 req->num_outstanding_cmds = ha->fw_iocb_count;
1719 }
1720
1721 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1722 req->num_outstanding_cmds, GFP_KERNEL);
1723
1724 if (!req->outstanding_cmds) {
1725
1726
1727
1728
1729 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS;
1730 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1731 req->num_outstanding_cmds, GFP_KERNEL);
1732
1733 if (!req->outstanding_cmds) {
1734 ql_log(ql_log_fatal, NULL, 0x0126,
1735 "Failed to allocate memory for "
1736 "outstanding_cmds for req_que %p.\n", req);
1737 req->num_outstanding_cmds = 0;
1738 return QLA_FUNCTION_FAILED;
1739 }
1740 }
1741
1742 return QLA_SUCCESS;
1743}
1744
1745
1746
1747
1748
1749
1750
1751static int
1752qla2x00_setup_chip(scsi_qla_host_t *vha)
1753{
1754 int rval;
1755 uint32_t srisc_address = 0;
1756 struct qla_hw_data *ha = vha->hw;
1757 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1758 unsigned long flags;
1759 uint16_t fw_major_version;
1760
1761 if (IS_P3P_TYPE(ha)) {
1762 rval = ha->isp_ops->load_risc(vha, &srisc_address);
1763 if (rval == QLA_SUCCESS) {
1764 qla2x00_stop_firmware(vha);
1765 goto enable_82xx_npiv;
1766 } else
1767 goto failed;
1768 }
1769
1770 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1771
1772 spin_lock_irqsave(&ha->hardware_lock, flags);
1773 WRT_REG_WORD(®->hccr, (HCCR_ENABLE_PARITY + 0x0));
1774 RD_REG_WORD(®->hccr);
1775 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1776 }
1777
1778 qla81xx_mpi_sync(vha);
1779
1780
1781 rval = ha->isp_ops->load_risc(vha, &srisc_address);
1782 if (rval == QLA_SUCCESS) {
1783 ql_dbg(ql_dbg_init, vha, 0x00c9,
1784 "Verifying Checksum of loaded RISC code.\n");
1785
1786 rval = qla2x00_verify_checksum(vha, srisc_address);
1787 if (rval == QLA_SUCCESS) {
1788
1789 ql_dbg(ql_dbg_init, vha, 0x00ca,
1790 "Starting firmware.\n");
1791
1792 rval = qla2x00_execute_fw(vha, srisc_address);
1793
1794 if (rval == QLA_SUCCESS) {
1795enable_82xx_npiv:
1796 fw_major_version = ha->fw_major_version;
1797 if (IS_P3P_TYPE(ha))
1798 qla82xx_check_md_needed(vha);
1799 else
1800 rval = qla2x00_get_fw_version(vha);
1801 if (rval != QLA_SUCCESS)
1802 goto failed;
1803 ha->flags.npiv_supported = 0;
1804 if (IS_QLA2XXX_MIDTYPE(ha) &&
1805 (ha->fw_attributes & BIT_2)) {
1806 ha->flags.npiv_supported = 1;
1807 if ((!ha->max_npiv_vports) ||
1808 ((ha->max_npiv_vports + 1) %
1809 MIN_MULTI_ID_FABRIC))
1810 ha->max_npiv_vports =
1811 MIN_MULTI_ID_FABRIC - 1;
1812 }
1813 qla2x00_get_resource_cnts(vha, NULL,
1814 &ha->fw_xcb_count, NULL, &ha->fw_iocb_count,
1815 &ha->max_npiv_vports, NULL);
1816
1817
1818
1819
1820
1821 rval = qla2x00_alloc_outstanding_cmds(ha,
1822 vha->req);
1823 if (rval != QLA_SUCCESS)
1824 goto failed;
1825
1826 if (!fw_major_version && ql2xallocfwdump
1827 && !(IS_P3P_TYPE(ha)))
1828 qla2x00_alloc_fw_dump(vha);
1829 } else {
1830 goto failed;
1831 }
1832 } else {
1833 ql_log(ql_log_fatal, vha, 0x00cd,
1834 "ISP Firmware failed checksum.\n");
1835 goto failed;
1836 }
1837 } else
1838 goto failed;
1839
1840 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1841
1842 spin_lock_irqsave(&ha->hardware_lock, flags);
1843 if (IS_QLA2300(ha))
1844
1845 WRT_REG_WORD(®->hccr, HCCR_ENABLE_PARITY + 0x1);
1846 else
1847
1848 WRT_REG_WORD(®->hccr, HCCR_ENABLE_PARITY + 0x7);
1849 RD_REG_WORD(®->hccr);
1850 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1851 }
1852
1853 if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1854 uint32_t size;
1855
1856 rval = qla81xx_fac_get_sector_size(vha, &size);
1857 if (rval == QLA_SUCCESS) {
1858 ha->flags.fac_supported = 1;
1859 ha->fdt_block_size = size << 2;
1860 } else {
1861 ql_log(ql_log_warn, vha, 0x00ce,
1862 "Unsupported FAC firmware (%d.%02d.%02d).\n",
1863 ha->fw_major_version, ha->fw_minor_version,
1864 ha->fw_subminor_version);
1865
1866 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
1867 ha->flags.fac_supported = 0;
1868 rval = QLA_SUCCESS;
1869 }
1870 }
1871 }
1872failed:
1873 if (rval) {
1874 ql_log(ql_log_fatal, vha, 0x00cf,
1875 "Setup chip ****FAILED****.\n");
1876 }
1877
1878 return (rval);
1879}
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890void
1891qla2x00_init_response_q_entries(struct rsp_que *rsp)
1892{
1893 uint16_t cnt;
1894 response_t *pkt;
1895
1896 rsp->ring_ptr = rsp->ring;
1897 rsp->ring_index = 0;
1898 rsp->status_srb = NULL;
1899 pkt = rsp->ring_ptr;
1900 for (cnt = 0; cnt < rsp->length; cnt++) {
1901 pkt->signature = RESPONSE_PROCESSED;
1902 pkt++;
1903 }
1904}
1905
1906
1907
1908
1909
1910
1911
1912void
1913qla2x00_update_fw_options(scsi_qla_host_t *vha)
1914{
1915 uint16_t swing, emphasis, tx_sens, rx_sens;
1916 struct qla_hw_data *ha = vha->hw;
1917
1918 memset(ha->fw_options, 0, sizeof(ha->fw_options));
1919 qla2x00_get_fw_options(vha, ha->fw_options);
1920
1921 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1922 return;
1923
1924
1925 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
1926 "Serial link options.\n");
1927 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
1928 (uint8_t *)&ha->fw_seriallink_options,
1929 sizeof(ha->fw_seriallink_options));
1930
1931 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1932 if (ha->fw_seriallink_options[3] & BIT_2) {
1933 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
1934
1935
1936 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
1937 emphasis = (ha->fw_seriallink_options[2] &
1938 (BIT_4 | BIT_3)) >> 3;
1939 tx_sens = ha->fw_seriallink_options[0] &
1940 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1941 rx_sens = (ha->fw_seriallink_options[0] &
1942 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1943 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
1944 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1945 if (rx_sens == 0x0)
1946 rx_sens = 0x3;
1947 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
1948 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1949 ha->fw_options[10] |= BIT_5 |
1950 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1951 (tx_sens & (BIT_1 | BIT_0));
1952
1953
1954 swing = (ha->fw_seriallink_options[2] &
1955 (BIT_7 | BIT_6 | BIT_5)) >> 5;
1956 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
1957 tx_sens = ha->fw_seriallink_options[1] &
1958 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1959 rx_sens = (ha->fw_seriallink_options[1] &
1960 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1961 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
1962 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1963 if (rx_sens == 0x0)
1964 rx_sens = 0x3;
1965 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
1966 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1967 ha->fw_options[11] |= BIT_5 |
1968 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1969 (tx_sens & (BIT_1 | BIT_0));
1970 }
1971
1972
1973
1974 ha->fw_options[3] |= BIT_13;
1975
1976
1977 if (ha->flags.enable_led_scheme)
1978 ha->fw_options[2] |= BIT_12;
1979
1980
1981 if (IS_QLA6312(ha))
1982 ha->fw_options[2] |= BIT_13;
1983
1984
1985 qla2x00_set_fw_options(vha, ha->fw_options);
1986}
1987
1988void
1989qla24xx_update_fw_options(scsi_qla_host_t *vha)
1990{
1991 int rval;
1992 struct qla_hw_data *ha = vha->hw;
1993
1994 if (IS_P3P_TYPE(ha))
1995 return;
1996
1997
1998 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
1999 return;
2000
2001 rval = qla2x00_set_serdes_params(vha,
2002 le16_to_cpu(ha->fw_seriallink_options24[1]),
2003 le16_to_cpu(ha->fw_seriallink_options24[2]),
2004 le16_to_cpu(ha->fw_seriallink_options24[3]));
2005 if (rval != QLA_SUCCESS) {
2006 ql_log(ql_log_warn, vha, 0x0104,
2007 "Unable to update Serial Link options (%x).\n", rval);
2008 }
2009}
2010
2011void
2012qla2x00_config_rings(struct scsi_qla_host *vha)
2013{
2014 struct qla_hw_data *ha = vha->hw;
2015 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2016 struct req_que *req = ha->req_q_map[0];
2017 struct rsp_que *rsp = ha->rsp_q_map[0];
2018
2019
2020 ha->init_cb->request_q_outpointer = __constant_cpu_to_le16(0);
2021 ha->init_cb->response_q_inpointer = __constant_cpu_to_le16(0);
2022 ha->init_cb->request_q_length = cpu_to_le16(req->length);
2023 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
2024 ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
2025 ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
2026 ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
2027 ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
2028
2029 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
2030 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
2031 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
2032 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
2033 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg));
2034}
2035
2036void
2037qla24xx_config_rings(struct scsi_qla_host *vha)
2038{
2039 struct qla_hw_data *ha = vha->hw;
2040 device_reg_t __iomem *reg = ISP_QUE_REG(ha, 0);
2041 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
2042 struct qla_msix_entry *msix;
2043 struct init_cb_24xx *icb;
2044 uint16_t rid = 0;
2045 struct req_que *req = ha->req_q_map[0];
2046 struct rsp_que *rsp = ha->rsp_q_map[0];
2047
2048
2049 icb = (struct init_cb_24xx *)ha->init_cb;
2050 icb->request_q_outpointer = __constant_cpu_to_le16(0);
2051 icb->response_q_inpointer = __constant_cpu_to_le16(0);
2052 icb->request_q_length = cpu_to_le16(req->length);
2053 icb->response_q_length = cpu_to_le16(rsp->length);
2054 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
2055 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
2056 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
2057 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
2058
2059
2060 icb->atio_q_inpointer = __constant_cpu_to_le16(0);
2061 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
2062 icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma));
2063 icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma));
2064
2065 if (IS_SHADOW_REG_CAPABLE(ha))
2066 icb->firmware_options_2 |=
2067 __constant_cpu_to_le32(BIT_30|BIT_29);
2068
2069 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
2070 icb->qos = __constant_cpu_to_le16(QLA_DEFAULT_QUE_QOS);
2071 icb->rid = __constant_cpu_to_le16(rid);
2072 if (ha->flags.msix_enabled) {
2073 msix = &ha->msix_entries[1];
2074 ql_dbg(ql_dbg_init, vha, 0x00fd,
2075 "Registering vector 0x%x for base que.\n",
2076 msix->entry);
2077 icb->msix = cpu_to_le16(msix->entry);
2078 }
2079
2080 if (MSB(rid))
2081 icb->firmware_options_2 |=
2082 __constant_cpu_to_le32(BIT_19);
2083
2084 if (LSB(rid))
2085 icb->firmware_options_2 |=
2086 __constant_cpu_to_le32(BIT_18);
2087
2088
2089 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
2090 (ha->flags.msix_enabled)) {
2091 icb->firmware_options_2 &=
2092 __constant_cpu_to_le32(~BIT_22);
2093 ha->flags.disable_msix_handshake = 1;
2094 ql_dbg(ql_dbg_init, vha, 0x00fe,
2095 "MSIX Handshake Disable Mode turned on.\n");
2096 } else {
2097 icb->firmware_options_2 |=
2098 __constant_cpu_to_le32(BIT_22);
2099 }
2100 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_23);
2101
2102 WRT_REG_DWORD(®->isp25mq.req_q_in, 0);
2103 WRT_REG_DWORD(®->isp25mq.req_q_out, 0);
2104 WRT_REG_DWORD(®->isp25mq.rsp_q_in, 0);
2105 WRT_REG_DWORD(®->isp25mq.rsp_q_out, 0);
2106 } else {
2107 WRT_REG_DWORD(®->isp24.req_q_in, 0);
2108 WRT_REG_DWORD(®->isp24.req_q_out, 0);
2109 WRT_REG_DWORD(®->isp24.rsp_q_in, 0);
2110 WRT_REG_DWORD(®->isp24.rsp_q_out, 0);
2111 }
2112 qlt_24xx_config_rings(vha);
2113
2114
2115 RD_REG_DWORD(&ioreg->hccr);
2116}
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127int
2128qla2x00_init_rings(scsi_qla_host_t *vha)
2129{
2130 int rval;
2131 unsigned long flags = 0;
2132 int cnt, que;
2133 struct qla_hw_data *ha = vha->hw;
2134 struct req_que *req;
2135 struct rsp_que *rsp;
2136 struct mid_init_cb_24xx *mid_init_cb =
2137 (struct mid_init_cb_24xx *) ha->init_cb;
2138
2139 spin_lock_irqsave(&ha->hardware_lock, flags);
2140
2141
2142 for (que = 0; que < ha->max_req_queues; que++) {
2143 req = ha->req_q_map[que];
2144 if (!req)
2145 continue;
2146 req->out_ptr = (void *)(req->ring + req->length);
2147 *req->out_ptr = 0;
2148 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++)
2149 req->outstanding_cmds[cnt] = NULL;
2150
2151 req->current_outstanding_cmd = 1;
2152
2153
2154 req->ring_ptr = req->ring;
2155 req->ring_index = 0;
2156 req->cnt = req->length;
2157 }
2158
2159 for (que = 0; que < ha->max_rsp_queues; que++) {
2160 rsp = ha->rsp_q_map[que];
2161 if (!rsp)
2162 continue;
2163 rsp->in_ptr = (void *)(rsp->ring + rsp->length);
2164 *rsp->in_ptr = 0;
2165
2166 if (IS_QLAFX00(ha))
2167 qlafx00_init_response_q_entries(rsp);
2168 else
2169 qla2x00_init_response_q_entries(rsp);
2170 }
2171
2172 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
2173 ha->tgt.atio_ring_index = 0;
2174
2175 qlt_init_atio_q_entries(vha);
2176
2177 ha->isp_ops->config_rings(vha);
2178
2179 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2180
2181 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
2182
2183 if (IS_QLAFX00(ha)) {
2184 rval = qlafx00_init_firmware(vha, ha->init_cb_size);
2185 goto next_check;
2186 }
2187
2188
2189 ha->isp_ops->update_fw_options(vha);
2190
2191 if (ha->flags.npiv_supported) {
2192 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
2193 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
2194 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
2195 }
2196
2197 if (IS_FWI2_CAPABLE(ha)) {
2198 mid_init_cb->options = __constant_cpu_to_le16(BIT_1);
2199 mid_init_cb->init_cb.execution_throttle =
2200 cpu_to_le16(ha->fw_xcb_count);
2201 }
2202
2203 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
2204next_check:
2205 if (rval) {
2206 ql_log(ql_log_fatal, vha, 0x00d2,
2207 "Init Firmware **** FAILED ****.\n");
2208 } else {
2209 ql_dbg(ql_dbg_init, vha, 0x00d3,
2210 "Init Firmware -- success.\n");
2211 }
2212
2213 return (rval);
2214}
2215
2216
2217
2218
2219
2220
2221
2222static int
2223qla2x00_fw_ready(scsi_qla_host_t *vha)
2224{
2225 int rval;
2226 unsigned long wtime, mtime, cs84xx_time;
2227 uint16_t min_wait;
2228 uint16_t wait_time;
2229 uint16_t state[5];
2230 struct qla_hw_data *ha = vha->hw;
2231
2232 if (IS_QLAFX00(vha->hw))
2233 return qlafx00_fw_ready(vha);
2234
2235 rval = QLA_SUCCESS;
2236
2237
2238 min_wait = 20;
2239
2240
2241
2242
2243
2244 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
2245 wait_time = min_wait;
2246 }
2247
2248
2249 mtime = jiffies + (min_wait * HZ);
2250
2251
2252 wtime = jiffies + (wait_time * HZ);
2253
2254
2255 if (!vha->flags.init_done)
2256 ql_log(ql_log_info, vha, 0x801e,
2257 "Waiting for LIP to complete.\n");
2258
2259 do {
2260 memset(state, -1, sizeof(state));
2261 rval = qla2x00_get_firmware_state(vha, state);
2262 if (rval == QLA_SUCCESS) {
2263 if (state[0] < FSTATE_LOSS_OF_SYNC) {
2264 vha->device_flags &= ~DFLG_NO_CABLE;
2265 }
2266 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
2267 ql_dbg(ql_dbg_taskm, vha, 0x801f,
2268 "fw_state=%x 84xx=%x.\n", state[0],
2269 state[2]);
2270 if ((state[2] & FSTATE_LOGGED_IN) &&
2271 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
2272 ql_dbg(ql_dbg_taskm, vha, 0x8028,
2273 "Sending verify iocb.\n");
2274
2275 cs84xx_time = jiffies;
2276 rval = qla84xx_init_chip(vha);
2277 if (rval != QLA_SUCCESS) {
2278 ql_log(ql_log_warn,
2279 vha, 0x8007,
2280 "Init chip failed.\n");
2281 break;
2282 }
2283
2284
2285 cs84xx_time = jiffies - cs84xx_time;
2286 wtime += cs84xx_time;
2287 mtime += cs84xx_time;
2288 ql_dbg(ql_dbg_taskm, vha, 0x8008,
2289 "Increasing wait time by %ld. "
2290 "New time %ld.\n", cs84xx_time,
2291 wtime);
2292 }
2293 } else if (state[0] == FSTATE_READY) {
2294 ql_dbg(ql_dbg_taskm, vha, 0x8037,
2295 "F/W Ready - OK.\n");
2296
2297 qla2x00_get_retry_cnt(vha, &ha->retry_count,
2298 &ha->login_timeout, &ha->r_a_tov);
2299
2300 rval = QLA_SUCCESS;
2301 break;
2302 }
2303
2304 rval = QLA_FUNCTION_FAILED;
2305
2306 if (atomic_read(&vha->loop_down_timer) &&
2307 state[0] != FSTATE_READY) {
2308
2309
2310
2311 if (time_after_eq(jiffies, mtime)) {
2312 ql_log(ql_log_info, vha, 0x8038,
2313 "Cable is unplugged...\n");
2314
2315 vha->device_flags |= DFLG_NO_CABLE;
2316 break;
2317 }
2318 }
2319 } else {
2320
2321 if (time_after_eq(jiffies, mtime) ||
2322 ha->flags.isp82xx_fw_hung)
2323 break;
2324 }
2325
2326 if (time_after_eq(jiffies, wtime))
2327 break;
2328
2329
2330 msleep(500);
2331 } while (1);
2332
2333 ql_dbg(ql_dbg_taskm, vha, 0x803a,
2334 "fw_state=%x (%x, %x, %x, %x) " "curr time=%lx.\n", state[0],
2335 state[1], state[2], state[3], state[4], jiffies);
2336
2337 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
2338 ql_log(ql_log_warn, vha, 0x803b,
2339 "Firmware ready **** FAILED ****.\n");
2340 }
2341
2342 return (rval);
2343}
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358static int
2359qla2x00_configure_hba(scsi_qla_host_t *vha)
2360{
2361 int rval;
2362 uint16_t loop_id;
2363 uint16_t topo;
2364 uint16_t sw_cap;
2365 uint8_t al_pa;
2366 uint8_t area;
2367 uint8_t domain;
2368 char connect_type[22];
2369 struct qla_hw_data *ha = vha->hw;
2370 unsigned long flags;
2371 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
2372
2373
2374 rval = qla2x00_get_adapter_id(vha,
2375 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
2376 if (rval != QLA_SUCCESS) {
2377 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
2378 IS_CNA_CAPABLE(ha) ||
2379 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
2380 ql_dbg(ql_dbg_disc, vha, 0x2008,
2381 "Loop is in a transition state.\n");
2382 } else {
2383 ql_log(ql_log_warn, vha, 0x2009,
2384 "Unable to get host loop ID.\n");
2385 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) &&
2386 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) {
2387 ql_log(ql_log_warn, vha, 0x1151,
2388 "Doing link init.\n");
2389 if (qla24xx_link_initialize(vha) == QLA_SUCCESS)
2390 return rval;
2391 }
2392 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2393 }
2394 return (rval);
2395 }
2396
2397 if (topo == 4) {
2398 ql_log(ql_log_info, vha, 0x200a,
2399 "Cannot get topology - retrying.\n");
2400 return (QLA_FUNCTION_FAILED);
2401 }
2402
2403 vha->loop_id = loop_id;
2404
2405
2406 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
2407 ha->operating_mode = LOOP;
2408 ha->switch_cap = 0;
2409
2410 switch (topo) {
2411 case 0:
2412 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
2413 ha->current_topology = ISP_CFG_NL;
2414 strcpy(connect_type, "(Loop)");
2415 break;
2416
2417 case 1:
2418 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
2419 ha->switch_cap = sw_cap;
2420 ha->current_topology = ISP_CFG_FL;
2421 strcpy(connect_type, "(FL_Port)");
2422 break;
2423
2424 case 2:
2425 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
2426 ha->operating_mode = P2P;
2427 ha->current_topology = ISP_CFG_N;
2428 strcpy(connect_type, "(N_Port-to-N_Port)");
2429 break;
2430
2431 case 3:
2432 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
2433 ha->switch_cap = sw_cap;
2434 ha->operating_mode = P2P;
2435 ha->current_topology = ISP_CFG_F;
2436 strcpy(connect_type, "(F_Port)");
2437 break;
2438
2439 default:
2440 ql_dbg(ql_dbg_disc, vha, 0x200f,
2441 "HBA in unknown topology %x, using NL.\n", topo);
2442 ha->current_topology = ISP_CFG_NL;
2443 strcpy(connect_type, "(Loop)");
2444 break;
2445 }
2446
2447
2448
2449 vha->d_id.b.domain = domain;
2450 vha->d_id.b.area = area;
2451 vha->d_id.b.al_pa = al_pa;
2452
2453 spin_lock_irqsave(&ha->vport_slock, flags);
2454 qlt_update_vp_map(vha, SET_AL_PA);
2455 spin_unlock_irqrestore(&ha->vport_slock, flags);
2456
2457 if (!vha->flags.init_done)
2458 ql_log(ql_log_info, vha, 0x2010,
2459 "Topology - %s, Host Loop address 0x%x.\n",
2460 connect_type, vha->loop_id);
2461
2462 return(rval);
2463}
2464
2465inline void
2466qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
2467 char *def)
2468{
2469 char *st, *en;
2470 uint16_t index;
2471 struct qla_hw_data *ha = vha->hw;
2472 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
2473 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
2474
2475 if (memcmp(model, BINZERO, len) != 0) {
2476 strncpy(ha->model_number, model, len);
2477 st = en = ha->model_number;
2478 en += len - 1;
2479 while (en > st) {
2480 if (*en != 0x20 && *en != 0x00)
2481 break;
2482 *en-- = '\0';
2483 }
2484
2485 index = (ha->pdev->subsystem_device & 0xff);
2486 if (use_tbl &&
2487 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
2488 index < QLA_MODEL_NAMES)
2489 strncpy(ha->model_desc,
2490 qla2x00_model_name[index * 2 + 1],
2491 sizeof(ha->model_desc) - 1);
2492 } else {
2493 index = (ha->pdev->subsystem_device & 0xff);
2494 if (use_tbl &&
2495 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
2496 index < QLA_MODEL_NAMES) {
2497 strcpy(ha->model_number,
2498 qla2x00_model_name[index * 2]);
2499 strncpy(ha->model_desc,
2500 qla2x00_model_name[index * 2 + 1],
2501 sizeof(ha->model_desc) - 1);
2502 } else {
2503 strcpy(ha->model_number, def);
2504 }
2505 }
2506 if (IS_FWI2_CAPABLE(ha))
2507 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
2508 sizeof(ha->model_desc));
2509}
2510
2511
2512
2513
2514static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
2515{
2516#ifdef CONFIG_SPARC
2517 struct qla_hw_data *ha = vha->hw;
2518 struct pci_dev *pdev = ha->pdev;
2519 struct device_node *dp = pci_device_to_OF_node(pdev);
2520 const u8 *val;
2521 int len;
2522
2523 val = of_get_property(dp, "port-wwn", &len);
2524 if (val && len >= WWN_SIZE)
2525 memcpy(nv->port_name, val, WWN_SIZE);
2526
2527 val = of_get_property(dp, "node-wwn", &len);
2528 if (val && len >= WWN_SIZE)
2529 memcpy(nv->node_name, val, WWN_SIZE);
2530#endif
2531}
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546int
2547qla2x00_nvram_config(scsi_qla_host_t *vha)
2548{
2549 int rval;
2550 uint8_t chksum = 0;
2551 uint16_t cnt;
2552 uint8_t *dptr1, *dptr2;
2553 struct qla_hw_data *ha = vha->hw;
2554 init_cb_t *icb = ha->init_cb;
2555 nvram_t *nv = ha->nvram;
2556 uint8_t *ptr = ha->nvram;
2557 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2558
2559 rval = QLA_SUCCESS;
2560
2561
2562 ha->nvram_size = sizeof(nvram_t);
2563 ha->nvram_base = 0;
2564 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
2565 if ((RD_REG_WORD(®->ctrl_status) >> 14) == 1)
2566 ha->nvram_base = 0x80;
2567
2568
2569 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
2570 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
2571 chksum += *ptr++;
2572
2573 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
2574 "Contents of NVRAM.\n");
2575 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
2576 (uint8_t *)nv, ha->nvram_size);
2577
2578
2579 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
2580 nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
2581
2582 ql_log(ql_log_warn, vha, 0x0064,
2583 "Inconsistent NVRAM "
2584 "detected: checksum=0x%x id=%c version=0x%x.\n",
2585 chksum, nv->id[0], nv->nvram_version);
2586 ql_log(ql_log_warn, vha, 0x0065,
2587 "Falling back to "
2588 "functioning (yet invalid -- WWPN) defaults.\n");
2589
2590
2591
2592
2593 memset(nv, 0, ha->nvram_size);
2594 nv->parameter_block_version = ICB_VERSION;
2595
2596 if (IS_QLA23XX(ha)) {
2597 nv->firmware_options[0] = BIT_2 | BIT_1;
2598 nv->firmware_options[1] = BIT_7 | BIT_5;
2599 nv->add_firmware_options[0] = BIT_5;
2600 nv->add_firmware_options[1] = BIT_5 | BIT_4;
2601 nv->frame_payload_size = __constant_cpu_to_le16(2048);
2602 nv->special_options[1] = BIT_7;
2603 } else if (IS_QLA2200(ha)) {
2604 nv->firmware_options[0] = BIT_2 | BIT_1;
2605 nv->firmware_options[1] = BIT_7 | BIT_5;
2606 nv->add_firmware_options[0] = BIT_5;
2607 nv->add_firmware_options[1] = BIT_5 | BIT_4;
2608 nv->frame_payload_size = __constant_cpu_to_le16(1024);
2609 } else if (IS_QLA2100(ha)) {
2610 nv->firmware_options[0] = BIT_3 | BIT_1;
2611 nv->firmware_options[1] = BIT_5;
2612 nv->frame_payload_size = __constant_cpu_to_le16(1024);
2613 }
2614
2615 nv->max_iocb_allocation = __constant_cpu_to_le16(256);
2616 nv->execution_throttle = __constant_cpu_to_le16(16);
2617 nv->retry_count = 8;
2618 nv->retry_delay = 1;
2619
2620 nv->port_name[0] = 33;
2621 nv->port_name[3] = 224;
2622 nv->port_name[4] = 139;
2623
2624 qla2xxx_nvram_wwn_from_ofw(vha, nv);
2625
2626 nv->login_timeout = 4;
2627
2628
2629
2630
2631 nv->host_p[1] = BIT_2;
2632 nv->reset_delay = 5;
2633 nv->port_down_retry_count = 8;
2634 nv->max_luns_per_target = __constant_cpu_to_le16(8);
2635 nv->link_down_timeout = 60;
2636
2637 rval = 1;
2638 }
2639
2640#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
2641
2642
2643
2644
2645
2646
2647 if (ia64_platform_is("sn2")) {
2648 nv->frame_payload_size = __constant_cpu_to_le16(2048);
2649 if (IS_QLA23XX(ha))
2650 nv->special_options[1] = BIT_7;
2651 }
2652#endif
2653
2654
2655 memset(icb, 0, ha->init_cb_size);
2656
2657
2658
2659
2660 nv->firmware_options[0] |= (BIT_6 | BIT_1);
2661 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
2662 nv->firmware_options[1] |= (BIT_5 | BIT_0);
2663 nv->firmware_options[1] &= ~BIT_4;
2664
2665 if (IS_QLA23XX(ha)) {
2666 nv->firmware_options[0] |= BIT_2;
2667 nv->firmware_options[0] &= ~BIT_3;
2668 nv->special_options[0] &= ~BIT_6;
2669 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
2670
2671 if (IS_QLA2300(ha)) {
2672 if (ha->fb_rev == FPM_2310) {
2673 strcpy(ha->model_number, "QLA2310");
2674 } else {
2675 strcpy(ha->model_number, "QLA2300");
2676 }
2677 } else {
2678 qla2x00_set_model_info(vha, nv->model_number,
2679 sizeof(nv->model_number), "QLA23xx");
2680 }
2681 } else if (IS_QLA2200(ha)) {
2682 nv->firmware_options[0] |= BIT_2;
2683
2684
2685
2686
2687 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
2688 (BIT_5 | BIT_4)) {
2689
2690 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
2691 nv->add_firmware_options[0] |= BIT_5;
2692 }
2693 strcpy(ha->model_number, "QLA22xx");
2694 } else {
2695 strcpy(ha->model_number, "QLA2100");
2696 }
2697
2698
2699
2700
2701 dptr1 = (uint8_t *)icb;
2702 dptr2 = (uint8_t *)&nv->parameter_block_version;
2703 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
2704 while (cnt--)
2705 *dptr1++ = *dptr2++;
2706
2707
2708 dptr1 = (uint8_t *)icb->add_firmware_options;
2709 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
2710 while (cnt--)
2711 *dptr1++ = *dptr2++;
2712
2713
2714 if (nv->host_p[1] & BIT_7) {
2715 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
2716 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
2717 }
2718
2719
2720 if ((icb->firmware_options[1] & BIT_6) == 0) {
2721
2722
2723
2724
2725 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
2726 icb->node_name[0] &= 0xF0;
2727 }
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737 if (nv->host_p[0] & BIT_7)
2738 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
2739 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
2740
2741 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
2742 ha->flags.disable_risc_code_load = 0;
2743 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
2744 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
2745 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
2746 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
2747 ha->flags.disable_serdes = 0;
2748
2749 ha->operating_mode =
2750 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
2751
2752 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
2753 sizeof(ha->fw_seriallink_options));
2754
2755
2756 ha->serial0 = icb->port_name[5];
2757 ha->serial1 = icb->port_name[6];
2758 ha->serial2 = icb->port_name[7];
2759 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
2760 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
2761
2762 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
2763
2764 ha->retry_count = nv->retry_count;
2765
2766
2767 if (nv->login_timeout != ql2xlogintimeout)
2768 nv->login_timeout = ql2xlogintimeout;
2769 if (nv->login_timeout < 4)
2770 nv->login_timeout = 4;
2771 ha->login_timeout = nv->login_timeout;
2772 icb->login_timeout = nv->login_timeout;
2773
2774
2775 ha->r_a_tov = 100;
2776
2777 ha->loop_reset_delay = nv->reset_delay;
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789 if (nv->link_down_timeout == 0) {
2790 ha->loop_down_abort_time =
2791 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
2792 } else {
2793 ha->link_down_timeout = nv->link_down_timeout;
2794 ha->loop_down_abort_time =
2795 (LOOP_DOWN_TIME - ha->link_down_timeout);
2796 }
2797
2798
2799
2800
2801 ha->port_down_retry_count = nv->port_down_retry_count;
2802 if (qlport_down_retry)
2803 ha->port_down_retry_count = qlport_down_retry;
2804
2805 ha->login_retry_count = nv->retry_count;
2806 if (ha->port_down_retry_count == nv->port_down_retry_count &&
2807 ha->port_down_retry_count > 3)
2808 ha->login_retry_count = ha->port_down_retry_count;
2809 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
2810 ha->login_retry_count = ha->port_down_retry_count;
2811 if (ql2xloginretrycount)
2812 ha->login_retry_count = ql2xloginretrycount;
2813
2814 icb->lun_enables = __constant_cpu_to_le16(0);
2815 icb->command_resource_count = 0;
2816 icb->immediate_notify_resource_count = 0;
2817 icb->timeout = __constant_cpu_to_le16(0);
2818
2819 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
2820
2821 icb->firmware_options[0] &= ~BIT_3;
2822 icb->add_firmware_options[0] &=
2823 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
2824 icb->add_firmware_options[0] |= BIT_2;
2825 icb->response_accumulation_timer = 3;
2826 icb->interrupt_delay_timer = 5;
2827
2828 vha->flags.process_response_queue = 1;
2829 } else {
2830
2831 if (!vha->flags.init_done) {
2832 ha->zio_mode = icb->add_firmware_options[0] &
2833 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
2834 ha->zio_timer = icb->interrupt_delay_timer ?
2835 icb->interrupt_delay_timer: 2;
2836 }
2837 icb->add_firmware_options[0] &=
2838 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
2839 vha->flags.process_response_queue = 0;
2840 if (ha->zio_mode != QLA_ZIO_DISABLED) {
2841 ha->zio_mode = QLA_ZIO_MODE_6;
2842
2843 ql_log(ql_log_info, vha, 0x0068,
2844 "ZIO mode %d enabled; timer delay (%d us).\n",
2845 ha->zio_mode, ha->zio_timer * 100);
2846
2847 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
2848 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
2849 vha->flags.process_response_queue = 1;
2850 }
2851 }
2852
2853 if (rval) {
2854 ql_log(ql_log_warn, vha, 0x0069,
2855 "NVRAM configuration failed.\n");
2856 }
2857 return (rval);
2858}
2859
2860static void
2861qla2x00_rport_del(void *data)
2862{
2863 fc_port_t *fcport = data;
2864 struct fc_rport *rport;
2865 scsi_qla_host_t *vha = fcport->vha;
2866 unsigned long flags;
2867
2868 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
2869 rport = fcport->drport ? fcport->drport: fcport->rport;
2870 fcport->drport = NULL;
2871 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
2872 if (rport) {
2873 fc_remote_port_delete(rport);
2874
2875
2876
2877
2878 qlt_fc_port_deleted(vha, fcport);
2879 }
2880}
2881
2882
2883
2884
2885
2886
2887
2888
2889fc_port_t *
2890qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
2891{
2892 fc_port_t *fcport;
2893
2894 fcport = kzalloc(sizeof(fc_port_t), flags);
2895 if (!fcport)
2896 return NULL;
2897
2898
2899 fcport->vha = vha;
2900 fcport->port_type = FCT_UNKNOWN;
2901 fcport->loop_id = FC_NO_LOOP_ID;
2902 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
2903 fcport->supported_classes = FC_COS_UNSPECIFIED;
2904
2905 return fcport;
2906}
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920static int
2921qla2x00_configure_loop(scsi_qla_host_t *vha)
2922{
2923 int rval;
2924 unsigned long flags, save_flags;
2925 struct qla_hw_data *ha = vha->hw;
2926 rval = QLA_SUCCESS;
2927
2928
2929 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
2930 rval = qla2x00_configure_hba(vha);
2931 if (rval != QLA_SUCCESS) {
2932 ql_dbg(ql_dbg_disc, vha, 0x2013,
2933 "Unable to configure HBA.\n");
2934 return (rval);
2935 }
2936 }
2937
2938 save_flags = flags = vha->dpc_flags;
2939 ql_dbg(ql_dbg_disc, vha, 0x2014,
2940 "Configure loop -- dpc flags = 0x%lx.\n", flags);
2941
2942
2943
2944
2945
2946 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2947 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
2948
2949 qla2x00_get_data_rate(vha);
2950
2951
2952 if (ha->current_topology == ISP_CFG_FL &&
2953 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2954
2955 set_bit(RSCN_UPDATE, &flags);
2956
2957 } else if (ha->current_topology == ISP_CFG_F &&
2958 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2959
2960 set_bit(RSCN_UPDATE, &flags);
2961 clear_bit(LOCAL_LOOP_UPDATE, &flags);
2962
2963 } else if (ha->current_topology == ISP_CFG_N) {
2964 clear_bit(RSCN_UPDATE, &flags);
2965
2966 } else if (!vha->flags.online ||
2967 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
2968
2969 set_bit(RSCN_UPDATE, &flags);
2970 set_bit(LOCAL_LOOP_UPDATE, &flags);
2971 }
2972
2973 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
2974 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
2975 ql_dbg(ql_dbg_disc, vha, 0x2015,
2976 "Loop resync needed, failing.\n");
2977 rval = QLA_FUNCTION_FAILED;
2978 } else
2979 rval = qla2x00_configure_local_loop(vha);
2980 }
2981
2982 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
2983 if (LOOP_TRANSITION(vha)) {
2984 ql_dbg(ql_dbg_disc, vha, 0x201e,
2985 "Needs RSCN update and loop transition.\n");
2986 rval = QLA_FUNCTION_FAILED;
2987 }
2988 else
2989 rval = qla2x00_configure_fabric(vha);
2990 }
2991
2992 if (rval == QLA_SUCCESS) {
2993 if (atomic_read(&vha->loop_down_timer) ||
2994 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
2995 rval = QLA_FUNCTION_FAILED;
2996 } else {
2997 atomic_set(&vha->loop_state, LOOP_READY);
2998 ql_dbg(ql_dbg_disc, vha, 0x2069,
2999 "LOOP READY.\n");
3000 }
3001 }
3002
3003 if (rval) {
3004 ql_dbg(ql_dbg_disc, vha, 0x206a,
3005 "%s *** FAILED ***.\n", __func__);
3006 } else {
3007 ql_dbg(ql_dbg_disc, vha, 0x206b,
3008 "%s: exiting normally.\n", __func__);
3009 }
3010
3011
3012 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
3013 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
3014 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
3015 if (test_bit(RSCN_UPDATE, &save_flags)) {
3016 set_bit(RSCN_UPDATE, &vha->dpc_flags);
3017 }
3018 }
3019
3020 return (rval);
3021}
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035static int
3036qla2x00_configure_local_loop(scsi_qla_host_t *vha)
3037{
3038 int rval, rval2;
3039 int found_devs;
3040 int found;
3041 fc_port_t *fcport, *new_fcport;
3042
3043 uint16_t index;
3044 uint16_t entries;
3045 char *id_iter;
3046 uint16_t loop_id;
3047 uint8_t domain, area, al_pa;
3048 struct qla_hw_data *ha = vha->hw;
3049
3050 found_devs = 0;
3051 new_fcport = NULL;
3052 entries = MAX_FIBRE_DEVICES_LOOP;
3053
3054
3055 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
3056 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
3057 &entries);
3058 if (rval != QLA_SUCCESS)
3059 goto cleanup_allocation;
3060
3061 ql_dbg(ql_dbg_disc, vha, 0x2017,
3062 "Entries in ID list (%d).\n", entries);
3063 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
3064 (uint8_t *)ha->gid_list,
3065 entries * sizeof(struct gid_list_info));
3066
3067
3068 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
3069 if (new_fcport == NULL) {
3070 ql_log(ql_log_warn, vha, 0x2018,
3071 "Memory allocation failed for fcport.\n");
3072 rval = QLA_MEMORY_ALLOC_FAILED;
3073 goto cleanup_allocation;
3074 }
3075 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
3076
3077
3078
3079
3080 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3081 if (atomic_read(&fcport->state) == FCS_ONLINE &&
3082 fcport->port_type != FCT_BROADCAST &&
3083 (fcport->flags & FCF_FABRIC_DEVICE) == 0) {
3084
3085 ql_dbg(ql_dbg_disc, vha, 0x2019,
3086 "Marking port lost loop_id=0x%04x.\n",
3087 fcport->loop_id);
3088
3089 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3090 }
3091 }
3092
3093
3094 id_iter = (char *)ha->gid_list;
3095 for (index = 0; index < entries; index++) {
3096 domain = ((struct gid_list_info *)id_iter)->domain;
3097 area = ((struct gid_list_info *)id_iter)->area;
3098 al_pa = ((struct gid_list_info *)id_iter)->al_pa;
3099 if (IS_QLA2100(ha) || IS_QLA2200(ha))
3100 loop_id = (uint16_t)
3101 ((struct gid_list_info *)id_iter)->loop_id_2100;
3102 else
3103 loop_id = le16_to_cpu(
3104 ((struct gid_list_info *)id_iter)->loop_id);
3105 id_iter += ha->gid_list_info_size;
3106
3107
3108 if ((domain & 0xf0) == 0xf0)
3109 continue;
3110
3111
3112 if (area && domain &&
3113 (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
3114 continue;
3115
3116
3117 if (loop_id > LAST_LOCAL_LOOP_ID)
3118 continue;
3119
3120 memset(new_fcport, 0, sizeof(fc_port_t));
3121
3122
3123 new_fcport->d_id.b.domain = domain;
3124 new_fcport->d_id.b.area = area;
3125 new_fcport->d_id.b.al_pa = al_pa;
3126 new_fcport->loop_id = loop_id;
3127 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
3128 if (rval2 != QLA_SUCCESS) {
3129 ql_dbg(ql_dbg_disc, vha, 0x201a,
3130 "Failed to retrieve fcport information "
3131 "-- get_port_database=%x, loop_id=0x%04x.\n",
3132 rval2, new_fcport->loop_id);
3133 ql_dbg(ql_dbg_disc, vha, 0x201b,
3134 "Scheduling resync.\n");
3135 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
3136 continue;
3137 }
3138
3139
3140 found = 0;
3141 fcport = NULL;
3142 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3143 if (memcmp(new_fcport->port_name, fcport->port_name,
3144 WWN_SIZE))
3145 continue;
3146
3147 fcport->flags &= ~FCF_FABRIC_DEVICE;
3148 fcport->loop_id = new_fcport->loop_id;
3149 fcport->port_type = new_fcport->port_type;
3150 fcport->d_id.b24 = new_fcport->d_id.b24;
3151 memcpy(fcport->node_name, new_fcport->node_name,
3152 WWN_SIZE);
3153
3154 found++;
3155 break;
3156 }
3157
3158 if (!found) {
3159
3160 list_add_tail(&new_fcport->list, &vha->vp_fcports);
3161
3162
3163 fcport = new_fcport;
3164 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
3165 if (new_fcport == NULL) {
3166 ql_log(ql_log_warn, vha, 0x201c,
3167 "Failed to allocate memory for fcport.\n");
3168 rval = QLA_MEMORY_ALLOC_FAILED;
3169 goto cleanup_allocation;
3170 }
3171 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
3172 }
3173
3174
3175 fcport->fp_speed = ha->link_data_rate;
3176
3177 qla2x00_update_fcport(vha, fcport);
3178
3179 found_devs++;
3180 }
3181
3182cleanup_allocation:
3183 kfree(new_fcport);
3184
3185 if (rval != QLA_SUCCESS) {
3186 ql_dbg(ql_dbg_disc, vha, 0x201d,
3187 "Configure local loop error exit: rval=%x.\n", rval);
3188 }
3189
3190 return (rval);
3191}
3192
3193static void
3194qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
3195{
3196 int rval;
3197 uint16_t mb[4];
3198 struct qla_hw_data *ha = vha->hw;
3199
3200 if (!IS_IIDMA_CAPABLE(ha))
3201 return;
3202
3203 if (atomic_read(&fcport->state) != FCS_ONLINE)
3204 return;
3205
3206 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
3207 fcport->fp_speed > ha->link_data_rate)
3208 return;
3209
3210 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
3211 mb);
3212 if (rval != QLA_SUCCESS) {
3213 ql_dbg(ql_dbg_disc, vha, 0x2004,
3214 "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n",
3215 fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]);
3216 } else {
3217 ql_dbg(ql_dbg_disc, vha, 0x2005,
3218 "iIDMA adjusted to %s GB/s on %8phN.\n",
3219 qla2x00_get_link_speed_str(ha, fcport->fp_speed),
3220 fcport->port_name);
3221 }
3222}
3223
3224static void
3225qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
3226{
3227 struct fc_rport_identifiers rport_ids;
3228 struct fc_rport *rport;
3229 unsigned long flags;
3230
3231 qla2x00_rport_del(fcport);
3232
3233 rport_ids.node_name = wwn_to_u64(fcport->node_name);
3234 rport_ids.port_name = wwn_to_u64(fcport->port_name);
3235 rport_ids.port_id = fcport->d_id.b.domain << 16 |
3236 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
3237 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
3238 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
3239 if (!rport) {
3240 ql_log(ql_log_warn, vha, 0x2006,
3241 "Unable to allocate fc remote port.\n");
3242 return;
3243 }
3244
3245
3246
3247
3248 qlt_fc_port_added(vha, fcport);
3249
3250 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
3251 *((fc_port_t **)rport->dd_data) = fcport;
3252 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
3253
3254 rport->supported_classes = fcport->supported_classes;
3255
3256 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
3257 if (fcport->port_type == FCT_INITIATOR)
3258 rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
3259 if (fcport->port_type == FCT_TARGET)
3260 rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
3261 fc_remote_port_rolechg(rport, rport_ids.roles);
3262}
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279void
3280qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
3281{
3282 fcport->vha = vha;
3283
3284 if (IS_QLAFX00(vha->hw)) {
3285 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
3286 qla2x00_reg_remote_port(vha, fcport);
3287 return;
3288 }
3289 fcport->login_retry = 0;
3290 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
3291
3292 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
3293 qla2x00_iidma_fcport(vha, fcport);
3294 qla24xx_update_fcport_fcp_prio(vha, fcport);
3295 qla2x00_reg_remote_port(vha, fcport);
3296}
3297
3298
3299
3300
3301
3302
3303
3304
3305
3306
3307
3308
3309static int
3310qla2x00_configure_fabric(scsi_qla_host_t *vha)
3311{
3312 int rval;
3313 fc_port_t *fcport, *fcptemp;
3314 uint16_t next_loopid;
3315 uint16_t mb[MAILBOX_REGISTER_COUNT];
3316 uint16_t loop_id;
3317 LIST_HEAD(new_fcports);
3318 struct qla_hw_data *ha = vha->hw;
3319 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
3320
3321
3322 if (IS_FWI2_CAPABLE(ha))
3323 loop_id = NPH_F_PORT;
3324 else
3325 loop_id = SNS_FL_PORT;
3326 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
3327 if (rval != QLA_SUCCESS) {
3328 ql_dbg(ql_dbg_disc, vha, 0x201f,
3329 "MBX_GET_PORT_NAME failed, No FL Port.\n");
3330
3331 vha->device_flags &= ~SWITCH_FOUND;
3332 return (QLA_SUCCESS);
3333 }
3334 vha->device_flags |= SWITCH_FOUND;
3335
3336 do {
3337
3338 if (ql2xfdmienable &&
3339 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
3340 qla2x00_fdmi_register(vha);
3341
3342
3343 if (IS_FWI2_CAPABLE(ha))
3344 loop_id = NPH_SNS;
3345 else
3346 loop_id = SIMPLE_NAME_SERVER;
3347 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
3348 0xfc, mb, BIT_1|BIT_0);
3349 if (rval != QLA_SUCCESS) {
3350 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
3351 return rval;
3352 }
3353 if (mb[0] != MBS_COMMAND_COMPLETE) {
3354 ql_dbg(ql_dbg_disc, vha, 0x2042,
3355 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
3356 "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1],
3357 mb[2], mb[6], mb[7]);
3358 return (QLA_SUCCESS);
3359 }
3360
3361 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
3362 if (qla2x00_rft_id(vha)) {
3363
3364 ql_dbg(ql_dbg_disc, vha, 0x2045,
3365 "Register FC-4 TYPE failed.\n");
3366 }
3367 if (qla2x00_rff_id(vha)) {
3368
3369 ql_dbg(ql_dbg_disc, vha, 0x2049,
3370 "Register FC-4 Features failed.\n");
3371 }
3372 if (qla2x00_rnn_id(vha)) {
3373
3374 ql_dbg(ql_dbg_disc, vha, 0x204f,
3375 "Register Node Name failed.\n");
3376 } else if (qla2x00_rsnn_nn(vha)) {
3377
3378 ql_dbg(ql_dbg_disc, vha, 0x2053,
3379 "Register Symobilic Node Name failed.\n");
3380 }
3381 }
3382
3383#define QLA_FCPORT_SCAN 1
3384#define QLA_FCPORT_FOUND 2
3385
3386 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3387 fcport->scan_state = QLA_FCPORT_SCAN;
3388 }
3389
3390 rval = qla2x00_find_all_fabric_devs(vha, &new_fcports);
3391 if (rval != QLA_SUCCESS)
3392 break;
3393
3394
3395
3396
3397
3398 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3399 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3400 break;
3401
3402 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0)
3403 continue;
3404
3405 if (fcport->scan_state == QLA_FCPORT_SCAN &&
3406 atomic_read(&fcport->state) == FCS_ONLINE) {
3407 qla2x00_mark_device_lost(vha, fcport,
3408 ql2xplogiabsentdevice, 0);
3409 if (fcport->loop_id != FC_NO_LOOP_ID &&
3410 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
3411 fcport->port_type != FCT_INITIATOR &&
3412 fcport->port_type != FCT_BROADCAST) {
3413 ha->isp_ops->fabric_logout(vha,
3414 fcport->loop_id,
3415 fcport->d_id.b.domain,
3416 fcport->d_id.b.area,
3417 fcport->d_id.b.al_pa);
3418 qla2x00_clear_loop_id(fcport);
3419 }
3420 }
3421 }
3422
3423
3424 next_loopid = ha->min_external_loopid;
3425
3426
3427
3428
3429
3430 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3431 if (atomic_read(&vha->loop_down_timer) ||
3432 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3433 break;
3434
3435 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
3436 (fcport->flags & FCF_LOGIN_NEEDED) == 0)
3437 continue;
3438
3439 if (fcport->loop_id == FC_NO_LOOP_ID) {
3440 fcport->loop_id = next_loopid;
3441 rval = qla2x00_find_new_loop_id(
3442 base_vha, fcport);
3443 if (rval != QLA_SUCCESS) {
3444
3445 break;
3446 }
3447 }
3448
3449 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
3450 }
3451
3452
3453 if (rval != QLA_SUCCESS) {
3454 break;
3455 }
3456
3457
3458
3459
3460 list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
3461 if (atomic_read(&vha->loop_down_timer) ||
3462 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3463 break;
3464
3465
3466 fcport->loop_id = next_loopid;
3467 rval = qla2x00_find_new_loop_id(base_vha, fcport);
3468 if (rval != QLA_SUCCESS) {
3469
3470 break;
3471 }
3472
3473
3474 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
3475
3476 list_move_tail(&fcport->list, &vha->vp_fcports);
3477 }
3478 } while (0);
3479
3480
3481 list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
3482 list_del(&fcport->list);
3483 kfree(fcport);
3484 }
3485
3486 if (rval) {
3487 ql_dbg(ql_dbg_disc, vha, 0x2068,
3488 "Configure fabric error exit rval=%d.\n", rval);
3489 }
3490
3491 return (rval);
3492}
3493
3494
3495
3496
3497
3498
3499
3500
3501
3502
3503
3504
3505
3506
3507static int
3508qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha,
3509 struct list_head *new_fcports)
3510{
3511 int rval;
3512 uint16_t loop_id;
3513 fc_port_t *fcport, *new_fcport, *fcptemp;
3514 int found;
3515
3516 sw_info_t *swl;
3517 int swl_idx;
3518 int first_dev, last_dev;
3519 port_id_t wrap = {}, nxt_d_id;
3520 struct qla_hw_data *ha = vha->hw;
3521 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
3522
3523 rval = QLA_SUCCESS;
3524
3525
3526 if (!ha->swl)
3527 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
3528 GFP_KERNEL);
3529 swl = ha->swl;
3530 if (!swl) {
3531
3532 ql_dbg(ql_dbg_disc, vha, 0x2054,
3533 "GID_PT allocations failed, fallback on GA_NXT.\n");
3534 } else {
3535 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
3536 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
3537 swl = NULL;
3538 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
3539 swl = NULL;
3540 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
3541 swl = NULL;
3542 } else if (ql2xiidmaenable &&
3543 qla2x00_gfpn_id(vha, swl) == QLA_SUCCESS) {
3544 qla2x00_gpsc(vha, swl);
3545 }
3546
3547
3548 if (swl)
3549 qla2x00_gff_id(vha, swl);
3550 }
3551 swl_idx = 0;
3552
3553
3554 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
3555 if (new_fcport == NULL) {
3556 ql_log(ql_log_warn, vha, 0x205e,
3557 "Failed to allocate memory for fcport.\n");
3558 return (QLA_MEMORY_ALLOC_FAILED);
3559 }
3560 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
3561
3562 first_dev = 1;
3563 last_dev = 0;
3564
3565
3566 loop_id = ha->min_external_loopid;
3567 for (; loop_id <= ha->max_loop_id; loop_id++) {
3568 if (qla2x00_is_reserved_id(vha, loop_id))
3569 continue;
3570
3571 if (ha->current_topology == ISP_CFG_FL &&
3572 (atomic_read(&vha->loop_down_timer) ||
3573 LOOP_TRANSITION(vha))) {
3574 atomic_set(&vha->loop_down_timer, 0);
3575 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
3576 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
3577 break;
3578 }
3579
3580 if (swl != NULL) {
3581 if (last_dev) {
3582 wrap.b24 = new_fcport->d_id.b24;
3583 } else {
3584 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
3585 memcpy(new_fcport->node_name,
3586 swl[swl_idx].node_name, WWN_SIZE);
3587 memcpy(new_fcport->port_name,
3588 swl[swl_idx].port_name, WWN_SIZE);
3589 memcpy(new_fcport->fabric_port_name,
3590 swl[swl_idx].fabric_port_name, WWN_SIZE);
3591 new_fcport->fp_speed = swl[swl_idx].fp_speed;
3592 new_fcport->fc4_type = swl[swl_idx].fc4_type;
3593
3594 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
3595 last_dev = 1;
3596 }
3597 swl_idx++;
3598 }
3599 } else {
3600
3601 rval = qla2x00_ga_nxt(vha, new_fcport);
3602 if (rval != QLA_SUCCESS) {
3603 ql_log(ql_log_warn, vha, 0x2064,
3604 "SNS scan failed -- assuming "
3605 "zero-entry result.\n");
3606 list_for_each_entry_safe(fcport, fcptemp,
3607 new_fcports, list) {
3608 list_del(&fcport->list);
3609 kfree(fcport);
3610 }
3611 rval = QLA_SUCCESS;
3612 break;
3613 }
3614 }
3615
3616
3617 if (first_dev) {
3618 wrap.b24 = new_fcport->d_id.b24;
3619 first_dev = 0;
3620 } else if (new_fcport->d_id.b24 == wrap.b24) {
3621 ql_dbg(ql_dbg_disc, vha, 0x2065,
3622 "Device wrap (%02x%02x%02x).\n",
3623 new_fcport->d_id.b.domain,
3624 new_fcport->d_id.b.area,
3625 new_fcport->d_id.b.al_pa);
3626 break;
3627 }
3628
3629
3630 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
3631 continue;
3632
3633
3634 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24))
3635 continue;
3636
3637
3638 if (((new_fcport->d_id.b24 & 0xffff00) ==
3639 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
3640 ISP_CFG_FL)
3641 continue;
3642
3643
3644 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
3645 continue;
3646
3647
3648 if (ql2xgffidenable &&
3649 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
3650 new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
3651 continue;
3652
3653
3654 found = 0;
3655 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3656 if (memcmp(new_fcport->port_name, fcport->port_name,
3657 WWN_SIZE))
3658 continue;
3659
3660 fcport->scan_state = QLA_FCPORT_FOUND;
3661
3662 found++;
3663
3664
3665 memcpy(fcport->fabric_port_name,
3666 new_fcport->fabric_port_name, WWN_SIZE);
3667 fcport->fp_speed = new_fcport->fp_speed;
3668
3669
3670
3671
3672
3673 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
3674 atomic_read(&fcport->state) == FCS_ONLINE) {
3675 break;
3676 }
3677
3678
3679
3680
3681 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
3682 fcport->d_id.b24 = new_fcport->d_id.b24;
3683 qla2x00_clear_loop_id(fcport);
3684 fcport->flags |= (FCF_FABRIC_DEVICE |
3685 FCF_LOGIN_NEEDED);
3686 break;
3687 }
3688
3689
3690
3691
3692
3693
3694 fcport->d_id.b24 = new_fcport->d_id.b24;
3695 fcport->flags |= FCF_LOGIN_NEEDED;
3696 if (fcport->loop_id != FC_NO_LOOP_ID &&
3697 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
3698 (fcport->flags & FCF_ASYNC_SENT) == 0 &&
3699 fcport->port_type != FCT_INITIATOR &&
3700 fcport->port_type != FCT_BROADCAST) {
3701 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
3702 fcport->d_id.b.domain, fcport->d_id.b.area,
3703 fcport->d_id.b.al_pa);
3704 qla2x00_clear_loop_id(fcport);
3705 }
3706
3707 break;
3708 }
3709
3710 if (found)
3711 continue;
3712
3713 list_add_tail(&new_fcport->list, new_fcports);
3714
3715
3716 nxt_d_id.b24 = new_fcport->d_id.b24;
3717 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
3718 if (new_fcport == NULL) {
3719 ql_log(ql_log_warn, vha, 0x2066,
3720 "Memory allocation failed for fcport.\n");
3721 return (QLA_MEMORY_ALLOC_FAILED);
3722 }
3723 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
3724 new_fcport->d_id.b24 = nxt_d_id.b24;
3725 }
3726
3727 kfree(new_fcport);
3728
3729 return (rval);
3730}
3731
3732
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743
3744
3745
3746int
3747qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
3748{
3749 int rval;
3750 struct qla_hw_data *ha = vha->hw;
3751 unsigned long flags = 0;
3752
3753 rval = QLA_SUCCESS;
3754
3755 spin_lock_irqsave(&ha->vport_slock, flags);
3756
3757 dev->loop_id = find_first_zero_bit(ha->loop_id_map,
3758 LOOPID_MAP_SIZE);
3759 if (dev->loop_id >= LOOPID_MAP_SIZE ||
3760 qla2x00_is_reserved_id(vha, dev->loop_id)) {
3761 dev->loop_id = FC_NO_LOOP_ID;
3762 rval = QLA_FUNCTION_FAILED;
3763 } else
3764 set_bit(dev->loop_id, ha->loop_id_map);
3765
3766 spin_unlock_irqrestore(&ha->vport_slock, flags);
3767
3768 if (rval == QLA_SUCCESS)
3769 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
3770 "Assigning new loopid=%x, portid=%x.\n",
3771 dev->loop_id, dev->d_id.b24);
3772 else
3773 ql_log(ql_log_warn, dev->vha, 0x2087,
3774 "No loop_id's available, portid=%x.\n",
3775 dev->d_id.b24);
3776
3777 return (rval);
3778}
3779
3780
3781
3782
3783
3784
3785
3786
3787
3788
3789
3790
3791
3792
3793
3794
3795
3796static int
3797qla2x00_fabric_dev_login(scsi_qla_host_t *vha, fc_port_t *fcport,
3798 uint16_t *next_loopid)
3799{
3800 int rval;
3801 int retry;
3802 uint8_t opts;
3803 struct qla_hw_data *ha = vha->hw;
3804
3805 rval = QLA_SUCCESS;
3806 retry = 0;
3807
3808 if (IS_ALOGIO_CAPABLE(ha)) {
3809 if (fcport->flags & FCF_ASYNC_SENT)
3810 return rval;
3811 fcport->flags |= FCF_ASYNC_SENT;
3812 rval = qla2x00_post_async_login_work(vha, fcport, NULL);
3813 if (!rval)
3814 return rval;
3815 }
3816
3817 fcport->flags &= ~FCF_ASYNC_SENT;
3818 rval = qla2x00_fabric_login(vha, fcport, next_loopid);
3819 if (rval == QLA_SUCCESS) {
3820
3821 opts = 0;
3822 if (fcport->flags & FCF_FCP2_DEVICE)
3823 opts |= BIT_1;
3824 rval = qla2x00_get_port_database(vha, fcport, opts);
3825 if (rval != QLA_SUCCESS) {
3826 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
3827 fcport->d_id.b.domain, fcport->d_id.b.area,
3828 fcport->d_id.b.al_pa);
3829 qla2x00_mark_device_lost(vha, fcport, 1, 0);
3830 } else {
3831 qla2x00_update_fcport(vha, fcport);
3832 }
3833 } else {
3834
3835 qla2x00_mark_device_lost(vha, fcport, 1, 0);
3836 }
3837
3838 return (rval);
3839}
3840
3841
3842
3843
3844
3845
3846
3847
3848
3849
3850
3851
3852
3853
3854
3855int
3856qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
3857 uint16_t *next_loopid)
3858{
3859 int rval;
3860 int retry;
3861 uint16_t tmp_loopid;
3862 uint16_t mb[MAILBOX_REGISTER_COUNT];
3863 struct qla_hw_data *ha = vha->hw;
3864
3865 retry = 0;
3866 tmp_loopid = 0;
3867
3868 for (;;) {
3869 ql_dbg(ql_dbg_disc, vha, 0x2000,
3870 "Trying Fabric Login w/loop id 0x%04x for port "
3871 "%02x%02x%02x.\n",
3872 fcport->loop_id, fcport->d_id.b.domain,
3873 fcport->d_id.b.area, fcport->d_id.b.al_pa);
3874
3875
3876 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
3877 fcport->d_id.b.domain, fcport->d_id.b.area,
3878 fcport->d_id.b.al_pa, mb, BIT_0);
3879 if (rval != QLA_SUCCESS) {
3880 return rval;
3881 }
3882 if (mb[0] == MBS_PORT_ID_USED) {
3883
3884
3885
3886
3887
3888
3889
3890 retry++;
3891 tmp_loopid = fcport->loop_id;
3892 fcport->loop_id = mb[1];
3893
3894 ql_dbg(ql_dbg_disc, vha, 0x2001,
3895 "Fabric Login: port in use - next loop "
3896 "id=0x%04x, port id= %02x%02x%02x.\n",
3897 fcport->loop_id, fcport->d_id.b.domain,
3898 fcport->d_id.b.area, fcport->d_id.b.al_pa);
3899
3900 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
3901
3902
3903
3904 if (retry) {
3905
3906 *next_loopid = tmp_loopid;
3907 } else {
3908
3909
3910
3911
3912 *next_loopid = (fcport->loop_id + 1);
3913 }
3914
3915 if (mb[1] & BIT_0) {
3916 fcport->port_type = FCT_INITIATOR;
3917 } else {
3918 fcport->port_type = FCT_TARGET;
3919 if (mb[1] & BIT_1) {
3920 fcport->flags |= FCF_FCP2_DEVICE;
3921 }
3922 }
3923
3924 if (mb[10] & BIT_0)
3925 fcport->supported_classes |= FC_COS_CLASS2;
3926 if (mb[10] & BIT_1)
3927 fcport->supported_classes |= FC_COS_CLASS3;
3928
3929 if (IS_FWI2_CAPABLE(ha)) {
3930 if (mb[10] & BIT_7)
3931 fcport->flags |=
3932 FCF_CONF_COMP_SUPPORTED;
3933 }
3934
3935 rval = QLA_SUCCESS;
3936 break;
3937 } else if (mb[0] == MBS_LOOP_ID_USED) {
3938
3939
3940
3941 fcport->loop_id++;
3942 rval = qla2x00_find_new_loop_id(vha, fcport);
3943 if (rval != QLA_SUCCESS) {
3944
3945 break;
3946 }
3947 } else if (mb[0] == MBS_COMMAND_ERROR) {
3948
3949
3950
3951
3952
3953 *next_loopid = fcport->loop_id;
3954 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
3955 fcport->d_id.b.domain, fcport->d_id.b.area,
3956 fcport->d_id.b.al_pa);
3957 qla2x00_mark_device_lost(vha, fcport, 1, 0);
3958
3959 rval = 1;
3960 break;
3961 } else {
3962
3963
3964
3965 ql_dbg(ql_dbg_disc, vha, 0x2002,
3966 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
3967 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
3968 fcport->d_id.b.area, fcport->d_id.b.al_pa,
3969 fcport->loop_id, jiffies);
3970
3971 *next_loopid = fcport->loop_id;
3972 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
3973 fcport->d_id.b.domain, fcport->d_id.b.area,
3974 fcport->d_id.b.al_pa);
3975 qla2x00_clear_loop_id(fcport);
3976 fcport->login_retry = 0;
3977
3978 rval = 3;
3979 break;
3980 }
3981 }
3982
3983 return (rval);
3984}
3985
3986
3987
3988
3989
3990
3991
3992
3993
3994
3995
3996
3997
3998
3999int
4000qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
4001{
4002 int rval;
4003 uint16_t mb[MAILBOX_REGISTER_COUNT];
4004
4005 memset(mb, 0, sizeof(mb));
4006 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
4007 if (rval == QLA_SUCCESS) {
4008
4009 if (mb[0] == MBS_COMMAND_ERROR)
4010 rval = 1;
4011 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
4012
4013 rval = 3;
4014 }
4015
4016 return (rval);
4017}
4018
4019
4020
4021
4022
4023
4024
4025
4026
4027
4028
4029int
4030qla2x00_loop_resync(scsi_qla_host_t *vha)
4031{
4032 int rval = QLA_SUCCESS;
4033 uint32_t wait_time;
4034 struct req_que *req;
4035 struct rsp_que *rsp;
4036
4037 if (vha->hw->flags.cpu_affinity_enabled)
4038 req = vha->hw->req_q_map[0];
4039 else
4040 req = vha->req;
4041 rsp = req->rsp;
4042
4043 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4044 if (vha->flags.online) {
4045 if (!(rval = qla2x00_fw_ready(vha))) {
4046
4047 wait_time = 256;
4048 do {
4049 if (!IS_QLAFX00(vha->hw)) {
4050
4051
4052
4053
4054 qla2x00_marker(vha, req, rsp, 0, 0,
4055 MK_SYNC_ALL);
4056 vha->marker_needed = 0;
4057 }
4058
4059
4060 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
4061
4062 if (IS_QLAFX00(vha->hw))
4063 qlafx00_configure_devices(vha);
4064 else
4065 qla2x00_configure_loop(vha);
4066
4067 wait_time--;
4068 } while (!atomic_read(&vha->loop_down_timer) &&
4069 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
4070 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
4071 &vha->dpc_flags)));
4072 }
4073 }
4074
4075 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
4076 return (QLA_FUNCTION_FAILED);
4077
4078 if (rval)
4079 ql_dbg(ql_dbg_disc, vha, 0x206c,
4080 "%s *** FAILED ***.\n", __func__);
4081
4082 return (rval);
4083}
4084
4085
4086
4087
4088
4089
4090
4091
4092
4093int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
4094{
4095 int32_t rval = 0;
4096
4097 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
4098
4099 atomic_set(&ha->loop_down_timer, 0);
4100 if (!(ha->device_flags & DFLG_NO_CABLE)) {
4101 atomic_set(&ha->loop_state, LOOP_UP);
4102 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
4103 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
4104 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
4105
4106 rval = qla2x00_loop_resync(ha);
4107 } else
4108 atomic_set(&ha->loop_state, LOOP_DEAD);
4109
4110 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
4111 }
4112
4113 return rval;
4114}
4115
4116void
4117qla2x00_update_fcports(scsi_qla_host_t *base_vha)
4118{
4119 fc_port_t *fcport;
4120 struct scsi_qla_host *vha;
4121 struct qla_hw_data *ha = base_vha->hw;
4122 unsigned long flags;
4123
4124 spin_lock_irqsave(&ha->vport_slock, flags);
4125
4126 list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
4127 atomic_inc(&vha->vref_count);
4128 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4129 if (fcport->drport &&
4130 atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
4131 spin_unlock_irqrestore(&ha->vport_slock, flags);
4132 qla2x00_rport_del(fcport);
4133 spin_lock_irqsave(&ha->vport_slock, flags);
4134 }
4135 }
4136 atomic_dec(&vha->vref_count);
4137 }
4138 spin_unlock_irqrestore(&ha->vport_slock, flags);
4139}
4140
4141
4142void
4143qla83xx_reset_ownership(scsi_qla_host_t *vha)
4144{
4145 struct qla_hw_data *ha = vha->hw;
4146 uint32_t drv_presence, drv_presence_mask;
4147 uint32_t dev_part_info1, dev_part_info2, class_type;
4148 uint32_t class_type_mask = 0x3;
4149 uint16_t fcoe_other_function = 0xffff, i;
4150
4151 if (IS_QLA8044(ha)) {
4152 drv_presence = qla8044_rd_direct(vha,
4153 QLA8044_CRB_DRV_ACTIVE_INDEX);
4154 dev_part_info1 = qla8044_rd_direct(vha,
4155 QLA8044_CRB_DEV_PART_INFO_INDEX);
4156 dev_part_info2 = qla8044_rd_direct(vha,
4157 QLA8044_CRB_DEV_PART_INFO2);
4158 } else {
4159 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4160 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
4161 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
4162 }
4163 for (i = 0; i < 8; i++) {
4164 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
4165 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
4166 (i != ha->portnum)) {
4167 fcoe_other_function = i;
4168 break;
4169 }
4170 }
4171 if (fcoe_other_function == 0xffff) {
4172 for (i = 0; i < 8; i++) {
4173 class_type = ((dev_part_info2 >> (i * 4)) &
4174 class_type_mask);
4175 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
4176 ((i + 8) != ha->portnum)) {
4177 fcoe_other_function = i + 8;
4178 break;
4179 }
4180 }
4181 }
4182
4183
4184
4185
4186 drv_presence_mask = ~((1 << (ha->portnum)) |
4187 ((fcoe_other_function == 0xffff) ?
4188 0 : (1 << (fcoe_other_function))));
4189
4190
4191
4192
4193 if (!(drv_presence & drv_presence_mask) &&
4194 (ha->portnum < fcoe_other_function)) {
4195 ql_dbg(ql_dbg_p3p, vha, 0xb07f,
4196 "This host is Reset owner.\n");
4197 ha->flags.nic_core_reset_owner = 1;
4198 }
4199}
4200
4201static int
4202__qla83xx_set_drv_ack(scsi_qla_host_t *vha)
4203{
4204 int rval = QLA_SUCCESS;
4205 struct qla_hw_data *ha = vha->hw;
4206 uint32_t drv_ack;
4207
4208 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4209 if (rval == QLA_SUCCESS) {
4210 drv_ack |= (1 << ha->portnum);
4211 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
4212 }
4213
4214 return rval;
4215}
4216
4217static int
4218__qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
4219{
4220 int rval = QLA_SUCCESS;
4221 struct qla_hw_data *ha = vha->hw;
4222 uint32_t drv_ack;
4223
4224 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4225 if (rval == QLA_SUCCESS) {
4226 drv_ack &= ~(1 << ha->portnum);
4227 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
4228 }
4229
4230 return rval;
4231}
4232
4233static const char *
4234qla83xx_dev_state_to_string(uint32_t dev_state)
4235{
4236 switch (dev_state) {
4237 case QLA8XXX_DEV_COLD:
4238 return "COLD/RE-INIT";
4239 case QLA8XXX_DEV_INITIALIZING:
4240 return "INITIALIZING";
4241 case QLA8XXX_DEV_READY:
4242 return "READY";
4243 case QLA8XXX_DEV_NEED_RESET:
4244 return "NEED RESET";
4245 case QLA8XXX_DEV_NEED_QUIESCENT:
4246 return "NEED QUIESCENT";
4247 case QLA8XXX_DEV_FAILED:
4248 return "FAILED";
4249 case QLA8XXX_DEV_QUIESCENT:
4250 return "QUIESCENT";
4251 default:
4252 return "Unknown";
4253 }
4254}
4255
4256
4257void
4258qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
4259{
4260 struct qla_hw_data *ha = vha->hw;
4261 uint32_t idc_audit_reg = 0, duration_secs = 0;
4262
4263 switch (audit_type) {
4264 case IDC_AUDIT_TIMESTAMP:
4265 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
4266 idc_audit_reg = (ha->portnum) |
4267 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
4268 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4269 break;
4270
4271 case IDC_AUDIT_COMPLETION:
4272 duration_secs = ((jiffies_to_msecs(jiffies) -
4273 jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
4274 idc_audit_reg = (ha->portnum) |
4275 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
4276 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4277 break;
4278
4279 default:
4280 ql_log(ql_log_warn, vha, 0xb078,
4281 "Invalid audit type specified.\n");
4282 break;
4283 }
4284}
4285
4286
4287static int
4288qla83xx_initiating_reset(scsi_qla_host_t *vha)
4289{
4290 struct qla_hw_data *ha = vha->hw;
4291 uint32_t idc_control, dev_state;
4292
4293 __qla83xx_get_idc_control(vha, &idc_control);
4294 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
4295 ql_log(ql_log_info, vha, 0xb080,
4296 "NIC Core reset has been disabled. idc-control=0x%x\n",
4297 idc_control);
4298 return QLA_FUNCTION_FAILED;
4299 }
4300
4301
4302 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4303 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
4304 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
4305 QLA8XXX_DEV_NEED_RESET);
4306 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
4307 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
4308 } else {
4309 const char *state = qla83xx_dev_state_to_string(dev_state);
4310 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
4311
4312
4313
4314 while (dev_state == QLA8XXX_DEV_READY) {
4315 qla83xx_idc_unlock(vha, 0);
4316 msleep(200);
4317 qla83xx_idc_lock(vha, 0);
4318 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4319 }
4320 }
4321
4322
4323 __qla83xx_set_drv_ack(vha);
4324
4325 return QLA_SUCCESS;
4326}
4327
4328int
4329__qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
4330{
4331 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4332}
4333
4334int
4335__qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
4336{
4337 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4338}
4339
4340static int
4341qla83xx_check_driver_presence(scsi_qla_host_t *vha)
4342{
4343 uint32_t drv_presence = 0;
4344 struct qla_hw_data *ha = vha->hw;
4345
4346 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4347 if (drv_presence & (1 << ha->portnum))
4348 return QLA_SUCCESS;
4349 else
4350 return QLA_TEST_FAILED;
4351}
4352
4353int
4354qla83xx_nic_core_reset(scsi_qla_host_t *vha)
4355{
4356 int rval = QLA_SUCCESS;
4357 struct qla_hw_data *ha = vha->hw;
4358
4359 ql_dbg(ql_dbg_p3p, vha, 0xb058,
4360 "Entered %s().\n", __func__);
4361
4362 if (vha->device_flags & DFLG_DEV_FAILED) {
4363 ql_log(ql_log_warn, vha, 0xb059,
4364 "Device in unrecoverable FAILED state.\n");
4365 return QLA_FUNCTION_FAILED;
4366 }
4367
4368 qla83xx_idc_lock(vha, 0);
4369
4370 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
4371 ql_log(ql_log_warn, vha, 0xb05a,
4372 "Function=0x%x has been removed from IDC participation.\n",
4373 ha->portnum);
4374 rval = QLA_FUNCTION_FAILED;
4375 goto exit;
4376 }
4377
4378 qla83xx_reset_ownership(vha);
4379
4380 rval = qla83xx_initiating_reset(vha);
4381
4382
4383
4384
4385
4386 if (rval == QLA_SUCCESS) {
4387 rval = qla83xx_idc_state_handler(vha);
4388
4389 if (rval == QLA_SUCCESS)
4390 ha->flags.nic_core_hung = 0;
4391 __qla83xx_clear_drv_ack(vha);
4392 }
4393
4394exit:
4395 qla83xx_idc_unlock(vha, 0);
4396
4397 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
4398
4399 return rval;
4400}
4401
4402int
4403qla2xxx_mctp_dump(scsi_qla_host_t *vha)
4404{
4405 struct qla_hw_data *ha = vha->hw;
4406 int rval = QLA_FUNCTION_FAILED;
4407
4408 if (!IS_MCTP_CAPABLE(ha)) {
4409
4410 ql_log(ql_log_info, vha, 0x506d,
4411 "This board is not MCTP capable\n");
4412 return rval;
4413 }
4414
4415 if (!ha->mctp_dump) {
4416 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
4417 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
4418
4419 if (!ha->mctp_dump) {
4420 ql_log(ql_log_warn, vha, 0x506e,
4421 "Failed to allocate memory for mctp dump\n");
4422 return rval;
4423 }
4424 }
4425
4426#define MCTP_DUMP_STR_ADDR 0x00000000
4427 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
4428 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
4429 if (rval != QLA_SUCCESS) {
4430 ql_log(ql_log_warn, vha, 0x506f,
4431 "Failed to capture mctp dump\n");
4432 } else {
4433 ql_log(ql_log_info, vha, 0x5070,
4434 "Mctp dump capture for host (%ld/%p).\n",
4435 vha->host_no, ha->mctp_dump);
4436 ha->mctp_dumped = 1;
4437 }
4438
4439 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) {
4440 ha->flags.nic_core_reset_hdlr_active = 1;
4441 rval = qla83xx_restart_nic_firmware(vha);
4442 if (rval)
4443
4444 ql_log(ql_log_warn, vha, 0x5071,
4445 "Failed to restart nic firmware\n");
4446 else
4447 ql_dbg(ql_dbg_p3p, vha, 0xb084,
4448 "Restarted NIC firmware successfully.\n");
4449 ha->flags.nic_core_reset_hdlr_active = 0;
4450 }
4451
4452 return rval;
4453
4454}
4455
4456
4457
4458
4459
4460
4461
4462
4463
4464void
4465qla2x00_quiesce_io(scsi_qla_host_t *vha)
4466{
4467 struct qla_hw_data *ha = vha->hw;
4468 struct scsi_qla_host *vp;
4469
4470 ql_dbg(ql_dbg_dpc, vha, 0x401d,
4471 "Quiescing I/O - ha=%p.\n", ha);
4472
4473 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
4474 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4475 atomic_set(&vha->loop_state, LOOP_DOWN);
4476 qla2x00_mark_all_devices_lost(vha, 0);
4477 list_for_each_entry(vp, &ha->vp_list, list)
4478 qla2x00_mark_all_devices_lost(vp, 0);
4479 } else {
4480 if (!atomic_read(&vha->loop_down_timer))
4481 atomic_set(&vha->loop_down_timer,
4482 LOOP_DOWN_TIME);
4483 }
4484
4485 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
4486}
4487
4488void
4489qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
4490{
4491 struct qla_hw_data *ha = vha->hw;
4492 struct scsi_qla_host *vp;
4493 unsigned long flags;
4494 fc_port_t *fcport;
4495
4496
4497
4498
4499 if (!(IS_P3P_TYPE(ha)))
4500 vha->flags.online = 0;
4501 ha->flags.chip_reset_done = 0;
4502 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
4503 vha->qla_stats.total_isp_aborts++;
4504
4505 ql_log(ql_log_info, vha, 0x00af,
4506 "Performing ISP error recovery - ha=%p.\n", ha);
4507
4508
4509
4510
4511
4512 if (!(IS_P3P_TYPE(ha)))
4513 ha->isp_ops->reset_chip(vha);
4514
4515 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
4516 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4517 atomic_set(&vha->loop_state, LOOP_DOWN);
4518 qla2x00_mark_all_devices_lost(vha, 0);
4519
4520 spin_lock_irqsave(&ha->vport_slock, flags);
4521 list_for_each_entry(vp, &ha->vp_list, list) {
4522 atomic_inc(&vp->vref_count);
4523 spin_unlock_irqrestore(&ha->vport_slock, flags);
4524
4525 qla2x00_mark_all_devices_lost(vp, 0);
4526
4527 spin_lock_irqsave(&ha->vport_slock, flags);
4528 atomic_dec(&vp->vref_count);
4529 }
4530 spin_unlock_irqrestore(&ha->vport_slock, flags);
4531 } else {
4532 if (!atomic_read(&vha->loop_down_timer))
4533 atomic_set(&vha->loop_down_timer,
4534 LOOP_DOWN_TIME);
4535 }
4536
4537
4538 list_for_each_entry(fcport, &vha->vp_fcports, list)
4539 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4540 spin_lock_irqsave(&ha->vport_slock, flags);
4541 list_for_each_entry(vp, &ha->vp_list, list) {
4542 atomic_inc(&vp->vref_count);
4543 spin_unlock_irqrestore(&ha->vport_slock, flags);
4544
4545 list_for_each_entry(fcport, &vp->vp_fcports, list)
4546 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4547
4548 spin_lock_irqsave(&ha->vport_slock, flags);
4549 atomic_dec(&vp->vref_count);
4550 }
4551 spin_unlock_irqrestore(&ha->vport_slock, flags);
4552
4553 if (!ha->flags.eeh_busy) {
4554
4555 if (IS_P3P_TYPE(ha)) {
4556 qla82xx_chip_reset_cleanup(vha);
4557 ql_log(ql_log_info, vha, 0x00b4,
4558 "Done chip reset cleanup.\n");
4559
4560
4561
4562
4563 vha->flags.online = 0;
4564 }
4565
4566
4567 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
4568 }
4569}
4570
4571
4572
4573
4574
4575
4576
4577
4578
4579
4580
4581int
4582qla2x00_abort_isp(scsi_qla_host_t *vha)
4583{
4584 int rval;
4585 uint8_t status = 0;
4586 struct qla_hw_data *ha = vha->hw;
4587 struct scsi_qla_host *vp;
4588 struct req_que *req = ha->req_q_map[0];
4589 unsigned long flags;
4590
4591 if (vha->flags.online) {
4592 qla2x00_abort_isp_cleanup(vha);
4593
4594 if (IS_QLA8031(ha)) {
4595 ql_dbg(ql_dbg_p3p, vha, 0xb05c,
4596 "Clearing fcoe driver presence.\n");
4597 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
4598 ql_dbg(ql_dbg_p3p, vha, 0xb073,
4599 "Error while clearing DRV-Presence.\n");
4600 }
4601
4602 if (unlikely(pci_channel_offline(ha->pdev) &&
4603 ha->flags.pci_channel_io_perm_failure)) {
4604 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4605 status = 0;
4606 return status;
4607 }
4608
4609 ha->isp_ops->get_flash_version(vha, req->ring);
4610
4611 ha->isp_ops->nvram_config(vha);
4612
4613 if (!qla2x00_restart_isp(vha)) {
4614 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
4615
4616 if (!atomic_read(&vha->loop_down_timer)) {
4617
4618
4619
4620
4621 vha->marker_needed = 1;
4622 }
4623
4624 vha->flags.online = 1;
4625
4626 ha->isp_ops->enable_intrs(ha);
4627
4628 ha->isp_abort_cnt = 0;
4629 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4630
4631 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
4632 qla2x00_get_fw_version(vha);
4633 if (ha->fce) {
4634 ha->flags.fce_enabled = 1;
4635 memset(ha->fce, 0,
4636 fce_calc_size(ha->fce_bufs));
4637 rval = qla2x00_enable_fce_trace(vha,
4638 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
4639 &ha->fce_bufs);
4640 if (rval) {
4641 ql_log(ql_log_warn, vha, 0x8033,
4642 "Unable to reinitialize FCE "
4643 "(%d).\n", rval);
4644 ha->flags.fce_enabled = 0;
4645 }
4646 }
4647
4648 if (ha->eft) {
4649 memset(ha->eft, 0, EFT_SIZE);
4650 rval = qla2x00_enable_eft_trace(vha,
4651 ha->eft_dma, EFT_NUM_BUFFERS);
4652 if (rval) {
4653 ql_log(ql_log_warn, vha, 0x8034,
4654 "Unable to reinitialize EFT "
4655 "(%d).\n", rval);
4656 }
4657 }
4658 } else {
4659 vha->flags.online = 1;
4660 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
4661 if (ha->isp_abort_cnt == 0) {
4662 ql_log(ql_log_fatal, vha, 0x8035,
4663 "ISP error recover failed - "
4664 "board disabled.\n");
4665
4666
4667
4668
4669 ha->isp_ops->reset_adapter(vha);
4670 vha->flags.online = 0;
4671 clear_bit(ISP_ABORT_RETRY,
4672 &vha->dpc_flags);
4673 status = 0;
4674 } else {
4675 ha->isp_abort_cnt--;
4676 ql_dbg(ql_dbg_taskm, vha, 0x8020,
4677 "ISP abort - retry remaining %d.\n",
4678 ha->isp_abort_cnt);
4679 status = 1;
4680 }
4681 } else {
4682 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
4683 ql_dbg(ql_dbg_taskm, vha, 0x8021,
4684 "ISP error recovery - retrying (%d) "
4685 "more times.\n", ha->isp_abort_cnt);
4686 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4687 status = 1;
4688 }
4689 }
4690
4691 }
4692
4693 if (!status) {
4694 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
4695
4696 spin_lock_irqsave(&ha->vport_slock, flags);
4697 list_for_each_entry(vp, &ha->vp_list, list) {
4698 if (vp->vp_idx) {
4699 atomic_inc(&vp->vref_count);
4700 spin_unlock_irqrestore(&ha->vport_slock, flags);
4701
4702 qla2x00_vp_abort_isp(vp);
4703
4704 spin_lock_irqsave(&ha->vport_slock, flags);
4705 atomic_dec(&vp->vref_count);
4706 }
4707 }
4708 spin_unlock_irqrestore(&ha->vport_slock, flags);
4709
4710 if (IS_QLA8031(ha)) {
4711 ql_dbg(ql_dbg_p3p, vha, 0xb05d,
4712 "Setting back fcoe driver presence.\n");
4713 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
4714 ql_dbg(ql_dbg_p3p, vha, 0xb074,
4715 "Error while setting DRV-Presence.\n");
4716 }
4717 } else {
4718 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
4719 __func__);
4720 }
4721
4722 return(status);
4723}
4724
4725
4726
4727
4728
4729
4730
4731
4732
4733
4734
4735static int
4736qla2x00_restart_isp(scsi_qla_host_t *vha)
4737{
4738 int status = 0;
4739 struct qla_hw_data *ha = vha->hw;
4740 struct req_que *req = ha->req_q_map[0];
4741 struct rsp_que *rsp = ha->rsp_q_map[0];
4742 unsigned long flags;
4743
4744
4745 if (qla2x00_isp_firmware(vha)) {
4746 vha->flags.online = 0;
4747 status = ha->isp_ops->chip_diag(vha);
4748 if (!status)
4749 status = qla2x00_setup_chip(vha);
4750 }
4751
4752 if (!status && !(status = qla2x00_init_rings(vha))) {
4753 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
4754 ha->flags.chip_reset_done = 1;
4755
4756
4757 qla25xx_init_queues(ha);
4758
4759 status = qla2x00_fw_ready(vha);
4760 if (!status) {
4761
4762 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
4763
4764 vha->flags.online = 1;
4765
4766
4767
4768
4769
4770 spin_lock_irqsave(&ha->hardware_lock, flags);
4771 if (qla_tgt_mode_enabled(vha))
4772 qlt_24xx_process_atio_queue(vha);
4773 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4774
4775 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
4776 }
4777
4778
4779 if ((vha->device_flags & DFLG_NO_CABLE))
4780 status = 0;
4781 }
4782 return (status);
4783}
4784
4785static int
4786qla25xx_init_queues(struct qla_hw_data *ha)
4787{
4788 struct rsp_que *rsp = NULL;
4789 struct req_que *req = NULL;
4790 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
4791 int ret = -1;
4792 int i;
4793
4794 for (i = 1; i < ha->max_rsp_queues; i++) {
4795 rsp = ha->rsp_q_map[i];
4796 if (rsp) {
4797 rsp->options &= ~BIT_0;
4798 ret = qla25xx_init_rsp_que(base_vha, rsp);
4799 if (ret != QLA_SUCCESS)
4800 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
4801 "%s Rsp que: %d init failed.\n",
4802 __func__, rsp->id);
4803 else
4804 ql_dbg(ql_dbg_init, base_vha, 0x0100,
4805 "%s Rsp que: %d inited.\n",
4806 __func__, rsp->id);
4807 }
4808 }
4809 for (i = 1; i < ha->max_req_queues; i++) {
4810 req = ha->req_q_map[i];
4811 if (req) {
4812
4813 req->options &= ~BIT_0;
4814 ret = qla25xx_init_req_que(base_vha, req);
4815 if (ret != QLA_SUCCESS)
4816 ql_dbg(ql_dbg_init, base_vha, 0x0101,
4817 "%s Req que: %d init failed.\n",
4818 __func__, req->id);
4819 else
4820 ql_dbg(ql_dbg_init, base_vha, 0x0102,
4821 "%s Req que: %d inited.\n",
4822 __func__, req->id);
4823 }
4824 }
4825 return ret;
4826}
4827
4828
4829
4830
4831
4832
4833
4834
4835void
4836qla2x00_reset_adapter(scsi_qla_host_t *vha)
4837{
4838 unsigned long flags = 0;
4839 struct qla_hw_data *ha = vha->hw;
4840 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
4841
4842 vha->flags.online = 0;
4843 ha->isp_ops->disable_intrs(ha);
4844
4845 spin_lock_irqsave(&ha->hardware_lock, flags);
4846 WRT_REG_WORD(®->hccr, HCCR_RESET_RISC);
4847 RD_REG_WORD(®->hccr);
4848 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC);
4849 RD_REG_WORD(®->hccr);
4850 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4851}
4852
4853void
4854qla24xx_reset_adapter(scsi_qla_host_t *vha)
4855{
4856 unsigned long flags = 0;
4857 struct qla_hw_data *ha = vha->hw;
4858 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
4859
4860 if (IS_P3P_TYPE(ha))
4861 return;
4862
4863 vha->flags.online = 0;
4864 ha->isp_ops->disable_intrs(ha);
4865
4866 spin_lock_irqsave(&ha->hardware_lock, flags);
4867 WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET);
4868 RD_REG_DWORD(®->hccr);
4869 WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE);
4870 RD_REG_DWORD(®->hccr);
4871 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4872
4873 if (IS_NOPOLLING_TYPE(ha))
4874 ha->isp_ops->enable_intrs(ha);
4875}
4876
4877
4878
4879
4880static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
4881 struct nvram_24xx *nv)
4882{
4883#ifdef CONFIG_SPARC
4884 struct qla_hw_data *ha = vha->hw;
4885 struct pci_dev *pdev = ha->pdev;
4886 struct device_node *dp = pci_device_to_OF_node(pdev);
4887 const u8 *val;
4888 int len;
4889
4890 val = of_get_property(dp, "port-wwn", &len);
4891 if (val && len >= WWN_SIZE)
4892 memcpy(nv->port_name, val, WWN_SIZE);
4893
4894 val = of_get_property(dp, "node-wwn", &len);
4895 if (val && len >= WWN_SIZE)
4896 memcpy(nv->node_name, val, WWN_SIZE);
4897#endif
4898}
4899
4900int
4901qla24xx_nvram_config(scsi_qla_host_t *vha)
4902{
4903 int rval;
4904 struct init_cb_24xx *icb;
4905 struct nvram_24xx *nv;
4906 uint32_t *dptr;
4907 uint8_t *dptr1, *dptr2;
4908 uint32_t chksum;
4909 uint16_t cnt;
4910 struct qla_hw_data *ha = vha->hw;
4911
4912 rval = QLA_SUCCESS;
4913 icb = (struct init_cb_24xx *)ha->init_cb;
4914 nv = ha->nvram;
4915
4916
4917 if (ha->port_no == 0) {
4918 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
4919 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
4920 } else {
4921 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
4922 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
4923 }
4924
4925 ha->nvram_size = sizeof(struct nvram_24xx);
4926 ha->vpd_size = FA_NVRAM_VPD_SIZE;
4927
4928
4929 ha->vpd = ha->nvram + VPD_OFFSET;
4930 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
4931 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
4932
4933
4934 dptr = (uint32_t *)nv;
4935 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
4936 ha->nvram_size);
4937 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
4938 chksum += le32_to_cpu(*dptr++);
4939
4940 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
4941 "Contents of NVRAM\n");
4942 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
4943 (uint8_t *)nv, ha->nvram_size);
4944
4945
4946 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
4947 || nv->id[3] != ' ' ||
4948 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
4949
4950 ql_log(ql_log_warn, vha, 0x006b,
4951 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
4952 "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
4953 ql_log(ql_log_warn, vha, 0x006c,
4954 "Falling back to functioning (yet invalid -- WWPN) "
4955 "defaults.\n");
4956
4957
4958
4959
4960 memset(nv, 0, ha->nvram_size);
4961 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
4962 nv->version = __constant_cpu_to_le16(ICB_VERSION);
4963 nv->frame_payload_size = __constant_cpu_to_le16(2048);
4964 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
4965 nv->exchange_count = __constant_cpu_to_le16(0);
4966 nv->hard_address = __constant_cpu_to_le16(124);
4967 nv->port_name[0] = 0x21;
4968 nv->port_name[1] = 0x00 + ha->port_no + 1;
4969 nv->port_name[2] = 0x00;
4970 nv->port_name[3] = 0xe0;
4971 nv->port_name[4] = 0x8b;
4972 nv->port_name[5] = 0x1c;
4973 nv->port_name[6] = 0x55;
4974 nv->port_name[7] = 0x86;
4975 nv->node_name[0] = 0x20;
4976 nv->node_name[1] = 0x00;
4977 nv->node_name[2] = 0x00;
4978 nv->node_name[3] = 0xe0;
4979 nv->node_name[4] = 0x8b;
4980 nv->node_name[5] = 0x1c;
4981 nv->node_name[6] = 0x55;
4982 nv->node_name[7] = 0x86;
4983 qla24xx_nvram_wwn_from_ofw(vha, nv);
4984 nv->login_retry_count = __constant_cpu_to_le16(8);
4985 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
4986 nv->login_timeout = __constant_cpu_to_le16(0);
4987 nv->firmware_options_1 =
4988 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
4989 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
4990 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
4991 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
4992 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
4993 nv->efi_parameters = __constant_cpu_to_le32(0);
4994 nv->reset_delay = 5;
4995 nv->max_luns_per_target = __constant_cpu_to_le16(128);
4996 nv->port_down_retry_count = __constant_cpu_to_le16(30);
4997 nv->link_down_timeout = __constant_cpu_to_le16(30);
4998
4999 rval = 1;
5000 }
5001
5002 if (!qla_ini_mode_enabled(vha)) {
5003
5004 nv->firmware_options_1 &= __constant_cpu_to_le32(~BIT_13);
5005
5006 nv->host_p &= __constant_cpu_to_le32(~BIT_10);
5007 }
5008
5009 qlt_24xx_config_nvram_stage1(vha, nv);
5010
5011
5012 memset(icb, 0, ha->init_cb_size);
5013
5014
5015 dptr1 = (uint8_t *)icb;
5016 dptr2 = (uint8_t *)&nv->version;
5017 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
5018 while (cnt--)
5019 *dptr1++ = *dptr2++;
5020
5021 icb->login_retry_count = nv->login_retry_count;
5022 icb->link_down_on_nos = nv->link_down_on_nos;
5023
5024
5025 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
5026 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
5027 cnt = (uint8_t *)&icb->reserved_3 -
5028 (uint8_t *)&icb->interrupt_delay_timer;
5029 while (cnt--)
5030 *dptr1++ = *dptr2++;
5031
5032
5033
5034
5035 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
5036 "QLA2462");
5037
5038 qlt_24xx_config_nvram_stage2(vha, icb);
5039
5040 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
5041
5042 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
5043 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
5044 }
5045
5046
5047 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
5048
5049
5050
5051
5052 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
5053 icb->node_name[0] &= 0xF0;
5054 }
5055
5056
5057 ha->flags.disable_risc_code_load = 0;
5058 ha->flags.enable_lip_reset = 0;
5059 ha->flags.enable_lip_full_login =
5060 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
5061 ha->flags.enable_target_reset =
5062 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
5063 ha->flags.enable_led_scheme = 0;
5064 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
5065
5066 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
5067 (BIT_6 | BIT_5 | BIT_4)) >> 4;
5068
5069 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
5070 sizeof(ha->fw_seriallink_options24));
5071
5072
5073 ha->serial0 = icb->port_name[5];
5074 ha->serial1 = icb->port_name[6];
5075 ha->serial2 = icb->port_name[7];
5076 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
5077 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
5078
5079 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5080
5081 ha->retry_count = le16_to_cpu(nv->login_retry_count);
5082
5083
5084 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
5085 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
5086 if (le16_to_cpu(nv->login_timeout) < 4)
5087 nv->login_timeout = __constant_cpu_to_le16(4);
5088 ha->login_timeout = le16_to_cpu(nv->login_timeout);
5089 icb->login_timeout = nv->login_timeout;
5090
5091
5092 ha->r_a_tov = 100;
5093
5094 ha->loop_reset_delay = nv->reset_delay;
5095
5096
5097
5098
5099
5100
5101
5102
5103
5104
5105
5106 if (le16_to_cpu(nv->link_down_timeout) == 0) {
5107 ha->loop_down_abort_time =
5108 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
5109 } else {
5110 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
5111 ha->loop_down_abort_time =
5112 (LOOP_DOWN_TIME - ha->link_down_timeout);
5113 }
5114
5115
5116 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
5117 if (qlport_down_retry)
5118 ha->port_down_retry_count = qlport_down_retry;
5119
5120
5121 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
5122 if (ha->port_down_retry_count ==
5123 le16_to_cpu(nv->port_down_retry_count) &&
5124 ha->port_down_retry_count > 3)
5125 ha->login_retry_count = ha->port_down_retry_count;
5126 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
5127 ha->login_retry_count = ha->port_down_retry_count;
5128 if (ql2xloginretrycount)
5129 ha->login_retry_count = ql2xloginretrycount;
5130
5131
5132 if (!vha->flags.init_done) {
5133 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
5134 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
5135 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
5136 le16_to_cpu(icb->interrupt_delay_timer): 2;
5137 }
5138 icb->firmware_options_2 &= __constant_cpu_to_le32(
5139 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
5140 vha->flags.process_response_queue = 0;
5141 if (ha->zio_mode != QLA_ZIO_DISABLED) {
5142 ha->zio_mode = QLA_ZIO_MODE_6;
5143
5144 ql_log(ql_log_info, vha, 0x006f,
5145 "ZIO mode %d enabled; timer delay (%d us).\n",
5146 ha->zio_mode, ha->zio_timer * 100);
5147
5148 icb->firmware_options_2 |= cpu_to_le32(
5149 (uint32_t)ha->zio_mode);
5150 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
5151 vha->flags.process_response_queue = 1;
5152 }
5153
5154 if (rval) {
5155 ql_log(ql_log_warn, vha, 0x0070,
5156 "NVRAM configuration failed.\n");
5157 }
5158 return (rval);
5159}
5160
5161static int
5162qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
5163 uint32_t faddr)
5164{
5165 int rval = QLA_SUCCESS;
5166 int segments, fragment;
5167 uint32_t *dcode, dlen;
5168 uint32_t risc_addr;
5169 uint32_t risc_size;
5170 uint32_t i;
5171 struct qla_hw_data *ha = vha->hw;
5172 struct req_que *req = ha->req_q_map[0];
5173
5174 ql_dbg(ql_dbg_init, vha, 0x008b,
5175 "FW: Loading firmware from flash (%x).\n", faddr);
5176
5177 rval = QLA_SUCCESS;
5178
5179 segments = FA_RISC_CODE_SEGMENTS;
5180 dcode = (uint32_t *)req->ring;
5181 *srisc_addr = 0;
5182
5183
5184 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
5185 for (i = 0; i < 4; i++)
5186 dcode[i] = be32_to_cpu(dcode[i]);
5187 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5188 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5189 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5190 dcode[3] == 0)) {
5191 ql_log(ql_log_fatal, vha, 0x008c,
5192 "Unable to verify the integrity of flash firmware "
5193 "image.\n");
5194 ql_log(ql_log_fatal, vha, 0x008d,
5195 "Firmware data: %08x %08x %08x %08x.\n",
5196 dcode[0], dcode[1], dcode[2], dcode[3]);
5197
5198 return QLA_FUNCTION_FAILED;
5199 }
5200
5201 while (segments && rval == QLA_SUCCESS) {
5202
5203 qla24xx_read_flash_data(vha, dcode, faddr, 4);
5204
5205 risc_addr = be32_to_cpu(dcode[2]);
5206 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5207 risc_size = be32_to_cpu(dcode[3]);
5208
5209 fragment = 0;
5210 while (risc_size > 0 && rval == QLA_SUCCESS) {
5211 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5212 if (dlen > risc_size)
5213 dlen = risc_size;
5214
5215 ql_dbg(ql_dbg_init, vha, 0x008e,
5216 "Loading risc segment@ risc addr %x "
5217 "number of dwords 0x%x offset 0x%x.\n",
5218 risc_addr, dlen, faddr);
5219
5220 qla24xx_read_flash_data(vha, dcode, faddr, dlen);
5221 for (i = 0; i < dlen; i++)
5222 dcode[i] = swab32(dcode[i]);
5223
5224 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5225 dlen);
5226 if (rval) {
5227 ql_log(ql_log_fatal, vha, 0x008f,
5228 "Failed to load segment %d of firmware.\n",
5229 fragment);
5230 break;
5231 }
5232
5233 faddr += dlen;
5234 risc_addr += dlen;
5235 risc_size -= dlen;
5236 fragment++;
5237 }
5238
5239
5240 segments--;
5241 }
5242
5243 if (!IS_QLA27XX(ha))
5244 return rval;
5245
5246 if (ha->fw_dump_template)
5247 vfree(ha->fw_dump_template);
5248 ha->fw_dump_template = NULL;
5249 ha->fw_dump_template_len = 0;
5250
5251 ql_dbg(ql_dbg_init, vha, 0x0161,
5252 "Loading fwdump template from %x\n", faddr);
5253 qla24xx_read_flash_data(vha, dcode, faddr, 7);
5254 risc_size = be32_to_cpu(dcode[2]);
5255 ql_dbg(ql_dbg_init, vha, 0x0162,
5256 "-> array size %x dwords\n", risc_size);
5257 if (risc_size == 0 || risc_size == ~0)
5258 goto default_template;
5259
5260 dlen = (risc_size - 8) * sizeof(*dcode);
5261 ql_dbg(ql_dbg_init, vha, 0x0163,
5262 "-> template allocating %x bytes...\n", dlen);
5263 ha->fw_dump_template = vmalloc(dlen);
5264 if (!ha->fw_dump_template) {
5265 ql_log(ql_log_warn, vha, 0x0164,
5266 "Failed fwdump template allocate %x bytes.\n", risc_size);
5267 goto default_template;
5268 }
5269
5270 faddr += 7;
5271 risc_size -= 8;
5272 dcode = ha->fw_dump_template;
5273 qla24xx_read_flash_data(vha, dcode, faddr, risc_size);
5274 for (i = 0; i < risc_size; i++)
5275 dcode[i] = le32_to_cpu(dcode[i]);
5276
5277 if (!qla27xx_fwdt_template_valid(dcode)) {
5278 ql_log(ql_log_warn, vha, 0x0165,
5279 "Failed fwdump template validate\n");
5280 goto default_template;
5281 }
5282
5283 dlen = qla27xx_fwdt_template_size(dcode);
5284 ql_dbg(ql_dbg_init, vha, 0x0166,
5285 "-> template size %x bytes\n", dlen);
5286 if (dlen > risc_size * sizeof(*dcode)) {
5287 ql_log(ql_log_warn, vha, 0x0167,
5288 "Failed fwdump template exceeds array by %x bytes\n",
5289 (uint32_t)(dlen - risc_size * sizeof(*dcode)));
5290 goto default_template;
5291 }
5292 ha->fw_dump_template_len = dlen;
5293 return rval;
5294
5295default_template:
5296 ql_log(ql_log_warn, vha, 0x0168, "Using default fwdump template\n");
5297 if (ha->fw_dump_template)
5298 vfree(ha->fw_dump_template);
5299 ha->fw_dump_template = NULL;
5300 ha->fw_dump_template_len = 0;
5301
5302 dlen = qla27xx_fwdt_template_default_size();
5303 ql_dbg(ql_dbg_init, vha, 0x0169,
5304 "-> template allocating %x bytes...\n", dlen);
5305 ha->fw_dump_template = vmalloc(dlen);
5306 if (!ha->fw_dump_template) {
5307 ql_log(ql_log_warn, vha, 0x016a,
5308 "Failed fwdump template allocate %x bytes.\n", risc_size);
5309 goto failed_template;
5310 }
5311
5312 dcode = ha->fw_dump_template;
5313 risc_size = dlen / sizeof(*dcode);
5314 memcpy(dcode, qla27xx_fwdt_template_default(), dlen);
5315 for (i = 0; i < risc_size; i++)
5316 dcode[i] = be32_to_cpu(dcode[i]);
5317
5318 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
5319 ql_log(ql_log_warn, vha, 0x016b,
5320 "Failed fwdump template validate\n");
5321 goto failed_template;
5322 }
5323
5324 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
5325 ql_dbg(ql_dbg_init, vha, 0x016c,
5326 "-> template size %x bytes\n", dlen);
5327 ha->fw_dump_template_len = dlen;
5328 return rval;
5329
5330failed_template:
5331 ql_log(ql_log_warn, vha, 0x016d, "Failed default fwdump template\n");
5332 if (ha->fw_dump_template)
5333 vfree(ha->fw_dump_template);
5334 ha->fw_dump_template = NULL;
5335 ha->fw_dump_template_len = 0;
5336 return rval;
5337}
5338
5339#define QLA_FW_URL "http://ldriver.qlogic.com/firmware/"
5340
5341int
5342qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5343{
5344 int rval;
5345 int i, fragment;
5346 uint16_t *wcode, *fwcode;
5347 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
5348 struct fw_blob *blob;
5349 struct qla_hw_data *ha = vha->hw;
5350 struct req_que *req = ha->req_q_map[0];
5351
5352
5353 blob = qla2x00_request_firmware(vha);
5354 if (!blob) {
5355 ql_log(ql_log_info, vha, 0x0083,
5356 "Fimware image unavailable.\n");
5357 ql_log(ql_log_info, vha, 0x0084,
5358 "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
5359 return QLA_FUNCTION_FAILED;
5360 }
5361
5362 rval = QLA_SUCCESS;
5363
5364 wcode = (uint16_t *)req->ring;
5365 *srisc_addr = 0;
5366 fwcode = (uint16_t *)blob->fw->data;
5367 fwclen = 0;
5368
5369
5370 if (blob->fw->size < 8 * sizeof(uint16_t)) {
5371 ql_log(ql_log_fatal, vha, 0x0085,
5372 "Unable to verify integrity of firmware image (%Zd).\n",
5373 blob->fw->size);
5374 goto fail_fw_integrity;
5375 }
5376 for (i = 0; i < 4; i++)
5377 wcode[i] = be16_to_cpu(fwcode[i + 4]);
5378 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
5379 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
5380 wcode[2] == 0 && wcode[3] == 0)) {
5381 ql_log(ql_log_fatal, vha, 0x0086,
5382 "Unable to verify integrity of firmware image.\n");
5383 ql_log(ql_log_fatal, vha, 0x0087,
5384 "Firmware data: %04x %04x %04x %04x.\n",
5385 wcode[0], wcode[1], wcode[2], wcode[3]);
5386 goto fail_fw_integrity;
5387 }
5388
5389 seg = blob->segs;
5390 while (*seg && rval == QLA_SUCCESS) {
5391 risc_addr = *seg;
5392 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
5393 risc_size = be16_to_cpu(fwcode[3]);
5394
5395
5396 fwclen += risc_size * sizeof(uint16_t);
5397 if (blob->fw->size < fwclen) {
5398 ql_log(ql_log_fatal, vha, 0x0088,
5399 "Unable to verify integrity of firmware image "
5400 "(%Zd).\n", blob->fw->size);
5401 goto fail_fw_integrity;
5402 }
5403
5404 fragment = 0;
5405 while (risc_size > 0 && rval == QLA_SUCCESS) {
5406 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
5407 if (wlen > risc_size)
5408 wlen = risc_size;
5409 ql_dbg(ql_dbg_init, vha, 0x0089,
5410 "Loading risc segment@ risc addr %x number of "
5411 "words 0x%x.\n", risc_addr, wlen);
5412
5413 for (i = 0; i < wlen; i++)
5414 wcode[i] = swab16(fwcode[i]);
5415
5416 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5417 wlen);
5418 if (rval) {
5419 ql_log(ql_log_fatal, vha, 0x008a,
5420 "Failed to load segment %d of firmware.\n",
5421 fragment);
5422 break;
5423 }
5424
5425 fwcode += wlen;
5426 risc_addr += wlen;
5427 risc_size -= wlen;
5428 fragment++;
5429 }
5430
5431
5432 seg++;
5433 }
5434 return rval;
5435
5436fail_fw_integrity:
5437 return QLA_FUNCTION_FAILED;
5438}
5439
5440static int
5441qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5442{
5443 int rval;
5444 int segments, fragment;
5445 uint32_t *dcode, dlen;
5446 uint32_t risc_addr;
5447 uint32_t risc_size;
5448 uint32_t i;
5449 struct fw_blob *blob;
5450 const uint32_t *fwcode;
5451 uint32_t fwclen;
5452 struct qla_hw_data *ha = vha->hw;
5453 struct req_que *req = ha->req_q_map[0];
5454
5455
5456 blob = qla2x00_request_firmware(vha);
5457 if (!blob) {
5458 ql_log(ql_log_warn, vha, 0x0090,
5459 "Fimware image unavailable.\n");
5460 ql_log(ql_log_warn, vha, 0x0091,
5461 "Firmware images can be retrieved from: "
5462 QLA_FW_URL ".\n");
5463
5464 return QLA_FUNCTION_FAILED;
5465 }
5466
5467 ql_dbg(ql_dbg_init, vha, 0x0092,
5468 "FW: Loading via request-firmware.\n");
5469
5470 rval = QLA_SUCCESS;
5471
5472 segments = FA_RISC_CODE_SEGMENTS;
5473 dcode = (uint32_t *)req->ring;
5474 *srisc_addr = 0;
5475 fwcode = (uint32_t *)blob->fw->data;
5476 fwclen = 0;
5477
5478
5479 if (blob->fw->size < 8 * sizeof(uint32_t)) {
5480 ql_log(ql_log_fatal, vha, 0x0093,
5481 "Unable to verify integrity of firmware image (%Zd).\n",
5482 blob->fw->size);
5483 return QLA_FUNCTION_FAILED;
5484 }
5485 for (i = 0; i < 4; i++)
5486 dcode[i] = be32_to_cpu(fwcode[i + 4]);
5487 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5488 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5489 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5490 dcode[3] == 0)) {
5491 ql_log(ql_log_fatal, vha, 0x0094,
5492 "Unable to verify integrity of firmware image (%Zd).\n",
5493 blob->fw->size);
5494 ql_log(ql_log_fatal, vha, 0x0095,
5495 "Firmware data: %08x %08x %08x %08x.\n",
5496 dcode[0], dcode[1], dcode[2], dcode[3]);
5497 return QLA_FUNCTION_FAILED;
5498 }
5499
5500 while (segments && rval == QLA_SUCCESS) {
5501 risc_addr = be32_to_cpu(fwcode[2]);
5502 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5503 risc_size = be32_to_cpu(fwcode[3]);
5504
5505
5506 fwclen += risc_size * sizeof(uint32_t);
5507 if (blob->fw->size < fwclen) {
5508 ql_log(ql_log_fatal, vha, 0x0096,
5509 "Unable to verify integrity of firmware image "
5510 "(%Zd).\n", blob->fw->size);
5511 return QLA_FUNCTION_FAILED;
5512 }
5513
5514 fragment = 0;
5515 while (risc_size > 0 && rval == QLA_SUCCESS) {
5516 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5517 if (dlen > risc_size)
5518 dlen = risc_size;
5519
5520 ql_dbg(ql_dbg_init, vha, 0x0097,
5521 "Loading risc segment@ risc addr %x "
5522 "number of dwords 0x%x.\n", risc_addr, dlen);
5523
5524 for (i = 0; i < dlen; i++)
5525 dcode[i] = swab32(fwcode[i]);
5526
5527 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5528 dlen);
5529 if (rval) {
5530 ql_log(ql_log_fatal, vha, 0x0098,
5531 "Failed to load segment %d of firmware.\n",
5532 fragment);
5533 break;
5534 }
5535
5536 fwcode += dlen;
5537 risc_addr += dlen;
5538 risc_size -= dlen;
5539 fragment++;
5540 }
5541
5542
5543 segments--;
5544 }
5545
5546 if (!IS_QLA27XX(ha))
5547 return rval;
5548
5549 if (ha->fw_dump_template)
5550 vfree(ha->fw_dump_template);
5551 ha->fw_dump_template = NULL;
5552 ha->fw_dump_template_len = 0;
5553
5554 ql_dbg(ql_dbg_init, vha, 0x171,
5555 "Loading fwdump template from %x\n",
5556 (uint32_t)((void *)fwcode - (void *)blob->fw->data));
5557 risc_size = be32_to_cpu(fwcode[2]);
5558 ql_dbg(ql_dbg_init, vha, 0x172,
5559 "-> array size %x dwords\n", risc_size);
5560 if (risc_size == 0 || risc_size == ~0)
5561 goto default_template;
5562
5563 dlen = (risc_size - 8) * sizeof(*fwcode);
5564 ql_dbg(ql_dbg_init, vha, 0x0173,
5565 "-> template allocating %x bytes...\n", dlen);
5566 ha->fw_dump_template = vmalloc(dlen);
5567 if (!ha->fw_dump_template) {
5568 ql_log(ql_log_warn, vha, 0x0174,
5569 "Failed fwdump template allocate %x bytes.\n", risc_size);
5570 goto default_template;
5571 }
5572
5573 fwcode += 7;
5574 risc_size -= 8;
5575 dcode = ha->fw_dump_template;
5576 for (i = 0; i < risc_size; i++)
5577 dcode[i] = le32_to_cpu(fwcode[i]);
5578
5579 if (!qla27xx_fwdt_template_valid(dcode)) {
5580 ql_log(ql_log_warn, vha, 0x0175,
5581 "Failed fwdump template validate\n");
5582 goto default_template;
5583 }
5584
5585 dlen = qla27xx_fwdt_template_size(dcode);
5586 ql_dbg(ql_dbg_init, vha, 0x0176,
5587 "-> template size %x bytes\n", dlen);
5588 if (dlen > risc_size * sizeof(*fwcode)) {
5589 ql_log(ql_log_warn, vha, 0x0177,
5590 "Failed fwdump template exceeds array by %x bytes\n",
5591 (uint32_t)(dlen - risc_size * sizeof(*fwcode)));
5592 goto default_template;
5593 }
5594 ha->fw_dump_template_len = dlen;
5595 return rval;
5596
5597default_template:
5598 ql_log(ql_log_warn, vha, 0x0178, "Using default fwdump template\n");
5599 if (ha->fw_dump_template)
5600 vfree(ha->fw_dump_template);
5601 ha->fw_dump_template = NULL;
5602 ha->fw_dump_template_len = 0;
5603
5604 dlen = qla27xx_fwdt_template_default_size();
5605 ql_dbg(ql_dbg_init, vha, 0x0179,
5606 "-> template allocating %x bytes...\n", dlen);
5607 ha->fw_dump_template = vmalloc(dlen);
5608 if (!ha->fw_dump_template) {
5609 ql_log(ql_log_warn, vha, 0x017a,
5610 "Failed fwdump template allocate %x bytes.\n", risc_size);
5611 goto failed_template;
5612 }
5613
5614 dcode = ha->fw_dump_template;
5615 risc_size = dlen / sizeof(*fwcode);
5616 fwcode = qla27xx_fwdt_template_default();
5617 for (i = 0; i < risc_size; i++)
5618 dcode[i] = be32_to_cpu(fwcode[i]);
5619
5620 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
5621 ql_log(ql_log_warn, vha, 0x017b,
5622 "Failed fwdump template validate\n");
5623 goto failed_template;
5624 }
5625
5626 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
5627 ql_dbg(ql_dbg_init, vha, 0x017c,
5628 "-> template size %x bytes\n", dlen);
5629 ha->fw_dump_template_len = dlen;
5630 return rval;
5631
5632failed_template:
5633 ql_log(ql_log_warn, vha, 0x017d, "Failed default fwdump template\n");
5634 if (ha->fw_dump_template)
5635 vfree(ha->fw_dump_template);
5636 ha->fw_dump_template = NULL;
5637 ha->fw_dump_template_len = 0;
5638 return rval;
5639}
5640
5641int
5642qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5643{
5644 int rval;
5645
5646 if (ql2xfwloadbin == 1)
5647 return qla81xx_load_risc(vha, srisc_addr);
5648
5649
5650
5651
5652
5653
5654 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5655 if (rval == QLA_SUCCESS)
5656 return rval;
5657
5658 return qla24xx_load_risc_flash(vha, srisc_addr,
5659 vha->hw->flt_region_fw);
5660}
5661
5662int
5663qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5664{
5665 int rval;
5666 struct qla_hw_data *ha = vha->hw;
5667
5668 if (ql2xfwloadbin == 2)
5669 goto try_blob_fw;
5670
5671
5672
5673
5674
5675
5676
5677 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
5678 if (rval == QLA_SUCCESS)
5679 return rval;
5680
5681try_blob_fw:
5682 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5683 if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
5684 return rval;
5685
5686 ql_log(ql_log_info, vha, 0x0099,
5687 "Attempting to fallback to golden firmware.\n");
5688 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
5689 if (rval != QLA_SUCCESS)
5690 return rval;
5691
5692 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
5693 ha->flags.running_gold_fw = 1;
5694 return rval;
5695}
5696
5697void
5698qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
5699{
5700 int ret, retries;
5701 struct qla_hw_data *ha = vha->hw;
5702
5703 if (ha->flags.pci_channel_io_perm_failure)
5704 return;
5705 if (!IS_FWI2_CAPABLE(ha))
5706 return;
5707 if (!ha->fw_major_version)
5708 return;
5709
5710 ret = qla2x00_stop_firmware(vha);
5711 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
5712 ret != QLA_INVALID_COMMAND && retries ; retries--) {
5713 ha->isp_ops->reset_chip(vha);
5714 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
5715 continue;
5716 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
5717 continue;
5718 ql_log(ql_log_info, vha, 0x8015,
5719 "Attempting retry of stop-firmware command.\n");
5720 ret = qla2x00_stop_firmware(vha);
5721 }
5722}
5723
5724int
5725qla24xx_configure_vhba(scsi_qla_host_t *vha)
5726{
5727 int rval = QLA_SUCCESS;
5728 int rval2;
5729 uint16_t mb[MAILBOX_REGISTER_COUNT];
5730 struct qla_hw_data *ha = vha->hw;
5731 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
5732 struct req_que *req;
5733 struct rsp_que *rsp;
5734
5735 if (!vha->vp_idx)
5736 return -EINVAL;
5737
5738 rval = qla2x00_fw_ready(base_vha);
5739 if (ha->flags.cpu_affinity_enabled)
5740 req = ha->req_q_map[0];
5741 else
5742 req = vha->req;
5743 rsp = req->rsp;
5744
5745 if (rval == QLA_SUCCESS) {
5746 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5747 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
5748 }
5749
5750 vha->flags.management_server_logged_in = 0;
5751
5752
5753 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
5754 BIT_1);
5755 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
5756 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
5757 ql_dbg(ql_dbg_init, vha, 0x0120,
5758 "Failed SNS login: loop_id=%x, rval2=%d\n",
5759 NPH_SNS, rval2);
5760 else
5761 ql_dbg(ql_dbg_init, vha, 0x0103,
5762 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
5763 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
5764 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
5765 return (QLA_FUNCTION_FAILED);
5766 }
5767
5768 atomic_set(&vha->loop_down_timer, 0);
5769 atomic_set(&vha->loop_state, LOOP_UP);
5770 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5771 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
5772 rval = qla2x00_loop_resync(base_vha);
5773
5774 return rval;
5775}
5776
5777
5778
5779static LIST_HEAD(qla_cs84xx_list);
5780static DEFINE_MUTEX(qla_cs84xx_mutex);
5781
5782static struct qla_chip_state_84xx *
5783qla84xx_get_chip(struct scsi_qla_host *vha)
5784{
5785 struct qla_chip_state_84xx *cs84xx;
5786 struct qla_hw_data *ha = vha->hw;
5787
5788 mutex_lock(&qla_cs84xx_mutex);
5789
5790
5791 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
5792 if (cs84xx->bus == ha->pdev->bus) {
5793 kref_get(&cs84xx->kref);
5794 goto done;
5795 }
5796 }
5797
5798 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
5799 if (!cs84xx)
5800 goto done;
5801
5802 kref_init(&cs84xx->kref);
5803 spin_lock_init(&cs84xx->access_lock);
5804 mutex_init(&cs84xx->fw_update_mutex);
5805 cs84xx->bus = ha->pdev->bus;
5806
5807 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
5808done:
5809 mutex_unlock(&qla_cs84xx_mutex);
5810 return cs84xx;
5811}
5812
5813static void
5814__qla84xx_chip_release(struct kref *kref)
5815{
5816 struct qla_chip_state_84xx *cs84xx =
5817 container_of(kref, struct qla_chip_state_84xx, kref);
5818
5819 mutex_lock(&qla_cs84xx_mutex);
5820 list_del(&cs84xx->list);
5821 mutex_unlock(&qla_cs84xx_mutex);
5822 kfree(cs84xx);
5823}
5824
5825void
5826qla84xx_put_chip(struct scsi_qla_host *vha)
5827{
5828 struct qla_hw_data *ha = vha->hw;
5829 if (ha->cs84xx)
5830 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
5831}
5832
5833static int
5834qla84xx_init_chip(scsi_qla_host_t *vha)
5835{
5836 int rval;
5837 uint16_t status[2];
5838 struct qla_hw_data *ha = vha->hw;
5839
5840 mutex_lock(&ha->cs84xx->fw_update_mutex);
5841
5842 rval = qla84xx_verify_chip(vha, status);
5843
5844 mutex_unlock(&ha->cs84xx->fw_update_mutex);
5845
5846 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
5847 QLA_SUCCESS;
5848}
5849
5850
5851
5852int
5853qla81xx_nvram_config(scsi_qla_host_t *vha)
5854{
5855 int rval;
5856 struct init_cb_81xx *icb;
5857 struct nvram_81xx *nv;
5858 uint32_t *dptr;
5859 uint8_t *dptr1, *dptr2;
5860 uint32_t chksum;
5861 uint16_t cnt;
5862 struct qla_hw_data *ha = vha->hw;
5863
5864 rval = QLA_SUCCESS;
5865 icb = (struct init_cb_81xx *)ha->init_cb;
5866 nv = ha->nvram;
5867
5868
5869 ha->nvram_size = sizeof(struct nvram_81xx);
5870 ha->vpd_size = FA_NVRAM_VPD_SIZE;
5871 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha))
5872 ha->vpd_size = FA_VPD_SIZE_82XX;
5873
5874
5875 ha->vpd = ha->nvram + VPD_OFFSET;
5876 ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
5877 ha->vpd_size);
5878
5879
5880 ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
5881 ha->nvram_size);
5882 dptr = (uint32_t *)nv;
5883 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
5884 chksum += le32_to_cpu(*dptr++);
5885
5886 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
5887 "Contents of NVRAM:\n");
5888 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
5889 (uint8_t *)nv, ha->nvram_size);
5890
5891
5892 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
5893 || nv->id[3] != ' ' ||
5894 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
5895
5896 ql_log(ql_log_info, vha, 0x0073,
5897 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
5898 "version=0x%x.\n", chksum, nv->id[0],
5899 le16_to_cpu(nv->nvram_version));
5900 ql_log(ql_log_info, vha, 0x0074,
5901 "Falling back to functioning (yet invalid -- WWPN) "
5902 "defaults.\n");
5903
5904
5905
5906
5907 memset(nv, 0, ha->nvram_size);
5908 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
5909 nv->version = __constant_cpu_to_le16(ICB_VERSION);
5910 nv->frame_payload_size = __constant_cpu_to_le16(2048);
5911 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5912 nv->exchange_count = __constant_cpu_to_le16(0);
5913 nv->port_name[0] = 0x21;
5914 nv->port_name[1] = 0x00 + ha->port_no + 1;
5915 nv->port_name[2] = 0x00;
5916 nv->port_name[3] = 0xe0;
5917 nv->port_name[4] = 0x8b;
5918 nv->port_name[5] = 0x1c;
5919 nv->port_name[6] = 0x55;
5920 nv->port_name[7] = 0x86;
5921 nv->node_name[0] = 0x20;
5922 nv->node_name[1] = 0x00;
5923 nv->node_name[2] = 0x00;
5924 nv->node_name[3] = 0xe0;
5925 nv->node_name[4] = 0x8b;
5926 nv->node_name[5] = 0x1c;
5927 nv->node_name[6] = 0x55;
5928 nv->node_name[7] = 0x86;
5929 nv->login_retry_count = __constant_cpu_to_le16(8);
5930 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
5931 nv->login_timeout = __constant_cpu_to_le16(0);
5932 nv->firmware_options_1 =
5933 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
5934 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
5935 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
5936 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
5937 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
5938 nv->efi_parameters = __constant_cpu_to_le32(0);
5939 nv->reset_delay = 5;
5940 nv->max_luns_per_target = __constant_cpu_to_le16(128);
5941 nv->port_down_retry_count = __constant_cpu_to_le16(30);
5942 nv->link_down_timeout = __constant_cpu_to_le16(180);
5943 nv->enode_mac[0] = 0x00;
5944 nv->enode_mac[1] = 0xC0;
5945 nv->enode_mac[2] = 0xDD;
5946 nv->enode_mac[3] = 0x04;
5947 nv->enode_mac[4] = 0x05;
5948 nv->enode_mac[5] = 0x06 + ha->port_no + 1;
5949
5950 rval = 1;
5951 }
5952
5953 if (IS_T10_PI_CAPABLE(ha))
5954 nv->frame_payload_size &= ~7;
5955
5956 qlt_81xx_config_nvram_stage1(vha, nv);
5957
5958
5959 memset(icb, 0, ha->init_cb_size);
5960
5961
5962 dptr1 = (uint8_t *)icb;
5963 dptr2 = (uint8_t *)&nv->version;
5964 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
5965 while (cnt--)
5966 *dptr1++ = *dptr2++;
5967
5968 icb->login_retry_count = nv->login_retry_count;
5969
5970
5971 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
5972 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
5973 cnt = (uint8_t *)&icb->reserved_5 -
5974 (uint8_t *)&icb->interrupt_delay_timer;
5975 while (cnt--)
5976 *dptr1++ = *dptr2++;
5977
5978 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
5979
5980 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
5981 icb->enode_mac[0] = 0x00;
5982 icb->enode_mac[1] = 0xC0;
5983 icb->enode_mac[2] = 0xDD;
5984 icb->enode_mac[3] = 0x04;
5985 icb->enode_mac[4] = 0x05;
5986 icb->enode_mac[5] = 0x06 + ha->port_no + 1;
5987 }
5988
5989
5990 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
5991
5992
5993
5994
5995 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
5996 "QLE8XXX");
5997
5998 qlt_81xx_config_nvram_stage2(vha, icb);
5999
6000
6001 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
6002 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
6003 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
6004 }
6005
6006
6007 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
6008
6009
6010
6011
6012 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
6013 icb->node_name[0] &= 0xF0;
6014 }
6015
6016
6017 ha->flags.disable_risc_code_load = 0;
6018 ha->flags.enable_lip_reset = 0;
6019 ha->flags.enable_lip_full_login =
6020 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
6021 ha->flags.enable_target_reset =
6022 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
6023 ha->flags.enable_led_scheme = 0;
6024 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
6025
6026 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
6027 (BIT_6 | BIT_5 | BIT_4)) >> 4;
6028
6029
6030 ha->serial0 = icb->port_name[5];
6031 ha->serial1 = icb->port_name[6];
6032 ha->serial2 = icb->port_name[7];
6033 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
6034 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
6035
6036 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
6037
6038 ha->retry_count = le16_to_cpu(nv->login_retry_count);
6039
6040
6041 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
6042 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
6043 if (le16_to_cpu(nv->login_timeout) < 4)
6044 nv->login_timeout = __constant_cpu_to_le16(4);
6045 ha->login_timeout = le16_to_cpu(nv->login_timeout);
6046 icb->login_timeout = nv->login_timeout;
6047
6048
6049 ha->r_a_tov = 100;
6050
6051 ha->loop_reset_delay = nv->reset_delay;
6052
6053
6054
6055
6056
6057
6058
6059
6060
6061
6062
6063 if (le16_to_cpu(nv->link_down_timeout) == 0) {
6064 ha->loop_down_abort_time =
6065 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
6066 } else {
6067 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
6068 ha->loop_down_abort_time =
6069 (LOOP_DOWN_TIME - ha->link_down_timeout);
6070 }
6071
6072
6073 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
6074 if (qlport_down_retry)
6075 ha->port_down_retry_count = qlport_down_retry;
6076
6077
6078 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
6079 if (ha->port_down_retry_count ==
6080 le16_to_cpu(nv->port_down_retry_count) &&
6081 ha->port_down_retry_count > 3)
6082 ha->login_retry_count = ha->port_down_retry_count;
6083 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
6084 ha->login_retry_count = ha->port_down_retry_count;
6085 if (ql2xloginretrycount)
6086 ha->login_retry_count = ql2xloginretrycount;
6087
6088
6089 if (!vha->hw->flags.msix_enabled && (IS_QLA83XX(ha) || IS_QLA27XX(ha)))
6090 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_22);
6091
6092
6093 if (!vha->flags.init_done) {
6094 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
6095 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
6096 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
6097 le16_to_cpu(icb->interrupt_delay_timer): 2;
6098 }
6099 icb->firmware_options_2 &= __constant_cpu_to_le32(
6100 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
6101 vha->flags.process_response_queue = 0;
6102 if (ha->zio_mode != QLA_ZIO_DISABLED) {
6103 ha->zio_mode = QLA_ZIO_MODE_6;
6104
6105 ql_log(ql_log_info, vha, 0x0075,
6106 "ZIO mode %d enabled; timer delay (%d us).\n",
6107 ha->zio_mode,
6108 ha->zio_timer * 100);
6109
6110 icb->firmware_options_2 |= cpu_to_le32(
6111 (uint32_t)ha->zio_mode);
6112 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
6113 vha->flags.process_response_queue = 1;
6114 }
6115
6116 if (rval) {
6117 ql_log(ql_log_warn, vha, 0x0076,
6118 "NVRAM configuration failed.\n");
6119 }
6120 return (rval);
6121}
6122
6123int
6124qla82xx_restart_isp(scsi_qla_host_t *vha)
6125{
6126 int status, rval;
6127 struct qla_hw_data *ha = vha->hw;
6128 struct req_que *req = ha->req_q_map[0];
6129 struct rsp_que *rsp = ha->rsp_q_map[0];
6130 struct scsi_qla_host *vp;
6131 unsigned long flags;
6132
6133 status = qla2x00_init_rings(vha);
6134 if (!status) {
6135 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
6136 ha->flags.chip_reset_done = 1;
6137
6138 status = qla2x00_fw_ready(vha);
6139 if (!status) {
6140
6141 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
6142 vha->flags.online = 1;
6143 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
6144 }
6145
6146
6147 if ((vha->device_flags & DFLG_NO_CABLE))
6148 status = 0;
6149 }
6150
6151 if (!status) {
6152 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
6153
6154 if (!atomic_read(&vha->loop_down_timer)) {
6155
6156
6157
6158
6159 vha->marker_needed = 1;
6160 }
6161
6162 ha->isp_ops->enable_intrs(ha);
6163
6164 ha->isp_abort_cnt = 0;
6165 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
6166
6167
6168 status = qla82xx_check_md_needed(vha);
6169
6170 if (ha->fce) {
6171 ha->flags.fce_enabled = 1;
6172 memset(ha->fce, 0,
6173 fce_calc_size(ha->fce_bufs));
6174 rval = qla2x00_enable_fce_trace(vha,
6175 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
6176 &ha->fce_bufs);
6177 if (rval) {
6178 ql_log(ql_log_warn, vha, 0x8001,
6179 "Unable to reinitialize FCE (%d).\n",
6180 rval);
6181 ha->flags.fce_enabled = 0;
6182 }
6183 }
6184
6185 if (ha->eft) {
6186 memset(ha->eft, 0, EFT_SIZE);
6187 rval = qla2x00_enable_eft_trace(vha,
6188 ha->eft_dma, EFT_NUM_BUFFERS);
6189 if (rval) {
6190 ql_log(ql_log_warn, vha, 0x8010,
6191 "Unable to reinitialize EFT (%d).\n",
6192 rval);
6193 }
6194 }
6195 }
6196
6197 if (!status) {
6198 ql_dbg(ql_dbg_taskm, vha, 0x8011,
6199 "qla82xx_restart_isp succeeded.\n");
6200
6201 spin_lock_irqsave(&ha->vport_slock, flags);
6202 list_for_each_entry(vp, &ha->vp_list, list) {
6203 if (vp->vp_idx) {
6204 atomic_inc(&vp->vref_count);
6205 spin_unlock_irqrestore(&ha->vport_slock, flags);
6206
6207 qla2x00_vp_abort_isp(vp);
6208
6209 spin_lock_irqsave(&ha->vport_slock, flags);
6210 atomic_dec(&vp->vref_count);
6211 }
6212 }
6213 spin_unlock_irqrestore(&ha->vport_slock, flags);
6214
6215 } else {
6216 ql_log(ql_log_warn, vha, 0x8016,
6217 "qla82xx_restart_isp **** FAILED ****.\n");
6218 }
6219
6220 return status;
6221}
6222
6223void
6224qla81xx_update_fw_options(scsi_qla_host_t *vha)
6225{
6226 struct qla_hw_data *ha = vha->hw;
6227
6228 if (!ql2xetsenable)
6229 return;
6230
6231
6232 memset(ha->fw_options, 0, sizeof(ha->fw_options));
6233 ha->fw_options[2] |= BIT_9;
6234 qla2x00_set_fw_options(vha, ha->fw_options);
6235}
6236
6237
6238
6239
6240
6241
6242
6243
6244
6245
6246
6247
6248
6249
6250
6251
6252
6253
6254
6255static int
6256qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
6257{
6258 int i, entries;
6259 uint8_t pid_match, wwn_match;
6260 int priority;
6261 uint32_t pid1, pid2;
6262 uint64_t wwn1, wwn2;
6263 struct qla_fcp_prio_entry *pri_entry;
6264 struct qla_hw_data *ha = vha->hw;
6265
6266 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
6267 return -1;
6268
6269 priority = -1;
6270 entries = ha->fcp_prio_cfg->num_entries;
6271 pri_entry = &ha->fcp_prio_cfg->entry[0];
6272
6273 for (i = 0; i < entries; i++) {
6274 pid_match = wwn_match = 0;
6275
6276 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
6277 pri_entry++;
6278 continue;
6279 }
6280
6281
6282 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
6283 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
6284 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
6285 if (pid1 == INVALID_PORT_ID)
6286 pid_match++;
6287 else if (pid1 == pid2)
6288 pid_match++;
6289 }
6290
6291
6292 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
6293 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
6294 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
6295 if (pid1 == INVALID_PORT_ID)
6296 pid_match++;
6297 else if (pid1 == pid2)
6298 pid_match++;
6299 }
6300
6301
6302 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
6303 wwn1 = wwn_to_u64(vha->port_name);
6304 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
6305 if (wwn2 == (uint64_t)-1)
6306 wwn_match++;
6307 else if (wwn1 == wwn2)
6308 wwn_match++;
6309 }
6310
6311
6312 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
6313 wwn1 = wwn_to_u64(fcport->port_name);
6314 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
6315 if (wwn2 == (uint64_t)-1)
6316 wwn_match++;
6317 else if (wwn1 == wwn2)
6318 wwn_match++;
6319 }
6320
6321 if (pid_match == 2 || wwn_match == 2) {
6322
6323 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
6324 priority = pri_entry->tag;
6325 break;
6326 }
6327
6328 pri_entry++;
6329 }
6330
6331 return priority;
6332}
6333
6334
6335
6336
6337
6338
6339
6340
6341
6342
6343
6344
6345
6346
6347
6348int
6349qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
6350{
6351 int ret;
6352 int priority;
6353 uint16_t mb[5];
6354
6355 if (fcport->port_type != FCT_TARGET ||
6356 fcport->loop_id == FC_NO_LOOP_ID)
6357 return QLA_FUNCTION_FAILED;
6358
6359 priority = qla24xx_get_fcp_prio(vha, fcport);
6360 if (priority < 0)
6361 return QLA_FUNCTION_FAILED;
6362
6363 if (IS_P3P_TYPE(vha->hw)) {
6364 fcport->fcp_prio = priority & 0xf;
6365 return QLA_SUCCESS;
6366 }
6367
6368 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
6369 if (ret == QLA_SUCCESS) {
6370 if (fcport->fcp_prio != priority)
6371 ql_dbg(ql_dbg_user, vha, 0x709e,
6372 "Updated FCP_CMND priority - value=%d loop_id=%d "
6373 "port_id=%02x%02x%02x.\n", priority,
6374 fcport->loop_id, fcport->d_id.b.domain,
6375 fcport->d_id.b.area, fcport->d_id.b.al_pa);
6376 fcport->fcp_prio = priority & 0xf;
6377 } else
6378 ql_dbg(ql_dbg_user, vha, 0x704f,
6379 "Unable to update FCP_CMND priority - ret=0x%x for "
6380 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
6381 fcport->d_id.b.domain, fcport->d_id.b.area,
6382 fcport->d_id.b.al_pa);
6383 return ret;
6384}
6385
6386
6387
6388
6389
6390
6391
6392
6393
6394
6395
6396
6397
6398
6399int
6400qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
6401{
6402 int ret;
6403 fc_port_t *fcport;
6404
6405 ret = QLA_FUNCTION_FAILED;
6406
6407 list_for_each_entry(fcport, &vha->vp_fcports, list)
6408 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
6409
6410 return ret;
6411}
6412
