LXR linux/drivers/staging/rtl8192ee/pci.h

   1/******************************************************************************
   2 *
   3 * Copyright(c) 2009-2010  Realtek Corporation.
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms of version 2 of the GNU General Public License as
   7 * published by the Free Software Foundation.
   8 *
   9 * This program is distributed in the hope that it will be useful, but WITHOUT
  10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12 * more details.
  13 *
  14 * The full GNU General Public License is included in this distribution in the
  15 * file called LICENSE.
  16 *
  17 * Contact Information:
  18 * wlanfae <wlanfae@realtek.com>
  19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20 * Hsinchu 300, Taiwan.
  21 *
  22 * Larry Finger <Larry.Finger@lwfinger.net>
  23 *
  24 *****************************************************************************/
  25
  26#ifndef __RTL_PCI_H__
  27#define __RTL_PCI_H__
  28
  29#include <linux/pci.h>
  30/*
  311: MSDU packet queue,
  322: Rx Command Queue
  33*/
  34#define RTL_PCI_RX_MPDU_QUEUE                   0
  35#define RTL_PCI_RX_CMD_QUEUE                    1
  36#define RTL_PCI_MAX_RX_QUEUE                    2
  37
  38#define RTL_PCI_MAX_RX_COUNT                    512/*64*/
  39#define RTL_PCI_MAX_TX_QUEUE_COUNT              9
  40
  41#define RT_TXDESC_NUM                           128
  42#define TX_DESC_NUM_92E                         512
  43#define RT_TXDESC_NUM_BE_QUEUE                  256
  44
  45#define BK_QUEUE                                0
  46#define BE_QUEUE                                1
  47#define VI_QUEUE                                2
  48#define VO_QUEUE                                3
  49#define BEACON_QUEUE                            4
  50#define TXCMD_QUEUE                             5
  51#define MGNT_QUEUE                              6
  52#define HIGH_QUEUE                              7
  53#define HCCA_QUEUE                              8
  54
  55#define RTL_PCI_DEVICE(vend, dev, cfg)  \
  56        .vendor = (vend), \
  57        .device = (dev), \
  58        .subvendor = PCI_ANY_ID, \
  59        .subdevice = PCI_ANY_ID,\
  60        .driver_data = (kernel_ulong_t)&(cfg)
  61
  62#define INTEL_VENDOR_ID                         0x8086
  63#define SIS_VENDOR_ID                           0x1039
  64#define ATI_VENDOR_ID                           0x1002
  65#define ATI_DEVICE_ID                           0x7914
  66#define AMD_VENDOR_ID                           0x1022
  67
  68#define PCI_MAX_BRIDGE_NUMBER                   255
  69#define PCI_MAX_DEVICES                         32
  70#define PCI_MAX_FUNCTION                        8
  71
  72#define PCI_CONF_ADDRESS        0x0CF8  /*PCI Configuration Space Address */
  73#define PCI_CONF_DATA           0x0CFC  /*PCI Configuration Space Data */
  74
  75#define PCI_CLASS_BRIDGE_DEV            0x06
  76#define PCI_SUBCLASS_BR_PCI_TO_PCI      0x04
  77#define PCI_CAPABILITY_ID_PCI_EXPRESS   0x10
  78#define PCI_CAP_ID_EXP                  0x10
  79
  80#define U1DONTCARE                      0xFF
  81#define U2DONTCARE                      0xFFFF
  82#define U4DONTCARE                      0xFFFFFFFF
  83
  84#define RTL_PCI_8192_DID        0x8192  /*8192 PCI-E */
  85#define RTL_PCI_8192SE_DID      0x8192  /*8192 SE */
  86#define RTL_PCI_8174_DID        0x8174  /*8192 SE */
  87#define RTL_PCI_8173_DID        0x8173  /*8191 SE Crab */
  88#define RTL_PCI_8172_DID        0x8172  /*8191 SE RE */
  89#define RTL_PCI_8171_DID        0x8171  /*8191 SE Unicron */
  90#define RTL_PCI_0045_DID        0x0045  /*8190 PCI for Ceraga */
  91#define RTL_PCI_0046_DID        0x0046  /*8190 Cardbus for Ceraga */
  92#define RTL_PCI_0044_DID        0x0044  /*8192e PCIE for Ceraga */
  93#define RTL_PCI_0047_DID        0x0047  /*8192e Express Card for Ceraga */
  94#define RTL_PCI_700F_DID        0x700F
  95#define RTL_PCI_701F_DID        0x701F
  96#define RTL_PCI_DLINK_DID       0x3304
  97#define RTL_PCI_8723AE_DID      0x8723  /*8723e */
  98#define RTL_PCI_8192CET_DID     0x8191  /*8192ce */
  99#define RTL_PCI_8192CE_DID      0x8178  /*8192ce */
 100#define RTL_PCI_8191CE_DID      0x8177  /*8192ce */
 101#define RTL_PCI_8188CE_DID      0x8176  /*8192ce */
 102#define RTL_PCI_8192CU_DID      0x8191  /*8192ce */
 103#define RTL_PCI_8192DE_DID      0x8193  /*8192de */
 104#define RTL_PCI_8192DE_DID2     0x002B  /*92DE*/
 105#define RTL_PCI_8188EE_DID      0x8179  /*8188ee*/
 106#define RTL_PCI_8723BE_DID      0xB723  /*8723be*/
 107#define RTL_PCI_8192EE_DID      0x818B  /*8192ee*/
 108#define RTL_PCI_8821AE_DID      0x8821  /*8821ae*/
 109#define RTL_PCI_8812AE_DID      0x8812  /*8812ae*/
 110
 111/*8192 support 16 pages of IO registers*/
 112#define RTL_MEM_MAPPED_IO_RANGE_8190PCI         0x1000
 113#define RTL_MEM_MAPPED_IO_RANGE_8192PCIE        0x4000
 114#define RTL_MEM_MAPPED_IO_RANGE_8192SE          0x4000
 115#define RTL_MEM_MAPPED_IO_RANGE_8192CE          0x4000
 116#define RTL_MEM_MAPPED_IO_RANGE_8192DE          0x4000
 117
 118#define RTL_PCI_REVISION_ID_8190PCI             0x00
 119#define RTL_PCI_REVISION_ID_8192PCIE            0x01
 120#define RTL_PCI_REVISION_ID_8192SE              0x10
 121#define RTL_PCI_REVISION_ID_8192CE              0x1
 122#define RTL_PCI_REVISION_ID_8192DE              0x0
 123
 124#define RTL_DEFAULT_HARDWARE_TYPE       HARDWARE_TYPE_RTL8192CE
 125
 126enum pci_bridge_vendor {
 127        PCI_BRIDGE_VENDOR_INTEL = 0x0,  /*0b'0000,0001 */
 128        PCI_BRIDGE_VENDOR_ATI,          /*0b'0000,0010*/
 129        PCI_BRIDGE_VENDOR_AMD,          /*0b'0000,0100*/
 130        PCI_BRIDGE_VENDOR_SIS,          /*0b'0000,1000*/
 131        PCI_BRIDGE_VENDOR_UNKNOWN,      /*0b'0100,0000*/
 132        PCI_BRIDGE_VENDOR_MAX,
 133};
 134
 135struct rtl_pci_capabilities_header {
 136        u8 capability_id;
 137        u8 next;
 138};
 139
 140/* In new TRX flow, Buffer_desc is new concept
 141  * But TX wifi info == TX descriptor in old flow
 142  * RX wifi info == RX descriptor in old flow */
 143struct rtl_tx_buffer_desc {
 144#if (RTL8192EE_SEG_NUM == 2)
 145        u32 dword[2*(DMA_IS_64BIT + 1)*8]; /*seg = 8*/
 146#elif (RTL8192EE_SEG_NUM == 1)
 147        u32 dword[2*(DMA_IS_64BIT + 1)*4]; /*seg = 4*/
 148#elif (RTL8192EE_SEG_NUM == 0)
 149        u32 dword[2*(DMA_IS_64BIT + 1)*2]; /*seg = 2*/
 150#endif
 151} __packed;
 152
 153struct rtl_tx_desc {/*old: tx desc new: tx wifi info*/
 154        u32 dword[16];
 155} __packed;
 156
 157struct rtl_rx_buffer_desc { /*rx buffer desc*/
 158        u32 dword[2];
 159} __packed;
 160
 161struct rtl_rx_desc { /*old: rx desc new: rx wifi info*/
 162        u32 dword[8];
 163} __packed;
 164
 165struct rtl_tx_cmd_desc {
 166        u32 dword[16];
 167} __packed;
 168
 169struct rtl8192_tx_ring {
 170        struct rtl_tx_desc *desc; /*tx desc / tx wifi info*/
 171        dma_addr_t dma; /*tx desc dma memory / tx wifi info dma memory*/
 172        unsigned int idx;
 173        unsigned int entries;
 174        struct sk_buff_head queue;
 175        /*add for new trx flow*/
 176        struct rtl_tx_buffer_desc *buffer_desc; /*tx buffer descriptor*/
 177        dma_addr_t buffer_desc_dma; /*tx bufferd desc dma memory*/
 178        u16 avl_desc; /* available_desc_to_write */
 179        u16 cur_tx_wp; /* current_tx_write_point */
 180        u16 cur_tx_rp; /* current_tx_read_point */
 181};
 182
 183struct rtl8192_rx_ring {
 184        struct rtl_rx_desc *desc;/*for old trx flow, not uesd in new trx*/
 185        /*dma matches either 'desc' or 'buffer_desc'*/
 186        dma_addr_t dma;
 187        unsigned int idx;
 188        struct sk_buff *rx_buf[RTL_PCI_MAX_RX_COUNT];
 189        /*add for new trx flow*/
 190        struct rtl_rx_buffer_desc *buffer_desc; /*rx buffer descriptor*/
 191        u16 next_rx_rp; /* next_rx_read_point */
 192};
 193
 194struct rtl_pci {
 195        struct pci_dev *pdev;
 196        bool irq_enabled;
 197
 198        /*Tx */
 199        struct rtl8192_tx_ring tx_ring[RTL_PCI_MAX_TX_QUEUE_COUNT];
 200        int txringcount[RTL_PCI_MAX_TX_QUEUE_COUNT];
 201        u32 transmit_config;
 202
 203        /*Rx */
 204        struct rtl8192_rx_ring rx_ring[RTL_PCI_MAX_RX_QUEUE];
 205        int rxringcount;
 206        u16 rxbuffersize;
 207        u32 receive_config;
 208
 209        /*irq */
 210        u8 irq_alloc;
 211        u32 irq_mask[2];
 212        u32 sys_irq_mask;
 213
 214        /*Bcn control register setting */
 215        u32 reg_bcn_ctrl_val;
 216
 217         /*ASPM*/ u8 const_pci_aspm;
 218        u8 const_amdpci_aspm;
 219        u8 const_hwsw_rfoff_d3;
 220        u8 const_support_pciaspm;
 221        /*pci-e bridge */
 222        u8 const_hostpci_aspm_setting;
 223        /*pci-e device */
 224        u8 const_devicepci_aspm_setting;
 225        /*If it supports ASPM, Offset[560h] = 0x40,
 226           otherwise Offset[560h] = 0x00. */
 227        bool b_support_aspm;
 228        bool b_support_backdoor;
 229
 230        /*QOS & EDCA */
 231        enum acm_method acm_method;
 232
 233        u16 shortretry_limit;
 234        u16 longretry_limit;
 235
 236        /* MSI support */
 237        bool msi_support;
 238        bool using_msi;
 239};
 240
 241struct mp_adapter {
 242        u8 linkctrl_reg;
 243
 244        u8 busnumber;
 245        u8 devnumber;
 246        u8 funcnumber;
 247
 248        u8 pcibridge_busnum;
 249        u8 pcibridge_devnum;
 250        u8 pcibridge_funcnum;
 251
 252        u8 pcibridge_vendor;
 253        u16 pcibridge_vendorid;
 254        u16 pcibridge_deviceid;
 255
 256        u32 pcicfg_addrport;
 257        u8 num4bytes;
 258
 259        u8 pcibridge_pciehdr_offset;
 260        u8 pcibridge_linkctrlreg;
 261
 262        bool amd_l1_patch;
 263};
 264
 265struct rtl_pci_priv {
 266        struct rtl_pci dev;
 267        struct mp_adapter ndis_adapter;
 268        struct rtl_led_ctl ledctl;
 269        struct bt_coexist_info btcoexist;
 270};
 271
 272#define rtl_pcipriv(hw)         (((struct rtl_pci_priv *)(rtl_priv(hw))->priv))
 273#define rtl_pcidev(pcipriv)     (&((pcipriv)->dev))
 274
 275int rtl92e_pci_reset_trx_ring(struct ieee80211_hw *hw);
 276
 277extern struct rtl_intf_ops rtl92e_pci_ops;
 278
 279int stg_rtl_pci_probe(struct pci_dev *pdev,
 280                      const struct pci_device_id *id);
 281void stg_rtl_pci_disconnect(struct pci_dev *pdev);
 282int stg_rtl_pci_suspend(struct device *dev);
 283int stg_rtl_pci_resume(struct device *dev);
 284
 285static inline u8 pci_read8_sync(struct rtl_priv *rtlpriv, u32 addr)
 286{
 287        return 0xff & readb((u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
 288}
 289
 290static inline u16 pci_read16_sync(struct rtl_priv *rtlpriv, u32 addr)
 291{
 292        return readw((u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
 293}
 294
 295static inline u32 pci_read32_sync(struct rtl_priv *rtlpriv, u32 addr)
 296{
 297        return readl((u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
 298}
 299
 300static inline void pci_write8_async(struct rtl_priv *rtlpriv, u32 addr, u8 val)
 301{
 302        writeb(val, (u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
 303}
 304
 305static inline void pci_write16_async(struct rtl_priv *rtlpriv,
 306                                     u32 addr, u16 val)
 307{
 308        writew(val, (u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
 309}
 310
 311static inline void pci_write32_async(struct rtl_priv *rtlpriv,
 312                                     u32 addr, u32 val)
 313{
 314        writel(val, (u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
 315}
 316
 317static inline void rtl_pci_raw_write_port_ulong(u32 port, u32 val)
 318{
 319        outl(val, port);
 320}
 321
 322static inline void rtl_pci_raw_write_port_uchar(u32 port, u8 val)
 323{
 324        outb(val, port);
 325}
 326
 327static inline void rtl_pci_raw_read_port_uchar(u32 port, u8 *pval)
 328{
 329        *pval = inb(port);
 330}
 331
 332static inline void rtl_pci_raw_read_port_ushort(u32 port, u16 *pval)
 333{
 334        *pval = inw(port);
 335}
 336
 337static inline void rtl_pci_raw_read_port_ulong(u32 port, u32 *pval)
 338{
 339        *pval = inl(port);
 340}
 341
 342#endif
 343