LXR linux/drivers/staging/rtl8821ae/rtl8821ae/phy.c

   1/******************************************************************************
   2 *
   3 * Copyright(c) 2009-2010  Realtek Corporation.
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms of version 2 of the GNU General Public License as
   7 * published by the Free Software Foundation.
   8 *
   9 * This program is distributed in the hope that it will be useful, but WITHOUT
  10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12 * more details.
  13 *
  14 * You should have received a copy of the GNU General Public License along with
  15 * this program; if not, write to the Free Software Foundation, Inc.,
  16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17 *
  18 * The full GNU General Public License is included in this distribution in the
  19 * file called LICENSE.
  20 *
  21 * Contact Information:
  22 * wlanfae <wlanfae@realtek.com>
  23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24 * Hsinchu 300, Taiwan.
  25 *
  26 * Larry Finger <Larry.Finger@lwfinger.net>
  27 *
  28 *****************************************************************************/
  29
  30#include "../wifi.h"
  31#include "../pci.h"
  32#include "../ps.h"
  33#include "reg.h"
  34#include "def.h"
  35#include "phy.h"
  36#include "rf.h"
  37#include "dm.h"
  38#include "table.h"
  39#include "trx.h"
  40#include "../btcoexist/halbt_precomp.h"
  41#include "hw.h"
  42
  43#define READ_NEXT_PAIR(array_table,v1, v2, i) do { i += 2; v1 = array_table[i]; v2 = array_table[i+1]; } while(0)
  44
  45static u32 _rtl8821ae_phy_rf_serial_read(struct ieee80211_hw *hw,
  46                                      enum radio_path rfpath, u32 offset);
  47static void _rtl8821ae_phy_rf_serial_write(struct ieee80211_hw *hw,
  48                                        enum radio_path rfpath, u32 offset,
  49                                        u32 data);
  50static u32 _rtl8821ae_phy_calculate_bit_shift(u32 bitmask);
  51static bool _rtl8821ae_phy_bb8821a_config_parafile(struct ieee80211_hw *hw);
  52static bool _rtl8812ae_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
  53static bool _rtl8821ae_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
  54static bool _rtl8821ae_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
  55                                                u8 configtype);
  56static bool _rtl8812ae_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
  57                                                u8 configtype);
  58static bool _rtl8821ae_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
  59                                                  u8 configtype);
  60static bool _rtl8812ae_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
  61                                                u8 configtype);
  62static void _rtl8821ae_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw);
  63
  64static long _rtl8821ae_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
  65                                         enum wireless_mode wirelessmode,
  66                                         u8 txpwridx);
  67static void rtl8821ae_phy_set_rf_on(struct ieee80211_hw *hw);
  68static void rtl8821ae_phy_set_io(struct ieee80211_hw *hw);
  69
  70void rtl8812ae_fixspur(
  71        struct ieee80211_hw *hw,
  72        enum ht_channel_width band_width,
  73        u8 channel
  74)
  75{
  76        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  77
  78        /*C cut Item12 ADC FIFO CLOCK*/
  79        if(IS_VENDOR_8812A_C_CUT(rtlhal->version))
  80        {
  81                if(band_width == HT_CHANNEL_WIDTH_20_40 && channel == 11)
  82                        rtl_set_bbreg(hw, RRFMOD, 0xC00, 0x3)   ;
  83                        /* 0x8AC[11:10] = 2'b11*/
  84                else
  85                        rtl_set_bbreg(hw, RRFMOD, 0xC00, 0x2);
  86                        /* 0x8AC[11:10] = 2'b10*/
  87
  88
  89                /* <20120914, Kordan> A workaround to resolve
  90                2480Mhz spur by setting ADC clock as 160M. (Asked by Binson)*/
  91                if (band_width == HT_CHANNEL_WIDTH_20 &&
  92                        (channel == 13 || channel == 14)) {
  93                        rtl_set_bbreg(hw, RRFMOD, 0x300, 0x3);
  94                        /*0x8AC[9:8] = 2'b11*/
  95                        rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 1);
  96                        /* 0x8C4[30] = 1*/
  97                } else if (band_width == HT_CHANNEL_WIDTH_20_40 &&
  98                        channel == 11) {
  99                        rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 1);
 100                        /*0x8C4[30] = 1*/
 101                } else if (band_width != HT_CHANNEL_WIDTH_80) {
 102                        rtl_set_bbreg(hw, RRFMOD, 0x300, 0x2);
 103                        /*0x8AC[9:8] = 2'b10*/
 104                        rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 0);
 105                        /*0x8C4[30] = 0*/
 106                }
 107        }
 108        else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 109        {
 110                /* <20120914, Kordan> A workaround to resolve
 111                2480Mhz spur by setting ADC clock as 160M. (Asked by Binson)*/
 112                if (band_width == HT_CHANNEL_WIDTH_20 &&
 113                        (channel == 13 || channel == 14))
 114                        rtl_set_bbreg(hw, RRFMOD, 0x300, 0x3);
 115                        /*0x8AC[9:8] = 11*/
 116                else if (channel  <= 14) /*2.4G only*/
 117                        rtl_set_bbreg(hw, RRFMOD, 0x300, 0x2);
 118                        /*0x8AC[9:8] = 10*/
 119        }
 120
 121}
 122
 123u32 rtl8821ae_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
 124{
 125        struct rtl_priv *rtlpriv = rtl_priv(hw);
 126        u32 returnvalue, originalvalue, bitshift;
 127
 128        RT_TRACE(COMP_RF, DBG_TRACE, ("regaddr(%#x), "
 129                                               "bitmask(%#x)\n", regaddr,
 130                                               bitmask));
 131        originalvalue = rtl_read_dword(rtlpriv, regaddr);
 132        bitshift = _rtl8821ae_phy_calculate_bit_shift(bitmask);
 133        returnvalue = (originalvalue & bitmask) >> bitshift;
 134
 135        RT_TRACE(COMP_RF, DBG_TRACE, ("BBR MASK=0x%x "
 136                                               "Addr[0x%x]=0x%x\n", bitmask,
 137                                               regaddr, originalvalue));
 138
 139        return returnvalue;
 140
 141}
 142
 143void rtl8821ae_phy_set_bb_reg(struct ieee80211_hw *hw,
 144                           u32 regaddr, u32 bitmask, u32 data)
 145{
 146        struct rtl_priv *rtlpriv = rtl_priv(hw);
 147        u32 originalvalue, bitshift;
 148
 149        RT_TRACE(COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x),"
 150                                               " data(%#x)\n", regaddr, bitmask,
 151                                               data));
 152
 153        if (bitmask != MASKDWORD) {
 154                originalvalue = rtl_read_dword(rtlpriv, regaddr);
 155                bitshift = _rtl8821ae_phy_calculate_bit_shift(bitmask);
 156                data = ((originalvalue & (~bitmask)) | ((data << bitshift) & bitmask));
 157        }
 158
 159        rtl_write_dword(rtlpriv, regaddr, data);
 160
 161        RT_TRACE(COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x),"
 162                                               " data(%#x)\n", regaddr, bitmask,
 163                                               data));
 164
 165}
 166
 167u32 rtl8821ae_phy_query_rf_reg(struct ieee80211_hw *hw,
 168                            enum radio_path rfpath, u32 regaddr, u32 bitmask)
 169{
 170        struct rtl_priv *rtlpriv = rtl_priv(hw);
 171        u32 original_value, readback_value, bitshift;
 172        unsigned long flags;
 173
 174        RT_TRACE(COMP_RF, DBG_TRACE, ("regaddr(%#x), "
 175                                               "rfpath(%#x), bitmask(%#x)\n",
 176                                               regaddr, rfpath, bitmask));
 177
 178        spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
 179
 180
 181        original_value = _rtl8821ae_phy_rf_serial_read(hw,rfpath, regaddr);
 182        bitshift = _rtl8821ae_phy_calculate_bit_shift(bitmask);
 183        readback_value = (original_value & bitmask) >> bitshift;
 184
 185        spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
 186
 187        RT_TRACE(COMP_RF, DBG_TRACE,
 188                 ("regaddr(%#x), rfpath(%#x), "
 189                  "bitmask(%#x), original_value(%#x)\n",
 190                  regaddr, rfpath, bitmask, original_value));
 191
 192        return readback_value;
 193}
 194
 195void rtl8821ae_phy_set_rf_reg(struct ieee80211_hw *hw,
 196                           enum radio_path rfpath,
 197                           u32 regaddr, u32 bitmask, u32 data)
 198{
 199        struct rtl_priv *rtlpriv = rtl_priv(hw);
 200        u32 original_value, bitshift;
 201        unsigned long flags;
 202
 203        RT_TRACE(COMP_RF, DBG_TRACE,
 204                 ("regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
 205                  regaddr, bitmask, data, rfpath));
 206
 207        spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
 208
 209        if (bitmask != RFREG_OFFSET_MASK) {
 210                        original_value = _rtl8821ae_phy_rf_serial_read(hw,
 211                                                                    rfpath,
 212                                                                    regaddr);
 213                        bitshift = _rtl8821ae_phy_calculate_bit_shift(bitmask);
 214                        data =
 215                            ((original_value & (~bitmask)) |
 216                             (data << bitshift));
 217                }
 218
 219        _rtl8821ae_phy_rf_serial_write(hw, rfpath, regaddr, data);
 220
 221
 222        spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
 223
 224        RT_TRACE(COMP_RF, DBG_TRACE, ("regaddr(%#x), "
 225                                               "bitmask(%#x), data(%#x), rfpath(%#x)\n",
 226                                               regaddr, bitmask, data, rfpath));
 227
 228}
 229
 230static u32 _rtl8821ae_phy_rf_serial_read(struct ieee80211_hw *hw,
 231                                      enum radio_path rfpath, u32 offset)
 232{
 233        struct rtl_priv *rtlpriv = rtl_priv(hw);
 234        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 235        bool b_is_pi_mode =false;
 236        u32 retvalue = 0;
 237
 238        /* 2009/06/17 MH We can not execute IO for power save or other accident mode.*/
 239        if (RT_CANNOT_IO(hw)) {
 240                RT_TRACE(COMP_ERR, DBG_EMERG, ("return all one\n"));
 241                return 0xFFFFFFFF;
 242        }
 243
 244        /* <20120809, Kordan> CCA OFF(when entering), asked by James to avoid reading the wrong value.
 245            <20120828, Kordan> Toggling CCA would affect RF 0x0, skip it!*/
 246        if (offset != 0x0 &&
 247                !((rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE)
 248                || (IS_VENDOR_8812A_C_CUT(rtlhal->version))))
 249                rtl_set_bbreg(hw, RCCAONSEC, 0x8, 1);
 250
 251        offset &= 0xff;
 252
 253        if (rfpath == RF90_PATH_A)
 254                b_is_pi_mode = (bool) rtl_get_bbreg(hw, 0xC00, 0x4);
 255        else if (rfpath == RF90_PATH_B)
 256                b_is_pi_mode = (bool) rtl_get_bbreg(hw, 0xE00, 0x4);
 257
 258        rtl_set_bbreg(hw, RHSSIREAD_8821AE, 0xff, offset);
 259
 260        if ((rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE)
 261                || (IS_VENDOR_8812A_C_CUT(rtlhal->version)))
 262                udelay(20);
 263
 264        if (b_is_pi_mode)
 265        {
 266                if (rfpath == RF90_PATH_A) {
 267                        retvalue = rtl_get_bbreg(hw, RA_PIREAD_8821A, BLSSIREADBACKDATA);
 268                }
 269                else if (rfpath == RF90_PATH_B){
 270                        retvalue = rtl_get_bbreg(hw, RB_PIREAD_8821A, BLSSIREADBACKDATA);
 271                }
 272        }
 273        else
 274        {
 275                if (rfpath == RF90_PATH_A) {
 276                        retvalue = rtl_get_bbreg(hw, RA_SIREAD_8821A, BLSSIREADBACKDATA);
 277                }
 278                else if (rfpath == RF90_PATH_B){
 279                        retvalue = rtl_get_bbreg(hw, RB_SIREAD_8821A, BLSSIREADBACKDATA);
 280                }
 281        }
 282
 283        /*<20120809, Kordan> CCA ON(when exiting), asked by James to avoid reading the wrong value.
 284            <20120828, Kordan> Toggling CCA would affect RF 0x0, skip it!*/
 285        if (offset != 0x0 &&  ! ((rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE)
 286                || (IS_VENDOR_8812A_C_CUT(rtlhal->version))))
 287                rtl_set_bbreg(hw, RCCAONSEC, 0x8, 0);
 288        return retvalue;
 289}
 290
 291#if 0
 292static u32 _rtl8821ae_phy_rf_serial_read(struct ieee80211_hw *hw,
 293                                      enum radio_path rfpath, u32 offset)
 294{
 295        struct rtl_priv *rtlpriv = rtl_priv(hw);
 296        struct rtl_phy *rtlphy = &(rtlpriv->phy);
 297        struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
 298        u32 newoffset;
 299        u32 tmplong, tmplong2;
 300        u8 rfpi_enable = 0;
 301        u32 retvalue;
 302
 303        offset &= 0xff;
 304        newoffset = offset;
 305        if (RT_CANNOT_IO(hw)) {
 306                RT_TRACE(COMP_ERR, DBG_EMERG, ("return all one\n"));
 307                return 0xFFFFFFFF;
 308        }
 309        tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
 310        if (rfpath == RF90_PATH_A)
 311                tmplong2 = tmplong;
 312        else
 313                tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
 314        tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
 315            (newoffset << 23) | BLSSIREADEDGE;
 316        rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
 317                      tmplong & (~BLSSIREADEDGE));
 318        mdelay(1);
 319        rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
 320        mdelay(1);
 321        /*rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
 322                      tmplong | BLSSIREADEDGE);*/
 323        mdelay(1);
 324        if (rfpath == RF90_PATH_A)
 325                rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
 326                                                 BIT(8));
 327        else if (rfpath == RF90_PATH_B)
 328                rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
 329                                                 BIT(8));
 330        if (rfpi_enable)
 331                retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readbackpi,
 332                                         BLSSIREADBACKDATA);
 333        else
 334                retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readback,
 335                                         BLSSIREADBACKDATA);
 336        RT_TRACE(COMP_RF, DBG_TRACE, ("RFR-%d Addr[0x%x]=0x%x\n",
 337                                               rfpath, pphyreg->rflssi_readback,
 338                                               retvalue));
 339        return retvalue;
 340}
 341#endif
 342
 343static void _rtl8821ae_phy_rf_serial_write(struct ieee80211_hw *hw,
 344                                        enum radio_path rfpath, u32 offset,
 345                                        u32 data)
 346{
 347        u32 data_and_addr;
 348        u32 newoffset;
 349        struct rtl_priv *rtlpriv = rtl_priv(hw);
 350        struct rtl_phy *rtlphy = &(rtlpriv->phy);
 351        struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
 352
 353        if (RT_CANNOT_IO(hw)) {
 354                RT_TRACE(COMP_ERR, DBG_EMERG, ("stop\n"));
 355                return;
 356        }
 357        offset &= 0xff;
 358        newoffset = offset;
 359        data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
 360        rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
 361        RT_TRACE(COMP_RF, DBG_TRACE, ("RFW-%d Addr[0x%x]=0x%x\n",
 362                                               rfpath, pphyreg->rf3wire_offset,
 363                                               data_and_addr));
 364}
 365
 366static u32 _rtl8821ae_phy_calculate_bit_shift(u32 bitmask)
 367{
 368        u32 i;
 369
 370        for (i = 0; i <= 31; i++) {
 371                if (((bitmask >> i) & 0x1) == 1)
 372                        break;
 373        }
 374        return i;
 375}
 376
 377bool rtl8821ae_phy_mac_config(struct ieee80211_hw *hw)
 378{
 379        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 380        bool rtstatus = 0;
 381
 382        if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 383                rtstatus = _rtl8812ae_phy_config_mac_with_headerfile(hw);
 384        else
 385                rtstatus = _rtl8821ae_phy_config_mac_with_headerfile(hw);
 386
 387        return rtstatus;
 388}
 389
 390bool rtl8821ae_phy_bb_config(struct ieee80211_hw *hw)
 391{
 392        bool rtstatus = true;
 393        struct rtl_priv *rtlpriv = rtl_priv(hw);
 394        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 395        struct rtl_phy *rtlphy = &(rtlpriv->phy);
 396        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 397        u8 regval;
 398        u8 crystal_cap;
 399        //u32 tmp;
 400
 401        _rtl8821ae_phy_init_bb_rf_register_definition(hw);
 402
 403        regval = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
 404        regval |= regval | FEN_PCIEA;
 405        rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, regval);
 406        rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN,
 407                                regval | FEN_BB_GLB_RSTN | FEN_BBRSTB);
 408
 409        rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x7);/*RF_EN | RF_RSTB | RF_SDMRSTB*/
 410        rtl_write_byte(rtlpriv, REG_OPT_CTRL + 2, 0x7);/*RF_EN | RF_RSTB | RF_SDMRSTB*/
 411
 412        rtstatus = _rtl8821ae_phy_bb8821a_config_parafile(hw);
 413
 414        if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 415        {
 416                crystal_cap = rtlefuse->crystalcap & 0x3F;
 417                rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0x7FF80000, (crystal_cap | (crystal_cap << 6)));
 418        }else{
 419                crystal_cap = rtlefuse->crystalcap & 0x3F;
 420                rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000, (crystal_cap | (crystal_cap << 6)));
 421        }
 422        rtlphy->reg_837 = rtl_read_byte(rtlpriv, 0x837);
 423
 424        return rtstatus;
 425}
 426
 427bool rtl8821ae_phy_rf_config(struct ieee80211_hw *hw)
 428{
 429        return rtl8821ae_phy_rf6052_config(hw);
 430}
 431
 432
 433u32 phy_get_tx_bb_swing_8812A(
 434        struct ieee80211_hw *hw,
 435        u8      band,
 436        u8      rf_path
 437        )
 438{
 439        struct rtl_priv *rtlpriv = rtl_priv(hw);
 440        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 441        struct rtl_dm *rtldm = rtl_dm(rtlpriv);
 442        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 443
 444        char bb_swing_2g = (char) ((-1 * 0xFF) & 0xFF);
 445        char bb_swing_5g = (char) ((-1 * 0xFF) & 0xFF);
 446        u32  out = 0x200;
 447        const char auto_temp = -1;
 448
 449        RT_TRACE(COMP_SCAN, DBG_LOUD,
 450                ("===> PHY_GetTxBBSwing_8812A, bbSwing_2G: %d, bbSwing_5G: %d\n",
 451                (int)bb_swing_2g, (int)bb_swing_5g));
 452
 453    if ( rtlefuse->autoload_failflag) {
 454                if ( band == BAND_ON_2_4G ) {
 455                        rtldm->bb_swing_diff_2g = bb_swing_2g;
 456                        if      (bb_swing_2g == 0)  out = 0x200; //  0 dB
 457                        else if (bb_swing_2g == -3) out = 0x16A; // -3 dB
 458                        else if (bb_swing_2g == -6) out = 0x101; // -6 dB
 459                        else if (bb_swing_2g == -9) out = 0x0B6; // -9 dB
 460                        else {
 461                                rtldm->bb_swing_diff_2g = 0;
 462                                out = 0x200;
 463                        }
 464
 465                } else if ( band == BAND_ON_5G ) {
 466                        rtldm->bb_swing_diff_5g = bb_swing_5g;
 467                        if      (bb_swing_5g == 0)  out = 0x200; //  0 dB
 468                        else if (bb_swing_5g == -3) out = 0x16A; // -3 dB
 469                        else if (bb_swing_5g == -6) out = 0x101; // -6 dB
 470                        else if (bb_swing_5g == -9) out = 0x0B6; // -9 dB
 471                        else {
 472                                if ( rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
 473                                        rtldm->bb_swing_diff_5g = -3;
 474                                        out = 0x16A;
 475                                } else  {
 476                                        rtldm->bb_swing_diff_5g = 0;
 477                                        out = 0x200;
 478                                }
 479                        }
 480                } else  {
 481                                rtldm->bb_swing_diff_2g = -3;
 482                                rtldm->bb_swing_diff_5g = -3;
 483                                out = 0x16A; // -3 dB
 484                }
 485        }
 486        else
 487        {
 488            u32 swing = 0, swing_a = 0, swing_b = 0;
 489
 490            if (band == BAND_ON_2_4G)
 491            {
 492                        if (0xFF == auto_temp)
 493                        {
 494                                efuse_shadow_read(hw, 1, 0xC6, (u32 *)&swing);
 495                                swing = (swing == 0xFF) ? 0x00 : swing;
 496                        }
 497                        else if (bb_swing_2g ==  0) swing = 0x00; //  0 dB
 498                        else if (bb_swing_2g == -3) swing = 0x05; // -3 dB
 499                        else if (bb_swing_2g == -6) swing = 0x0A; // -6 dB
 500                        else if (bb_swing_2g == -9) swing = 0xFF; // -9 dB
 501                        else swing = 0x00;
 502                }
 503                else
 504                {
 505                        if (0xFF == auto_temp)
 506                        {
 507                                efuse_shadow_read(hw, 1, 0xC7, (u32 *)&swing);
 508                                swing = (swing == 0xFF) ? 0x00 : swing;
 509                        }
 510                        else if (bb_swing_5g ==  0) swing = 0x00; //  0 dB
 511                        else if (bb_swing_5g == -3) swing = 0x05; // -3 dB
 512                        else if (bb_swing_5g == -6) swing = 0x0A; // -6 dB
 513                        else if (bb_swing_5g == -9) swing = 0xFF; // -9 dB
 514                        else swing = 0x00;
 515                }
 516
 517                swing_a = (swing & 0x3) >> 0; // 0xC6/C7[1:0]
 518                swing_b = (swing & 0xC) >> 2; // 0xC6/C7[3:2]
 519                RT_TRACE(COMP_SCAN, DBG_LOUD,
 520                ("===> PHY_GetTxBBSwing_8812A, swingA: 0x%X, swingB: 0x%X\n",
 521                swing_a, swing_b));
 522
 523                //3 Path-A
 524                if (swing_a == 0x0) {
 525                        if (band == BAND_ON_2_4G)
 526                                rtldm->bb_swing_diff_2g = 0;
 527                        else
 528                                rtldm->bb_swing_diff_5g = 0;
 529                        out = 0x200; // 0 dB
 530                } else if (swing_a == 0x1) {
 531                        if (band == BAND_ON_2_4G)
 532                                rtldm->bb_swing_diff_2g = -3;
 533                        else
 534                                rtldm->bb_swing_diff_5g = -3;
 535                        out = 0x16A; // -3 dB
 536                } else if (swing_a == 0x2) {
 537                        if (band == BAND_ON_2_4G)
 538                                rtldm->bb_swing_diff_2g = -6;
 539                        else
 540                                rtldm->bb_swing_diff_5g = -6;
 541                        out = 0x101; // -6 dB
 542                } else if (swing_a == 0x3) {
 543                        if (band == BAND_ON_2_4G)
 544                                rtldm->bb_swing_diff_2g = -9;
 545                        else
 546                                rtldm->bb_swing_diff_5g = -9;
 547                        out = 0x0B6; // -9 dB
 548                }
 549
 550                        //3 Path-B
 551                if (swing_b == 0x0) {
 552                        if (band == BAND_ON_2_4G)
 553                                rtldm->bb_swing_diff_2g = 0;
 554                        else
 555                                rtldm->bb_swing_diff_5g = 0;
 556                        out = 0x200; // 0 dB
 557                } else if (swing_b == 0x1) {
 558                        if (band == BAND_ON_2_4G)
 559                                rtldm->bb_swing_diff_2g = -3;
 560                        else
 561                                rtldm->bb_swing_diff_5g = -3;
 562                        out = 0x16A; // -3 dB
 563                } else if (swing_b == 0x2) {
 564                        if (band == BAND_ON_2_4G)
 565                                rtldm->bb_swing_diff_2g = -6;
 566                        else
 567                                rtldm->bb_swing_diff_5g = -6;
 568                        out = 0x101; // -6 dB
 569                } else if (swing_b == 0x3) {
 570                        if (band == BAND_ON_2_4G)
 571                                rtldm->bb_swing_diff_2g = -9;
 572                        else
 573                                rtldm->bb_swing_diff_5g = -9;
 574                        out = 0x0B6; // -9 dB
 575                }
 576        }
 577
 578        RT_TRACE(COMP_SCAN, DBG_LOUD,
 579                ("<=== PHY_GetTxBBSwing_8812A, out = 0x%X\n", out));
 580         return out;
 581}
 582void rtl8821ae_phy_switch_wirelessband(struct ieee80211_hw *hw, u8 band)
 583{
 584        struct rtl_priv *rtlpriv = rtl_priv(hw);
 585        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 586        struct rtl_dm *rtldm = rtl_dm(rtlpriv);
 587        u8 current_band = rtlhal->current_bandtype;
 588        u32 txpath, rxpath;
 589        //u8 i, value8;
 590        char bb_diff_between_band;
 591
 592        RT_TRACE(COMP_INIT, DBG_LOUD, ("\n"));
 593        txpath = rtl8821ae_phy_query_bb_reg(hw, RTXPATH, 0xf0);
 594        rxpath = rtl8821ae_phy_query_bb_reg(hw, RCCK_RX, 0x0f000000);
 595        rtlhal->current_bandtype = (enum band_type) band;
 596        /* reconfig BB/RF according to wireless mode */
 597        if (rtlhal->current_bandtype == BAND_ON_2_4G) {
 598                /* BB & RF Config */
 599                RT_TRACE(COMP_CMD, DBG_DMESG, ("2.4G\n"));
 600                rtl_set_bbreg(hw, ROFDMCCKEN, BOFDMEN|BCCKEN, 0x03);
 601
 602                if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
 603                        /* 0xCB0[15:12] = 0x7 (LNA_On)*/
 604                        rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF000, 0x7);
 605                        /* 0xCB0[7:4] = 0x7 (PAPE_A)*/
 606                        rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF0, 0x7);
 607                }
 608
 609                if(rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
 610                        rtl_set_bbreg(hw, 0x830, 0xE, 0x4);     /*0x830[3:1] = 0x4*/
 611                        rtl_set_bbreg(hw, 0x834, 0x3, 0x1);     /*0x834[1:0] = 0x1*/
 612                }
 613
 614                if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE)
 615                        rtl_set_bbreg(hw, RA_TXSCALE, 0xF00, 0); // 0xC1C[11:8] = 0
 616                else
 617                        rtl_set_bbreg(hw, 0x82c, 0x3, 0);       // 0x82C[1:0] = 2b'00
 618
 619                if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
 620                        rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x77777777);
 621                        rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77777777);
 622                        rtl_set_bbreg(hw, RA_RFE_INV, 0x3ff00000, 0x000);
 623                        rtl_set_bbreg(hw, RB_RFE_INV, 0x3ff00000, 0x000);
 624                }
 625
 626                rtl_set_bbreg(hw, RTXPATH, 0xf0, txpath);
 627                rtl_set_bbreg(hw, RCCK_RX, 0x0f000000, rxpath);
 628
 629                rtl_write_byte(rtlpriv, REG_CCK_CHECK, 0x0);
 630        } else {/* 5G band */
 631                u16 count, reg_41a;
 632                RT_TRACE(COMP_CMD, DBG_DMESG, ("5G\n"));
 633
 634                if(rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
 635                        /*0xCB0[15:12] = 0x5 (LNA_On)*/
 636                        rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF000, 0x5);
 637                        /*0xCB0[7:4] = 0x4 (PAPE_A)*/
 638                        rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF0, 0x4);
 639                }
 640                /*CCK_CHECK_en*/
 641                rtl_write_byte(rtlpriv, REG_CCK_CHECK, 0x80);
 642
 643                count = 0;
 644                reg_41a = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
 645                RT_TRACE(COMP_SCAN, DBG_LOUD, ("Reg41A value %d", reg_41a));
 646                reg_41a &= 0x30;
 647                while ((reg_41a!= 0x30) && (count < 50)) {
 648                        udelay(50);
 649                        RT_TRACE(COMP_SCAN, DBG_LOUD, ("Delay 50us \n"));
 650
 651                        reg_41a = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
 652                        reg_41a &= 0x30;
 653                        count++;
 654                        RT_TRACE(COMP_SCAN, DBG_LOUD, ("Reg41A value %d", reg_41a));
 655                }
 656                if (count != 0)
 657                        RT_TRACE(COMP_MLME, DBG_LOUD,
 658                        ("PHY_SwitchWirelessBand8812(): Switch to 5G Band. "
 659                        "Count = %d reg41A=0x%x\n", count, reg_41a));
 660
 661                // 2012/02/01, Sinda add registry to switch workaround without long-run verification for scan issue.
 662                rtl_set_bbreg(hw, ROFDMCCKEN, BOFDMEN|BCCKEN, 0x03);
 663
 664                if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
 665                        rtl_set_bbreg(hw, 0x830, 0xE, 0x3);     /*0x830[3:1] = 0x3*/
 666                        rtl_set_bbreg(hw, 0x834, 0x3, 0x2);     /*0x834[1:0] = 0x2*/
 667                }
 668
 669                if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
 670                        /* AGC table select */
 671                        rtl_set_bbreg(hw, RA_TXSCALE, 0xF00, 1); /* 0xC1C[11:8] = 1*/
 672                } else
 673                        rtl_set_bbreg(hw, 0x82c, 0x3, 1);       // 0x82C[1:0] = 2'b00
 674
 675                if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
 676                        rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x77337777);
 677                        rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77337777);
 678                        rtl_set_bbreg(hw, RA_RFE_INV, 0x3ff00000, 0x010);
 679                        rtl_set_bbreg(hw, RB_RFE_INV, 0x3ff00000, 0x010);
 680                }
 681
 682                rtl_set_bbreg(hw, RTXPATH, 0xf0, txpath);
 683                rtl_set_bbreg(hw, RCCK_RX, 0x0f000000, rxpath);
 684
 685                RT_TRACE(COMP_SCAN, DBG_LOUD,
 686                        ("==>PHY_SwitchWirelessBand8812() BAND_ON_5G settings OFDM index 0x%x\n",
 687                        rtlpriv->dm.ofdm_index[RF90_PATH_A]));
 688        }
 689
 690        if ((rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) ||
 691                        (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)) {
 692                rtl_set_bbreg(hw, RA_TXSCALE, 0xFFE00000,
 693                                                 phy_get_tx_bb_swing_8812A(hw, band, RF90_PATH_A)); // 0xC1C[31:21]
 694                rtl_set_bbreg(hw, RB_TXSCALE, 0xFFE00000,
 695                                                 phy_get_tx_bb_swing_8812A(hw, band, RF90_PATH_B)); // 0xE1C[31:21]
 696
 697                /* <20121005, Kordan> When TxPowerTrack is ON, we should take care of the change of BB swing.
 698                    That is, reset all info to trigger Tx power tracking.*/
 699                if (band != current_band) {
 700                        bb_diff_between_band = (rtldm->bb_swing_diff_2g - rtldm->bb_swing_diff_5g);
 701                        bb_diff_between_band = (band == BAND_ON_2_4G) ? bb_diff_between_band : (-1 * bb_diff_between_band);
 702                        rtldm->default_ofdm_index += bb_diff_between_band * 2;
 703                }
 704                rtl8821ae_dm_clear_txpower_tracking_state(hw);
 705        }
 706
 707        RT_TRACE(COMP_SCAN, DBG_TRACE,
 708                ("<==rtl8821ae_phy_switch_wirelessband():Switch Band OK.\n"));
 709        return;
 710}
 711
 712static bool _rtl8821ae_check_condition(struct ieee80211_hw *hw,
 713        const u32  Condition
 714        )
 715{
 716        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 717        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 718        u32 _board = rtlefuse->board_type; /*need efuse define*/
 719        u32 _interface = rtlhal->interface;
 720        u32 _platform = 0x08;/*SupportPlatform */
 721        u32 cond = Condition;
 722
 723        if ( Condition == 0xCDCDCDCD )
 724                return true;
 725
 726        cond = Condition & 0xFF;
 727        if ( (_board != cond) == 0 && cond != 0xFF)
 728                return false;
 729
 730        cond = Condition & 0xFF00;
 731        cond = cond >> 8;
 732        if ( (_interface & cond) == 0 && cond != 0x07)
 733                return false;
 734
 735        cond = Condition & 0xFF0000;
 736        cond = cond >> 16;
 737        if ( (_platform & cond) == 0 && cond != 0x0F)
 738                return false;
 739        return true;
 740}
 741
 742static void _rtl8821ae_config_rf_reg(struct ieee80211_hw *hw,
 743        u32 addr,
 744        u32 data,
 745        enum radio_path rfpath,
 746        u32 regaddr
 747        )
 748{
 749        if ( addr == 0xfe || addr == 0xffe) {
 750                mdelay(50);
 751        } else {
 752                rtl_set_rfreg(hw, rfpath, regaddr, RFREG_OFFSET_MASK, data);
 753                udelay(1);
 754        }
 755}
 756
 757static void _rtl8821ae_config_rf_radio_a(struct ieee80211_hw *hw,
 758        u32 addr, u32 data)
 759{
 760        u32 content = 0x1000; /*RF Content: radio_a_txt*/
 761        u32 maskforphyset = (u32)(content & 0xE000);
 762
 763        _rtl8821ae_config_rf_reg(hw, addr, data, RF90_PATH_A, addr | maskforphyset);
 764
 765}
 766
 767static void _rtl8821ae_config_rf_radio_b(struct ieee80211_hw *hw,
 768        u32 addr, u32 data)
 769{
 770        u32 content = 0x1001; /*RF Content: radio_b_txt*/
 771        u32 maskforphyset = (u32)(content & 0xE000);
 772
 773        _rtl8821ae_config_rf_reg(hw, addr, data, RF90_PATH_B, addr | maskforphyset);
 774
 775}
 776
 777static void _rtl8812ae_config_bb_reg(struct ieee80211_hw *hw,
 778        u32 addr, u32 data)
 779{
 780        if ( addr == 0xfe) {
 781                mdelay(50);
 782        } else if ( addr == 0xfd)
 783                mdelay(5);
 784        else if ( addr == 0xfc)
 785                mdelay(1);
 786        else if ( addr == 0xfb)
 787                udelay(50);
 788        else if ( addr == 0xfa)
 789                udelay(5);
 790        else if ( addr == 0xf9)
 791                udelay(1);
 792        else {
 793                rtl_set_bbreg(hw, addr, MASKDWORD,data);
 794        }
 795        udelay(1);
 796}
 797
 798static void _rtl8821ae_config_bb_reg(struct ieee80211_hw *hw,
 799        u32 addr, u32 data)
 800{
 801        if ( addr == 0xfe) {
 802                mdelay(50);
 803        } else if ( addr == 0xfd)
 804                mdelay(5);
 805        else if ( addr == 0xfc)
 806                mdelay(1);
 807        else if ( addr == 0xfb)
 808                udelay(50);
 809        else if ( addr == 0xfa)
 810                udelay(5);
 811        else if ( addr == 0xf9)
 812                udelay(1);
 813
 814        rtl_set_bbreg(hw, addr, MASKDWORD,data);
 815        udelay(1);
 816}
 817
 818static void _rtl8821ae_phy_init_tx_power_by_rate(struct ieee80211_hw *hw)
 819{
 820        struct rtl_priv *rtlpriv = rtl_priv(hw);
 821        struct rtl_phy *rtlphy = &(rtlpriv->phy);
 822
 823        u8 band, rfpath, txnum, rate_section;
 824
 825        for ( band = BAND_ON_2_4G; band <= BAND_ON_5G; ++band )
 826                for ( rfpath = 0; rfpath < TX_PWR_BY_RATE_NUM_RF; ++rfpath )
 827                        for ( txnum = 0; txnum < TX_PWR_BY_RATE_NUM_RF; ++txnum )
 828                                for ( rate_section = 0; rate_section < TX_PWR_BY_RATE_NUM_SECTION; ++rate_section )
 829                                        rtlphy->tx_power_by_rate_offset[band][rfpath][txnum][rate_section] = 0;
 830}
 831
 832void _rtl8821ae_phy_set_txpower_by_rate_base(struct ieee80211_hw *hw,
 833                                                                                                                   u8 band, u8 path,
 834                                                                                                                   u8 rate_section,
 835                                                                                                                   u8 txnum, u8 value)
 836{
 837        struct rtl_priv *rtlpriv = rtl_priv(hw);
 838        struct rtl_phy *rtlphy = &(rtlpriv->phy);
 839
 840        if (path > RF90_PATH_D) {
 841                RT_TRACE(COMP_INIT, DBG_LOUD,
 842                        ("Invalid Rf Path %d in phy_SetTxPowerByRatBase()\n", path));
 843                return;
 844        }
 845
 846        if (band == BAND_ON_2_4G) {
 847                switch (rate_section) {
 848                case CCK:
 849                        rtlphy->txpwr_by_rate_base_24g[path][txnum][0] = value;
 850                        break;
 851                case OFDM:
 852                        rtlphy->txpwr_by_rate_base_24g[path][txnum][1] = value;
 853                        break;
 854                case HT_MCS0_MCS7:
 855                        rtlphy->txpwr_by_rate_base_24g[path][txnum][2] = value;
 856                        break;
 857                case HT_MCS8_MCS15:
 858                        rtlphy->txpwr_by_rate_base_24g[path][txnum][3] = value;
 859                        break;
 860                case VHT_1SSMCS0_1SSMCS9:
 861                        rtlphy->txpwr_by_rate_base_24g[path][txnum][4] = value;
 862                        break;
 863                case VHT_2SSMCS0_2SSMCS9:
 864                        rtlphy->txpwr_by_rate_base_24g[path][txnum][5] = value;
 865                        break;
 866                default:
 867                        RT_TRACE(COMP_INIT, DBG_LOUD, ( "Invalid RateSection %d in Band 2.4G, Rf Path %d, %dTx in PHY_SetTxPowerByRateBase()\n",
 868                                         rate_section, path, txnum ) );
 869                        break;
 870                };
 871        } else if (band == BAND_ON_5G) {
 872                switch (rate_section) {
 873                case OFDM:
 874                        rtlphy->txpwr_by_rate_base_5g[path][txnum][0] = value;
 875                        break;
 876                case HT_MCS0_MCS7:
 877                        rtlphy->txpwr_by_rate_base_5g[path][txnum][1] = value;
 878                        break;
 879                case HT_MCS8_MCS15:
 880                        rtlphy->txpwr_by_rate_base_5g[path][txnum][2] = value;
 881                        break;
 882                case VHT_1SSMCS0_1SSMCS9:
 883                        rtlphy->txpwr_by_rate_base_5g[path][txnum][3] = value;
 884                        break;
 885                case VHT_2SSMCS0_2SSMCS9:
 886                        rtlphy->txpwr_by_rate_base_5g[path][txnum][4] = value;
 887                        break;
 888                default:
 889                        RT_TRACE(COMP_INIT, DBG_LOUD,
 890                                ("Invalid RateSection %d in Band 5G, Rf Path %d, "
 891                                "%dTx in PHY_SetTxPowerByRateBase()\n",
 892                                rate_section, path, txnum));
 893                        break;
 894                };
 895        } else {
 896                RT_TRACE(COMP_INIT, DBG_LOUD,
 897                        ("Invalid Band %d in PHY_SetTxPowerByRateBase()\n", band));
 898        }
 899
 900}
 901
 902u8 _rtl8821ae_phy_get_txpower_by_rate_base(struct ieee80211_hw *hw,
 903                                                                                                                 u8 band, u8 path,
 904                                                                                                                 u8 txnum, u8 rate_section)
 905{
 906        struct rtl_priv *rtlpriv = rtl_priv(hw);
 907        struct rtl_phy *rtlphy = &(rtlpriv->phy);
 908        u8 value = 0;
 909
 910        if (path > RF90_PATH_D) {
 911                RT_TRACE(COMP_INIT, DBG_LOUD,
 912                        ("Invalid Rf Path %d in PHY_GetTxPowerByRateBase()\n", path));
 913                return 0;
 914        }
 915
 916        if (band == BAND_ON_2_4G) {
 917                switch (rate_section) {
 918                case CCK:
 919                        value = rtlphy->txpwr_by_rate_base_24g[path][txnum][0];
 920                        break;
 921                case OFDM:
 922                        value = rtlphy->txpwr_by_rate_base_24g[path][txnum][1];
 923                        break;
 924                case HT_MCS0_MCS7:
 925                        value = rtlphy->txpwr_by_rate_base_24g[path][txnum][2];
 926                        break;
 927                case HT_MCS8_MCS15:
 928                        value = rtlphy->txpwr_by_rate_base_24g[path][txnum][3];
 929                        break;
 930                case VHT_1SSMCS0_1SSMCS9:
 931                        value = rtlphy->txpwr_by_rate_base_24g[path][txnum][4];
 932                        break;
 933                case VHT_2SSMCS0_2SSMCS9:
 934                        value = rtlphy->txpwr_by_rate_base_24g[path][txnum][5];
 935                        break;
 936                default:
 937                        RT_TRACE(COMP_INIT, DBG_LOUD,
 938                                ("Invalid RateSection %d in Band 2.4G, Rf Path %d,"
 939                                " %dTx in PHY_GetTxPowerByRateBase()\n",
 940                                rate_section, path, txnum));
 941                        break;
 942                };
 943        } else if (band == BAND_ON_5G) {
 944                switch (rate_section) {
 945                case OFDM:
 946                        value = rtlphy->txpwr_by_rate_base_5g[path][txnum][0];
 947                        break;
 948                case HT_MCS0_MCS7:
 949                        value = rtlphy->txpwr_by_rate_base_5g[path][txnum][1];
 950                        break;
 951                case HT_MCS8_MCS15:
 952                        value = rtlphy->txpwr_by_rate_base_5g[path][txnum][2];
 953                        break;
 954                case VHT_1SSMCS0_1SSMCS9:
 955                        value = rtlphy->txpwr_by_rate_base_5g[path][txnum][3];
 956                        break;
 957                case VHT_2SSMCS0_2SSMCS9:
 958                        value = rtlphy->txpwr_by_rate_base_5g[path][txnum][4];
 959                        break;
 960                default:
 961                        RT_TRACE(COMP_INIT, DBG_LOUD,
 962                                ("Invalid RateSection %d in Band 5G, Rf Path %d,"
 963                                " %dTx in PHY_GetTxPowerByRateBase()\n",
 964                                rate_section, path, txnum));
 965                        break;
 966                };
 967        } else {
 968                RT_TRACE(COMP_INIT, DBG_LOUD,
 969                        ("Invalid Band %d in PHY_GetTxPowerByRateBase()\n", band));
 970        }
 971
 972        return value;
 973
 974}
 975void _rtl8821ae_phy_store_txpower_by_rate_base(struct ieee80211_hw *hw)
 976{
 977        struct rtl_priv *rtlpriv = rtl_priv(hw);
 978        struct rtl_phy *rtlphy = &(rtlpriv->phy);
 979        u16 rawValue = 0;
 980        u8 base = 0, path = 0;
 981
 982        for (path = RF90_PATH_A; path <= RF90_PATH_B; ++path) {
 983                rawValue = (u16) (rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][0] >> 24) & 0xFF;
 984                base = (rawValue >> 4) * 10 + (rawValue & 0xF);
 985                _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, CCK, RF_1TX, base);
 986
 987                rawValue = (u16) (rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][2] >> 24) & 0xFF;
 988                base = (rawValue >> 4) * 10 + (rawValue & 0xF);
 989                _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, OFDM, RF_1TX, base );
 990
 991                rawValue = (u16) (rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][4] >> 24) & 0xFF;
 992                base = (rawValue >> 4) * 10 + (rawValue & 0xF);
 993                _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, HT_MCS0_MCS7, RF_1TX, base );
 994
 995                rawValue = (u16) (rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_2TX][6] >> 24) & 0xFF;
 996                base = (rawValue >> 4) * 10 + (rawValue & 0xF);
 997                _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, HT_MCS8_MCS15, RF_2TX, base );
 998
 999                rawValue = (u16) (rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][8] >> 24) & 0xFF;
1000                base = (rawValue >> 4) * 10 + (rawValue & 0xF);

1001                _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, VHT_1SSMCS0_1SSMCS9, RF_1TX, base );
1002
1003                rawValue = (u16) (rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_2TX][11] >> 8) & 0xFF;
1004                base = (rawValue >> 4) * 10 + (rawValue & 0xF);
1005                _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, VHT_2SSMCS0_2SSMCS9, RF_2TX, base );
1006
1007                rawValue = (u16) (rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_1TX][2] >> 24) & 0xFF;
1008                base = (rawValue >> 4) * 10 + (rawValue & 0xF);
1009                _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, OFDM, RF_1TX, base );
1010
1011                rawValue = (u16) (rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_1TX][4] >> 24) & 0xFF;
1012                base = (rawValue >> 4) * 10 + (rawValue & 0xF);
1013                _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, HT_MCS0_MCS7, RF_1TX, base );
1014
1015                rawValue = (u16) (rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_2TX][6] >> 24) & 0xFF;
1016                base = (rawValue >> 4) * 10 + (rawValue & 0xF);
1017                _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, HT_MCS8_MCS15, RF_2TX, base );
1018
1019                rawValue = (u16) (rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_1TX][8] >> 24) & 0xFF;
1020                base = (rawValue >> 4) * 10 + (rawValue & 0xF);
1021                _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, VHT_1SSMCS0_1SSMCS9, RF_1TX, base );
1022
1023                rawValue = (u16) (rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_2TX][11] >> 8) & 0xFF;
1024                base = (rawValue >> 4) * 10 + (rawValue & 0xF);
1025                _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, VHT_2SSMCS0_2SSMCS9, RF_2TX, base );
1026        }
1027}
1028
1029void _phy_convert_txpower_dbm_to_relative_value(u32 *data, u8 start,
1030                                                                                                                                u8 end, u8 base_val)
1031{
1032        char i = 0;
1033        u8 temp_value = 0;
1034        u32 temp_data = 0;
1035
1036        for (i = 3; i >= 0; --i)
1037        {
1038                if (i >= start && i <= end) {
1039                        // Get the exact value
1040                        temp_value = (u8) (*data >> (i * 8)) & 0xF;
1041                        temp_value += ((u8) ((*data >> (i * 8 + 4)) & 0xF)) * 10;
1042
1043                        // Change the value to a relative value
1044                        temp_value = (temp_value > base_val) ? temp_value - base_val : base_val - temp_value;
1045                } else {
1046                        temp_value = (u8) (*data >> (i * 8)) & 0xFF;
1047                }
1048                temp_data <<= 8;
1049                temp_data |= temp_value;
1050        }
1051        *data = temp_data;
1052}
1053
1054void _rtl8821ae_phy_convert_txpower_dbm_to_relative_value(struct ieee80211_hw *hw)
1055{
1056        struct rtl_priv *rtlpriv = rtl_priv(hw);
1057        struct rtl_phy *rtlphy = &(rtlpriv->phy);
1058        u8 base = 0, rfPath = 0;
1059
1060        for (rfPath = RF90_PATH_A; rfPath <= RF90_PATH_B; ++rfPath) {
1061                base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfPath, RF_1TX, CCK);
1062                RT_DISP( FPHY, PHY_TXPWR, ( "base of 2.4G CCK 1TX: %d\n", base ) );
1063                _phy_convert_txpower_dbm_to_relative_value(
1064                        &(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_1TX][0] ),
1065                        0, 3, base );
1066
1067                base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfPath, RF_1TX, OFDM );
1068                RT_DISP( FPHY, PHY_TXPWR, ( "base of 2.4G OFDM 1TX: %d\n", base ) );
1069                _phy_convert_txpower_dbm_to_relative_value(
1070                        &(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_1TX][1] ),
1071                        0, 3, base );
1072                _phy_convert_txpower_dbm_to_relative_value(
1073                        &(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_1TX][2] ),
1074                        0, 3, base );
1075
1076                base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfPath, RF_1TX, HT_MCS0_MCS7 );
1077                RT_DISP( FPHY, PHY_TXPWR, ( "base of 2.4G HTMCS0-7 1TX: %d\n", base ) );
1078                _phy_convert_txpower_dbm_to_relative_value(
1079                        &(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_1TX][3] ),
1080                        0, 3, base );
1081                _phy_convert_txpower_dbm_to_relative_value(
1082                        &(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_1TX][4] ),
1083                        0, 3, base );
1084
1085                base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfPath, RF_2TX, HT_MCS8_MCS15 );
1086                RT_DISP( FPHY, PHY_TXPWR, ( "base of 2.4G HTMCS8-15 2TX: %d\n", base ) );
1087
1088                _phy_convert_txpower_dbm_to_relative_value(
1089                        &(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_2TX][5] ),
1090                        0, 3, base );
1091
1092                _phy_convert_txpower_dbm_to_relative_value(
1093                        &(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_2TX][6] ),
1094                        0, 3, base );
1095
1096                base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfPath, RF_1TX, VHT_1SSMCS0_1SSMCS9 );
1097                RT_DISP( FPHY, PHY_TXPWR, ( "base of 2.4G VHT1SSMCS0-9 1TX: %d\n", base ) );
1098                _phy_convert_txpower_dbm_to_relative_value(
1099                        &(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_1TX][7] ),
1100                        0, 3, base );
1101                _phy_convert_txpower_dbm_to_relative_value(
1102                        &(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_1TX][8] ),
1103                        0, 3, base );
1104                _phy_convert_txpower_dbm_to_relative_value(
1105                        &(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_1TX][9] ),
1106                        0, 1, base );
1107
1108                base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfPath, RF_2TX, VHT_2SSMCS0_2SSMCS9 );
1109                RT_DISP( FPHY, PHY_TXPWR, ( "base of 2.4G VHT2SSMCS0-9 2TX: %d\n", base ) );
1110                _phy_convert_txpower_dbm_to_relative_value(
1111                        &(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_1TX][9] ),
1112                        2, 3, base );
1113                _phy_convert_txpower_dbm_to_relative_value(
1114                        &(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_2TX][10] ),
1115                        0, 3, base );
1116                _phy_convert_txpower_dbm_to_relative_value(
1117                        &(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_2TX][11] ),
1118                        0, 3, base );
1119
1120                base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfPath, RF_1TX, OFDM );
1121                RT_DISP( FPHY, PHY_TXPWR, ( "base of 5G OFDM 1TX: %d\n", base ) );
1122                _phy_convert_txpower_dbm_to_relative_value(
1123                        &(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfPath][RF_1TX][1] ),
1124                        0, 3, base );
1125                _phy_convert_txpower_dbm_to_relative_value(
1126                        &(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfPath][RF_1TX][2] ),
1127                        0, 3, base );
1128
1129                base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfPath, RF_1TX, HT_MCS0_MCS7 );
1130                RT_DISP( FPHY, PHY_TXPWR, ( "base of 5G HTMCS0-7 1TX: %d\n", base ) );
1131                _phy_convert_txpower_dbm_to_relative_value(
1132                        &(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfPath][RF_1TX][3] ),
1133                        0, 3, base );
1134                _phy_convert_txpower_dbm_to_relative_value(
1135                        &(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfPath][RF_1TX][4] ),
1136                        0, 3, base );
1137
1138                base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfPath, RF_2TX, HT_MCS8_MCS15 );
1139                RT_DISP( FPHY, PHY_TXPWR, ( "base of 5G HTMCS8-15 2TX: %d\n", base ) );
1140                _phy_convert_txpower_dbm_to_relative_value(
1141                        &(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfPath][RF_2TX][5] ),
1142                        0, 3, base );
1143                _phy_convert_txpower_dbm_to_relative_value(
1144                        &(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfPath][RF_2TX][6] ),
1145                        0, 3, base );
1146
1147                base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfPath, RF_1TX, VHT_1SSMCS0_1SSMCS9 );
1148                RT_DISP( FPHY, PHY_TXPWR, ( "base of 5G VHT1SSMCS0-9 1TX: %d\n", base ) );
1149                _phy_convert_txpower_dbm_to_relative_value(
1150                        &(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfPath][RF_1TX][7] ),
1151                        0, 3, base );
1152                _phy_convert_txpower_dbm_to_relative_value(
1153                        &(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfPath][RF_1TX][8] ),
1154                        0, 3, base );
1155                _phy_convert_txpower_dbm_to_relative_value(
1156                        &(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfPath][RF_1TX][9] ),
1157                        0, 1, base );
1158
1159                base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfPath, RF_2TX, VHT_2SSMCS0_2SSMCS9 );
1160                RT_DISP( FPHY, PHY_TXPWR, ( "base of 5G VHT2SSMCS0-9 2TX: %d\n", base ) );
1161                _phy_convert_txpower_dbm_to_relative_value(
1162                        &(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfPath][RF_1TX][9] ),
1163                        2, 3, base );
1164                _phy_convert_txpower_dbm_to_relative_value(
1165                        &(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfPath][RF_2TX][10] ),
1166                        0, 3, base );
1167                _phy_convert_txpower_dbm_to_relative_value(
1168                        &(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfPath][RF_2TX][11] ),
1169                        0, 3, base );
1170        }
1171
1172        RT_TRACE(COMP_POWER, DBG_TRACE,
1173                ("<===_rtl8821ae_phy_convert_txpower_dbm_to_relative_value()\n"));
1174
1175}
1176
1177void _rtl8821ae_phy_txpower_by_rate_configuration(struct ieee80211_hw *hw)
1178{
1179        _rtl8821ae_phy_store_txpower_by_rate_base(hw);
1180        _rtl8821ae_phy_convert_txpower_dbm_to_relative_value(hw);
1181}
1182
1183static bool _rtl8821ae_phy_bb8821a_config_parafile(struct ieee80211_hw *hw)
1184{
1185        struct rtl_priv *rtlpriv = rtl_priv(hw);
1186        struct rtl_phy *rtlphy = &(rtlpriv->phy);
1187        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1188        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1189        bool rtstatus;
1190
1191        /*TX POWER LIMIT
1192            PHY_InitTxPowerLimit
1193            PHY_ConfigRFWithCustomPowerLimitTableParaFile*/
1194        if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
1195                rtstatus = _rtl8812ae_phy_config_bb_with_headerfile(hw,
1196                                                                BASEBAND_CONFIG_PHY_REG);
1197        else{
1198                rtstatus = _rtl8821ae_phy_config_bb_with_headerfile(hw,
1199                                                                BASEBAND_CONFIG_PHY_REG);
1200        }
1201        if (rtstatus != true) {
1202                RT_TRACE(COMP_ERR, DBG_EMERG, ("Write BB Reg Fail!!"));
1203                return false;
1204        }
1205        _rtl8821ae_phy_init_tx_power_by_rate(hw);
1206        if (rtlefuse->autoload_failflag == false) {
1207                //rtlphy->pwrgroup_cnt = 0;
1208                if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
1209                        rtstatus = _rtl8812ae_phy_config_bb_with_pgheaderfile(hw,
1210                                                                   BASEBAND_CONFIG_PHY_REG);
1211                else{
1212                        rtstatus = _rtl8821ae_phy_config_bb_with_pgheaderfile(hw,
1213                                                                   BASEBAND_CONFIG_PHY_REG);
1214                }
1215        }
1216        if (rtstatus != true) {
1217                RT_TRACE(COMP_ERR, DBG_EMERG, ("BB_PG Reg Fail!!"));
1218                return false;
1219        }
1220
1221        _rtl8821ae_phy_txpower_by_rate_configuration(hw);
1222
1223        if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
1224                rtstatus = _rtl8812ae_phy_config_bb_with_headerfile(hw,
1225                                                         BASEBAND_CONFIG_AGC_TAB);
1226        else
1227                rtstatus = _rtl8821ae_phy_config_bb_with_headerfile(hw,
1228                                                         BASEBAND_CONFIG_AGC_TAB);
1229
1230        if (rtstatus != true) {
1231                RT_TRACE(COMP_ERR, DBG_EMERG, ("AGC Table Fail\n"));
1232                return false;
1233        }
1234        rtlphy->bcck_high_power = (bool) (rtl_get_bbreg(hw,
1235                                                        RFPGA0_XA_HSSIPARAMETER2,
1236                                                        0x200));
1237        return true;
1238}
1239
1240static bool _rtl8812ae_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
1241{
1242        struct rtl_priv *rtlpriv = rtl_priv(hw);
1243        u32 i, v1, v2;
1244        u32 arraylength;
1245        u32 *ptrarray;
1246
1247        RT_TRACE(COMP_INIT, DBG_TRACE, ("Read rtl8812AE_MAC_REG_Array\n"));
1248        arraylength = RTL8812AEMAC_1T_ARRAYLEN;
1249        ptrarray = RTL8812AE_MAC_REG_ARRAY;
1250        RT_TRACE(COMP_INIT, DBG_LOUD,
1251                 ("Img:RTL8812AE_MAC_REG_ARRAY LEN %d\n",arraylength));
1252        for (i = 0; i < arraylength; i += 2) {
1253                v1 = ptrarray[i];
1254                v2 = (u8) ptrarray[i + 1];
1255                if (v1<0xCDCDCDCD) {
1256                        rtl_write_byte(rtlpriv, v1, (u8) v2);
1257                } else {
1258                        if (!_rtl8821ae_check_condition(hw,v1)) {
1259                                /*Discard the following (offset, data) pairs*/
1260                                READ_NEXT_PAIR(ptrarray, v1, v2, i);
1261                                while (v2 != 0xDEAD &&
1262                                           v2 != 0xCDEF &&
1263                                           v2 != 0xCDCD && i < arraylength -2)
1264                                        READ_NEXT_PAIR(ptrarray, v1, v2, i);
1265
1266                                i -= 2; /* prevent from for-loop += 2*/
1267                        } else {/*Configure matched pairs and skip to end of if-else.*/
1268                                READ_NEXT_PAIR(ptrarray, v1, v2, i);
1269                                while (v2 != 0xDEAD &&
1270                                           v2 != 0xCDEF &&
1271                                           v2 != 0xCDCD && i < arraylength -2) {
1272                                        rtl_write_byte(rtlpriv,v1,v2);
1273                                        READ_NEXT_PAIR(ptrarray, v1, v2, i);
1274                                }
1275
1276                                while (v2 != 0xDEAD && i < arraylength -2)
1277                                        READ_NEXT_PAIR(ptrarray, v1, v2, i);
1278                        }
1279                }
1280        }
1281        return true;
1282}
1283
1284static bool _rtl8821ae_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
1285{
1286        struct rtl_priv *rtlpriv = rtl_priv(hw);
1287        u32 i, v1, v2;
1288        u32 arraylength;
1289        u32 *ptrarray;
1290
1291        RT_TRACE(COMP_INIT, DBG_TRACE, ("Read rtl8821AE_MAC_REG_Array\n"));
1292        arraylength = RTL8821AEMAC_1T_ARRAYLEN;
1293        ptrarray = RTL8821AE_MAC_REG_ARRAY;
1294        RT_TRACE(COMP_INIT, DBG_LOUD,
1295                 ("Img:RTL8821AE_MAC_REG_ARRAY LEN %d\n",arraylength));
1296        for (i = 0; i < arraylength; i += 2) {
1297                v1 = ptrarray[i];
1298                v2 = (u8) ptrarray[i + 1];
1299                if (v1<0xCDCDCDCD) {
1300                        rtl_write_byte(rtlpriv, v1, (u8) v2);
1301                        continue;
1302                } else {
1303                        if (!_rtl8821ae_check_condition(hw,v1)) {
1304                                /*Discard the following (offset, data) pairs*/
1305                                READ_NEXT_PAIR(ptrarray, v1, v2, i);
1306                                while (v2 != 0xDEAD &&
1307                                           v2 != 0xCDEF &&
1308                                           v2 != 0xCDCD && i < arraylength -2)
1309                                        READ_NEXT_PAIR(ptrarray, v1, v2, i);
1310
1311                                i -= 2; /* prevent from for-loop += 2*/
1312                        } else {/*Configure matched pairs and skip to end of if-else.*/
1313                                READ_NEXT_PAIR(ptrarray, v1, v2, i);
1314                                while (v2 != 0xDEAD &&
1315                                           v2 != 0xCDEF &&
1316                                           v2 != 0xCDCD && i < arraylength -2) {
1317                                        rtl_write_byte(rtlpriv,v1,v2);
1318                                        READ_NEXT_PAIR(ptrarray, v1, v2, i);
1319                                }
1320
1321                                while (v2 != 0xDEAD && i < arraylength -2)
1322                                        READ_NEXT_PAIR(ptrarray, v1, v2, i);
1323                        }
1324                }
1325        }
1326        return true;
1327}
1328
1329static bool _rtl8812ae_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
1330                                                  u8 configtype)
1331{
1332        int i;
1333        u32 *array_table;
1334        u16 arraylen;
1335        struct rtl_priv *rtlpriv = rtl_priv(hw);
1336        u32 v1 = 0, v2 = 0;
1337
1338        if (configtype == BASEBAND_CONFIG_PHY_REG) {
1339                arraylen = RTL8812AEPHY_REG_1TARRAYLEN;
1340                array_table = RTL8812AE_PHY_REG_ARRAY;
1341
1342                for (i = 0; i < arraylen; i += 2) {
1343                        v1 = array_table[i];
1344                        v2 = array_table[i+1];
1345                        if (v1<0xCDCDCDCD) {
1346                                _rtl8812ae_config_bb_reg(hw, v1, v2);
1347                                continue;
1348                        } else {/*This line is the start line of branch.*/
1349                                if (!_rtl8821ae_check_condition(hw,v1)) {
1350                                        /*Discard the following (offset, data) pairs*/
1351                                        READ_NEXT_PAIR(array_table,v1, v2, i);
1352                                        while (v2 != 0xDEAD &&
1353                                               v2 != 0xCDEF &&
1354                                               v2 != 0xCDCD && i < arraylen -2)
1355                                            READ_NEXT_PAIR(array_table,v1, v2, i);
1356
1357                                        i -= 2; /* prevent from for-loop += 2*/
1358                                } else {/*Configure matched pairs and skip to end of if-else.*/
1359                                        READ_NEXT_PAIR(array_table,v1, v2, i);
1360                                        while (v2 != 0xDEAD &&
1361                                               v2 != 0xCDEF &&
1362                                               v2 != 0xCDCD && i < arraylen -2) {
1363                                                _rtl8812ae_config_bb_reg(hw,v1,v2);
1364                                                READ_NEXT_PAIR(array_table,v1, v2, i);
1365                                        }
1366
1367                                        while (v2 != 0xDEAD && i < arraylen -2)
1368                                                READ_NEXT_PAIR(array_table,v1, v2, i);
1369                                }
1370                        }
1371                }
1372        } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
1373                        arraylen = RTL8812AEAGCTAB_1TARRAYLEN;
1374                        array_table = RTL8812AE_AGC_TAB_ARRAY;
1375
1376                        for (i = 0; i < arraylen; i = i + 2) {
1377                                v1 = array_table[i];
1378                                v2 = array_table[i+1];
1379                                if (v1 < 0xCDCDCDCD) {
1380                                        rtl_set_bbreg(hw, v1, MASKDWORD, v2);
1381                                        udelay(1);
1382                                        continue;
1383                            } else {/*This line is the start line of branch.*/
1384                                        if (!_rtl8821ae_check_condition(hw,v1)) {
1385                                                /*Discard the following (offset, data) pairs*/
1386                                                READ_NEXT_PAIR(array_table,v1, v2, i);
1387                                                while (v2 != 0xDEAD &&
1388                                                       v2 != 0xCDEF &&
1389                                                       v2 != 0xCDCD && i < arraylen -2)
1390                                                    READ_NEXT_PAIR(array_table,v1, v2, i);
1391
1392                                                i -= 2; /* prevent from for-loop += 2*/
1393                                        }else{/*Configure matched pairs and skip to end of if-else.*/
1394                                                READ_NEXT_PAIR(array_table,v1, v2, i);
1395                                                while (v2 != 0xDEAD &&
1396                                                       v2 != 0xCDEF &&
1397                                                       v2 != 0xCDCD && i < arraylen -2)
1398                                                {
1399                                                        rtl_set_bbreg(hw, v1, MASKDWORD, v2);
1400                                                        udelay(1);
1401                                                        READ_NEXT_PAIR(array_table,v1, v2, i);
1402                                                }
1403
1404                                                while (v2 != 0xDEAD && i < arraylen -2)
1405                                                        READ_NEXT_PAIR(array_table,v1, v2, i);
1406                                        }
1407                                }
1408                                RT_TRACE(COMP_INIT, DBG_TRACE,
1409                                 ("The agctab_array_table[0] is "
1410                                  "%x Rtl818EEPHY_REGArray[1] is %x \n",
1411                                  array_table[i],
1412                                  array_table[i + 1]));
1413                }
1414        }
1415        return true;
1416}
1417
1418static bool _rtl8821ae_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
1419                                                  u8 configtype)
1420{
1421        int i;
1422        u32 *array_table;
1423        u16 arraylen;
1424        struct rtl_priv *rtlpriv = rtl_priv(hw);
1425        u32 v1 = 0, v2 = 0;
1426
1427        if (configtype == BASEBAND_CONFIG_PHY_REG) {
1428                arraylen = RTL8821AEPHY_REG_1TARRAYLEN;
1429                array_table = RTL8821AE_PHY_REG_ARRAY;
1430
1431                for (i = 0; i < arraylen; i += 2) {
1432                        v1 = array_table[i];
1433                        v2 = array_table[i+1];
1434                        if (v1<0xCDCDCDCD) {
1435                                _rtl8821ae_config_bb_reg(hw, v1, v2);
1436                                continue;
1437                        } else {/*This line is the start line of branch.*/
1438                                if (!_rtl8821ae_check_condition(hw,v1)) {
1439                                        /*Discard the following (offset, data) pairs*/
1440                                        READ_NEXT_PAIR(array_table, v1, v2, i);
1441                                        while (v2 != 0xDEAD &&
1442                                               v2 != 0xCDEF &&
1443                                               v2 != 0xCDCD && i < arraylen -2)
1444                                            READ_NEXT_PAIR(array_table, v1, v2, i);
1445
1446                                        i -= 2; /* prevent from for-loop += 2*/
1447                                } else {/*Configure matched pairs and skip to end of if-else.*/
1448                                        READ_NEXT_PAIR(array_table, v1, v2, i);
1449                                        while (v2 != 0xDEAD &&
1450                                               v2 != 0xCDEF &&
1451                                               v2 != 0xCDCD && i < arraylen -2) {
1452                                                _rtl8821ae_config_bb_reg(hw,v1,v2);
1453                                                READ_NEXT_PAIR(array_table, v1, v2, i);
1454                                        }
1455
1456                                        while (v2 != 0xDEAD && i < arraylen -2)
1457                                                READ_NEXT_PAIR(array_table, v1, v2, i);
1458                                }
1459                        }
1460                }
1461        } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
1462                        arraylen = RTL8821AEAGCTAB_1TARRAYLEN;
1463                        array_table = RTL8821AE_AGC_TAB_ARRAY;
1464
1465                        for (i = 0; i < arraylen; i = i + 2) {
1466                                v1 = array_table[i];
1467                                v2 = array_table[i+1];
1468                                if (v1 < 0xCDCDCDCD) {
1469                                        rtl_set_bbreg(hw, v1, MASKDWORD, v2);
1470                                        udelay(1);
1471                                        continue;
1472                            } else {/*This line is the start line of branch.*/
1473                                        if (!_rtl8821ae_check_condition(hw,v1)) {
1474                                                /*Discard the following (offset, data) pairs*/
1475                                                READ_NEXT_PAIR(array_table, v1, v2, i);
1476                                                while (v2 != 0xDEAD &&
1477                                                       v2 != 0xCDEF &&
1478                                                       v2 != 0xCDCD && i < arraylen -2)
1479                                                    READ_NEXT_PAIR(array_table, v1, v2, i);
1480
1481                                                i -= 2; /* prevent from for-loop += 2*/
1482                                        }else{/*Configure matched pairs and skip to end of if-else.*/
1483                                                READ_NEXT_PAIR(array_table, v1, v2, i);
1484                                                while (v2 != 0xDEAD &&
1485                                                       v2 != 0xCDEF &&
1486                                                       v2 != 0xCDCD && i < arraylen -2)
1487                                                {
1488                                                        rtl_set_bbreg(hw, v1, MASKDWORD, v2);
1489                                                        udelay(1);
1490                                                        READ_NEXT_PAIR(array_table, v1, v2, i);
1491                                                }
1492
1493                                                while (v2 != 0xDEAD && i < arraylen -2)
1494                                                        READ_NEXT_PAIR(array_table, v1, v2, i);
1495                                        }
1496                                }
1497                                RT_TRACE(COMP_INIT, DBG_TRACE,
1498                                 ("The agctab_array_table[0] is "
1499                                  "%x Rtl818EEPHY_REGArray[1] is %x \n",
1500                                  array_table[i],
1501                                  array_table[i + 1]));
1502                }
1503        }
1504        return true;
1505}
1506
1507static u8 _rtl8821ae_get_rate_selection_index(u32 regaddr)
1508{
1509        u8 index = 0;
1510
1511        regaddr &= 0xFFF;
1512        if (regaddr >= 0xC20 && regaddr <= 0xC4C)
1513                index = (u8) ((regaddr - 0xC20) / 4);
1514        else if (regaddr >= 0xE20 && regaddr <= 0xE4C)
1515                index = (u8) ((regaddr - 0xE20) / 4);
1516        else
1517                RT_ASSERT(!COMP_INIT,
1518                        ("Invalid RegAddr 0x%x in"
1519                         "PHY_GetRateSectionIndexOfTxPowerByRate()\n",regaddr));
1520
1521        return index;
1522}
1523
1524static void _rtl8821ae_store_tx_power_by_rate(struct ieee80211_hw *hw,
1525                                                                                                                 u32 band, u32 rfpath,
1526                                                                                                                 u32 txnum, u32 regaddr,
1527                                                                                                                 u32 bitmask, u32 data)
1528{
1529        struct rtl_priv *rtlpriv = rtl_priv(hw);
1530        struct rtl_phy *rtlphy = &(rtlpriv->phy);
1531        u8 rate_section = _rtl8821ae_get_rate_selection_index(regaddr);
1532
1533        if (band != BAND_ON_2_4G && band != BAND_ON_5G)
1534                RT_TRACE(COMP_INIT, DBG_WARNING, ("Invalid Band %d\n", band));
1535
1536        if (rfpath > MAX_RF_PATH)
1537                RT_TRACE(COMP_INIT, DBG_WARNING, ("Invalid RfPath %d\n", rfpath));
1538
1539        if (txnum > MAX_RF_PATH)
1540                RT_TRACE(COMP_INIT, DBG_WARNING, ("Invalid TxNum %d\n", txnum ) );
1541
1542        rtlphy->tx_power_by_rate_offset[band][rfpath][txnum][rate_section] = data;
1543        RT_TRACE(COMP_INIT, DBG_WARNING,( "pHalData->TxPwrByRateOffset[Band %d][RfPath %d][TxNum %d][RateSection %d] = 0x%x\n",
1544                        band, rfpath, txnum, rate_section, rtlphy->tx_power_by_rate_offset[band][rfpath][txnum][rate_section]));
1545
1546}
1547
1548static bool _rtl8812ae_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
1549                                                                                                                                         u8 configtype)
1550{
1551        struct rtl_priv *rtlpriv = rtl_priv(hw);
1552        int i;
1553        u32 *phy_regarray_table_pg;
1554        u16 phy_regarray_pg_len;
1555        u32 v1, v2, v3, v4, v5, v6;
1556
1557        phy_regarray_pg_len = RTL8812AEPHY_REG_ARRAY_PGLEN;
1558        phy_regarray_table_pg = RTL8812AE_PHY_REG_ARRAY_PG;
1559
1560        if (configtype == BASEBAND_CONFIG_PHY_REG) {
1561                for (i = 0; i < phy_regarray_pg_len; i += 6) {
1562                        v1 = phy_regarray_table_pg[i];
1563                        v2 = phy_regarray_table_pg[i+1];
1564                        v3 = phy_regarray_table_pg[i+2];
1565                        v4 = phy_regarray_table_pg[i+3];
1566                        v5 = phy_regarray_table_pg[i+4];
1567                        v6 = phy_regarray_table_pg[i+5];
1568
1569                        if (v1<0xCDCDCDCD) {
1570                                if ( (v4 == 0xfe) || (v4 == 0xffe))
1571                                        mdelay(50);
1572                                else
1573                                        /*_rtl8821ae_store_pwrIndex_diffrate_offset*/
1574                                        _rtl8821ae_store_tx_power_by_rate(hw, v1, v2, v3, v4, v5, v6);
1575                                continue;
1576                        } else {
1577                                if (!_rtl8821ae_check_condition(hw,v1)) { /*don't need the hw_body*/
1578                                i += 2; /* skip the pair of expression*/
1579                                v1 = phy_regarray_table_pg[i];
1580                                v2 = phy_regarray_table_pg[i+1];
1581                                v3 = phy_regarray_table_pg[i+2];
1582                                while (v2 != 0xDEAD) {
1583                                    i += 3;
1584                                    v1 = phy_regarray_table_pg[i];
1585                                    v2 = phy_regarray_table_pg[i+1];
1586                                    v3 = phy_regarray_table_pg[i+2];
1587                                }
1588                            }
1589                        }
1590                }
1591        } else {
1592
1593                RT_TRACE(COMP_SEND, DBG_TRACE,
1594                         ("configtype != BaseBand_Config_PHY_REG\n"));
1595        }
1596        return true;
1597}
1598
1599static bool _rtl8821ae_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
1600                                                                                                                                         u8 configtype)
1601{
1602        struct rtl_priv *rtlpriv = rtl_priv(hw);
1603        int i;
1604        u32 *phy_regarray_table_pg;
1605        u16 phy_regarray_pg_len;
1606        u32 v1, v2, v3, v4, v5, v6;
1607
1608        phy_regarray_pg_len = RTL8821AEPHY_REG_ARRAY_PGLEN;
1609        phy_regarray_table_pg = RTL8821AE_PHY_REG_ARRAY_PG;
1610
1611        if (configtype == BASEBAND_CONFIG_PHY_REG) {
1612                for (i = 0; i < phy_regarray_pg_len; i += 6) {
1613                        v1 = phy_regarray_table_pg[i];
1614                        v2 = phy_regarray_table_pg[i+1];
1615                        v3 = phy_regarray_table_pg[i+2];
1616                        v4 = phy_regarray_table_pg[i+3];
1617                        v5 = phy_regarray_table_pg[i+4];
1618                        v6 = phy_regarray_table_pg[i+5];
1619
1620                        if (v1<0xCDCDCDCD) {
1621                                if (v4 == 0xfe)
1622                                        mdelay(50);
1623                                else if (v4 == 0xfd)
1624                                        mdelay(5);
1625                                else if (v4 == 0xfc)
1626                                        mdelay(1);
1627                                else if (v4 == 0xfb)
1628                                        udelay(50);
1629                                else if (v4 == 0xfa)
1630                                        udelay(5);
1631                                else if (v4 == 0xf9)
1632                                        udelay(1);
1633
1634                                /*_rtl8821ae_store_pwrIndex_diffrate_offset*/
1635                                _rtl8821ae_store_tx_power_by_rate(hw, v1, v2, v3, v4, v5, v6);
1636                                continue;
1637                        } else {
1638                                if (!_rtl8821ae_check_condition(hw,v1)) { /*don't need the hw_body*/
1639                                i += 2; /* skip the pair of expression*/
1640                                v1 = phy_regarray_table_pg[i];
1641                                v2 = phy_regarray_table_pg[i+1];
1642                                v3 = phy_regarray_table_pg[i+2];
1643                                while (v2 != 0xDEAD) {
1644                                    i += 3;
1645                                    v1 = phy_regarray_table_pg[i];
1646                                    v2 = phy_regarray_table_pg[i+1];
1647                                    v3 = phy_regarray_table_pg[i+2];
1648                                }
1649                            }
1650                        }
1651                }
1652        } else {
1653
1654                RT_TRACE(COMP_SEND, DBG_TRACE,
1655                         ("configtype != BaseBand_Config_PHY_REG\n"));
1656        }
1657        return true;
1658}
1659
1660bool rtl8812ae_phy_config_rf_with_headerfile(struct ieee80211_hw * hw,
1661                                                                                                                 enum radio_path rfpath)
1662{
1663        #define READ_NEXT_RF_PAIR_8812(radioa_array_table,v1, v2, i) do { i += 2; v1 = radioa_array_table[i]; v2 = radioa_array_table[i+1]; } while(0)
1664
1665        int i;
1666        bool rtstatus = true;
1667        u32 *radioa_array_table_a, *radioa_array_table_b;
1668        u16 radioa_arraylen_a, radioa_arraylen_b;
1669        struct rtl_priv *rtlpriv = rtl_priv(hw);
1670        u32 v1 = 0, v2 = 0;
1671
1672        radioa_arraylen_a = RTL8812AE_RADIOA_1TARRAYLEN;
1673        radioa_array_table_a= RTL8812AE_RADIOA_ARRAY;
1674        radioa_arraylen_b= RTL8812AE_RADIOB_1TARRAYLEN;
1675        radioa_array_table_b = RTL8812AE_RADIOB_ARRAY;
1676        RT_TRACE(COMP_INIT, DBG_LOUD,
1677                 ("Radio_A:RTL8821AE_RADIOA_ARRAY %d\n",radioa_arraylen_a));
1678        RT_TRACE(COMP_INIT, DBG_LOUD, ("Radio No %x\n", rfpath));
1679        rtstatus = true;
1680        switch (rfpath) {
1681        case RF90_PATH_A:
1682                for (i = 0; i < radioa_arraylen_a; i = i + 2) {
1683                        v1 = radioa_array_table_a[i];
1684                        v2 = radioa_array_table_a[i+1];
1685                        if (v1<0xcdcdcdcd) {
1686                                _rtl8821ae_config_rf_radio_a(hw,v1,v2);
1687                                continue;
1688                        }else{/*This line is the start line of branch.*/
1689                                if(!_rtl8821ae_check_condition(hw,v1)){
1690                                        /*Discard the following (offset, data) pairs*/
1691                                        READ_NEXT_RF_PAIR_8812(radioa_array_table_a,v1, v2, i);
1692                                        while (v2 != 0xDEAD &&
1693                                               v2 != 0xCDEF &&
1694                                               v2 != 0xCDCD && i < radioa_arraylen_a-2)
1695                                            READ_NEXT_RF_PAIR_8812(radioa_array_table_a,v1, v2, i);
1696
1697                                        i -= 2; /* prevent from for-loop += 2*/
1698                                } else {/*Configure matched pairs and skip to end of if-else.*/
1699                                        READ_NEXT_RF_PAIR_8812(radioa_array_table_a,v1, v2, i);
1700                                        while (v2 != 0xDEAD &&
1701                                               v2 != 0xCDEF &&
1702                                               v2 != 0xCDCD && i < radioa_arraylen_a -2) {
1703                                                _rtl8821ae_config_rf_radio_a(hw,v1,v2);
1704                                                READ_NEXT_RF_PAIR_8812(radioa_array_table_a,v1, v2, i);
1705                                        }
1706
1707                                        while (v2 != 0xDEAD && i < radioa_arraylen_a-2)
1708                                                READ_NEXT_RF_PAIR_8812(radioa_array_table_a,v1, v2, i);
1709                                }
1710                        }
1711                }
1712                break;
1713        case RF90_PATH_B:
1714                for (i = 0; i < radioa_arraylen_b; i = i + 2) {
1715                        v1 = radioa_array_table_b[i];
1716                        v2 = radioa_array_table_b[i+1];
1717                        if (v1<0xcdcdcdcd) {
1718                                _rtl8821ae_config_rf_radio_b(hw,v1,v2);
1719                                continue;
1720                        }else{/*This line is the start line of branch.*/
1721                                if(!_rtl8821ae_check_condition(hw,v1)){
1722                                        /*Discard the following (offset, data) pairs*/
1723                                        READ_NEXT_RF_PAIR_8812(radioa_array_table_b,v1, v2, i);
1724                                        while (v2 != 0xDEAD &&
1725                                               v2 != 0xCDEF &&
1726                                               v2 != 0xCDCD && i < radioa_arraylen_b-2)
1727                                            READ_NEXT_RF_PAIR_8812(radioa_array_table_b,v1, v2, i);
1728
1729                                        i -= 2; /* prevent from for-loop += 2*/
1730                                } else {/*Configure matched pairs and skip to end of if-else.*/
1731                                        READ_NEXT_RF_PAIR_8812(radioa_array_table_b,v1, v2, i);
1732                                        while (v2 != 0xDEAD &&
1733                                               v2 != 0xCDEF &&
1734                                               v2 != 0xCDCD && i < radioa_arraylen_b-2) {
1735                                                _rtl8821ae_config_rf_radio_b(hw,v1,v2);
1736                                                READ_NEXT_RF_PAIR_8812(radioa_array_table_b,v1, v2, i);
1737                                        }
1738
1739                                        while (v2 != 0xDEAD && i < radioa_arraylen_b-2)
1740                                                READ_NEXT_RF_PAIR_8812(radioa_array_table_b,v1, v2, i);
1741                                }
1742                        }
1743                }
1744                break;
1745        case RF90_PATH_C:
1746                RT_TRACE(COMP_ERR, DBG_EMERG,
1747                         ("switch case not process \n"));
1748                break;
1749        case RF90_PATH_D:
1750                RT_TRACE(COMP_ERR, DBG_EMERG,
1751                         ("switch case not process \n"));
1752                break;
1753        }
1754        return true;
1755}
1756
1757
1758bool rtl8821ae_phy_config_rf_with_headerfile(struct ieee80211_hw * hw,
1759                                                                                                                 enum radio_path rfpath)
1760{
1761        #define READ_NEXT_RF_PAIR(v1, v2, i) do { i += 2; v1 = radioa_array_table[i]; v2 = radioa_array_table[i+1]; } while(0)
1762
1763        int i;
1764        bool rtstatus = true;
1765        u32 *radioa_array_table;
1766        u16 radioa_arraylen;
1767        struct rtl_priv *rtlpriv = rtl_priv(hw);
1768        //struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1769        u32 v1 = 0, v2 = 0;
1770
1771        radioa_arraylen = RTL8821AE_RADIOA_1TARRAYLEN;
1772        radioa_array_table = RTL8821AE_RADIOA_ARRAY;
1773        RT_TRACE(COMP_INIT, DBG_LOUD,
1774                 ("Radio_A:RTL8821AE_RADIOA_ARRAY %d\n",radioa_arraylen));
1775        RT_TRACE(COMP_INIT, DBG_LOUD, ("Radio No %x\n", rfpath));
1776        rtstatus = true;
1777        switch (rfpath) {
1778        case RF90_PATH_A:
1779                for (i = 0; i < radioa_arraylen; i = i + 2) {
1780                        v1 = radioa_array_table[i];
1781                        v2 = radioa_array_table[i+1];
1782                        if (v1<0xcdcdcdcd) {
1783                                _rtl8821ae_config_rf_radio_a(hw,v1,v2);
1784                        }else{/*This line is the start line of branch.*/
1785                                if(!_rtl8821ae_check_condition(hw,v1)){
1786                                        /*Discard the following (offset, data) pairs*/
1787                                        READ_NEXT_RF_PAIR(v1, v2, i);
1788                                        while (v2 != 0xDEAD &&
1789                                               v2 != 0xCDEF &&
1790                                               v2 != 0xCDCD && i < radioa_arraylen -2)
1791                                            READ_NEXT_RF_PAIR(v1, v2, i);
1792
1793                                        i -= 2; /* prevent from for-loop += 2*/
1794                                } else {/*Configure matched pairs and skip to end of if-else.*/
1795                                        READ_NEXT_RF_PAIR(v1, v2, i);
1796                                        while (v2 != 0xDEAD &&
1797                                               v2 != 0xCDEF &&
1798                                               v2 != 0xCDCD && i < radioa_arraylen -2) {
1799                                                _rtl8821ae_config_rf_radio_a(hw,v1,v2);
1800                                                READ_NEXT_RF_PAIR(v1, v2, i);
1801                                        }
1802
1803                                        while (v2 != 0xDEAD && i < radioa_arraylen -2)
1804                                                READ_NEXT_RF_PAIR(v1, v2, i);
1805                                }
1806                        }
1807                }
1808                break;
1809
1810        case RF90_PATH_B:
1811                RT_TRACE(COMP_ERR, DBG_EMERG,
1812                         ("switch case not process \n"));
1813                break;
1814        case RF90_PATH_C:
1815                RT_TRACE(COMP_ERR, DBG_EMERG,
1816                         ("switch case not process \n"));
1817                break;
1818        case RF90_PATH_D:
1819                RT_TRACE(COMP_ERR, DBG_EMERG,
1820                         ("switch case not process \n"));
1821                break;
1822        }
1823        return true;
1824}
1825
1826void rtl8821ae_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
1827{
1828        struct rtl_priv *rtlpriv = rtl_priv(hw);
1829        struct rtl_phy *rtlphy = &(rtlpriv->phy);
1830
1831        rtlphy->default_initialgain[0] =
1832            (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
1833        rtlphy->default_initialgain[1] =
1834            (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
1835        rtlphy->default_initialgain[2] =
1836            (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
1837        rtlphy->default_initialgain[3] =
1838            (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
1839
1840        RT_TRACE(COMP_INIT, DBG_TRACE,
1841                 ("Default initial gain (c50=0x%x, "
1842                  "c58=0x%x, c60=0x%x, c68=0x%x \n",
1843                  rtlphy->default_initialgain[0],
1844                  rtlphy->default_initialgain[1],
1845                  rtlphy->default_initialgain[2],
1846                  rtlphy->default_initialgain[3]));
1847
1848        rtlphy->framesync = (u8) rtl_get_bbreg(hw,
1849                                               ROFDM0_RXDETECTOR3, MASKBYTE0);
1850        rtlphy->framesync_c34 = rtl_get_bbreg(hw,
1851                                              ROFDM0_RXDETECTOR2, MASKDWORD);
1852
1853        RT_TRACE(COMP_INIT, DBG_TRACE,
1854                 ("Default framesync (0x%x) = 0x%x \n",
1855                  ROFDM0_RXDETECTOR3, rtlphy->framesync));
1856}
1857
1858static void _rtl8821ae_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
1859{
1860        struct rtl_priv *rtlpriv = rtl_priv(hw);
1861        struct rtl_phy *rtlphy = &(rtlpriv->phy);
1862
1863        rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
1864        rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
1865
1866        rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
1867        rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
1868
1869        rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
1870        rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
1871
1872        rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset = RA_LSSIWRITE_8821A;
1873        rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset = RB_LSSIWRITE_8821A;
1874
1875        rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RHSSIREAD_8821AE;
1876        rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RHSSIREAD_8821AE;
1877
1878        rtlphy->phyreg_def[RF90_PATH_A].rflssi_readback = RA_SIREAD_8821A;
1879        rtlphy->phyreg_def[RF90_PATH_B].rflssi_readback = RB_SIREAD_8821A;
1880
1881        rtlphy->phyreg_def[RF90_PATH_A].rflssi_readbackpi = RA_PIREAD_8821A;
1882        rtlphy->phyreg_def[RF90_PATH_B].rflssi_readbackpi = RB_PIREAD_8821A;
1883}
1884
1885void rtl8821ae_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
1886{
1887        struct rtl_priv *rtlpriv = rtl_priv(hw);
1888        struct rtl_phy *rtlphy = &(rtlpriv->phy);
1889        u8 txpwr_level;
1890        long txpwr_dbm;
1891
1892        txpwr_level = rtlphy->cur_cck_txpwridx;
1893        txpwr_dbm = _rtl8821ae_phy_txpwr_idx_to_dbm(hw,
1894                                                 WIRELESS_MODE_B, txpwr_level);
1895        txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
1896        if (_rtl8821ae_phy_txpwr_idx_to_dbm(hw,
1897                                         WIRELESS_MODE_G,
1898                                         txpwr_level) > txpwr_dbm)
1899                txpwr_dbm =
1900                    _rtl8821ae_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
1901                                                 txpwr_level);
1902        txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
1903        if (_rtl8821ae_phy_txpwr_idx_to_dbm(hw,
1904                                         WIRELESS_MODE_N_24G,
1905                                         txpwr_level) > txpwr_dbm)
1906                txpwr_dbm =
1907                    _rtl8821ae_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
1908                                                 txpwr_level);
1909        *powerlevel = txpwr_dbm;
1910}
1911
1912static bool _rtl8821ae_phy_get_chnl_index(u8 channel, u8 *chnl_index)
1913{
1914        u8 channel_5g[CHANNEL_MAX_NUMBER_5G] =
1915                                 {36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,100,102,104,106,108,110,112,
1916                                114,116,118,120,122,124,126,128,130,132,134,136,138,140,142,144,149,151,
1917                                153,155,157,159,161,163,165,167,168,169,171,173,175,177};
1918        u8 i = 0;
1919        bool in_24g = true;
1920
1921        if (channel <= 14) {
1922                in_24g = true;
1923                *chnl_index = channel - 1;
1924        } else {
1925                in_24g = false;
1926
1927                for (i = 0; i < sizeof(channel_5g) / sizeof(u8); ++i) {
1928                        if (channel_5g[i] == channel) {
1929                                *chnl_index = i;
1930                                return in_24g;
1931                        }
1932                }
1933        }
1934        return in_24g;
1935}
1936
1937static char _rtl8821ae_phy_get_ratesection_intxpower_byrate(u8 path, u8 rate)
1938{
1939        char rate_section = 0;
1940        switch (rate) {
1941        case DESC_RATE1M:
1942        case DESC_RATE2M:
1943        case DESC_RATE5_5M:
1944        case DESC_RATE11M:
1945                rate_section = 0;
1946                break;
1947
1948        case DESC_RATE6M:
1949        case DESC_RATE9M:
1950        case DESC_RATE12M:
1951        case DESC_RATE18M:
1952                rate_section = 1;
1953                break;
1954
1955        case DESC_RATE24M:
1956        case DESC_RATE36M:
1957        case DESC_RATE48M:
1958        case DESC_RATE54M:
1959                rate_section = 2;
1960                break;
1961
1962        case DESC_RATEMCS0:
1963        case DESC_RATEMCS1:
1964        case DESC_RATEMCS2:
1965        case DESC_RATEMCS3:
1966                rate_section = 3;
1967                break;
1968
1969        case DESC_RATEMCS4:
1970        case DESC_RATEMCS5:
1971        case DESC_RATEMCS6:
1972        case DESC_RATEMCS7:
1973                rate_section = 4;
1974                break;
1975
1976        case DESC_RATEMCS8:
1977        case DESC_RATEMCS9:
1978        case DESC_RATEMCS10:
1979        case DESC_RATEMCS11:
1980                rate_section = 5;
1981                break;
1982
1983        case DESC_RATEMCS12:
1984        case DESC_RATEMCS13:
1985        case DESC_RATEMCS14:
1986        case DESC_RATEMCS15:
1987                rate_section = 6;
1988                break;
1989
1990        case DESC_RATEVHT1SS_MCS0:
1991        case DESC_RATEVHT1SS_MCS1:
1992        case DESC_RATEVHT1SS_MCS2:
1993        case DESC_RATEVHT1SS_MCS3:
1994                rate_section = 7;
1995                break;
1996
1997        case DESC_RATEVHT1SS_MCS4:
1998        case DESC_RATEVHT1SS_MCS5:
1999        case DESC_RATEVHT1SS_MCS6:
2000        case DESC_RATEVHT1SS_MCS7:

2001                rate_section = 8;
2002                break;
2003
2004        case DESC_RATEVHT1SS_MCS8:
2005        case DESC_RATEVHT1SS_MCS9:
2006        case DESC_RATEVHT2SS_MCS0:
2007        case DESC_RATEVHT2SS_MCS1:
2008                rate_section = 9;
2009                break;
2010
2011        case DESC_RATEVHT2SS_MCS2:
2012        case DESC_RATEVHT2SS_MCS3:
2013        case DESC_RATEVHT2SS_MCS4:
2014        case DESC_RATEVHT2SS_MCS5:
2015                rate_section = 10;
2016                break;
2017
2018        case DESC_RATEVHT2SS_MCS6:
2019        case DESC_RATEVHT2SS_MCS7:
2020        case DESC_RATEVHT2SS_MCS8:
2021        case DESC_RATEVHT2SS_MCS9:
2022                rate_section = 11;
2023                break;
2024
2025        default:
2026                RT_ASSERT(true, ("Rate_Section is Illegal\n"));
2027                break;
2028        }
2029
2030        return rate_section;
2031}
2032
2033static char _rtl8821ae_phy_get_txpower_by_rate(struct ieee80211_hw *hw,
2034                                                                                                                   u8 band, u8 path, u8 rate)
2035{
2036        struct rtl_priv *rtlpriv = rtl_priv(hw);
2037        struct rtl_phy *rtlphy = &(rtlpriv->phy);
2038        u8 shift = 0, rate_section, tx_num;
2039        char tx_pwr_diff = 0;
2040
2041        rate_section = _rtl8821ae_phy_get_ratesection_intxpower_byrate(path, rate);
2042        tx_num = RF_TX_NUM_NONIMPLEMENT;
2043
2044        if (tx_num == RF_TX_NUM_NONIMPLEMENT) {
2045                if ((rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS15 ) ||
2046                        (rate >= DESC_RATEVHT2SS_MCS2 && rate <= DESC_RATEVHT2SS_MCS9))
2047                         tx_num = RF_2TX;
2048                else
2049                        tx_num = RF_1TX;
2050        }
2051
2052        switch (rate) {
2053        case DESC_RATE1M:       shift = 0;              break;
2054        case DESC_RATE2M:       shift = 8;              break;
2055        case DESC_RATE5_5M:     shift = 16;             break;
2056        case DESC_RATE11M:      shift = 24;             break;
2057
2058        case DESC_RATE6M:       shift = 0;              break;
2059        case DESC_RATE9M:       shift = 8;      break;
2060        case DESC_RATE12M:      shift = 16;     break;
2061        case DESC_RATE18M:      shift = 24;     break;
2062
2063        case DESC_RATE24M:      shift = 0;      break;
2064        case DESC_RATE36M:      shift = 8;      break;
2065        case DESC_RATE48M:      shift = 16;     break;
2066        case DESC_RATE54M:      shift = 24;     break;
2067
2068        case DESC_RATEMCS0:     shift = 0;              break;
2069        case DESC_RATEMCS1:     shift = 8;      break;
2070        case DESC_RATEMCS2:     shift = 16;     break;
2071        case DESC_RATEMCS3:     shift = 24;     break;
2072
2073        case DESC_RATEMCS4:     shift = 0;              break;
2074        case DESC_RATEMCS5:     shift = 8;      break;
2075        case DESC_RATEMCS6:     shift = 16;     break;
2076        case DESC_RATEMCS7:     shift = 24;     break;
2077
2078        case DESC_RATEMCS8:     shift = 0;              break;
2079        case DESC_RATEMCS9:     shift = 8;      break;
2080        case DESC_RATEMCS10:    shift = 16;     break;
2081        case DESC_RATEMCS11:    shift = 24;     break;
2082
2083        case DESC_RATEMCS12:    shift = 0;              break;
2084        case DESC_RATEMCS13:    shift = 8;      break;
2085        case DESC_RATEMCS14:    shift = 16;     break;
2086        case DESC_RATEMCS15:    shift = 24;     break;
2087
2088        case DESC_RATEVHT1SS_MCS0:      shift = 0;              break;
2089        case DESC_RATEVHT1SS_MCS1:      shift = 8;      break;
2090        case DESC_RATEVHT1SS_MCS2:      shift = 16;     break;
2091        case DESC_RATEVHT1SS_MCS3:      shift = 24;     break;
2092
2093        case DESC_RATEVHT1SS_MCS4:      shift = 0;              break;
2094        case DESC_RATEVHT1SS_MCS5:      shift = 8;      break;
2095        case DESC_RATEVHT1SS_MCS6:      shift = 16;     break;
2096        case DESC_RATEVHT1SS_MCS7:      shift = 24;     break;
2097
2098        case DESC_RATEVHT1SS_MCS8:      shift = 0;              break;
2099        case DESC_RATEVHT1SS_MCS9:      shift = 8;      break;
2100        case DESC_RATEVHT2SS_MCS0:      shift = 16;     break;
2101        case DESC_RATEVHT2SS_MCS1:      shift = 24;     break;
2102
2103        case DESC_RATEVHT2SS_MCS2:      shift = 0;              break;
2104        case DESC_RATEVHT2SS_MCS3:      shift = 8;      break;
2105        case DESC_RATEVHT2SS_MCS4:      shift = 16;     break;
2106        case DESC_RATEVHT2SS_MCS5:      shift = 24;     break;
2107
2108        case DESC_RATEVHT2SS_MCS6:      shift = 0;              break;
2109        case DESC_RATEVHT2SS_MCS7:      shift = 8;      break;
2110        case DESC_RATEVHT2SS_MCS8:      shift = 16;     break;
2111        case DESC_RATEVHT2SS_MCS9:      shift = 24;     break;
2112
2113        default:
2114                RT_ASSERT(true, ("Rate_Section is Illegal\n"));
2115                break;
2116        }
2117
2118        tx_pwr_diff = (u8) (rtlphy->tx_power_by_rate_offset[band][path][tx_num][rate_section] >> shift) & 0xff;
2119
2120        return  tx_pwr_diff;
2121}
2122
2123static u8 _rtl8821ae_get_txpower_index(struct ieee80211_hw *hw, u8 path,
2124                                                                                         u8 rate, u8 bandwidth, u8 channel)
2125{
2126        struct rtl_priv *rtlpriv = rtl_priv(hw);
2127        struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2128        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2129        u8 index = (channel - 1);
2130        u8 txpower = 0;
2131        bool in_24g = false;
2132        char powerdiff_byrate = 0;
2133
2134        if (((rtlhal->current_bandtype == BAND_ON_2_4G) && (channel > 14 || channel < 1)) ||
2135                ((rtlhal->current_bandtype == BAND_ON_5G) && (channel <= 14))) {
2136                index = 0;
2137                RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("Illegal channel!!\n"));
2138        }
2139
2140        in_24g = _rtl8821ae_phy_get_chnl_index(channel, &index);
2141        if (in_24g) {
2142                if (RX_HAL_IS_CCK_RATE(rate))
2143                        txpower = rtlefuse->txpwrlevel_cck[path][index];
2144                else if ( DESC_RATE6M <= rate )
2145                        txpower = rtlefuse->txpwrlevel_ht40_1s[path][index];
2146                else
2147                        RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("invalid rate\n"));
2148
2149                if (DESC_RATE6M <= rate && rate <= DESC_RATE54M && !RX_HAL_IS_CCK_RATE(rate))
2150                        txpower += rtlefuse->txpwr_legacyhtdiff[path][TX_1S];
2151
2152                if (bandwidth == HT_CHANNEL_WIDTH_20) {
2153                        if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) ||
2154                                (DESC_RATEVHT1SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2155                                txpower += rtlefuse->txpwr_ht20diff[path][TX_1S];
2156                        if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) ||
2157                                (DESC_RATEVHT2SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2158                                txpower += rtlefuse->txpwr_ht20diff[path][TX_2S];
2159                } else if (bandwidth == HT_CHANNEL_WIDTH_20_40) {
2160                        if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) ||
2161                                (DESC_RATEVHT1SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2162                                txpower += rtlefuse->txpwr_ht40diff[path][TX_1S];
2163                        if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) ||
2164                                (DESC_RATEVHT2SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2165                                txpower += rtlefuse->txpwr_ht40diff[path][TX_2S];
2166                } else if (bandwidth == HT_CHANNEL_WIDTH_80) {
2167                        if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) ||
2168                                (DESC_RATEVHT1SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2169                                txpower += rtlefuse->txpwr_ht40diff[path][TX_1S];
2170                        if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) ||
2171                                (DESC_RATEVHT2SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2172                                txpower += rtlefuse->txpwr_ht40diff[path][TX_2S];
2173                }
2174
2175        } else {
2176                if (DESC_RATE6M <= rate)
2177                        txpower = rtlefuse->txpwr_5g_bw40base[path][index];
2178            else
2179                RT_TRACE(COMP_POWER_TRACKING, DBG_WARNING,("INVALID Rate.\n"));
2180
2181        if (DESC_RATE6M <= rate && rate <= DESC_RATE54M && !RX_HAL_IS_CCK_RATE(rate))
2182                txpower += rtlefuse->txpwr_5g_ofdmdiff[path][TX_1S];
2183
2184            if (bandwidth == HT_CHANNEL_WIDTH_20) {
2185                if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) ||
2186                                (DESC_RATEVHT1SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2187                    txpower += rtlefuse->txpwr_5g_bw20diff[path][TX_1S];
2188                if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) ||
2189                                (DESC_RATEVHT2SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2190                    txpower += rtlefuse->txpwr_5g_bw20diff[path][TX_2S];
2191            } else if (bandwidth == HT_CHANNEL_WIDTH_20_40) {
2192                if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) ||
2193                                (DESC_RATEVHT1SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2194                    txpower += rtlefuse->txpwr_5g_bw40diff[path][TX_1S];
2195                if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) ||
2196                                (DESC_RATEVHT2SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2197                    txpower += rtlefuse->txpwr_5g_bw40diff[path][TX_2S];
2198            } else if (bandwidth == HT_CHANNEL_WIDTH_80) {
2199                        u8 channel_5g_80m[CHANNEL_MAX_NUMBER_5G_80M] = {42, 58, 106, 122, 138, 155, 171};
2200                        u8 i = 0;
2201                        for (i = 0; i < sizeof(channel_5g_80m) / sizeof(u8); ++i)
2202                                if (channel_5g_80m[i] == channel)
2203                                        index = i;
2204
2205                if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) ||
2206                                (DESC_RATEVHT1SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2207                    txpower = rtlefuse->txpwr_5g_bw80base[path][index]
2208                                + rtlefuse->txpwr_5g_bw80diff[path][TX_1S];
2209                if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) ||
2210                                (DESC_RATEVHT2SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2211                    txpower = rtlefuse->txpwr_5g_bw80base[path][index]
2212                                + rtlefuse->txpwr_5g_bw80diff[path][TX_1S]
2213                                + rtlefuse->txpwr_5g_bw80diff[path][TX_2S];
2214            }
2215        }
2216        if (rtlefuse->eeprom_regulatory != 2)
2217                powerdiff_byrate = _rtl8821ae_phy_get_txpower_by_rate(hw,
2218                                                                        (u8)(!in_24g), path, rate);
2219
2220        if (rate == DESC_RATEVHT1SS_MCS8 || rate == DESC_RATEVHT1SS_MCS9 ||
2221                rate == DESC_RATEVHT2SS_MCS8 || rate == DESC_RATEVHT2SS_MCS9)
2222                txpower -= powerdiff_byrate;
2223        else
2224                txpower += powerdiff_byrate;
2225
2226        if (rate > DESC_RATE11M)
2227                txpower += rtlpriv->dm.remnant_ofdm_swing_idx[path];
2228        else
2229                txpower += rtlpriv->dm.remnant_cck_idx;
2230
2231        if (txpower > MAX_POWER_INDEX)
2232                txpower = MAX_POWER_INDEX;
2233
2234        return txpower;
2235}
2236
2237static void _rtl8821ae_phy_set_txpower_index(struct ieee80211_hw *hw,
2238                                                                                                u8 power_index, u8 path, u8 rate)
2239{
2240        struct rtl_priv* rtlpriv = rtl_priv(hw);
2241
2242        if (path == RF90_PATH_A) {
2243        switch (rate) {
2244        case DESC_RATE1M:
2245                rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1, MASKBYTE0, power_index);
2246                break;
2247        case DESC_RATE2M:
2248                rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1, MASKBYTE1, power_index);
2249                break;
2250        case DESC_RATE5_5M:
2251                rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1, MASKBYTE2, power_index);
2252                break;
2253        case DESC_RATE11M:
2254                rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1, MASKBYTE3, power_index);
2255                break;
2256
2257        case DESC_RATE6M:
2258                rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6, MASKBYTE0, power_index);
2259                break;
2260        case DESC_RATE9M:
2261                rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6, MASKBYTE1, power_index);
2262                break;
2263        case DESC_RATE12M:
2264                rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6, MASKBYTE2, power_index);
2265                break;
2266        case DESC_RATE18M:
2267                rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6, MASKBYTE3, power_index);
2268                break;
2269
2270        case DESC_RATE24M:
2271                rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24, MASKBYTE0, power_index);
2272                break;
2273        case DESC_RATE36M:
2274                rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24, MASKBYTE1, power_index);
2275                break;
2276        case DESC_RATE48M:
2277                rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24, MASKBYTE2, power_index);
2278                break;
2279        case DESC_RATE54M:
2280                rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24, MASKBYTE3, power_index);
2281                break;
2282
2283        case DESC_RATEMCS0:
2284                rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE0, power_index);
2285                break;
2286        case DESC_RATEMCS1:
2287                rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE1, power_index);
2288                break;
2289        case DESC_RATEMCS2:
2290                rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE2, power_index);
2291                break;
2292        case DESC_RATEMCS3:
2293                rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE3, power_index);
2294                break;
2295
2296        case DESC_RATEMCS4:
2297                rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE0, power_index);
2298                break;
2299        case DESC_RATEMCS5:
2300                rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE1, power_index);
2301                break;
2302        case DESC_RATEMCS6:
2303                rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE2, power_index);
2304                break;
2305        case DESC_RATEMCS7:
2306                rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE3, power_index);
2307                break;
2308
2309        case DESC_RATEMCS8:
2310                rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE0, power_index);
2311                break;
2312        case DESC_RATEMCS9:
2313                rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE1, power_index);
2314                break;
2315        case DESC_RATEMCS10:
2316                rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE2, power_index);
2317                break;
2318        case DESC_RATEMCS11:
2319                rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE3, power_index);
2320                break;
2321
2322        case DESC_RATEMCS12:
2323                rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE0, power_index);
2324                break;
2325        case DESC_RATEMCS13:
2326                rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE1, power_index);
2327                break;
2328        case DESC_RATEMCS14:
2329                rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE2, power_index);
2330                break;
2331        case DESC_RATEMCS15:
2332                rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE3, power_index);
2333                break;
2334
2335        case DESC_RATEVHT1SS_MCS0:
2336                rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0, MASKBYTE0, power_index);
2337                break;
2338        case DESC_RATEVHT1SS_MCS1:
2339                rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0, MASKBYTE1, power_index);
2340                break;
2341        case DESC_RATEVHT1SS_MCS2:
2342                rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0, MASKBYTE2, power_index);
2343                break;
2344        case DESC_RATEVHT1SS_MCS3:
2345                rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0, MASKBYTE3, power_index);
2346                break;
2347
2348        case DESC_RATEVHT1SS_MCS4:
2349                rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4, MASKBYTE0, power_index);
2350                break;
2351        case DESC_RATEVHT1SS_MCS5:
2352                rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4, MASKBYTE1, power_index);
2353                break;
2354        case DESC_RATEVHT1SS_MCS6:
2355                rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4, MASKBYTE2, power_index);
2356                break;
2357        case DESC_RATEVHT1SS_MCS7:
2358                rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4, MASKBYTE3, power_index);
2359                break;
2360
2361        case DESC_RATEVHT1SS_MCS8:
2362                rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8, MASKBYTE0, power_index);
2363                break;
2364        case DESC_RATEVHT1SS_MCS9:
2365                rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8, MASKBYTE1, power_index);
2366                break;
2367        case DESC_RATEVHT2SS_MCS0:
2368                rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8, MASKBYTE2, power_index);
2369                break;
2370        case DESC_RATEVHT2SS_MCS1:
2371                rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8, MASKBYTE3, power_index);
2372                break;
2373
2374        case DESC_RATEVHT2SS_MCS2:
2375                rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2, MASKBYTE0, power_index);
2376                break;
2377        case DESC_RATEVHT2SS_MCS3:
2378                rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2, MASKBYTE1, power_index);
2379                break;
2380        case DESC_RATEVHT2SS_MCS4:
2381                rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2, MASKBYTE2, power_index);
2382                break;
2383        case DESC_RATEVHT2SS_MCS5:
2384                rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2, MASKBYTE3, power_index);
2385                break;
2386
2387        case DESC_RATEVHT2SS_MCS6:
2388                rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6, MASKBYTE0, power_index);
2389                break;
2390        case DESC_RATEVHT2SS_MCS7:
2391                rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6, MASKBYTE1, power_index);
2392                break;
2393        case DESC_RATEVHT2SS_MCS8:
2394                rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6, MASKBYTE2, power_index);
2395                break;
2396        case DESC_RATEVHT2SS_MCS9:
2397                rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6, MASKBYTE3, power_index);
2398                break;
2399
2400        default:
2401                        RT_TRACE(COMP_POWER, DBG_LOUD, ("Invalid Rate!!\n"));
2402            break;
2403        }
2404    } else if (path == RF90_PATH_B) {
2405        switch (rate) {
2406        case DESC_RATE1M:
2407                rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1, MASKBYTE0, power_index);
2408                break;
2409        case DESC_RATE2M:
2410                rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1, MASKBYTE1, power_index);
2411                break;
2412        case DESC_RATE5_5M:
2413                rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1, MASKBYTE2, power_index);
2414                break;
2415        case DESC_RATE11M:
2416                rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1, MASKBYTE3, power_index);
2417                break;
2418
2419        case DESC_RATE6M:
2420                rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6, MASKBYTE0, power_index);
2421                break;
2422        case DESC_RATE9M:
2423                rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6, MASKBYTE1, power_index);
2424                break;
2425        case DESC_RATE12M:
2426                rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6, MASKBYTE2, power_index);
2427                break;
2428        case DESC_RATE18M:
2429                rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6, MASKBYTE3, power_index);
2430                break;
2431
2432        case DESC_RATE24M:
2433                rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24, MASKBYTE0, power_index);
2434                break;
2435        case DESC_RATE36M:
2436                rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24, MASKBYTE1, power_index);
2437                break;
2438        case DESC_RATE48M:
2439                rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24, MASKBYTE2, power_index);
2440                break;
2441        case DESC_RATE54M:
2442                rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24, MASKBYTE3, power_index);
2443                break;
2444
2445        case DESC_RATEMCS0:
2446                rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE0, power_index);
2447                break;
2448        case DESC_RATEMCS1:
2449                rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE1, power_index);
2450                break;
2451        case DESC_RATEMCS2:
2452                rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE2, power_index);
2453                break;
2454        case DESC_RATEMCS3:
2455                rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE3, power_index);
2456                break;
2457
2458        case DESC_RATEMCS4:
2459                rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE0, power_index);
2460                break;
2461        case DESC_RATEMCS5:
2462                rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE1, power_index);
2463                break;
2464        case DESC_RATEMCS6:
2465                rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE2, power_index);
2466                break;
2467        case DESC_RATEMCS7:
2468                rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE3, power_index);
2469                break;
2470
2471        case DESC_RATEMCS8:
2472                rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE0, power_index);
2473                break;
2474        case DESC_RATEMCS9:
2475                rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE1, power_index);
2476                break;
2477        case DESC_RATEMCS10:
2478                rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE2, power_index);
2479                break;
2480        case DESC_RATEMCS11:
2481                rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE3, power_index);
2482                break;
2483
2484        case DESC_RATEMCS12:
2485                rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE0, power_index);
2486                break;
2487        case DESC_RATEMCS13:
2488                rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE1, power_index);
2489                break;
2490        case DESC_RATEMCS14:
2491                rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE2, power_index);
2492                break;
2493        case DESC_RATEMCS15:
2494                rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE3, power_index);
2495                break;
2496
2497        case DESC_RATEVHT1SS_MCS0:
2498                rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0, MASKBYTE0, power_index);
2499                break;
2500        case DESC_RATEVHT1SS_MCS1:
2501                rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0, MASKBYTE1, power_index);
2502                break;
2503        case DESC_RATEVHT1SS_MCS2:
2504                rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0, MASKBYTE2, power_index);
2505                break;
2506        case DESC_RATEVHT1SS_MCS3:
2507                rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0, MASKBYTE3, power_index);
2508                break;
2509
2510        case DESC_RATEVHT1SS_MCS4:
2511                rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4, MASKBYTE0, power_index);
2512                break;
2513        case DESC_RATEVHT1SS_MCS5:
2514                rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4, MASKBYTE1, power_index);
2515                break;
2516        case DESC_RATEVHT1SS_MCS6:
2517                rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4, MASKBYTE2, power_index);
2518                break;
2519        case DESC_RATEVHT1SS_MCS7:
2520                rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4, MASKBYTE3, power_index);
2521                break;
2522
2523        case DESC_RATEVHT1SS_MCS8:
2524                rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8, MASKBYTE0, power_index);
2525                break;
2526        case DESC_RATEVHT1SS_MCS9:
2527                rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8, MASKBYTE1, power_index);
2528                break;
2529        case DESC_RATEVHT2SS_MCS0:
2530                rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8, MASKBYTE2, power_index);
2531                break;
2532        case DESC_RATEVHT2SS_MCS1:
2533                rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8, MASKBYTE3, power_index);
2534                break;
2535
2536        case DESC_RATEVHT2SS_MCS2:
2537                rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2, MASKBYTE0, power_index);
2538                break;
2539        case DESC_RATEVHT2SS_MCS3:
2540                rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2, MASKBYTE1, power_index);
2541                break;
2542        case DESC_RATEVHT2SS_MCS4:
2543                rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2, MASKBYTE2, power_index);
2544                break;
2545        case DESC_RATEVHT2SS_MCS5:
2546                rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2, MASKBYTE3, power_index);
2547                break;
2548
2549        case DESC_RATEVHT2SS_MCS6:
2550                rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6, MASKBYTE0, power_index);
2551                break;
2552        case DESC_RATEVHT2SS_MCS7:
2553                rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6, MASKBYTE1, power_index);
2554                break;
2555        case DESC_RATEVHT2SS_MCS8:
2556                rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6, MASKBYTE2, power_index);
2557                break;
2558        case DESC_RATEVHT2SS_MCS9:
2559                rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6, MASKBYTE3, power_index);
2560                break;
2561
2562       default:
2563                RT_TRACE(COMP_POWER, DBG_LOUD, ("Invalid Rate!!\n"));
2564                break;
2565        }
2566    } else {
2567                RT_TRACE(COMP_POWER, DBG_LOUD, ("Invalid RFPath!!\n"));
2568    }
2569}
2570
2571void _rtl8821ae_phy_set_txpower_level_by_path(struct ieee80211_hw *hw,
2572                                                                                                        u8 *array, u8 path, u8 channel,
2573                                                                                                        u8 size)
2574{
2575        struct rtl_phy *rtlphy = &(rtl_priv(hw)->phy);
2576        u8 i;
2577        u8 power_index;
2578        for (i = 0; i < size; i ++) {
2579                power_index = _rtl8821ae_get_txpower_index(hw, path, array[i],
2580                                                                        rtlphy->current_chan_bw, channel);
2581                _rtl8821ae_phy_set_txpower_index(hw, power_index, path, array[i]);
2582        }
2583}
2584
2585static void _rtl8821ae_phy_txpower_training_by_path(struct ieee80211_hw *hw,
2586                                                                                                                u8 bw, u8 channel, u8 path)
2587{
2588        struct rtl_priv *rtlpriv = rtl_priv(hw);
2589        struct rtl_phy *rtlphy = &(rtlpriv->phy);
2590
2591        u8 i;
2592        u32 power_level, data, offset;
2593
2594        if(path >= rtlphy->num_total_rfpath)
2595                return;
2596
2597        data = 0;
2598        if (path == RF90_PATH_A) {
2599                power_level =
2600                        _rtl8821ae_get_txpower_index(hw, RF90_PATH_A,
2601                        DESC_RATEMCS7, bw, channel);
2602                offset =  RA_TXPWRTRAING;
2603        } else {
2604                power_level =
2605                        _rtl8821ae_get_txpower_index(hw, RF90_PATH_A,
2606                        DESC_RATEMCS7, bw, channel);
2607                offset =  RB_TXPWRTRAING;
2608        }
2609
2610        for (i = 0; i < 3; i++) {
2611                if (i == 0)
2612                        power_level = power_level - 10;
2613                else if (i == 1)
2614                        power_level = power_level - 8;
2615                else
2616                        power_level = power_level - 6;
2617
2618                data |= (((power_level > 2) ? (power_level) : 2) << (i * 8));
2619        }
2620        rtl_set_bbreg(hw, offset, 0xffffff, data);
2621}
2622
2623void rtl8821ae_phy_set_txpower_level_by_path(struct ieee80211_hw *hw, u8 channel, u8 path)
2624{
2625        //struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2626        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2627        struct rtl_phy *rtlphy = &(rtl_priv(hw)->phy);
2628        u8 cck_rates[]  = {DESC_RATE1M, DESC_RATE2M, DESC_RATE5_5M, DESC_RATE11M};
2629        u8 ofdm_rates[]  = {DESC_RATE6M, DESC_RATE9M, DESC_RATE12M, DESC_RATE18M,
2630                                                DESC_RATE24M, DESC_RATE36M, DESC_RATE48M, DESC_RATE54M};
2631        u8 ht_rates_1t[]  = {DESC_RATEMCS0, DESC_RATEMCS1, DESC_RATEMCS2, DESC_RATEMCS3,
2632                                                 DESC_RATEMCS4, DESC_RATEMCS5, DESC_RATEMCS6, DESC_RATEMCS7};
2633        u8 ht_rates_2t[]  = {DESC_RATEMCS8, DESC_RATEMCS9, DESC_RATEMCS10, DESC_RATEMCS11,
2634                                                 DESC_RATEMCS12, DESC_RATEMCS13, DESC_RATEMCS14, DESC_RATEMCS15};
2635        u8 vht_rates_1t[]  = {DESC_RATEVHT1SS_MCS0, DESC_RATEVHT1SS_MCS1, DESC_RATEVHT1SS_MCS2,
2636                                                DESC_RATEVHT1SS_MCS3, DESC_RATEVHT1SS_MCS4,
2637                                                  DESC_RATEVHT1SS_MCS5, DESC_RATEVHT1SS_MCS6, DESC_RATEVHT1SS_MCS7,
2638                                                  DESC_RATEVHT1SS_MCS8, DESC_RATEVHT1SS_MCS9};
2639        u8 vht_rates_2t[]  = {DESC_RATEVHT2SS_MCS0, DESC_RATEVHT2SS_MCS1, DESC_RATEVHT2SS_MCS2,
2640                                                DESC_RATEVHT2SS_MCS3, DESC_RATEVHT2SS_MCS4,
2641                                                  DESC_RATEVHT2SS_MCS5, DESC_RATEVHT2SS_MCS6, DESC_RATEVHT2SS_MCS7,
2642                                                  DESC_RATEVHT2SS_MCS8, DESC_RATEVHT2SS_MCS9};
2643        //u8 i,size;
2644        //u8 power_index;
2645
2646        if (rtlhal->current_bandtype == BAND_ON_2_4G)
2647                _rtl8821ae_phy_set_txpower_level_by_path(hw,cck_rates,path,channel,
2648                                                         sizeof(cck_rates) / sizeof(u8));
2649
2650        _rtl8821ae_phy_set_txpower_level_by_path(hw,ofdm_rates,path,channel,
2651                                                     sizeof(ofdm_rates) / sizeof(u8));
2652        _rtl8821ae_phy_set_txpower_level_by_path(hw,ht_rates_1t,path,channel,
2653                                                     sizeof(ht_rates_1t) / sizeof(u8));
2654        _rtl8821ae_phy_set_txpower_level_by_path(hw,vht_rates_1t,path,channel,
2655                                                     sizeof(vht_rates_1t) / sizeof(u8));
2656
2657        if (rtlphy->num_total_rfpath >= 2) {
2658                _rtl8821ae_phy_set_txpower_level_by_path(hw,ht_rates_2t,path,channel,
2659                                                             sizeof(ht_rates_2t) / sizeof(u8));
2660                _rtl8821ae_phy_set_txpower_level_by_path(hw,vht_rates_2t,path,channel,
2661                                                             sizeof(vht_rates_2t) / sizeof(u8));
2662        }
2663
2664        _rtl8821ae_phy_txpower_training_by_path(hw, rtlphy->current_chan_bw, channel, path);
2665}
2666/*just in case, write txpower in DW, to reduce time*/
2667#if 0
2668void _rtl8821ae_phy_get_txpower_index_by_rate_array(struct ieee80211_hw *hw, u8 channel,
2669                                                                                        u8 *rate, u8 path, u8 bw, u8 *power_index, u8 size)
2670{
2671        u8 i;
2672        for (i = 0; i < size; i++)
2673                power_index[i] = _rtl8821ae_get_txpower_index(hw, path, rate[i], bw, channel);
2674}
2675
2676void rtl8821ae_phy_set_txpower_level_by_path2(struct ieee80211_hw *hw, u8 channel, u8 path)
2677{
2678        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2679        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2680        struct rtl_phy *rtlphy = &(rtl_priv(hw)->phy);
2681        u8 cck_rates[]  = {DESC_RATE1M, DESC_RATE2M, DESC_RATE5_5M, DESC_RATE11M};
2682        u8 ofdm_rates[]  = {DESC_RATE6M, DESC_RATE9M, DESC_RATE12M, DESC_RATE18M,
2683                                                DESC_RATE24M, DESC_RATE36M, DESC_RATE48M, DESC_RATE54M};
2684        u8 ht_rates_1t[]  = {DESC_RATEMCS0, DESC_RATEMCS1, DESC_RATEMCS2, DESC_RATEMCS3,
2685                                                 DESC_RATEMCS4, DESC_RATEMCS5, DESC_RATEMCS6, DESC_RATEMCS7};
2686        u8 ht_rates_2t[]  = {DESC_RATEMCS8, DESC_RATEMCS9, DESC_RATEMCS10, DESC_RATEMCS11,
2687                                                 DESC_RATEMCS12, DESC_RATEMCS13, DESC_RATEMCS14, DESC_RATEMCS15};
2688        u8 vht_rates_1t[]  = {DESC_RATEVHT1SS_MCS0, DESC_RATEVHT1SS_MCS1, DESC_RATEVHT1SS_MCS2, DESC_RATEVHT1SS_MCS3, DESC_RATEVHT1SS_MCS4,
2689                                                  DESC_RATEVHT1SS_MCS5, DESC_RATEVHT1SS_MCS6, DESC_RATEVHT1SS_MCS7, DESC_RATEVHT1SS_MCS8, DESC_RATEVHT1SS_MCS9};
2690        u8 vht_rates_2t[]  = {DESC_RATEVHT2SS_MCS0, DESC_RATEVHT2SS_MCS1, DESC_RATEVHT2SS_MCS2, DESC_RATEVHT2SS_MCS3, DESC_RATEVHT2SS_MCS4,
2691                                                  DESC_RATEVHT2SS_MCS5, DESC_RATEVHT2SS_MCS6, DESC_RATEVHT2SS_MCS7, DESC_RATEVHT2SS_MCS8, DESC_RATEVHT2SS_MCS9};
2692        u8 i, j;
2693        u8 pwridx[48] = {0};
2694        u8 cs = sizeof(cck_rates) / sizeof(u8);
2695        u8 os = sizeof(ofdm_rates) / sizeof(u8);
2696        u8 h1s = sizeof(ht_rates_1t) / sizeof(u8);
2697        u8 h2s = sizeof(ht_rates_2t) / sizeof(u8);
2698        u8 v1s = sizeof(vht_rates_1t) / sizeof(u8);
2699        u8 v2s = sizeof(vht_rates_2t) / sizeof(u8);
2700
2701        u8 len, start;
2702        u32 reg_addr, power_index;
2703        u8 bw = rtlphy->current_chan_bw;
2704
2705        _rtl8821ae_phy_get_txpower_index_by_rate_array(hw, channel,
2706                ofdm_rates, path, bw, &pwridx[cs], os);
2707
2708        _rtl8821ae_phy_get_txpower_index_by_rate_array(hw, channel,
2709                ht_rates_1t, path, bw, &pwridx[cs+os], h1s);
2710
2711        _rtl8821ae_phy_get_txpower_index_by_rate_array(hw, channel,
2712                vht_rates_1t, path, bw, &pwridx[cs+os+h1s+h2s], v1s);
2713
2714
2715        if (rtlhal->current_bandtype == BAND_ON_2_4G) {
2716                _rtl8821ae_phy_get_txpower_index_by_rate_array(hw, channel,
2717                        cck_rates, path, bw, pwridx, cs);
2718
2719                start = 0;
2720        } else {
2721                start = cs;
2722        }
2723
2724        reg_addr = (path == 0) ? RTXAGC_A_CCK11_CCK1 : RTXAGC_B_CCK11_CCK1;
2725        reg_addr += start;
2726
2727        len = cs + os + h1s + h2s + v1s;
2728        if (rtlphy->num_total_rfpath >= 2) {
2729                _rtl8821ae_phy_get_txpower_index_by_rate_array(hw, channel,
2730                        ht_rates_2t, path, bw, &pwridx[cs+os+h1s], h2s);
2731
2732                _rtl8821ae_phy_get_txpower_index_by_rate_array(hw, channel,
2733                        vht_rates_2t, path, bw, &pwridx[cs+os+h1s+h2s+v1s], v2s);
2734
2735                len += v2s;
2736        }
2737        for (i = start; i < len; i += 4) {
2738                power_index = 0;
2739                for (j = 0; j < 4; j++)
2740                        power_index |= (pwridx[i+j] << (j*8));
2741                rtl_set_bbreg(hw, reg_addr + i, MASKDWORD, power_index);
2742        }
2743
2744        _rtl8821ae_phy_txpower_training_by_path(hw, rtlphy->current_chan_bw, channel, path);
2745}
2746#endif
2747
2748void rtl8821ae_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
2749{
2750        struct rtl_priv *rtlpriv = rtl_priv(hw);
2751        struct rtl_phy *rtlphy = &(rtlpriv->phy);
2752        u8 path = 0;
2753
2754        for (path = RF90_PATH_A; path < rtlphy->num_total_rfpath; ++path )
2755                rtl8821ae_phy_set_txpower_level_by_path(hw, channel, path);
2756}
2757
2758static long _rtl8821ae_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
2759                                         enum wireless_mode wirelessmode,
2760                                         u8 txpwridx)
2761{
2762        long offset;
2763        long pwrout_dbm;
2764
2765        switch (wirelessmode) {
2766        case WIRELESS_MODE_B:
2767                offset = -7;
2768                break;
2769        case WIRELESS_MODE_G:
2770        case WIRELESS_MODE_N_24G:
2771                offset = -8;
2772                break;
2773        default:
2774                offset = -8;
2775                break;
2776        }
2777        pwrout_dbm = txpwridx / 2 + offset;
2778        return pwrout_dbm;
2779}
2780
2781void rtl8821ae_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation)
2782{
2783        struct rtl_priv *rtlpriv = rtl_priv(hw);
2784        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2785        enum io_type iotype = IO_CMD_PAUSE_BAND0_DM_BY_SCAN;
2786
2787        if (!is_hal_stop(rtlhal)) {
2788                switch (operation) {
2789                case SCAN_OPT_BACKUP_BAND0:
2790                        iotype = IO_CMD_PAUSE_BAND0_DM_BY_SCAN;
2791                        rtlpriv->cfg->ops->set_hw_reg(hw,
2792                                                      HW_VAR_IO_CMD,
2793                                                      (u8 *) & iotype);
2794
2795                        break;
2796                case SCAN_OPT_BACKUP_BAND1:
2797                        iotype = IO_CMD_PAUSE_BAND1_DM_BY_SCAN;
2798                        rtlpriv->cfg->ops->set_hw_reg(hw,
2799                                                      HW_VAR_IO_CMD,
2800                                                      (u8 *) & iotype);
2801
2802                        break;
2803                case SCAN_OPT_RESTORE:
2804                        iotype = IO_CMD_RESUME_DM_BY_SCAN;
2805                        rtlpriv->cfg->ops->set_hw_reg(hw,
2806                                                      HW_VAR_IO_CMD,
2807                                                      (u8 *) & iotype);
2808                        break;
2809                default:
2810                        RT_TRACE(COMP_ERR, DBG_EMERG,
2811                                 ("Unknown Scan Backup operation.\n"));
2812                        break;
2813                }
2814        }
2815}
2816
2817static void _rtl8821ae_phy_set_reg_bw(struct rtl_priv * rtlpriv, u8 bw)
2818{
2819        u16 reg_rf_mode_bw, tmp = 0;
2820        reg_rf_mode_bw = rtl_read_word(rtlpriv, REG_TRXPTCL_CTL);
2821        switch (bw) {
2822        case HT_CHANNEL_WIDTH_20:
2823                rtl_write_word(rtlpriv, REG_TRXPTCL_CTL, reg_rf_mode_bw & 0xFE7F);
2824                break;
2825        case HT_CHANNEL_WIDTH_20_40:
2826                tmp = reg_rf_mode_bw | BIT(7);
2827                rtl_write_word(rtlpriv, REG_TRXPTCL_CTL, tmp & 0xFEFF);
2828                break;
2829        case HT_CHANNEL_WIDTH_80:
2830                tmp = reg_rf_mode_bw | BIT(8);
2831                rtl_write_word(rtlpriv, REG_TRXPTCL_CTL, tmp & 0xFF7F);
2832                break;
2833        default:
2834                RT_TRACE(COMP_ERR, DBG_WARNING,("unknown Bandwidth: 0x%x\n",bw));
2835                break;
2836        }
2837}
2838
2839static u8 _rtl8821ae_phy_get_secondary_chnl(struct rtl_priv * rtlpriv)
2840{
2841        struct rtl_phy *rtlphy = &(rtlpriv->phy);
2842        struct rtl_mac *mac = rtl_mac(rtlpriv);
2843        u8 sc_set_40 = 0, sc_set_20 =0;
2844
2845        if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80) {
2846                if(mac->cur_80_prime_sc == PRIME_CHNL_OFFSET_LOWER)
2847                        sc_set_40 = VHT_DATA_SC_40_LOWER_OF_80MHZ;
2848                else if(mac->cur_80_prime_sc == PRIME_CHNL_OFFSET_UPPER)
2849                        sc_set_40 = VHT_DATA_SC_40_UPPER_OF_80MHZ;
2850                else
2851                        RT_TRACE(COMP_ERR, DBG_EMERG,
2852                                ("SCMapping: Not Correct Primary40MHz Setting \n"));
2853
2854                if((mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_LOWER) &&
2855                        (mac->cur_80_prime_sc == HAL_PRIME_CHNL_OFFSET_LOWER))
2856                        sc_set_20 = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
2857                else if((mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_UPPER) &&
2858                        (mac->cur_80_prime_sc == HAL_PRIME_CHNL_OFFSET_LOWER))
2859                        sc_set_20 = VHT_DATA_SC_20_LOWER_OF_80MHZ;
2860                else if((mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_LOWER) &&
2861                        (mac->cur_80_prime_sc == HAL_PRIME_CHNL_OFFSET_UPPER))
2862                        sc_set_20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;
2863                else if((mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_UPPER) &&
2864                        (mac->cur_80_prime_sc == HAL_PRIME_CHNL_OFFSET_UPPER))
2865                        sc_set_20 = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
2866                else
2867                        RT_TRACE(COMP_ERR, DBG_EMERG,
2868                                ("SCMapping: Not Correct Primary40MHz Setting \n"));
2869        } else if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
2870                if (mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_UPPER)
2871                        sc_set_20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;
2872                else if (mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_LOWER)
2873                        sc_set_20 = VHT_DATA_SC_20_LOWER_OF_80MHZ;
2874                else
2875                        RT_TRACE(COMP_ERR, DBG_EMERG,
2876                         ("SCMapping: Not Correct Primary40MHz Setting \n"));
2877        }
2878        return ((sc_set_40 << 4) | sc_set_20);
2879}
2880
2881void rtl8821ae_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
2882{
2883        struct rtl_priv *rtlpriv = rtl_priv(hw);
2884        struct rtl_phy *rtlphy = &(rtlpriv->phy);
2885        u8 sub_chnl = 0;
2886        u8 l1pk_val = 0;
2887
2888        RT_TRACE(COMP_SCAN, DBG_TRACE,
2889                 ("Switch to %s bandwidth\n",
2890                  (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
2891                  "20MHz" :
2892                  (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40 ?
2893                  "40MHz" : "80MHz"))))
2894
2895
2896
2897        _rtl8821ae_phy_set_reg_bw(rtlpriv, rtlphy->current_chan_bw);
2898        sub_chnl = _rtl8821ae_phy_get_secondary_chnl(rtlpriv);
2899        rtl_write_byte(rtlpriv, 0x0483, sub_chnl);
2900
2901        switch (rtlphy->current_chan_bw) {
2902        case HT_CHANNEL_WIDTH_20:
2903                rtl_set_bbreg(hw, RRFMOD, 0x003003C3, 0x00300200);
2904                rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 0);
2905
2906                if(rtlphy->rf_type == RF_2T2R)
2907                        rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, 7);
2908                else
2909                        rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, 8);
2910                break;
2911        case HT_CHANNEL_WIDTH_20_40:
2912                rtl_set_bbreg(hw, RRFMOD, 0x003003C3, 0x00300201);
2913                rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 0);
2914                rtl_set_bbreg(hw, RRFMOD, 0x3C, sub_chnl);
2915                rtl_set_bbreg(hw, RCCAONSEC, 0xf0000000, sub_chnl);
2916
2917                if(rtlphy->reg_837 & BIT(2))
2918                        l1pk_val = 6;
2919                else
2920                {
2921                        if(rtlphy->rf_type == RF_2T2R)
2922                                l1pk_val = 7;
2923                        else
2924                                l1pk_val = 8;
2925                }
2926                rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, l1pk_val);     // 0x848[25:22] = 0x6
2927
2928                if(sub_chnl == VHT_DATA_SC_20_UPPER_OF_80MHZ)
2929                        rtl_set_bbreg(hw, RCCK_SYSTEM, BCCK_SYSTEM, 1);
2930                else
2931                        rtl_set_bbreg(hw, RCCK_SYSTEM, BCCK_SYSTEM, 0);
2932                break;
2933
2934        case HT_CHANNEL_WIDTH_80:
2935                rtl_set_bbreg(hw, RRFMOD, 0x003003C3, 0x00300202); // 0x8ac[21,20,9:6,1,0]=8'b11100010
2936                rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 1);                    // 0x8c4[30] = 1
2937                rtl_set_bbreg(hw, RRFMOD, 0x3C, sub_chnl);
2938                rtl_set_bbreg(hw, RCCAONSEC, 0xf0000000, sub_chnl);
2939
2940                if(rtlphy->reg_837 & BIT(2))
2941                        l1pk_val = 5;
2942                else
2943                {
2944                        if(rtlphy->rf_type == RF_2T2R)
2945                                l1pk_val = 6;
2946                        else
2947                                l1pk_val = 7;
2948                }
2949                rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, l1pk_val);
2950
2951                break;
2952        default:
2953                RT_TRACE(COMP_ERR, DBG_EMERG,
2954                         ("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
2955                break;
2956        }
2957
2958        rtl8812ae_fixspur(hw, rtlphy->current_chan_bw, rtlphy->current_channel);
2959
2960        rtl8821ae_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
2961        rtlphy->set_bwmode_inprogress = false;
2962
2963        RT_TRACE(COMP_SCAN, DBG_LOUD, (" \n"));
2964}
2965
2966void rtl8821ae_phy_set_bw_mode(struct ieee80211_hw *hw,
2967                            enum nl80211_channel_type ch_type)
2968{
2969        struct rtl_priv *rtlpriv = rtl_priv(hw);
2970        struct rtl_phy *rtlphy = &(rtlpriv->phy);
2971        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2972        u8 tmp_bw = rtlphy->current_chan_bw;
2973
2974        if (rtlphy->set_bwmode_inprogress)
2975                return;
2976        rtlphy->set_bwmode_inprogress = true;
2977        if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
2978                rtl8821ae_phy_set_bw_mode_callback(hw);
2979        } else {
2980                RT_TRACE(COMP_ERR, DBG_WARNING,
2981                         ("FALSE driver sleep or unload\n"));
2982                rtlphy->set_bwmode_inprogress = false;
2983                rtlphy->current_chan_bw = tmp_bw;
2984        }
2985}
2986
2987void rtl8821ae_phy_sw_chnl_callback(struct ieee80211_hw *hw)
2988{
2989        struct rtl_priv *rtlpriv = rtl_priv(hw);
2990        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2991        struct rtl_phy *rtlphy = &(rtlpriv->phy);
2992        u8 channel = rtlphy->current_channel;
2993        u8 path;
2994        u32 data;
2995
2996        RT_TRACE(COMP_SCAN, DBG_TRACE,
2997                 ("switch to channel%d\n", rtlphy->current_channel));
2998        if (is_hal_stop(rtlhal))
2999                return;
3000

3001        if (36 <= channel && channel <= 48)
3002                data = 0x494;
3003        else if (50 <= channel && channel <= 64)
3004                data = 0x453;
3005        else if (100 <= channel && channel <= 116)
3006                data = 0x452;
3007        else if (118 <= channel)
3008                data = 0x412;
3009        else
3010                data = 0x96a;
3011        rtl_set_bbreg(hw, RFC_AREA, 0x1ffe0000, data);
3012
3013
3014        for(path = RF90_PATH_A; path < rtlphy->num_total_rfpath; path++)
3015        {
3016                if (36 <= channel && channel <= 64)
3017                        data = 0x101;
3018                else if (100 <= channel && channel <= 140)
3019                        data = 0x301;
3020                else if (140 < channel)
3021                        data = 0x501;
3022                else
3023                        data = 0x000;
3024                rtl8821ae_phy_set_rf_reg(hw, path, RF_CHNLBW,
3025                        BIT(18)|BIT(17)|BIT(16)|BIT(9)|BIT(8), data);
3026
3027                rtl8821ae_phy_set_rf_reg(hw, path, RF_CHNLBW,
3028                        BMASKBYTE0, channel);
3029
3030                if (channel > 14) {
3031                        if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
3032                                if (36 <= channel && channel <= 64)
3033                                        data = 0x114E9;
3034                                else if (100 <= channel && channel <= 140)
3035                                        data = 0x110E9;
3036                                else
3037                                        data = 0x110E9;
3038                                rtl8821ae_phy_set_rf_reg(hw, path, RF_APK,
3039                                        BRFREGOFFSETMASK, data);
3040                        }
3041                }
3042        }
3043        RT_TRACE(COMP_SCAN, DBG_TRACE, ("\n"));
3044}
3045
3046u8 rtl8821ae_phy_sw_chnl(struct ieee80211_hw *hw)
3047{
3048        struct rtl_priv *rtlpriv = rtl_priv(hw);
3049        struct rtl_phy *rtlphy = &(rtlpriv->phy);
3050        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3051        u32 timeout = 1000, timecount = 0;
3052        u8 channel = rtlphy->current_channel;
3053
3054        if (rtlphy->sw_chnl_inprogress)
3055                return 0;
3056        if (rtlphy->set_bwmode_inprogress)
3057                return 0;
3058
3059        if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) {
3060                RT_TRACE(COMP_CHAN, DBG_LOUD,
3061                         ("sw_chnl_inprogress false driver sleep or unload\n"));
3062                return 0;
3063        }
3064        while (rtlphy->lck_inprogress && timecount < timeout) {
3065                mdelay(50);
3066                timecount += 50;
3067        }
3068
3069        if (rtlphy->current_channel > 14 && rtlhal->current_bandtype != BAND_ON_5G)
3070                rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_5G);
3071        else if (rtlphy->current_channel <= 14 && rtlhal->current_bandtype != BAND_ON_2_4G)
3072                rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_2_4G);
3073
3074        rtlphy->sw_chnl_inprogress = true;
3075        if (channel == 0)
3076                channel = 1;
3077
3078        RT_TRACE(COMP_SCAN, DBG_TRACE,
3079                 ("switch to channel%d, band type is %d\n", rtlphy->current_channel, rtlhal->current_bandtype));
3080
3081        rtl8821ae_phy_sw_chnl_callback(hw);
3082
3083        rtl8821ae_dm_clear_txpower_tracking_state(hw);
3084        rtl8821ae_phy_set_txpower_level(hw, rtlphy->current_channel);
3085
3086        RT_TRACE(COMP_SCAN, DBG_TRACE, ("\n"));
3087        rtlphy->sw_chnl_inprogress = false;
3088        return 1;
3089}
3090
3091#if 0
3092static u8 _rtl8821ae_phy_path_b_iqk(struct ieee80211_hw *hw)
3093{
3094        u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3095        u8 result = 0x00;
3096
3097        rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002);
3098        rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000);
3099        mdelay(IQK_DELAY_TIME);
3100        reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
3101        reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
3102        reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
3103        reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
3104        reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
3105
3106        if (!(reg_eac & BIT(31)) &&
3107            (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) &&
3108            (((reg_ebc & 0x03FF0000) >> 16) != 0x42))
3109                result |= 0x01;
3110        else
3111                return result;
3112        if (!(reg_eac & BIT(30)) &&
3113            (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) &&
3114            (((reg_ecc & 0x03FF0000) >> 16) != 0x36))
3115                result |= 0x02;
3116        return result;
3117}
3118
3119static u8 _rtl8821ae_phy_path_a_rx_iqk(struct ieee80211_hw *hw, bool config_pathb)
3120{
3121        u32 reg_eac, reg_e94, reg_e9c, reg_ea4,u32temp;
3122        u8 result = 0x00;
3123
3124        /*Get TXIMR Setting*/
3125        /*Modify RX IQK mode table*/
3126        rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
3127        rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);
3128        rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
3129        rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f);
3130        rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b);
3131        rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
3132
3133        /*IQK Setting*/
3134        rtl_set_bbreg(hw, RTx_IQK, MASKDWORD, 0x01007c00);
3135        rtl_set_bbreg(hw, RRx_IQK, MASKDWORD, 0x81004800);
3136
3137        /*path a IQK setting*/
3138        rtl_set_bbreg(hw, RTx_IQK_Tone_A, MASKDWORD, 0x10008c1c);
3139        rtl_set_bbreg(hw, RRx_IQK_Tone_A, MASKDWORD, 0x30008c1c);
3140        rtl_set_bbreg(hw, RTx_IQK_PI_A, MASKDWORD, 0x82160804);
3141        rtl_set_bbreg(hw, RRx_IQK_PI_A, MASKDWORD, 0x28160000);
3142
3143        /*LO calibration Setting*/
3144        rtl_set_bbreg(hw, RIQK_AGC_Rsp, MASKDWORD, 0x0046a911);
3145        /*one shot,path A LOK & iqk*/
3146        rtl_set_bbreg(hw, RIQK_AGC_Pts, MASKDWORD, 0xf9000000);
3147        rtl_set_bbreg(hw, RIQK_AGC_Pts, MASKDWORD, 0xf8000000);
3148
3149        mdelay(IQK_DELAY_TIME);
3150
3151        reg_eac = rtl_get_bbreg(hw, RRx_Power_After_IQK_A_2, MASKDWORD);
3152        reg_e94 = rtl_get_bbreg(hw, RTx_Power_Before_IQK_A, MASKDWORD);
3153        reg_e9c = rtl_get_bbreg(hw, RTx_Power_After_IQK_A, MASKDWORD);
3154
3155
3156        if (!(reg_eac & BIT(28)) &&
3157            (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
3158            (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
3159                result |= 0x01;
3160        else
3161                return result;
3162
3163        u32temp = 0x80007C00 | (reg_e94&0x3FF0000)  | ((reg_e9c&0x3FF0000) >> 16);
3164        rtl_set_bbreg(hw, RTx_IQK, MASKDWORD, u32temp);
3165        /*RX IQK*/
3166        /*Modify RX IQK mode table*/
3167        rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
3168        rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);
3169        rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
3170        rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f);
3171        rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa);
3172        rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
3173
3174        /*IQK Setting*/
3175        rtl_set_bbreg(hw, RRx_IQK, MASKDWORD, 0x01004800);
3176
3177        /*path a IQK setting*/
3178        rtl_set_bbreg(hw, RTx_IQK_Tone_A, MASKDWORD, 0x30008c1c);
3179        rtl_set_bbreg(hw, RRx_IQK_Tone_A, MASKDWORD, 0x10008c1c);
3180        rtl_set_bbreg(hw, RTx_IQK_PI_A, MASKDWORD, 0x82160c05);
3181        rtl_set_bbreg(hw, RRx_IQK_PI_A, MASKDWORD, 0x28160c05);
3182
3183        /*LO calibration Setting*/
3184        rtl_set_bbreg(hw, RIQK_AGC_Rsp, MASKDWORD, 0x0046a911);
3185        /*one shot,path A LOK & iqk*/
3186        rtl_set_bbreg(hw, RIQK_AGC_Pts, MASKDWORD, 0xf9000000);
3187        rtl_set_bbreg(hw, RIQK_AGC_Pts, MASKDWORD, 0xf8000000);
3188
3189        mdelay(IQK_DELAY_TIME);
3190
3191        reg_eac = rtl_get_bbreg(hw, RRx_Power_After_IQK_A_2, MASKDWORD);
3192        reg_e94 = rtl_get_bbreg(hw, RTx_Power_Before_IQK_A, MASKDWORD);
3193        reg_e9c = rtl_get_bbreg(hw, RTx_Power_After_IQK_A, MASKDWORD);
3194        reg_ea4 = rtl_get_bbreg(hw, RRx_Power_Before_IQK_A_2, MASKDWORD);
3195
3196        if (!(reg_eac & BIT(27)) &&
3197            (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
3198            (((reg_eac & 0x03FF0000) >> 16) != 0x36))
3199                result |= 0x02;
3200        return result;
3201}
3202#endif
3203
3204u8 _rtl8812ae_get_right_chnl_place_for_iqk(u8 chnl)
3205{
3206        u8 channel_all[TARGET_CHNL_NUM_2G_5G_8812] =
3207                {1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,38,40,42,\
3208                44,46,48,50,52,54,56,58,60,62,64,100,\
3209                102,104,106,108,110,112,114,116,118,\
3210                120,122,124,126,128,130,132,134,136,\
3211                138,140,149,151,153,155,157,159,161,\
3212                163,165};
3213        u8 place = chnl;
3214
3215        if(chnl > 14)
3216        {
3217                for(place = 14; place<sizeof(channel_all); place++)
3218                {
3219                        if(channel_all[place] == chnl)
3220                        {
3221                                return place-13;
3222                        }
3223                }
3224        }
3225
3226        return 0;
3227}
3228
3229void _rtl8812ae_iqk_rx_fill_iqc(
3230        struct ieee80211_hw *hw,
3231        enum radio_path path,
3232        u32 rx_x,
3233        u32 rx_y
3234        )
3235{
3236        struct rtl_priv *rtlpriv = rtl_priv(hw);
3237
3238        switch (path) {
3239        case RF90_PATH_A:
3240                {
3241                        rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3242                        if (rx_x >> 1 ==0x112 || rx_y >> 1 == 0x3ee){
3243                                rtl_set_bbreg(hw, 0xc10, 0x000003ff, 0x100);
3244                                rtl_set_bbreg(hw, 0xc10, 0x03ff0000, 0);
3245                                RT_TRACE(COMP_IQK, DBG_LOUD,
3246                                        ("RX_X = %x;;RX_Y = %x ====>fill to IQC\n",
3247                                        rx_x >> 1 & 0x000003ff, rx_y >> 1 & 0x000003ff));
3248                        }
3249                        else{
3250                                rtl_set_bbreg(hw, 0xc10, 0x000003ff, rx_x >> 1);
3251                                rtl_set_bbreg(hw, 0xc10, 0x03ff0000, rx_y >> 1);
3252                                RT_TRACE(COMP_IQK, DBG_LOUD,
3253                                        ("RX_X = %x;;RX_Y = %x ====>fill to IQC\n",
3254                                        rx_x >> 1 & 0x000003ff, rx_y >> 1 & 0x000003ff));
3255                                RT_TRACE(COMP_IQK, DBG_LOUD,
3256                                        ("0xc10 = %x ====>fill to IQC\n",
3257                                        rtl_read_dword(rtlpriv, 0xc10)));
3258                        }
3259                }
3260                break;
3261        case RF90_PATH_B:
3262                {
3263                        rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3264                        if (rx_x >> 1 ==0x112 || rx_y >> 1 == 0x3ee){
3265                                rtl_set_bbreg(hw, 0xe10, 0x000003ff, 0x100);
3266                                rtl_set_bbreg(hw, 0xe10, 0x03ff0000, 0);
3267                                RT_TRACE(COMP_IQK, DBG_LOUD,
3268                                        ("RX_X = %x;;RX_Y = %x ====>fill to IQC\n",
3269                                        rx_x >> 1 & 0x000003ff, rx_y >> 1 & 0x000003ff));
3270                        }
3271                        else{
3272                                rtl_set_bbreg(hw, 0xe10, 0x000003ff, rx_x >> 1);
3273                                rtl_set_bbreg(hw, 0xe10, 0x03ff0000, rx_y >> 1);
3274                                RT_TRACE(COMP_IQK, DBG_LOUD,
3275                                        ("RX_X = %x;;RX_Y = %x====>fill to IQC\n ",
3276                                        rx_x >> 1 & 0x000003ff, rx_y >> 1 & 0x000003ff));
3277                                RT_TRACE(COMP_IQK, DBG_LOUD,
3278                                        ("0xe10 = %x====>fill to IQC\n",
3279                                        rtl_read_dword(rtlpriv, 0xe10)));
3280                        }
3281                }
3282                break;
3283        default:
3284                break;
3285        };
3286}
3287
3288void _rtl8812ae_iqk_tx_fill_iqc(
3289        struct ieee80211_hw *hw,
3290        enum radio_path path,
3291        u32 tx_x,
3292        u32 tx_y
3293        )
3294{
3295        struct rtl_priv *rtlpriv = rtl_priv(hw);
3296
3297        switch (path) {
3298        case RF90_PATH_A:
3299                {
3300                        rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /*[31] = 1 --> Page C1*/
3301                        rtl_write_dword(rtlpriv, 0xc90, 0x00000080);
3302                        rtl_write_dword(rtlpriv, 0xcc4, 0x20040000);
3303                        rtl_write_dword(rtlpriv, 0xcc8, 0x20000000);
3304                        rtl_set_bbreg(hw, 0xccc, 0x000007ff, tx_y);
3305                        rtl_set_bbreg(hw, 0xcd4, 0x000007ff, tx_x);
3306                        RT_TRACE(COMP_IQK, DBG_LOUD,
3307                                ("TX_X = %x;;TX_Y = %x =====> fill to IQC\n",
3308                                tx_x & 0x000007ff, tx_y & 0x000007ff));
3309                        RT_TRACE(COMP_IQK, DBG_LOUD,
3310                                ("0xcd4 = %x;;0xccc = %x ====>fill to IQC\n",
3311                                rtl_get_bbreg(hw, 0xcd4, 0x000007ff),
3312                                rtl_get_bbreg(hw, 0xccc, 0x000007ff)));
3313                }
3314                break;
3315        case RF90_PATH_B:
3316                {
3317                        rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /*[31] = 1 --> Page C1*/
3318                        rtl_write_dword(rtlpriv, 0xe90, 0x00000080);
3319                        rtl_write_dword(rtlpriv, 0xec4, 0x20040000);
3320                        rtl_write_dword(rtlpriv, 0xec8, 0x20000000);
3321                        rtl_set_bbreg(hw, 0xecc, 0x000007ff, tx_y);
3322                        rtl_set_bbreg(hw, 0xed4, 0x000007ff, tx_x);
3323                        RT_TRACE(COMP_IQK, DBG_LOUD,
3324                                ("TX_X = %x;;TX_Y = %x =====> fill to IQC\n",
3325                                tx_x&0x000007ff, tx_y&0x000007ff));
3326                        RT_TRACE(COMP_IQK, DBG_LOUD,
3327                                ("0xed4 = %x;;0xecc = %x ====>fill to IQC\n",
3328                                rtl_get_bbreg(hw, 0xed4, 0x000007ff),
3329                                rtl_get_bbreg(hw, 0xecc, 0x000007ff)));
3330                }
3331                break;
3332        default:
3333                break;
3334        };
3335}
3336
3337void _rtl8812ae_iqk_backup_macbb(
3338        struct ieee80211_hw *hw,
3339        u32 *macbb_backup,
3340        u32 *backup_macbb_reg,
3341        u32 mac_bb_num
3342        )
3343{
3344        struct rtl_priv *rtlpriv = rtl_priv(hw);
3345        u32 i;
3346
3347        rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3348         /*save MACBB default value*/
3349        for (i = 0; i < mac_bb_num; i++) {
3350                macbb_backup[i] =rtl_read_dword(rtlpriv,backup_macbb_reg[i]);
3351        }
3352
3353        RT_TRACE(COMP_IQK, DBG_LOUD, ("BackupMacBB Success!!!!\n"));
3354}
3355
3356void _rtl8812ae_iqk_backup_afe(
3357        struct ieee80211_hw *hw,
3358        u32 *afe_backup,
3359        u32 *backup_afe_REG,
3360        u32 afe_num
3361        )
3362{
3363        struct rtl_priv *rtlpriv = rtl_priv(hw);
3364        u32 i;
3365
3366        rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3367        /*Save AFE Parameters */
3368        for (i = 0; i < afe_num; i++){
3369                afe_backup[i] = rtl_read_dword(rtlpriv, backup_afe_REG[i]);
3370        }
3371        RT_TRACE(COMP_IQK, DBG_LOUD, ("BackupAFE Success!!!!\n"));
3372}
3373
3374void _rtl8812ae_iqk_backup_rf(
3375        struct ieee80211_hw *hw,
3376        u32 *rfa_backup,
3377        u32 *rfb_backup,
3378        u32 *backup_rf_reg,
3379        u32 rf_num
3380        )
3381{
3382
3383        struct rtl_priv *rtlpriv = rtl_priv(hw);
3384        u32 i;
3385
3386        rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3387        /*Save RF Parameters*/
3388        for (i = 0; i < rf_num; i++){
3389                rfa_backup[i] = rtl_get_rfreg(hw, RF90_PATH_A, backup_rf_reg[i], BMASKDWORD);
3390                rfb_backup[i] = rtl_get_rfreg(hw, RF90_PATH_B, backup_rf_reg[i], BMASKDWORD);
3391        }
3392        RT_TRACE(COMP_IQK, DBG_LOUD, ("BackupRF Success!!!!\n"));
3393}
3394
3395void _rtl8812ae_iqk_configure_mac(
3396        struct ieee80211_hw *hw
3397        )
3398{
3399        struct rtl_priv *rtlpriv = rtl_priv(hw);
3400        /* ========MAC register setting========*/
3401        rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3402        rtl_write_byte(rtlpriv, 0x522, 0x3f);
3403        rtl_set_bbreg(hw, 0x550, BIT(11) | BIT(3), 0x0);
3404        rtl_write_byte(rtlpriv, 0x808, 0x00);           /*RX ante off*/
3405        rtl_set_bbreg(hw, 0x838, 0xf, 0xc);             /*CCA off*/
3406}
3407
3408#define cal_num 10
3409
3410void _rtl8812ae_iqk_tx(
3411        struct ieee80211_hw *hw,
3412        u8 chnl_idx
3413        )
3414{
3415        struct rtl_priv *rtlpriv = rtl_priv(hw);
3416        struct rtl_phy *rtlphy = &(rtlpriv->phy);
3417        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3418
3419        u8 delay_count;
3420        u8 cal0_retry, cal1_retry;
3421        u8 tx0_average = 0, tx1_average = 0, rx0_average = 0, rx1_average = 0;
3422        int tx0_x = 0, tx0_y = 0, rx0_x = 0, rx0_y = 0;
3423        int tx_x0[cal_num], tx_y0[cal_num], rx_x0[cal_num], rx_y0[cal_num];
3424        int tx1_x = 0, tx1_y = 0, rx1_x = 0, rx1_y = 0;
3425        int tx_x1[cal_num], tx_y1[cal_num], rx_x1[cal_num], rx_y1[cal_num];
3426        bool tx0iqkok= false, rx0iqkok = false, tx0_fail = true, rx0_fail;
3427        bool iqk0_ready = false, tx0_finish = false, rx0_finish = false;
3428        bool tx1iqkok = false, rx1iqkok = false, tx1_fail = true, rx1_fail;
3429        bool iqk1_ready = false, tx1_finish = false, rx1_finish = false, vdf_enable = false;
3430        int i, tx_dt[3] = {0}, rx_dt[3] = {0}, ii, dx = 0, dy = 0;
3431
3432        RT_TRACE(COMP_IQK, DBG_LOUD,
3433                        ("BandWidth = %d.\n",
3434                        rtlphy->current_chan_bw));
3435        if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80){
3436                vdf_enable = true;
3437        }
3438        vdf_enable = false;
3439
3440
3441        rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3442        /*========Path-A AFE all on========*/
3443        /*Port 0 DAC/ADC on*/
3444        rtl_write_dword(rtlpriv, 0xc60, 0x77777777);
3445        rtl_write_dword(rtlpriv, 0xc64, 0x77777777);
3446
3447        /* Port 1 DAC/ADC off*/
3448        rtl_write_dword(rtlpriv, 0xe60, 0x77777777);
3449        rtl_write_dword(rtlpriv, 0xe64, 0x77777777);
3450
3451        rtl_write_dword(rtlpriv, 0xc68, 0x19791979);
3452        rtl_write_dword(rtlpriv, 0xe68, 0x19791979);
3453        rtl_set_bbreg(hw,0xc00, 0xf, 0x4);/*hardware 3-wire off*/
3454        rtl_set_bbreg(hw,0xe00, 0xf, 0x4);/*hardware 3-wire off*/
3455
3456        /*DAC/ADC sampling rate (160 MHz)*/
3457        rtl_set_bbreg(hw, 0xc5c, BIT(26) | BIT(25) | BIT(24), 0x7);
3458        rtl_set_bbreg(hw, 0xe5c, BIT(26) | BIT(25) | BIT(24), 0x7);
3459        rtl_set_bbreg(hw, 0x8c4, BIT(30), 0x1);
3460
3461        /*====== Path A TX IQK RF Setting ======*/
3462        rtl_set_bbreg(hw,0x82c, BIT(31), 0x0); // [31] = 0 --> Page C
3463        rtl_set_rfreg(hw,RF90_PATH_A, 0xef, BRFREGOFFSETMASK, 0x80002);
3464        rtl_set_rfreg(hw,RF90_PATH_A, 0x30, BRFREGOFFSETMASK, 0x20000);
3465        rtl_set_rfreg(hw,RF90_PATH_A, 0x31, BRFREGOFFSETMASK, 0x3fffd);
3466        rtl_set_rfreg(hw,RF90_PATH_A, 0x32, BRFREGOFFSETMASK, 0xfe83f);
3467        rtl_set_rfreg(hw,RF90_PATH_A, 0x65, BRFREGOFFSETMASK, 0x931d5);
3468        rtl_set_rfreg(hw,RF90_PATH_A, 0x8f, BRFREGOFFSETMASK, 0x8a001);
3469        /*====== Path A TX IQK RF Setting ======*/
3470        rtl_set_rfreg(hw,RF90_PATH_B, 0xef, BRFREGOFFSETMASK, 0x80002);
3471        rtl_set_rfreg(hw,RF90_PATH_B, 0x30, BRFREGOFFSETMASK, 0x20000);
3472        rtl_set_rfreg(hw,RF90_PATH_B, 0x31, BRFREGOFFSETMASK, 0x3fffd);
3473        rtl_set_rfreg(hw,RF90_PATH_B, 0x32, BRFREGOFFSETMASK, 0xfe83f);
3474        rtl_set_rfreg(hw,RF90_PATH_B, 0x65, BRFREGOFFSETMASK, 0x931d5);
3475        rtl_set_rfreg(hw,RF90_PATH_B, 0x8f, BRFREGOFFSETMASK, 0x8a001);
3476        rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
3477        rtl_write_dword(rtlpriv, 0xb00, 0x03000100);
3478        rtl_set_bbreg(hw, 0xc94, BIT(0), 0x1);
3479        rtl_set_bbreg(hw, 0xe94, BIT(0), 0x1);
3480        rtl_write_dword(rtlpriv, 0x978, 0x29002000);/* TX (X,Y)*/
3481        rtl_write_dword(rtlpriv, 0x97c, 0xa9002000);/* RX (X,Y)*/
3482        rtl_write_dword(rtlpriv, 0x984, 0x00462910);/*[0]:AGC_en, [15]:idac_K_Mask*/
3483        rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1*/
3484
3485        /*ExternalPA_5G == 0*/
3486        rtl_write_dword(rtlpriv, 0xc88, 0x821403f1);
3487        rtl_write_dword(rtlpriv, 0xe88, 0x821403f1);
3488
3489        if (rtlhal->current_bandtype){
3490                rtl_write_dword(rtlpriv, 0xc8c, 0x68163e96);
3491                rtl_write_dword(rtlpriv, 0xe8c, 0x68163e96);
3492        }
3493        else{
3494                rtl_write_dword(rtlpriv, 0xc8c, 0x28163e96);
3495                rtl_write_dword(rtlpriv, 0xe8c, 0x28163e96);
3496        }
3497
3498        if (vdf_enable){}
3499        else{
3500                rtl_write_dword(rtlpriv, 0xc80, 0x18008c10);/*TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16*/
3501                rtl_write_dword(rtlpriv, 0xc84, 0x38008c10);/*RX_Tone_idx[9:0], RxK_Mask[29]*/
3502                rtl_write_dword(rtlpriv, 0xce8, 0x00000000);
3503                rtl_write_dword(rtlpriv, 0xe80, 0x18008c10);/*TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16*/
3504                rtl_write_dword(rtlpriv, 0xe84, 0x38008c10);/*RX_Tone_idx[9:0], RxK_Mask[29]*/
3505                rtl_write_dword(rtlpriv, 0xee8, 0x00000000);
3506
3507                cal0_retry = 0;
3508                cal1_retry = 0;
3509                while(1){
3510                        /*one shot*/
3511                        rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] �N SI/PI �ϥ��v���� iqk_dpk module*/
3512                        rtl_write_dword(rtlpriv, 0xeb8, 0x00100000);/* cb8[20] �N SI/PI �ϥ��v���� iqk_dpk module*/
3513                        rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
3514                        rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
3515
3516                        mdelay(10); /*Delay 25ms*/
3517                        rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
3518                        rtl_write_dword(rtlpriv, 0xeb8, 0x00000000);
3519                        delay_count = 0;
3520                        while (1){
3521                                if (!tx0_finish)
3522                                        iqk0_ready = (bool) rtl_get_bbreg(hw, 0xd00, BIT(10));
3523                                if (!tx1_finish)
3524                                        iqk1_ready = (bool) rtl_get_bbreg(hw, 0xd40, BIT(10));
3525                                if ((iqk0_ready && iqk1_ready) || (delay_count>20))
3526                                        break;
3527                                else{
3528                                mdelay(1);
3529                                delay_count++;
3530                                }
3531                        }
3532                        RT_TRACE(COMP_IQK, DBG_LOUD, ("TX delay_count = %d\n", delay_count));
3533                        if (delay_count < 20){                                                  // If 20ms No Result, then cal_retry++
3534                                /* ============TXIQK Check==============*/
3535                                tx0_fail = (bool) rtl_get_bbreg(hw, 0xd00, BIT(12));
3536                                tx1_fail = (bool) rtl_get_bbreg(hw, 0xd40, BIT(12));
3537                                if (!(tx0_fail || tx0_finish)){
3538                                        rtl_write_dword(rtlpriv, 0xcb8, 0x02000000);
3539                                        tx_x0[tx0_average] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000) << 21;
3540                                        rtl_write_dword(rtlpriv, 0xcb8, 0x04000000);
3541                                        tx_y0[tx0_average] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000) << 21;
3542                                        tx0iqkok = true;
3543                                        RT_TRACE(COMP_IQK, DBG_LOUD,
3544                                                ("TX_X0[%d] = %x ;; TX_Y0[%d] = %x\n",
3545                                                tx0_average, (tx_x0[tx0_average]) >> 21 & 0x000007ff,
3546                                                tx0_average, (tx_y0[tx0_average]) >> 21 & 0x000007ff));
3547
3548                                        tx0_average++;
3549                        }
3550                        else{
3551                                tx0iqkok = false;
3552                                cal0_retry++;
3553                                if (cal0_retry == 10)
3554                                        break;
3555                                }
3556                        if (!(tx1_fail || tx1_finish)){
3557                                rtl_write_dword(rtlpriv, 0xeb8, 0x02000000);
3558                                tx_x1[tx1_average] = rtl_get_bbreg(hw, 0xd40, 0x07ff0000) << 21;
3559                                rtl_write_dword(rtlpriv, 0xeb8, 0x04000000);
3560                                tx_y1[tx1_average] = rtl_get_bbreg(hw, 0xd40, 0x07ff0000) << 21;
3561                                tx1iqkok= true;
3562                                RT_TRACE(COMP_IQK, DBG_LOUD,
3563                                        ("TX_X1[%d] = %x ;; TX_Y1[%d] = %x\n",
3564                                        tx1_average, (tx_x1[tx1_average]) >> 21 & 0x000007ff,
3565                                        tx1_average, (tx_y1[tx1_average]) >> 21 & 0x000007ff));
3566
3567                                tx1_average++;
3568                                }
3569                        else{
3570                                tx1iqkok = false;
3571                                cal1_retry++;
3572                                if (cal1_retry == 10)
3573                                        break;
3574                                }
3575                        }
3576                        else{
3577                                tx0iqkok = false;
3578                                tx1iqkok = false;
3579                                cal0_retry++;
3580                                cal1_retry++;
3581                                RT_TRACE(COMP_IQK, DBG_LOUD,
3582                                        ("Delay 20ms TX IQK Not Ready!!!!!\n"));
3583                                if (cal0_retry == 10)
3584                                        break;
3585                        }
3586                        if (tx0_average >= 2){
3587                                for (i = 0; i < tx0_average; i++){
3588                                        for (ii = i+1; ii <tx0_average; ii++){
3589                                                dx = (tx_x0[i] >> 21) - (tx_x0[ii] >> 21);
3590                                                if (dx < 4 && dx > -4){
3591                                                        dy = (tx_y0[i]>>21) - (tx_y0[ii]>>21);
3592                                                        if (dy < 4 && dy > -4){
3593                                                                tx0_x = ((tx_x0[i] >> 21) + (tx_x0[ii] >> 21)) / 2;
3594                                                                tx0_y = ((tx_y0[i] >> 21) + (tx_y0[ii] >> 21)) / 2;
3595                                                                tx_x0[0] = tx_x0[i];
3596                                                                tx_y0[1] = tx_y0[ii];
3597                                                                RT_TRACE(COMP_IQK, DBG_LOUD,
3598                                                                        ("TX0_X = %x;;TX0_Y = %x\n",
3599                                                                        tx0_x & 0x000007ff, tx0_y & 0x000007ff));
3600                                                                if ((rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80)
3601                                                                        && vdf_enable) {
3602                                                                        tx_dt[0] = (tx_dt[i] + tx_dt[ii]) / 2;
3603                                                                }
3604                                                                tx0_finish = true;
3605                                                        }
3606                                                }
3607                                        }
3608                                }
3609                        }
3610                        if (tx1_average >= 2){
3611                                for (i = 0; i < tx1_average; i++){
3612                                        for (ii = i+1; ii < tx1_average; ii++){
3613                                                dx = (tx_x1[i] >> 21) - (tx_x1[ii] >> 21);
3614                                                if (dx < 4 && dx > -4){
3615                                                        dy = (tx_y1[i] >> 21) - (tx_y1[ii] >> 21);
3616                                                        if (dy < 4 && dy > -4){
3617                                                                tx1_x = ((tx_x1[i] >> 21) + (tx_x1[ii] >> 21)) / 2;
3618                                                                tx1_y = ((tx_y1[i] >> 21) + (tx_y1[ii] >> 21)) / 2;
3619                                                                tx_x1[0] = tx_x1[i];
3620                                                                tx_y1[1] = tx_y1[ii];
3621                                                                RT_TRACE(COMP_IQK, DBG_LOUD,
3622                                                                        ("TX1_X = %x;;TX1_Y = %x\n",
3623                                                                        tx1_x & 0x000007ff, tx1_y & 0x000007ff));
3624                                                                if ((rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80)
3625                                                                        && vdf_enable) {
3626                                                                        tx_dt[0] = (tx_dt[i] +  tx_dt[ii]) / 2;
3627                                                                }
3628                                                                tx1_finish = true;
3629                                                        }
3630                                                }
3631                                        }
3632                                }
3633                        }
3634                        RT_TRACE(COMP_IQK, DBG_LOUD,
3635                                ("TX0_Average = %d, TX1_Average = %d\n",
3636                                tx0_average, tx1_average));
3637                        RT_TRACE(COMP_IQK, DBG_LOUD,
3638                                ("TX0_finish = %d, TX1_finish = %d\n",
3639                                tx0_finish, tx1_finish));
3640                        if (tx0_finish && tx1_finish)
3641                                break;
3642                        if ((cal0_retry + tx0_average) >= 10
3643                                || (cal1_retry + tx1_average) >= 10 )
3644                                break;
3645                }
3646                RT_TRACE(COMP_IQK, DBG_LOUD,
3647                        ("TXA_cal_retry = %d\n", cal0_retry));
3648                RT_TRACE(COMP_IQK, DBG_LOUD,
3649                        ("TXB_cal_retry = %d\n", cal1_retry));
3650
3651        }
3652
3653        rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C*/
3654        rtl_set_rfreg(hw, RF90_PATH_A, 0x58, 0x7fe00,
3655                rtl_get_rfreg(hw, RF90_PATH_A, 0x8, 0xffc00)); /*Load LOK*/
3656        rtl_set_rfreg(hw, RF90_PATH_B, 0x58, 0x7fe00,
3657                rtl_get_rfreg(hw, RF90_PATH_B, 0x8, 0xffc00)); /* Load LOK*/
3658        rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /*[31] = 1 --> Page C1*/
3659
3660
3661        if (vdf_enable) {}
3662        else{
3663                rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3664                if (tx0_finish) {
3665                        /*====== Path A RX IQK RF Setting======*/
3666                        rtl_set_rfreg(hw, RF90_PATH_A, 0xef, BRFREGOFFSETMASK, 0x80000);
3667                        rtl_set_rfreg(hw, RF90_PATH_A, 0x18, 0x00c00, 0x3);     /* BW 20M*/
3668                        rtl_set_rfreg(hw, RF90_PATH_A, 0x30, BRFREGOFFSETMASK, 0x30000);
3669                        rtl_set_rfreg(hw, RF90_PATH_A, 0x31, BRFREGOFFSETMASK, 0x3f7ff);
3670                        rtl_set_rfreg(hw, RF90_PATH_A, 0x32, BRFREGOFFSETMASK, 0xfe7bf);
3671                        rtl_set_rfreg(hw, RF90_PATH_A, 0x8f, BRFREGOFFSETMASK, 0x88001);
3672                        rtl_set_rfreg(hw, RF90_PATH_A, 0x65, BRFREGOFFSETMASK, 0x931d6);
3673                        rtl_set_rfreg(hw, RF90_PATH_A, 0xef, BRFREGOFFSETMASK, 0x00000);
3674                }
3675                if (tx1_finish){
3676                        /*====== Path B RX IQK RF Setting======*/
3677                        rtl_set_rfreg(hw, RF90_PATH_B, 0xef, BRFREGOFFSETMASK, 0x80000);
3678                        rtl_set_rfreg(hw, RF90_PATH_B, 0x30, BRFREGOFFSETMASK, 0x30000);
3679                        rtl_set_rfreg(hw, RF90_PATH_B, 0x31, BRFREGOFFSETMASK, 0x3f7ff);
3680                        rtl_set_rfreg(hw, RF90_PATH_B, 0x32, BRFREGOFFSETMASK, 0xfe7bf);
3681                        rtl_set_rfreg(hw, RF90_PATH_B, 0x8f, BRFREGOFFSETMASK, 0x88001);
3682                        rtl_set_rfreg(hw, RF90_PATH_B, 0x65, BRFREGOFFSETMASK, 0x931d1);
3683                        rtl_set_rfreg(hw, RF90_PATH_B, 0xef, BRFREGOFFSETMASK, 0x00000);
3684                }
3685                rtl_set_bbreg(hw, 0x978, BIT(31), 0x1);
3686                rtl_set_bbreg(hw, 0x97c, BIT(31), 0x0);
3687                rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
3688                rtl_write_dword(rtlpriv, 0x984, 0x0046a890);
3689
3690                rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /*[31] = 1 --> Page C1*/
3691                if (tx0_finish) {
3692                        rtl_write_dword(rtlpriv, 0xc80, 0x38008c10);/*TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16*/
3693                        rtl_write_dword(rtlpriv, 0xc84, 0x18008c10);/*RX_Tone_idx[9:0], RxK_Mask[29]*/
3694                        rtl_write_dword(rtlpriv, 0xc88, 0x02140119);
3695                        rtl_write_dword(rtlpriv, 0xc8c, 0x28160cc0);
3696                }
3697                if (tx1_finish){
3698                        rtl_write_dword(rtlpriv, 0xe80, 0x38008c10);/*TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16*/
3699                        rtl_write_dword(rtlpriv, 0xe84, 0x18008c10);/*RX_Tone_idx[9:0], RxK_Mask[29]*/
3700                        rtl_write_dword(rtlpriv, 0xe88, 0x02140119);
3701                        rtl_write_dword(rtlpriv, 0xe8c, 0x28160ca0);
3702                }
3703              cal0_retry = 0;
3704                cal1_retry = 0;
3705                while(1){
3706                    /* one shot*/
3707                        rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3708                        if (tx0_finish){
3709                                rtl_set_bbreg(hw, 0x978, 0x03FF8000, (tx_x0[rx0_average % 2]) >> 21 & 0x000007ff);
3710                                rtl_set_bbreg(hw, 0x978, 0x000007FF, (tx_y0[rx0_average % 2]) >> 21 & 0x000007ff);
3711                                rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1*/
3712                                rtl_write_dword(rtlpriv, 0xcb8, 0x00300000);/*cb8[20] �N SI/PI �ϥ��v���� iqk_dpk module*/
3713                                rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);
3714                                mdelay(5); /*Delay 10ms*/
3715                        }
3716                        if (tx1_finish){
3717                                rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3718                                rtl_set_bbreg(hw, 0x978, 0x03FF8000, (tx_x1[rx1_average % 2]) >> 21 & 0x000007ff);
3719                                rtl_set_bbreg(hw, 0x978, 0x000007FF, (tx_y1[rx1_average % 2]) >> 21 & 0x000007ff);
3720                                rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /*[31] = 1 --> Page C1*/
3721                                rtl_write_dword(rtlpriv, 0xeb8, 0x00300000);/*cb8[20] �N SI/PI �ϥ��v���� iqk_dpk module*/
3722                                rtl_write_dword(rtlpriv, 0xeb8, 0x00100000);/* cb8[20] �N SI/PI �ϥ��v���� iqk_dpk module*/
3723                        }
3724                        mdelay(10); /*Delay 10ms*/
3725                        rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
3726                        rtl_write_dword(rtlpriv, 0xeb8, 0x00000000);
3727                        delay_count = 0;
3728                        while (1){
3729                                if (!rx0_finish && tx0_finish)
3730                                        iqk0_ready = (bool) rtl_get_bbreg(hw, 0xd00, BIT(10));
3731                                if (!rx1_finish && tx1_finish)
3732                                        iqk1_ready = (bool) rtl_get_bbreg(hw, 0xd40, BIT(10));
3733                                if ((iqk0_ready && iqk1_ready)||(delay_count>20))
3734                                        break;
3735                                else{
3736                                        mdelay(1);
3737                                        delay_count++;
3738                                }
3739                        }
3740                        RT_TRACE(COMP_IQK, DBG_LOUD,
3741                                ("RX delay_count = %d\n", delay_count));
3742                        if (delay_count < 20){  // If 20ms No Result, then cal_retry++
3743                                // ============RXIQK Check==============
3744                                rx0_fail = (bool) rtl_get_bbreg(hw, 0xd00, BIT(11));
3745                                rx1_fail = (bool) rtl_get_bbreg(hw, 0xd40, BIT(11));
3746                                if (!(rx0_fail || rx0_finish) && tx0_finish){
3747                                        rtl_write_dword(rtlpriv, 0xcb8, 0x06000000);
3748                                        rx_x0[rx0_average] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000) << 21;
3749                                        rtl_write_dword(rtlpriv, 0xcb8, 0x08000000);
3750                                        rx_y0[rx0_average] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000) << 21;
3751                                        rx0iqkok= true;
3752                                        RT_TRACE(COMP_IQK, DBG_LOUD,
3753                                                ("RX_X0[%d] = %x ;; RX_Y0[%d] = %x\n",
3754                                                rx0_average, (rx_x0[rx0_average]) >> 21 & 0x000007ff,
3755                                                rx0_average, (rx_y0[rx0_average]) >> 21 & 0x000007ff));
3756
3757                                        rx0_average++;
3758                                }
3759                                else{
3760                                        RT_TRACE(COMP_IQK, DBG_LOUD,
3761                                                ("1. RXA_cal_retry = %d\n", cal0_retry));
3762                                        rx0iqkok = false;
3763                                        cal0_retry++;
3764                                        if (cal0_retry == 10)
3765                                        break;
3766                                }
3767                                if (!(rx1_fail || rx1_finish) && tx1_finish){
3768                                        rtl_write_dword(rtlpriv, 0xeb8, 0x06000000);
3769                                        rx_x1[rx1_average] = rtl_get_bbreg(hw, 0xd40, 0x07ff0000) << 21;
3770                                        rtl_write_dword(rtlpriv, 0xeb8, 0x08000000);
3771                                        rx_y1[rx1_average] = rtl_get_bbreg(hw, 0xd40, 0x07ff0000) << 21;
3772                                        rx1iqkok = true;
3773                                        RT_TRACE(COMP_IQK, DBG_LOUD,
3774                                                ("RX_X1[%d] = %x ;; RX_Y1[%d] = %x\n",
3775                                                rx1_average, (rx_x1[rx1_average]) >> 21 & 0x000007ff,
3776                                                rx1_average, (rx_y1[rx1_average]) >> 21 & 0x000007ff));
3777
3778                                        rx1_average++;
3779                                }
3780                                else{
3781                                        rx1iqkok= false;
3782                                        cal1_retry++;
3783                                        if (cal1_retry == 10)
3784                                                break;
3785                                }
3786
3787                        }
3788                        else{
3789                                RT_TRACE(COMP_IQK, DBG_LOUD,
3790                                        ("2. RXA_cal_retry = %d\n", cal0_retry));
3791                                rx0iqkok = false;
3792                                rx1iqkok = false;
3793                                cal0_retry++;
3794                                cal1_retry++;
3795                                RT_TRACE(COMP_IQK, DBG_LOUD,
3796                                        ("Delay 20ms RX IQK Not Ready!!!!!\n"));
3797                            if (cal0_retry == 10)
3798                                break;
3799                        }
3800                        RT_TRACE(COMP_IQK, DBG_LOUD,
3801                                ("3. RXA_cal_retry = %d\n", cal0_retry));
3802                        if (rx0_average >= 2){
3803                                for (i = 0; i < rx0_average; i++){
3804                                        for (ii = i+1; ii < rx0_average; ii++){
3805                                        dx = (rx_x0[i] >> 21) - (rx_x0[ii] >> 21);
3806                                                if (dx < 4 && dx > -4){
3807                                                dy = (rx_y0[i] >> 21) - (rx_y0[ii] >> 21);
3808                                                        if (dy < 4 && dy > -4){
3809                                                                rx0_x = ((rx_x0[i]>>21) + (rx_x0[ii] >> 21)) / 2;
3810                                                                rx0_y = ((rx_y0[i]>>21) + (rx_y0[ii] >> 21)) / 2;
3811                                                                if ((rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80)
3812                                                                        && vdf_enable) {
3813                                                                        rx_dt[0] = (rx_dt[i] + rx_dt[ii]) / 2;
3814                                                                }
3815                                                                rx0_finish = true;
3816                                                                break;
3817                                                        }
3818                                                }
3819                                        }
3820                                }
3821                        }
3822                        if (rx1_average >= 2){
3823                                for (i = 0; i < rx1_average; i++){
3824                                        for (ii = i+1; ii < rx1_average; ii++){
3825                                        dx = (rx_x1[i] >> 21) - (rx_x1[ii] >> 21);
3826                                                if (dx < 4 && dx > -4){
3827                                                dy = (rx_y1[i] >> 21) - (rx_y1[ii] >> 21);
3828                                                        if (dy < 4 && dy > -4){
3829                                                                rx1_x = ((rx_x1[i] >> 21) + (rx_x1[ii] >> 21)) / 2;
3830                                                                rx1_y = ((rx_y1[i] >> 21) + (rx_y1[ii] >> 21)) / 2;
3831                                                                if ((rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80)
3832                                                                        && vdf_enable) {
3833                                                                        rx_dt[0] = (rx_dt[i] + rx_dt[ii]) / 2;
3834                                                                }
3835                                                                rx1_finish = true;
3836                                                                break;
3837                                                        }
3838                                                }
3839                                        }
3840                                }
3841                        }
3842                        RT_TRACE(COMP_IQK, DBG_LOUD,
3843                                ("RX0_Average = %d, RX1_Average = %d\n",
3844                                rx0_average, rx1_average));
3845                        RT_TRACE(COMP_IQK, DBG_LOUD,
3846                                ("RX0_finish = %d, RX1_finish = %d\n",
3847                                rx0_finish, rx1_finish));
3848                        if ((rx0_finish|| !tx0_finish) && (rx1_finish || !tx1_finish) )
3849                                break;
3850                        if ((cal0_retry + rx0_average) >= 10
3851                                || (cal1_retry + rx1_average) >= 10
3852                                || rx0_average == 3
3853                                || rx1_average == 3)
3854                                break;
3855                }
3856                RT_TRACE(COMP_IQK, DBG_LOUD,
3857                        ("RXA_cal_retry = %d\n", cal0_retry));
3858                RT_TRACE(COMP_IQK, DBG_LOUD,
3859                        ("RXB_cal_retry = %d\n", cal1_retry));
3860        }
3861        rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C*/
3862        switch (rtlphy->current_chan_bw)
3863        {
3864        case HT_CHANNEL_WIDTH_20_40:
3865                {
3866                rtl_set_rfreg(hw, RF90_PATH_A, 0x18, 0x00c00, 0x1);
3867                }
3868                break;
3869        case HT_CHANNEL_WIDTH_80:
3870                {
3871                rtl_set_rfreg(hw, RF90_PATH_A, 0x18, 0x00c00, 0x0);
3872                }
3873                break;
3874        default:
3875                break;
3876
3877        }
3878
3879        rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 0 --> Page C*/
3880        /*FillIQK Result*/
3881        RT_TRACE(COMP_IQK, DBG_LOUD,
3882                ("========Path_A =======\n"));
3883
3884        if (tx0_finish){
3885                _rtl8812ae_iqk_tx_fill_iqc(hw, RF90_PATH_A, tx0_x, tx0_y);
3886        }
3887        else{
3888                _rtl8812ae_iqk_tx_fill_iqc(hw, RF90_PATH_A, 0x200, 0x0);
3889        }
3890
3891        if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80
3892                || vdf_enable){
3893                rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /*[31] = 0 --> Page C*/
3894                rtl_set_bbreg(hw, 0xce8, 0x3fff0000, tx_dt[0] & 0x00003fff);
3895                rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3896        }
3897
3898        if (rx0_finish == 1){
3899                _rtl8812ae_iqk_rx_fill_iqc(hw, RF90_PATH_A, rx0_x, rx0_y);
3900        }
3901        else{
3902                _rtl8812ae_iqk_rx_fill_iqc(hw, RF90_PATH_A, 0x200, 0x0);
3903        }
3904
3905        if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80
3906                || vdf_enable){
3907                rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /*[31] = 0 --> Page C*/
3908                rtl_set_bbreg(hw, 0xce8, 0x00003fff, rx_dt[0] & 0x00003fff);
3909                rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C*/
3910        }
3911
3912        RT_TRACE(COMP_IQK, DBG_LOUD,
3913                ("========Path_B =======\n"));
3914
3915        if (tx1_finish){
3916                _rtl8812ae_iqk_tx_fill_iqc(hw, RF90_PATH_B, tx1_x, tx1_y);
3917        }
3918        else{
3919                _rtl8812ae_iqk_tx_fill_iqc(hw, RF90_PATH_B, 0x200, 0x0);
3920        }
3921
3922        if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80
3923                || vdf_enable){
3924                rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 0 --> Page C*/
3925                rtl_set_bbreg(hw, 0xee8, 0x3fff0000, tx_dt[0] & 0x00003fff);
3926                rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C*/
3927        }
3928
3929        if (rx1_finish == 1){
3930                _rtl8812ae_iqk_rx_fill_iqc(hw, RF90_PATH_B, rx1_x, rx1_y);
3931        }
3932        else{
3933                _rtl8812ae_iqk_rx_fill_iqc(hw, RF90_PATH_B, 0x200, 0x0);
3934        }
3935
3936        if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80
3937                || vdf_enable){
3938                rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 0 --> Page C*/
3939                rtl_set_bbreg(hw, 0xee8, 0x00003fff, rx_dt[0] & 0x00003fff);
3940                rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C*/
3941        }
3942}
3943
3944void _rtl8812ae_iqk_restore_rf(
3945        struct ieee80211_hw *hw,
3946        enum radio_path path,
3947        u32 *backup_rf_reg,
3948        u32 *rf_backup,
3949        u32 rf_reg_num
3950        )
3951{
3952        struct rtl_priv *rtlpriv = rtl_priv(hw);
3953        u32 i;
3954
3955        rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3956        for (i = 0; i < rf_reg_num; i++)
3957                rtl_set_rfreg(hw, path, backup_rf_reg[i], BRFREGOFFSETMASK, rf_backup[i]);
3958
3959        rtl_set_rfreg(hw, path, 0xef, BRFREGOFFSETMASK, 0x0);
3960
3961        switch(path){
3962        case RF90_PATH_A:
3963       {
3964        RT_TRACE(COMP_IQK, DBG_LOUD,
3965                        ("RestoreRF Path A Success!!!!\n"));
3966       }
3967                break;
3968        case RF90_PATH_B:
3969       {
3970        RT_TRACE(COMP_IQK, DBG_LOUD,
3971                        ("RestoreRF Path B Success!!!!\n"));
3972       }
3973                break;
3974        default:
3975                break;
3976        }
3977}
3978
3979void _rtl8812ae_iqk_restore_afe(
3980        struct ieee80211_hw *hw,
3981        u32 *afe_backup,
3982        u32 *backup_afe_reg,
3983        u32 afe_num
3984        )
3985{
3986        struct rtl_priv *rtlpriv = rtl_priv(hw);
3987        u32 i;
3988        rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3989        /*Reload AFE Parameters */
3990        for (i = 0; i < afe_num; i++){
3991                rtl_write_dword(rtlpriv, backup_afe_reg[i], afe_backup[i]);
3992        }
3993        rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1*/
3994        rtl_write_dword(rtlpriv, 0xc80, 0x0);
3995        rtl_write_dword(rtlpriv, 0xc84, 0x0);
3996        rtl_write_dword(rtlpriv, 0xc88, 0x0);
3997        rtl_write_dword(rtlpriv, 0xc8c, 0x3c000000);
3998        rtl_write_dword(rtlpriv, 0xc90, 0x00000080);
3999        rtl_write_dword(rtlpriv, 0xc94, 0x00000000);
4000        rtl_write_dword(rtlpriv, 0xcc4, 0x20040000);

4001        rtl_write_dword(rtlpriv, 0xcc8, 0x20000000);
4002        rtl_write_dword(rtlpriv, 0xcb8, 0x0);
4003        rtl_write_dword(rtlpriv, 0xe80, 0x0);
4004        rtl_write_dword(rtlpriv, 0xe84, 0x0);
4005        rtl_write_dword(rtlpriv, 0xe88, 0x0);
4006        rtl_write_dword(rtlpriv, 0xe8c, 0x3c000000);
4007        rtl_write_dword(rtlpriv, 0xe90, 0x00000080);
4008        rtl_write_dword(rtlpriv, 0xe94, 0x00000000);
4009        rtl_write_dword(rtlpriv, 0xec4, 0x20040000);
4010        rtl_write_dword(rtlpriv, 0xec8, 0x20000000);
4011        rtl_write_dword(rtlpriv, 0xeb8, 0x0);
4012        RT_TRACE(COMP_IQK, DBG_LOUD,
4013                ("RestoreAFE Success!!!!\n"));
4014}
4015
4016void _rtl8812ae_iqk_restore_macbb(
4017        struct ieee80211_hw *hw,
4018        u32 *macbb_backup,
4019        u32 *backup_macbb_reg,
4020        u32 macbb_num
4021        )
4022{
4023        struct rtl_priv *rtlpriv = rtl_priv(hw);
4024        u32 i;
4025        rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C*/
4026        //Reload MacBB Parameters
4027        for (i = 0; i < macbb_num; i++){
4028                rtl_write_dword(rtlpriv, backup_macbb_reg[i], macbb_backup[i]);
4029        }
4030        RT_TRACE(COMP_IQK, DBG_LOUD,
4031                        ("RestoreMacBB Success!!!!\n"));
4032}
4033
4034#define MACBB_REG_NUM 10
4035#define AFE_REG_NUM 14
4036#define RF_REG_NUM 3
4037
4038static void _rtl8812ae_phy_iq_calibrate(
4039                struct ieee80211_hw *hw,
4040                u8 channel)
4041{
4042        u32     macbb_backup[MACBB_REG_NUM];
4043        u32 afe_backup[AFE_REG_NUM];
4044        u32 rfa_backup[RF_REG_NUM];
4045        u32 rfb_backup[RF_REG_NUM];
4046        u32     backup_macbb_reg[MACBB_REG_NUM] = {0xb00, 0x520, 0x550,
4047                                                                                        0x808, 0x90c, 0xc00, 0xe00,
4048                                                                                        0x8c4,0x838,  0x82c};
4049        u32     backup_afe_reg[AFE_REG_NUM] = {0xc5c, 0xc60, 0xc64, 0xc68,
4050                                                                                0xcb8, 0xcb0, 0xcb4,0xe5c,
4051                                                                                0xe60, 0xe64, 0xe68, 0xeb8,
4052                                                                                0xeb0, 0xeb4};
4053        u32     backup_rf_reg[RF_REG_NUM] = {0x65, 0x8f, 0x0};
4054        u8      chnl_idx = _rtl8812ae_get_right_chnl_place_for_iqk(channel);
4055
4056        _rtl8812ae_iqk_backup_macbb(hw, macbb_backup, backup_macbb_reg, MACBB_REG_NUM);
4057        _rtl8812ae_iqk_backup_afe(hw, afe_backup, backup_afe_reg, AFE_REG_NUM);
4058        _rtl8812ae_iqk_backup_rf(hw, rfa_backup, rfb_backup, backup_rf_reg, RF_REG_NUM);
4059
4060        _rtl8812ae_iqk_configure_mac(hw);
4061        _rtl8812ae_iqk_tx(hw, chnl_idx);
4062        _rtl8812ae_iqk_restore_rf(hw, RF90_PATH_A, backup_rf_reg, rfa_backup, RF_REG_NUM);
4063        _rtl8812ae_iqk_restore_rf(hw, RF90_PATH_A, backup_rf_reg, rfb_backup, RF_REG_NUM); // PATH_A ?
4064
4065        _rtl8812ae_iqk_restore_afe(hw, afe_backup, backup_afe_reg, AFE_REG_NUM);
4066        _rtl8812ae_iqk_restore_macbb(hw, macbb_backup, backup_macbb_reg, MACBB_REG_NUM);
4067}
4068
4069
4070void _rtl8821ae_iqk_backup_macbb(
4071                struct ieee80211_hw *hw,
4072                u32 *macbb_backup,
4073                u32 *backup_macbb_reg,
4074                u32 mac_bb_num
4075                )
4076{
4077        struct rtl_priv *rtlpriv = rtl_priv(hw);
4078        u32 i;
4079
4080        rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
4081        /*save MACBB default value*/
4082        for (i = 0; i < mac_bb_num; i++) {
4083                macbb_backup[i] =rtl_read_dword(rtlpriv,backup_macbb_reg[i]);
4084        }
4085
4086        RT_TRACE(COMP_IQK, DBG_LOUD, ("BackupMacBB Success!!!!\n"));
4087}
4088
4089void _rtl8821ae_iqk_backup_afe(
4090                struct ieee80211_hw *hw,
4091                u32 *afe_backup,
4092                u32 *backup_afe_REG,
4093                u32 afe_num
4094                )
4095{
4096        struct rtl_priv *rtlpriv = rtl_priv(hw);
4097        u32 i;
4098
4099        rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
4100        /*Save AFE Parameters */
4101        for (i = 0; i < afe_num; i++){
4102                afe_backup[i] = rtl_read_dword(rtlpriv, backup_afe_REG[i]);
4103        }
4104        RT_TRACE(COMP_IQK, DBG_LOUD, ("BackupAFE Success!!!!\n"));
4105}
4106
4107void _rtl8821ae_iqk_backup_rf(
4108                struct ieee80211_hw *hw,
4109                u32 *rfa_backup,
4110                u32 *rfb_backup,
4111                u32 *backup_rf_reg,
4112                u32 rf_num
4113                )
4114{
4115
4116        struct rtl_priv *rtlpriv = rtl_priv(hw);
4117        u32 i;
4118
4119        rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
4120        /*Save RF Parameters*/
4121        for (i = 0; i < rf_num; i++){
4122                rfa_backup[i] = rtl_get_rfreg(hw, RF90_PATH_A, backup_rf_reg[i], BMASKDWORD);
4123                rfb_backup[i] = rtl_get_rfreg(hw, RF90_PATH_B, backup_rf_reg[i], BMASKDWORD);
4124        }
4125        RT_TRACE(COMP_IQK, DBG_LOUD, ("BackupRF Success!!!!\n"));
4126}
4127
4128void _rtl8821ae_iqk_configure_mac(
4129                struct ieee80211_hw *hw
4130                )
4131{
4132        struct rtl_priv *rtlpriv = rtl_priv(hw);
4133        /* ========MAC register setting========*/
4134        rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
4135        rtl_write_byte(rtlpriv, 0x522, 0x3f);
4136        rtl_set_bbreg(hw, 0x550, BIT(11) | BIT(3), 0x0);
4137        rtl_write_byte(rtlpriv, 0x808, 0x00);           /*RX ante off*/
4138        rtl_set_bbreg(hw, 0x838, 0xf, 0xc);             /*CCA off*/
4139}
4140
4141
4142void _rtl8821ae_iqk_tx_fill_iqc(
4143                struct ieee80211_hw *hw,
4144                enum radio_path path,
4145                u32 tx_x,
4146                u32 tx_y
4147                )
4148{
4149        struct rtl_priv *rtlpriv = rtl_priv(hw);
4150        switch (path) {
4151                case RF90_PATH_A:
4152                        {
4153                                rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1
4154                                rtl_write_dword(rtlpriv, 0xc90, 0x00000080);
4155                                rtl_write_dword(rtlpriv, 0xcc4, 0x20040000);
4156                                rtl_write_dword(rtlpriv, 0xcc8, 0x20000000);
4157                                rtl_set_bbreg(hw, 0xccc, 0x000007ff, tx_y);
4158                                rtl_set_bbreg(hw, 0xcd4, 0x000007ff, tx_x);
4159                                RT_TRACE(COMP_IQK, DBG_LOUD, ("TX_X = %x;;TX_Y = %x =====> fill to IQC\n", tx_x, tx_y));
4160                                RT_TRACE(COMP_IQK, DBG_LOUD, ("0xcd4 = %x;;0xccc = %x ====>fill to IQC\n", rtl_get_bbreg(hw, 0xcd4, 0x000007ff), rtl_get_bbreg(hw, 0xccc, 0x000007ff)));
4161                        }
4162                        break;
4163                default:
4164                        break;
4165        };
4166}
4167
4168
4169void _rtl8821ae_iqk_rx_fill_iqc(
4170                struct ieee80211_hw *hw,
4171                enum radio_path path,
4172                u32 rx_x,
4173                u32 rx_y
4174                )
4175{
4176        struct rtl_priv *rtlpriv = rtl_priv(hw);
4177        switch (path) {
4178                case RF90_PATH_A:
4179                        {
4180                                rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C
4181                                rtl_set_bbreg(hw, 0xc10, 0x000003ff, rx_x>>1);
4182                                rtl_set_bbreg(hw, 0xc10, 0x03ff0000, rx_y>>1);
4183                                RT_TRACE(COMP_IQK, DBG_LOUD, ("rx_x = %x;;rx_y = %x ====>fill to IQC\n", rx_x>>1, rx_y>>1));
4184                                RT_TRACE(COMP_IQK, DBG_LOUD, ("0xc10 = %x ====>fill to IQC\n", rtl_read_dword(rtlpriv, 0xc10)));
4185                        }
4186                        break;
4187                default:
4188                        break;
4189        };
4190}
4191
4192
4193
4194#define cal_num 10
4195
4196void _rtl8821ae_iqk_tx(
4197                struct ieee80211_hw *hw,
4198                enum radio_path path
4199                )
4200{
4201        struct rtl_priv *rtlpriv = rtl_priv(hw);
4202        struct rtl_phy *rtlphy = &(rtlpriv->phy);
4203        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
4204
4205        u32     tx_fail, rx_fail, delay_count, iqk_ready, cal_retry, cal = 0, temp_reg65;
4206        int     tx_x = 0, tx_y = 0, rx_x = 0, rx_y = 0, tx_average = 0, rx_average = 0;
4207        int     tx_x0[cal_num], tx_y0[cal_num], tx_x0_rxk[cal_num], tx_y0_rxk[cal_num], rx_x0[cal_num], rx_y0[cal_num];
4208        bool    tx0iqkok = false, rx0iqkok = false;
4209        bool    vdf_enable = false;
4210        int     i, k, vdf_y[3], vdf_x[3], tx_dt[3], rx_dt[3], ii, dx = 0, dy = 0, tx_finish = 0, rx_finish = 0;
4211
4212
4213        RT_TRACE(COMP_IQK, DBG_LOUD,
4214                        ("BandWidth = %d.\n",
4215                         rtlphy->current_chan_bw));
4216        if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80){
4217                vdf_enable = true;
4218        }
4219
4220        while (cal < cal_num) {
4221                switch (path) {
4222                        case RF90_PATH_A:
4223                                {
4224                                        temp_reg65 = rtl_get_rfreg(hw, path, 0x65, 0xffffffff);
4225                                        //Path-A LOK
4226                                        rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
4227                                        /*========Path-A AFE all on========*/
4228                                        /*Port 0 DAC/ADC on*/
4229                                        rtl_write_dword(rtlpriv, 0xc60, 0x77777777);
4230                                        rtl_write_dword(rtlpriv, 0xc64, 0x77777777);
4231                                        rtl_write_dword(rtlpriv, 0xc68, 0x19791979);
4232                                        rtl_write_dword(rtlpriv, 0xc6c, 0x19791979);
4233                                        rtl_write_dword(rtlpriv, 0xc70, 0x19791979);
4234                                        rtl_write_dword(rtlpriv, 0xc74, 0x19791979);
4235                                        rtl_write_dword(rtlpriv, 0xc78, 0x19791979);
4236                                        rtl_write_dword(rtlpriv, 0xc7c, 0x19791979);
4237                                        rtl_write_dword(rtlpriv, 0xc80, 0x19791979);
4238                                        rtl_write_dword(rtlpriv, 0xc84, 0x19791979);
4239
4240                                        rtl_set_bbreg(hw, 0xc00, 0xf, 0x4); /*hardware 3-wire off*/
4241
4242                                        // LOK Setting
4243                                        //====== LOK ======
4244                                        /*DAC/ADC sampling rate (160 MHz)*/
4245                                        rtl_set_bbreg(hw, 0xc5c, BIT(26) | BIT(25) | BIT(24), 0x7);
4246
4247                                        // 2. LoK RF Setting (at BW = 20M)
4248                                        rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80002);
4249                                        rtl_set_rfreg(hw, path, 0x18, 0x00c00, 0x3);     // BW 20M
4250                                        rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x20000);
4251                                        rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x0003f);
4252                                        rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xf3fc3);
4253                                        rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, 0x931d5);
4254                                        rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x8a001);
4255                                        rtl_set_bbreg(hw, 0xcb8, 0xf, 0xd);
4256                                        rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
4257                                        rtl_write_dword(rtlpriv, 0xb00, 0x03000100);
4258                                        rtl_set_bbreg(hw, 0xc94, BIT(0), 0x1);
4259                                        rtl_write_dword(rtlpriv, 0x978, 0x29002000);// TX (X,Y)
4260                                        rtl_write_dword(rtlpriv, 0x97c, 0xa9002000);// RX (X,Y)
4261                                        rtl_write_dword(rtlpriv, 0x984, 0x00462910);// [0]:AGC_en, [15]:idac_K_Mask
4262
4263                                        rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1
4264                                        rtl_write_dword(rtlpriv, 0xc88, 0x821403f4);
4265
4266                                        if (rtlhal->current_bandtype)
4267                                                rtl_write_dword(rtlpriv, 0xc8c, 0x68163e96);
4268                                        else
4269                                                rtl_write_dword(rtlpriv, 0xc8c, 0x28163e96);
4270
4271                                        rtl_write_dword(rtlpriv, 0xc80, 0x18008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16
4272                                        rtl_write_dword(rtlpriv, 0xc84, 0x38008c10);// RX_Tone_idx[9:0], RxK_Mask[29]
4273                                        rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);// cb8[20] �N SI/PI �ϥ��v���� iqk_dpk module
4274                                        rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
4275                                        rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
4276
4277                                        mdelay(10); //Delay 10ms
4278                                        rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
4279
4280                                        rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C
4281                                        rtl_set_rfreg(hw, path, 0x58, 0x7fe00, rtl_get_rfreg(hw, path, 0x8, 0xffc00)); // Load LOK
4282
4283                                        switch (rtlphy->current_chan_bw)
4284                                        {
4285                                                case 1:
4286                                                        {
4287                                                                rtl_set_rfreg(hw, path, 0x18, 0x00c00, 0x1);
4288                                                        }
4289                                                        break;
4290                                                case 2:
4291                                                        {
4292                                                                rtl_set_rfreg(hw, path, 0x18, 0x00c00, 0x0);
4293                                                        }
4294                                                        break;
4295                                                default:
4296                                                        break;
4297
4298                                        }
4299
4300                                        rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1
4301
4302                                        // 3. TX RF Setting
4303                                        rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C
4304                                        rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000);
4305                                        rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x20000);
4306                                        rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x0003f);
4307                                        rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xf3fc3);
4308                                        rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, 0x931d5);
4309                                        rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x8a001);
4310                                        rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000);
4311                                        //ODM_SetBBReg(pDM_Odm, 0xcb8, 0xf, 0xd);
4312                                        rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
4313                                        rtl_write_dword(rtlpriv, 0xb00, 0x03000100);
4314                                        rtl_set_bbreg(hw, 0xc94, BIT(0), 0x1);
4315                                        rtl_write_dword(rtlpriv, 0x978, 0x29002000);// TX (X,Y)
4316                                        rtl_write_dword(rtlpriv, 0x97c, 0xa9002000);// RX (X,Y)
4317                                        rtl_write_dword(rtlpriv, 0x984, 0x0046a910);// [0]:AGC_en, [15]:idac_K_Mask
4318
4319                                        rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1
4320                                        rtl_write_dword(rtlpriv, 0xc88, 0x821403f1);
4321                                        if (rtlhal->current_bandtype)
4322                                                rtl_write_dword(rtlpriv, 0xc8c, 0x40163e96);
4323                                        else
4324                                                rtl_write_dword(rtlpriv, 0xc8c, 0x00163e96);
4325
4326                                        if (vdf_enable == 1){
4327                                                RT_TRACE(COMP_IQK, DBG_LOUD, ("VDF_enable\n"));
4328                                                for (k = 0;k <= 2; k++){
4329                                                        switch (k){
4330                                                                case 0:
4331                                                                        {
4332                                                                                rtl_write_dword(rtlpriv, 0xc80, 0x18008c38);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16
4333                                                                                rtl_write_dword(rtlpriv, 0xc84, 0x38008c38);// RX_Tone_idx[9:0], RxK_Mask[29]
4334                                                                                rtl_set_bbreg(hw, 0xce8, BIT(31), 0x0);
4335                                                                        }
4336                                                                        break;
4337                                                                case 1:
4338                                                                        {
4339                                                                                rtl_set_bbreg(hw, 0xc80, BIT(28), 0x0);
4340                                                                                rtl_set_bbreg(hw, 0xc84, BIT(28), 0x0);
4341                                                                                rtl_set_bbreg(hw, 0xce8, BIT(31), 0x0);
4342                                                                        }
4343                                                                        break;
4344                                                                case 2:
4345                                                                        {
4346                                                                                RT_TRACE(COMP_IQK, DBG_LOUD, ("vdf_y[1] = %x;;;vdf_y[0] = %x\n", vdf_y[1]>>21 & 0x00007ff, vdf_y[0]>>21 & 0x00007ff));
4347                                                                                RT_TRACE(COMP_IQK, DBG_LOUD, ("vdf_x[1] = %x;;;vdf_x[0] = %x\n", vdf_x[1]>>21 & 0x00007ff, vdf_x[0]>>21 & 0x00007ff));
4348                                                                                tx_dt[cal] = (vdf_y[1]>>20)-(vdf_y[0]>>20);
4349                                                                                tx_dt[cal] = ((16*tx_dt[cal])*10000/15708);
4350                                                                                tx_dt[cal] = (tx_dt[cal] >> 1 )+(tx_dt[cal] & BIT(0));
4351                                                                                rtl_write_dword(rtlpriv, 0xc80, 0x18008c20);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16
4352                                                                                rtl_write_dword(rtlpriv, 0xc84, 0x38008c20);// RX_Tone_idx[9:0], RxK_Mask[29]
4353                                                                                rtl_set_bbreg(hw, 0xce8, BIT(31), 0x1);
4354                                                                                rtl_set_bbreg(hw, 0xce8, 0x3fff0000, tx_dt[cal] & 0x00003fff);
4355                                                                        }
4356                                                                        break;
4357                                                                default:
4358                                                                        break;
4359                                                        }
4360                                                        rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);// cb8[20] �N SI/PI �ϥ��v���� iqk_dpk module
4361                                                        cal_retry = 0;
4362                                                        while(1){
4363                                                                // one shot
4364                                                                rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
4365                                                                rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
4366
4367                                                                mdelay(10); //Delay 10ms
4368                                                                rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
4369                                                                delay_count = 0;
4370                                                                while (1){
4371                                                                        iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10));
4372                                                                        if ((~iqk_ready) || (delay_count>20)){
4373                                                                                break;
4374                                                                        }
4375                                                                        else{
4376                                                                                mdelay(1);
4377                                                                                delay_count++;
4378                                                                        }
4379                                                                }
4380
4381                                                                if (delay_count < 20){                                                  // If 20ms No Result, then cal_retry++
4382                                                                        // ============TXIQK Check==============
4383                                                                        tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12));
4384
4385                                                                        if (~tx_fail){
4386                                                                                rtl_write_dword(rtlpriv, 0xcb8, 0x02000000);
4387                                                                                vdf_x[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4388                                                                                rtl_write_dword(rtlpriv, 0xcb8, 0x04000000);
4389                                                                                vdf_y[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4390                                                                                tx0iqkok = true;
4391                                                                                break;
4392                                                                        }
4393                                                                        else{
4394                                                                                rtl_set_bbreg(hw, 0xccc, 0x000007ff, 0x0);
4395                                                                                rtl_set_bbreg(hw, 0xcd4, 0x000007ff, 0x200);
4396                                                                                tx0iqkok = false;
4397                                                                                cal_retry++;
4398                                                                                if (cal_retry == 10) {
4399                                                                                        break;
4400                                                                                }
4401                                                                        }
4402                                                                }
4403                                                                else{
4404                                                                        tx0iqkok = false;
4405                                                                        cal_retry++;
4406                                                                        if (cal_retry == 10){
4407                                                                                break;
4408                                                                        }
4409                                                                }
4410                                                        }
4411                                                }
4412                                                if (k == 3){
4413                                                        tx_x0[cal] = vdf_x[k-1] ;
4414                                                        tx_y0[cal] = vdf_y[k-1];
4415                                                }
4416                                        }
4417
4418                                        else {
4419                                                rtl_write_dword(rtlpriv, 0xc80, 0x18008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16
4420                                                rtl_write_dword(rtlpriv, 0xc84, 0x38008c10);// RX_Tone_idx[9:0], RxK_Mask[29]
4421                                                rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);// cb8[20] �N SI/PI �ϥ��v���� iqk_dpk module
4422                                                cal_retry = 0;
4423                                                while(1){
4424                                                        // one shot
4425                                                        rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
4426                                                        rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
4427
4428                                                        mdelay(10); //Delay 10ms
4429                                                        rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
4430                                                        delay_count = 0;
4431                                                        while (1){
4432                                                                iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10));
4433                                                                if ((~iqk_ready) || (delay_count>20)) {
4434                                                                        break;
4435                                                                }
4436                                                                else{
4437                                                                        mdelay(1);
4438                                                                        delay_count++;
4439                                                                }
4440                                                        }
4441
4442                                                        if (delay_count < 20){                                                  // If 20ms No Result, then cal_retry++
4443                                                                // ============TXIQK Check==============
4444                                                                tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12));
4445
4446                                                                if (~tx_fail){
4447                                                                        rtl_write_dword(rtlpriv, 0xcb8, 0x02000000);
4448                                                                        tx_x0[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4449                                                                        rtl_write_dword(rtlpriv, 0xcb8, 0x04000000);
4450                                                                        tx_y0[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4451                                                                        tx0iqkok = true;
4452                                                                        break;
4453                                                                }
4454                                                                else{
4455                                                                        rtl_set_bbreg(hw, 0xccc, 0x000007ff, 0x0);
4456                                                                        rtl_set_bbreg(hw, 0xcd4, 0x000007ff, 0x200);
4457                                                                        tx0iqkok = false;
4458                                                                        cal_retry++;
4459                                                                        if (cal_retry == 10) {
4460                                                                                break;
4461                                                                        }
4462                                                                }
4463                                                        }
4464                                                        else{
4465                                                                tx0iqkok = false;
4466                                                                cal_retry++;
4467                                                                if (cal_retry == 10)
4468                                                                        break;
4469                                                        }
4470                                                }
4471                                        }
4472
4473
4474                                        if (tx0iqkok == false)
4475                                                break;                          // TXK fail, Don't do RXK
4476
4477                                        if (vdf_enable == 1){
4478                                                rtl_set_bbreg(hw, 0xce8, BIT(31), 0x0);    // TX VDF Disable
4479                                                RT_TRACE(COMP_IQK, DBG_LOUD, ("RXVDF Start\n"));
4480                                                for (k = 0;k <= 2; k++){
4481                                                        //====== RX mode TXK (RXK Step 1) ======
4482                                                        rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C
4483                                                        // 1. TX RF Setting
4484                                                        rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000);
4485                                                        rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x30000);
4486                                                        rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x00029);
4487                                                        rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xd7ffb);
4488                                                        rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, temp_reg65);
4489                                                        rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x8a001);
4490                                                        rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000);
4491
4492                                                        rtl_set_bbreg(hw, 0xcb8, 0xf, 0xd);
4493                                                        rtl_write_dword(rtlpriv, 0x978, 0x29002000);// TX (X,Y)
4494                                                        rtl_write_dword(rtlpriv, 0x97c, 0xa9002000);// RX (X,Y)
4495                                                        rtl_write_dword(rtlpriv, 0x984, 0x0046a910);// [0]:AGC_en, [15]:idac_K_Mask
4496                                                        rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
4497                                                        rtl_write_dword(rtlpriv, 0xb00, 0x03000100);
4498                                                        rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1
4499                                                        switch (k){
4500                                                                case 0:
4501                                                                        {
4502                                                                                rtl_write_dword(rtlpriv, 0xc80, 0x18008c38);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16
4503                                                                                rtl_write_dword(rtlpriv, 0xc84, 0x38008c38);// RX_Tone_idx[9:0], RxK_Mask[29]
4504                                                                                rtl_set_bbreg(hw, 0xce8, BIT(30), 0x0);
4505                                                                        }
4506                                                                        break;
4507                                                                case 1:
4508                                                                        {
4509                                                                                rtl_write_dword(rtlpriv, 0xc80, 0x08008c38);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16
4510                                                                                rtl_write_dword(rtlpriv, 0xc84, 0x28008c38);// RX_Tone_idx[9:0], RxK_Mask[29]
4511                                                                                rtl_set_bbreg(hw, 0xce8, BIT(30), 0x0);
4512                                                                        }
4513                                                                        break;
4514                                                                case 2:
4515                                                                        {
4516                                                                                RT_TRACE(COMP_IQK, DBG_LOUD, ("VDF_Y[1] = %x;;;VDF_Y[0] = %x\n", vdf_y[1]>>21 & 0x00007ff, vdf_y[0]>>21 & 0x00007ff));
4517                                                                                RT_TRACE(COMP_IQK, DBG_LOUD, ("VDF_X[1] = %x;;;VDF_X[0] = %x\n", vdf_x[1]>>21 & 0x00007ff, vdf_x[0]>>21 & 0x00007ff));
4518                                                                                rx_dt[cal] = (vdf_y[1]>>20)-(vdf_y[0]>>20);
4519                                                                                RT_TRACE(COMP_IQK, DBG_LOUD, ("Rx_dt = %d\n", rx_dt[cal]));
4520                                                                                rx_dt[cal] = ((16*rx_dt[cal])*10000/13823);
4521                                                                                rx_dt[cal] = (rx_dt[cal] >> 1 )+(rx_dt[cal] & BIT(0));
4522                                                                                rtl_write_dword(rtlpriv, 0xc80, 0x18008c20);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16
4523                                                                                rtl_write_dword(rtlpriv, 0xc84, 0x38008c20);// RX_Tone_idx[9:0], RxK_Mask[29]
4524                                                                                rtl_set_bbreg(hw, 0xce8, 0x00003fff, rx_dt[cal] & 0x00003fff);
4525                                                                        }
4526                                                                        break;
4527                                                                default:
4528                                                                        break;
4529                                                        }
4530                                                        rtl_write_dword(rtlpriv, 0xc88, 0x821603e0);
4531                                                        rtl_write_dword(rtlpriv, 0xc8c, 0x68163e96);
4532                                                        rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);// cb8[20] �N SI/PI �ϥ��v���� iqk_dpk module
4533                                                        cal_retry = 0;
4534                                                        while(1){
4535                                                                // one shot
4536                                                                rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
4537                                                                rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
4538
4539                                                                mdelay(10); //Delay 10ms
4540                                                                rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
4541                                                                delay_count = 0;
4542                                                                while (1){
4543                                                                        iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10));
4544                                                                        if ((~iqk_ready)||(delay_count>20)){
4545                                                                                break;
4546                                                                        }
4547                                                                        else{
4548                                                                                mdelay(1);
4549                                                                                delay_count++;
4550                                                                        }
4551                                                                }
4552
4553                                                                if (delay_count < 20){                                                  // If 20ms No Result, then cal_retry++
4554                                                                        // ============TXIQK Check==============
4555                                                                        tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12));
4556
4557                                                                        if (~tx_fail){
4558                                                                                rtl_write_dword(rtlpriv, 0xcb8, 0x02000000);
4559                                                                                tx_x0_rxk[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4560                                                                                rtl_write_dword(rtlpriv, 0xcb8, 0x04000000);
4561                                                                                tx_y0_rxk[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4562                                                                                tx0iqkok = true;
4563                                                                                break;
4564                                                                        }
4565                                                                        else{
4566                                                                                tx0iqkok = false;
4567                                                                                cal_retry++;
4568                                                                                if (cal_retry == 10)
4569                                                                                        break;
4570                                                                        }
4571                                                                }
4572                                                                else{
4573                                                                        tx0iqkok = false;
4574                                                                        cal_retry++;
4575                                                                        if (cal_retry == 10)
4576                                                                                break;
4577                                                                }
4578                                                        }
4579
4580                                                        if (tx0iqkok == false){   //If RX mode TXK fail, then take TXK Result
4581                                                                tx_x0_rxk[cal] = tx_x0[cal];
4582                                                                tx_y0_rxk[cal] = tx_y0[cal];
4583                                                                tx0iqkok = true;
4584                                                                RT_TRACE(COMP_IQK, DBG_LOUD, ("RXK Step 1 fail\n"));
4585                                                        }
4586
4587
4588                                                        //====== RX IQK ======
4589                                                        rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C
4590                                                        // 1. RX RF Setting
4591                                                        rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000);
4592                                                        rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x30000);
4593                                                        rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x0002f);
4594                                                        rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xfffbb);
4595                                                        rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x88001);
4596                                                        rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, 0x931d8);
4597                                                        rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000);
4598
4599                                                        rtl_set_bbreg(hw, 0x978, 0x03FF8000, (tx_x0_rxk[cal])>>21&0x000007ff);
4600                                                        rtl_set_bbreg(hw, 0x978, 0x000007FF, (tx_y0_rxk[cal])>>21&0x000007ff);
4601                                                        rtl_set_bbreg(hw, 0x978, BIT(31), 0x1);
4602                                                        rtl_set_bbreg(hw, 0x97c, BIT(31), 0x0);
4603                                                        rtl_set_bbreg(hw, 0xcb8, 0xF, 0xe);
4604                                                        rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
4605                                                        rtl_write_dword(rtlpriv, 0x984, 0x0046a911);
4606
4607                                                        rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1
4608                                                        rtl_set_bbreg(hw, 0xc80, BIT(29), 0x1);
4609                                                        rtl_set_bbreg(hw, 0xc84, BIT(29), 0x0);
4610                                                        rtl_write_dword(rtlpriv, 0xc88, 0x02140119);
4611
4612                                                        rtl_write_dword(rtlpriv, 0xc8c, 0x28160d00); /* pDM_Odm->SupportInterface == 1 */
4613
4614                                                        if (k==2){
4615                                                                rtl_set_bbreg(hw, 0xce8, BIT(30), 0x1);  //RX VDF Enable
4616                                                        }
4617                                                        rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);// cb8[20] �N SI/PI �ϥ��v���� iqk_dpk module
4618
4619                                                        cal_retry = 0;
4620                                                        while(1){
4621                                                                // one shot
4622                                                                rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
4623                                                                rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
4624
4625                                                                mdelay(10); //Delay 10ms
4626                                                                rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
4627                                                                delay_count = 0;
4628                                                                while (1){
4629                                                                        iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10));
4630                                                                        if ((~iqk_ready)||(delay_count>20)){
4631                                                                                break;
4632                                                                        }
4633                                                                        else{
4634                                                                                mdelay(1);
4635                                                                                delay_count++;
4636                                                                        }
4637                                                                }
4638
4639                                                                if (delay_count < 20){  // If 20ms No Result, then cal_retry++
4640                                                                        // ============RXIQK Check==============
4641                                                                        rx_fail = rtl_get_bbreg(hw, 0xd00, BIT(11));
4642                                                                        if (rx_fail == 0){
4643                                                                                rtl_write_dword(rtlpriv, 0xcb8, 0x06000000);
4644                                                                                vdf_x[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4645                                                                                rtl_write_dword(rtlpriv, 0xcb8, 0x08000000);
4646                                                                                vdf_y[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4647                                                                                rx0iqkok = true;
4648                                                                                break;
4649                                                                        }
4650                                                                        else{
4651                                                                                rtl_set_bbreg(hw, 0xc10, 0x000003ff, 0x200>>1);
4652                                                                                rtl_set_bbreg(hw, 0xc10, 0x03ff0000, 0x0>>1);
4653                                                                                rx0iqkok = false;
4654                                                                                cal_retry++;
4655                                                                                if (cal_retry == 10)
4656                                                                                        break;
4657
4658                                                                        }
4659                                                                }
4660                                                                else{
4661                                                                        rx0iqkok = false;
4662                                                                        cal_retry++;
4663                                                                        if (cal_retry == 10)
4664                                                                                break;
4665                                                                }
4666                                                        }
4667
4668                                                }
4669                                                if (k == 3){
4670                                                        rx_x0[cal] = vdf_x[k-1] ;
4671                                                        rx_y0[cal] = vdf_y[k-1];
4672                                                }
4673                                                rtl_set_bbreg(hw, 0xce8, BIT(31), 0x1);    // TX VDF Enable
4674                                        }
4675
4676                                        else{
4677                                                //====== RX mode TXK (RXK Step 1) ======
4678                                                rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C
4679                                                // 1. TX RF Setting
4680                                                rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000);
4681                                                rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x30000);
4682                                                rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x00029);
4683                                                rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xd7ffb);
4684                                                rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, temp_reg65);
4685                                                rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x8a001);
4686                                                rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000);
4687                                                rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
4688                                                rtl_write_dword(rtlpriv, 0xb00, 0x03000100);
4689                                                rtl_write_dword(rtlpriv, 0x984, 0x0046a910);// [0]:AGC_en, [15]:idac_K_Mask
4690
4691                                                rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1
4692                                                rtl_write_dword(rtlpriv, 0xc80, 0x18008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16
4693                                                rtl_write_dword(rtlpriv, 0xc84, 0x38008c10);// RX_Tone_idx[9:0], RxK_Mask[29]
4694                                                rtl_write_dword(rtlpriv, 0xc88, 0x821603e0);
4695                                                //ODM_Write4Byte(pDM_Odm, 0xc8c, 0x68163e96);
4696                                                rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);// cb8[20] �N SI/PI �ϥ��v���� iqk_dpk module
4697                                                cal_retry = 0;
4698                                                while(1){
4699                                                        // one shot
4700                                                        rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
4701                                                        rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
4702
4703                                                        mdelay(10); //Delay 10ms
4704                                                        rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
4705                                                        delay_count = 0;
4706                                                        while (1){
4707                                                                iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10));
4708                                                                if ((~iqk_ready)||(delay_count>20)){
4709                                                                        break;
4710                                                                }
4711                                                                else{
4712                                                                        mdelay(1);
4713                                                                        delay_count++;
4714                                                                }
4715                                                        }
4716
4717                                                        if (delay_count < 20){                                                  // If 20ms No Result, then cal_retry++
4718                                                                // ============TXIQK Check==============
4719                                                                tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12));
4720
4721                                                                if (~tx_fail){
4722                                                                        rtl_write_dword(rtlpriv, 0xcb8, 0x02000000);
4723                                                                        tx_x0_rxk[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4724                                                                        rtl_write_dword(rtlpriv, 0xcb8, 0x04000000);
4725                                                                        tx_y0_rxk[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4726                                                                        tx0iqkok = true;
4727                                                                        break;
4728                                                                }
4729                                                                else{
4730                                                                        tx0iqkok = false;
4731                                                                        cal_retry++;
4732                                                                        if (cal_retry == 10)
4733                                                                                break;
4734                                                                }
4735                                                        }
4736                                                        else{
4737                                                                tx0iqkok = false;
4738                                                                cal_retry++;
4739                                                                if (cal_retry == 10)
4740                                                                        break;
4741                                                        }
4742                                                }
4743
4744
4745                                                if (tx0iqkok == false){   //If RX mode TXK fail, then take TXK Result
4746                                                        tx_x0_rxk[cal] = tx_x0[cal];
4747                                                        tx_y0_rxk[cal] = tx_y0[cal];
4748                                                        tx0iqkok = true;
4749                                                        RT_TRACE(COMP_IQK, DBG_LOUD, ("1"));
4750                                                }
4751
4752
4753                                                //====== RX IQK ======
4754                                                rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C
4755                                                // 1. RX RF Setting
4756                                                rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000);
4757                                                rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x30000);
4758                                                rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x0002f);
4759                                                rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xfffbb);
4760                                                rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x88001);
4761                                                rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, 0x931d8);
4762                                                rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000);
4763
4764                                                rtl_set_bbreg(hw, 0x978, 0x03FF8000, (tx_x0_rxk[cal])>>21&0x000007ff);
4765                                                rtl_set_bbreg(hw, 0x978, 0x000007FF, (tx_y0_rxk[cal])>>21&0x000007ff);
4766                                                rtl_set_bbreg(hw, 0x978, BIT(31), 0x1);
4767                                                rtl_set_bbreg(hw, 0x97c, BIT(31), 0x0);
4768                                                //ODM_SetBBReg(pDM_Odm, 0xcb8, 0xF, 0xe);
4769                                                rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
4770                                                rtl_write_dword(rtlpriv, 0x984, 0x0046a911);
4771
4772                                                rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1
4773                                                rtl_write_dword(rtlpriv, 0xc80, 0x38008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16
4774                                                rtl_write_dword(rtlpriv, 0xc84, 0x18008c10);// RX_Tone_idx[9:0], RxK_Mask[29]
4775                                                rtl_write_dword(rtlpriv, 0xc88, 0x02140119);
4776
4777                                                rtl_write_dword(rtlpriv, 0xc8c, 0x28160d00); /*pDM_Odm->SupportInterface == 1*/
4778
4779                                                rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);// cb8[20] �N SI/PI �ϥ��v���� iqk_dpk module
4780
4781                                                cal_retry = 0;
4782                                                while(1){
4783                                                        // one shot
4784                                                        rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
4785                                                        rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
4786
4787                                                        mdelay(10); //Delay 10ms
4788                                                        rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
4789                                                        delay_count = 0;
4790                                                        while (1){
4791                                                                iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10));
4792                                                                if ((~iqk_ready)||(delay_count>20)){
4793                                                                        break;
4794                                                                }
4795                                                                else{
4796                                                                        mdelay(1);
4797                                                                        delay_count++;
4798                                                                }
4799                                                        }
4800
4801                                                        if (delay_count < 20){  // If 20ms No Result, then cal_retry++
4802                                                                // ============RXIQK Check==============
4803                                                                rx_fail = rtl_get_bbreg(hw, 0xd00, BIT(11));
4804                                                                if (rx_fail == 0){
4805                                                                        /*
4806                                                                           ODM_Write4Byte(pDM_Odm, 0xcb8, 0x05000000);
4807                                                                           reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff);
4808                                                                           ODM_Write4Byte(pDM_Odm, 0xcb8, 0x06000000);
4809                                                                           reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f);
4810                                                                           DbgPrint("reg1 = %d, reg2 = %d", reg1, reg2);
4811                                                                           Image_Power = (reg2<<32)+reg1;
4812                                                                           DbgPrint("Before PW = %d\n", Image_Power);
4813                                                                           ODM_Write4Byte(pDM_Odm, 0xcb8, 0x07000000);
4814                                                                           reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff);
4815                                                                           ODM_Write4Byte(pDM_Odm, 0xcb8, 0x08000000);
4816                                                                           reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f);
4817                                                                           Image_Power = (reg2<<32)+reg1;
4818                                                                           DbgPrint("After PW = %d\n", Image_Power);
4819                                                                           */
4820
4821                                                                        rtl_write_dword(rtlpriv, 0xcb8, 0x06000000);
4822                                                                        rx_x0[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4823                                                                        rtl_write_dword(rtlpriv, 0xcb8, 0x08000000);
4824                                                                        rx_y0[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4825                                                                        rx0iqkok = true;
4826                                                                        break;
4827                                                                }
4828                                                                else{
4829                                                                        rtl_set_bbreg(hw, 0xc10, 0x000003ff, 0x200>>1);
4830                                                                        rtl_set_bbreg(hw, 0xc10, 0x03ff0000, 0x0>>1);
4831                                                                        rx0iqkok = false;
4832                                                                        cal_retry++;
4833                                                                        if (cal_retry == 10)
4834                                                                                break;
4835
4836                                                                }
4837                                                        }
4838                                                        else{
4839                                                                rx0iqkok = false;
4840                                                                cal_retry++;
4841                                                                if (cal_retry == 10)
4842                                                                        break;
4843                                                        }
4844                                                }
4845                                        }
4846
4847                                        if (tx0iqkok)
4848                                                tx_average++;
4849                                        if (rx0iqkok)
4850                                                rx_average++;
4851                                        rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C
4852                                        rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, temp_reg65);
4853                                }
4854                                break;
4855                        default:
4856                                break;
4857                }
4858                cal++;
4859        }
4860
4861        // FillIQK Result
4862        switch (path){
4863                case RF90_PATH_A:
4864                        {
4865                                RT_TRACE(COMP_IQK, DBG_LOUD, ("========Path_A =======\n"));
4866                                if (tx_average == 0)
4867                                        break;
4868
4869                                for (i = 0; i < tx_average; i++){
4870                                        RT_TRACE(COMP_IQK, DBG_LOUD, (" TX_X0_RXK[%d] = %x ;; TX_Y0_RXK[%d] = %x\n", i, (tx_x0_rxk[i])>>21&0x000007ff, i, (tx_y0_rxk[i])>>21&0x000007ff));
4871                                        RT_TRACE(COMP_IQK, DBG_LOUD, ("TX_X0[%d] = %x ;; TX_Y0[%d] = %x\n", i, (tx_x0[i])>>21&0x000007ff, i, (tx_y0[i])>>21&0x000007ff));
4872                                }
4873                                for (i = 0; i < tx_average; i++){
4874                                        for (ii = i+1; ii <tx_average; ii++){
4875                                                dx = (tx_x0[i]>>21) - (tx_x0[ii]>>21);
4876                                                if (dx < 3 && dx > -3){
4877                                                        dy = (tx_y0[i]>>21) - (tx_y0[ii]>>21);
4878                                                        if (dy < 3 && dy > -3){
4879                                                                tx_x = ((tx_x0[i]>>21) + (tx_x0[ii]>>21))/2;
4880                                                                tx_y = ((tx_y0[i]>>21) + (tx_y0[ii]>>21))/2;
4881                                                                tx_finish = 1;
4882                                                                break;
4883                                                        }
4884                                                }
4885                                        }
4886                                        if (tx_finish == 1)
4887                                                break;
4888                                }
4889
4890                                if (tx_finish == 1){
4891                                        _rtl8821ae_iqk_tx_fill_iqc(hw, path, tx_x, tx_y); // ?
4892                                }
4893                                else{
4894                                        _rtl8821ae_iqk_tx_fill_iqc(hw, path, 0x200, 0x0);
4895                                }
4896
4897                                if (rx_average == 0)
4898                                        break;
4899
4900                                for (i = 0; i < rx_average; i++){
4901                                        RT_TRACE(COMP_IQK, DBG_LOUD, ("RX_X0[%d] = %x ;; RX_Y0[%d] = %x\n", i, (rx_x0[i])>>21&0x000007ff, i, (rx_y0[i])>>21&0x000007ff));
4902                                }
4903                                for (i = 0; i < rx_average; i++){
4904                                        for (ii = i+1; ii <rx_average; ii++){
4905                                                dx = (rx_x0[i]>>21) - (rx_x0[ii]>>21);
4906                                                if (dx < 4 && dx > -4){
4907                                                        dy = (rx_y0[i]>>21) - (rx_y0[ii]>>21);
4908                                                        if (dy < 4 && dy > -4){
4909                                                                rx_x = ((rx_x0[i]>>21) + (rx_x0[ii]>>21))/2;
4910                                                                rx_y = ((rx_y0[i]>>21) + (rx_y0[ii]>>21))/2;
4911                                                                rx_finish = 1;
4912                                                                break;
4913                                                        }
4914                                                }
4915                                        }
4916                                        if (rx_finish == 1)
4917                                                break;
4918                                }
4919
4920                                if (rx_finish == 1){
4921                                        _rtl8821ae_iqk_rx_fill_iqc(hw, path, rx_x, rx_y);
4922                                }
4923                                else{
4924                                        _rtl8821ae_iqk_rx_fill_iqc(hw, path, 0x200, 0x0);
4925                                }
4926                        }
4927                        break;
4928                default:
4929                        break;
4930        }
4931}
4932
4933void _rtl8821ae_iqk_restore_rf(
4934                struct ieee80211_hw *hw,
4935                enum radio_path path,
4936                u32*                    backup_rf_reg,
4937                u32*                    rf_backup,
4938                u32                     rf_reg_num
4939                )
4940{
4941        u32 i;
4942        struct rtl_priv* rtlpriv = rtl_priv(hw);
4943
4944        rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C
4945        for (i = 0; i < RF_REG_NUM; i++)
4946                rtl_set_rfreg(hw, path, backup_rf_reg[i], RFREG_OFFSET_MASK, rf_backup[i]);
4947
4948        switch(path){
4949                case RF90_PATH_A:
4950                        {
4951                                RT_TRACE(COMP_IQK, DBG_LOUD, ("RestoreRF Path A Success!!!!\n"));
4952                        }
4953                        break;
4954                default:
4955                        break;
4956        }
4957}
4958
4959void _rtl8821ae_iqk_restore_afe(
4960                struct ieee80211_hw *hw,
4961                u32*            afe_backup,
4962                u32*            backup_afe_reg,
4963                u32             afe_num
4964                )
4965{
4966        u32 i;
4967        struct rtl_priv* rtlpriv = rtl_priv(hw);
4968
4969        rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C
4970        //Reload AFE Parameters
4971        for (i = 0; i < afe_num; i++){
4972                rtl_write_dword(rtlpriv, backup_afe_reg[i], afe_backup[i]);
4973        }
4974        rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1
4975        rtl_write_dword(rtlpriv, 0xc80, 0x0);
4976        rtl_write_dword(rtlpriv, 0xc84, 0x0);
4977        rtl_write_dword(rtlpriv, 0xc88, 0x0);
4978        rtl_write_dword(rtlpriv, 0xc8c, 0x3c000000);
4979        rtl_write_dword(rtlpriv, 0xc90, 0x00000080);
4980        rtl_write_dword(rtlpriv, 0xc94, 0x00000000);
4981        rtl_write_dword(rtlpriv, 0xcc4, 0x20040000);
4982        rtl_write_dword(rtlpriv, 0xcc8, 0x20000000);
4983        rtl_write_dword(rtlpriv, 0xcb8, 0x0);
4984        RT_TRACE(COMP_IQK, DBG_LOUD, ("RestoreAFE Success!!!!\n"));
4985}
4986
4987void _rtl8821ae_iqk_restore_macbb(
4988                struct ieee80211_hw *hw,
4989                u32*            macbb_backup,
4990                u32*            backup_macbb_reg,
4991                u32             macbb_num
4992                )
4993{
4994        u32 i;
4995        struct rtl_priv* rtlpriv = rtl_priv(hw);
4996
4997        rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C
4998        //Reload MacBB Parameters
4999        for (i = 0; i < macbb_num; i++){
5000                rtl_write_dword(rtlpriv, backup_macbb_reg[i], macbb_backup[i]);

5001        }
5002        RT_TRACE(COMP_IQK, DBG_LOUD, ("RestoreMacBB Success!!!!\n"));
5003}
5004
5005
5006#undef MACBB_REG_NUM
5007#undef AFE_REG_NUM
5008#undef RF_REG_NUM
5009
5010#define MACBB_REG_NUM 11
5011#define AFE_REG_NUM 12
5012#define RF_REG_NUM 3
5013
5014static void _rtl8821ae_phy_iq_calibrate(struct ieee80211_hw *hw)
5015{
5016        u32     macbb_backup[MACBB_REG_NUM];
5017        u32 afe_backup[AFE_REG_NUM];
5018        u32 rfa_backup[RF_REG_NUM];
5019        u32 rfb_backup[RF_REG_NUM];
5020        u32     backup_macbb_reg[MACBB_REG_NUM] = {0xb00, 0x520, 0x550, 0x808, 0x90c, 0xc00, 0xc50,
5021                                                        0xe00, 0xe50, 0x838, 0x82c};
5022        u32     backup_afe_reg[AFE_REG_NUM] = {0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74,
5023                                                        0xc78, 0xc7c, 0xc80, 0xc84, 0xcb8};
5024        u32     backup_rf_reg[RF_REG_NUM] = {0x65, 0x8f, 0x0};
5025
5026        _rtl8821ae_iqk_backup_macbb(hw, macbb_backup, backup_macbb_reg, MACBB_REG_NUM);
5027        _rtl8821ae_iqk_backup_afe(hw, afe_backup, backup_afe_reg, AFE_REG_NUM);
5028        _rtl8821ae_iqk_backup_rf(hw, rfa_backup, rfb_backup, backup_rf_reg, RF_REG_NUM);
5029
5030        _rtl8821ae_iqk_configure_mac(hw);
5031        _rtl8821ae_iqk_tx(hw, RF90_PATH_A);
5032        _rtl8821ae_iqk_restore_rf(hw, RF90_PATH_A, backup_rf_reg, rfa_backup, RF_REG_NUM);
5033
5034        _rtl8821ae_iqk_restore_afe(hw, afe_backup, backup_afe_reg, AFE_REG_NUM);
5035        _rtl8821ae_iqk_restore_macbb(hw, macbb_backup, backup_macbb_reg, MACBB_REG_NUM);
5036}
5037
5038static void _rtl8821ae_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
5039{
5040        u8 tmpreg;
5041        u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
5042        struct rtl_priv *rtlpriv = rtl_priv(hw);
5043
5044        tmpreg = rtl_read_byte(rtlpriv, 0xd03);
5045
5046        if ((tmpreg & 0x70) != 0)
5047                rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
5048        else
5049                rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
5050
5051        if ((tmpreg & 0x70) != 0) {
5052                rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
5053
5054                if (is2t)
5055                        rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
5056                                                  MASK12BITS);
5057
5058                rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
5059                              (rf_a_mode & 0x8FFFF) | 0x10000);
5060
5061                if (is2t)
5062                        rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
5063                                      (rf_b_mode & 0x8FFFF) | 0x10000);
5064        }
5065        lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
5066
5067        rtl_set_rfreg(hw, RF90_PATH_A, 0xb0, RFREG_OFFSET_MASK, 0xdfbe0);
5068        /* rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000); */
5069        rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, 0x8c0a);
5070
5071        mdelay(100);
5072
5073        rtl_set_rfreg(hw, RF90_PATH_A, 0xb0, RFREG_OFFSET_MASK, 0xdffe0);
5074
5075        if ((tmpreg & 0x70) != 0) {
5076                rtl_write_byte(rtlpriv, 0xd03, tmpreg);
5077                rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
5078
5079                if (is2t)
5080                        rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, rf_b_mode);
5081        } else {
5082                rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
5083        }
5084RT_TRACE(COMP_INIT,DBG_LOUD,("\n"));
5085
5086}
5087
5088static void _rtl8821ae_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool main)
5089{
5090        struct rtl_priv *rtlpriv = rtl_priv(hw);
5091        //struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
5092        //struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
5093        RT_TRACE(COMP_INIT,DBG_LOUD,("\n"));
5094
5095        if (main)
5096                rtl_set_bbreg(hw, RA_RFE_PINMUX + 4, BIT(29) | BIT(28), 0x1);
5097        else
5098                rtl_set_bbreg(hw, RA_RFE_PINMUX + 4, BIT(29) | BIT(28), 0x2);
5099}
5100
5101#undef IQK_ADDA_REG_NUM
5102#undef IQK_DELAY_TIME
5103
5104void rtl8812ae_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery)
5105{
5106        struct rtl_priv *rtlpriv = rtl_priv(hw);
5107        struct rtl_phy *rtlphy = &(rtlpriv->phy);
5108
5109        if (!rtlphy->b_iqk_in_progress)
5110        {
5111                spin_lock(&rtlpriv->locks.iqk_lock);
5112                rtlphy->b_iqk_in_progress = true;
5113                spin_unlock(&rtlpriv->locks.iqk_lock);
5114
5115                _rtl8812ae_phy_iq_calibrate(hw, rtlphy->current_channel);
5116
5117                spin_lock(&rtlpriv->locks.iqk_lock);
5118                rtlphy->b_iqk_in_progress = false;
5119                spin_unlock(&rtlpriv->locks.iqk_lock);
5120        }
5121}
5122
5123void rtl8812ae_reset_iqk_result(struct ieee80211_hw *hw)
5124{
5125        struct rtl_priv *rtlpriv = rtl_priv(hw);
5126        struct rtl_phy *rtlphy = &(rtlpriv->phy);
5127        u8 i;
5128
5129        RT_TRACE(COMP_IQK, DBG_LOUD,
5130                ("rtl8812ae_dm_reset_iqk_result:: settings regs %d default regs %d\n",
5131                (int)(sizeof(rtlphy->iqk_matrix_regsetting) /
5132                sizeof(struct iqk_matrix_regs)),
5133                IQK_MATRIX_SETTINGS_NUM));
5134
5135        for(i = 0; i < IQK_MATRIX_SETTINGS_NUM; i++) {
5136                {
5137                        rtlphy->iqk_matrix_regsetting[i].value[0][0] =
5138                                rtlphy->iqk_matrix_regsetting[i].value[0][2] =
5139                                rtlphy->iqk_matrix_regsetting[i].value[0][4] =
5140                                rtlphy->iqk_matrix_regsetting[i].value[0][6] = 0x100;
5141
5142                        rtlphy->iqk_matrix_regsetting[i].value[0][1] =
5143                                rtlphy->iqk_matrix_regsetting[i].value[0][3] =
5144                                rtlphy->iqk_matrix_regsetting[i].value[0][5] =
5145                                rtlphy->iqk_matrix_regsetting[i].value[0][7] = 0x0;
5146
5147                        rtlphy->iqk_matrix_regsetting[i].b_iqk_done = false;
5148
5149                }
5150        }
5151}
5152
5153void rtl8812ae_do_iqk(struct ieee80211_hw *hw,u8 delta_thermal_index,
5154        u8 thermal_value, u8 threshold)
5155{
5156        struct rtl_dm   *rtldm = rtl_dm(rtl_priv(hw));
5157
5158        rtl8812ae_reset_iqk_result(hw);
5159
5160        rtldm->thermalvalue_iqk= thermal_value;
5161        rtl8812ae_phy_iq_calibrate(hw, false);
5162}
5163
5164void rtl8821ae_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery)
5165{
5166        struct rtl_priv *rtlpriv = rtl_priv(hw);
5167        struct rtl_phy *rtlphy = &(rtlpriv->phy);
5168
5169        if (!rtlphy->b_iqk_in_progress)
5170        {
5171                spin_lock(&rtlpriv->locks.iqk_lock);
5172                rtlphy->b_iqk_in_progress = true;
5173                spin_unlock(&rtlpriv->locks.iqk_lock);
5174
5175                _rtl8821ae_phy_iq_calibrate(hw);
5176
5177                spin_lock(&rtlpriv->locks.iqk_lock);
5178                rtlphy->b_iqk_in_progress = false;
5179                spin_unlock(&rtlpriv->locks.iqk_lock);
5180        }
5181}
5182
5183void rtl8821ae_reset_iqk_result(struct ieee80211_hw *hw)
5184{
5185        struct rtl_priv *rtlpriv = rtl_priv(hw);
5186        struct rtl_phy *rtlphy = &(rtlpriv->phy);
5187        u8 i;
5188
5189        RT_TRACE(COMP_IQK, DBG_LOUD,
5190                ("rtl8812ae_dm_reset_iqk_result:: settings regs %d default regs %d\n",
5191                (int)(sizeof(rtlphy->iqk_matrix_regsetting) /
5192                sizeof(struct iqk_matrix_regs)),
5193                IQK_MATRIX_SETTINGS_NUM));
5194
5195        for(i = 0; i < IQK_MATRIX_SETTINGS_NUM; i++) {
5196                {
5197                        rtlphy->iqk_matrix_regsetting[i].value[0][0] =
5198                                rtlphy->iqk_matrix_regsetting[i].value[0][2] =
5199                                rtlphy->iqk_matrix_regsetting[i].value[0][4] =
5200                                rtlphy->iqk_matrix_regsetting[i].value[0][6] = 0x100;
5201
5202                        rtlphy->iqk_matrix_regsetting[i].value[0][1] =
5203                                rtlphy->iqk_matrix_regsetting[i].value[0][3] =
5204                                rtlphy->iqk_matrix_regsetting[i].value[0][5] =
5205                                rtlphy->iqk_matrix_regsetting[i].value[0][7] = 0x0;
5206
5207                        rtlphy->iqk_matrix_regsetting[i].b_iqk_done = false;
5208
5209                }
5210        }
5211}
5212
5213void rtl8821ae_do_iqk(struct ieee80211_hw *hw,u8 delta_thermal_index,
5214        u8 thermal_value, u8 threshold)
5215{
5216        struct rtl_dm   *rtldm = rtl_dm(rtl_priv(hw));
5217
5218        rtl8821ae_reset_iqk_result(hw);
5219
5220        rtldm->thermalvalue_iqk= thermal_value;
5221        rtl8821ae_phy_iq_calibrate(hw, false);
5222}
5223
5224void rtl8821ae_phy_lc_calibrate(struct ieee80211_hw *hw)
5225{
5226        struct rtl_priv *rtlpriv = rtl_priv(hw);
5227        struct rtl_phy *rtlphy = &(rtlpriv->phy);
5228        struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
5229        u32 timeout = 2000, timecount = 0;
5230
5231
5232        while (rtlpriv->mac80211.act_scanning && timecount < timeout) {
5233                udelay(50);
5234                timecount += 50;
5235        }
5236
5237        rtlphy->lck_inprogress = true;
5238        RTPRINT(rtlpriv, FINIT, INIT_IQK,
5239                ("LCK:Start!!! currentband %x delay %d ms\n",
5240                 rtlhal->current_bandtype, timecount));
5241
5242        _rtl8821ae_phy_lc_calibrate(hw, false);
5243
5244        rtlphy->lck_inprogress = false;
5245}
5246
5247void rtl8821ae_phy_ap_calibrate(struct ieee80211_hw *hw, char delta)
5248{
5249        struct rtl_priv *rtlpriv = rtl_priv(hw);
5250        struct rtl_phy *rtlphy = &(rtlpriv->phy);
5251
5252        if (rtlphy->b_apk_done)
5253                return;
5254
5255        return;
5256}
5257
5258void rtl8821ae_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain)
5259{
5260        _rtl8821ae_phy_set_rfpath_switch(hw, bmain);
5261}
5262
5263bool rtl8821ae_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
5264{
5265        struct rtl_priv *rtlpriv = rtl_priv(hw);
5266        struct rtl_phy *rtlphy = &(rtlpriv->phy);
5267        bool b_postprocessing = false;
5268
5269        RT_TRACE(COMP_CMD, DBG_TRACE,
5270                 ("-->IO Cmd(%#x), set_io_inprogress(%d)\n",
5271                  iotype, rtlphy->set_io_inprogress));
5272        do {
5273                switch (iotype) {
5274                case IO_CMD_RESUME_DM_BY_SCAN:
5275                        RT_TRACE(COMP_CMD, DBG_TRACE,
5276                                 ("[IO CMD] Resume DM after scan.\n"));
5277                        b_postprocessing = true;
5278                        break;
5279                case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
5280                case IO_CMD_PAUSE_BAND1_DM_BY_SCAN:
5281                        RT_TRACE(COMP_CMD, DBG_TRACE,
5282                                 ("[IO CMD] Pause DM before scan.\n"));
5283                        b_postprocessing = true;
5284                        break;
5285                default:
5286                        RT_TRACE(COMP_ERR, DBG_EMERG,
5287                                 ("switch case not process \n"));
5288                        break;
5289                }
5290        } while (false);
5291        if (b_postprocessing && !rtlphy->set_io_inprogress) {
5292                rtlphy->set_io_inprogress = true;
5293                rtlphy->current_io_type = iotype;
5294        } else {
5295                return false;
5296        }
5297        rtl8821ae_phy_set_io(hw);
5298        RT_TRACE(COMP_CMD, DBG_TRACE, ("IO Type(%#x)\n", iotype));
5299        return true;
5300}
5301
5302static void rtl8821ae_phy_set_io(struct ieee80211_hw *hw)
5303{
5304        struct rtl_priv *rtlpriv = rtl_priv(hw);
5305        struct rtl_phy *rtlphy = &(rtlpriv->phy);
5306
5307        RT_TRACE(COMP_CMD, DBG_TRACE,
5308                 ("--->Cmd(%#x), set_io_inprogress(%d)\n",
5309                  rtlphy->current_io_type, rtlphy->set_io_inprogress));
5310        switch (rtlphy->current_io_type) {
5311        case IO_CMD_RESUME_DM_BY_SCAN:
5312                if (rtlpriv->mac80211.opmode== NL80211_IFTYPE_ADHOC)
5313                        _rtl8821ae_resume_tx_beacon(hw);
5314                rtl8821ae_dm_write_dig(hw, rtlphy->initgain_backup.xaagccore1);
5315                rtl8821ae_dm_write_cck_cca_thres(hw, rtlphy->initgain_backup.cca);
5316                break;
5317        case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
5318                if (rtlpriv->mac80211.opmode== NL80211_IFTYPE_ADHOC)
5319                        _rtl8821ae_stop_tx_beacon(hw);
5320                rtlphy->initgain_backup.xaagccore1 = dm_digtable.cur_igvalue;
5321                rtl8821ae_dm_write_dig(hw, 0x17);
5322                rtlphy->initgain_backup.cca = dm_digtable.cur_cck_cca_thres;
5323                rtl8821ae_dm_write_cck_cca_thres(hw, 0x40);
5324                break;
5325        case IO_CMD_PAUSE_BAND1_DM_BY_SCAN:
5326                break;
5327        default:
5328                RT_TRACE(COMP_ERR, DBG_EMERG,
5329                         ("switch case not process \n"));
5330                break;
5331        }
5332        rtlphy->set_io_inprogress = false;
5333        RT_TRACE(COMP_CMD, DBG_TRACE,
5334                 ("(%#x)\n", rtlphy->current_io_type));
5335}
5336
5337static void rtl8821ae_phy_set_rf_on(struct ieee80211_hw *hw)
5338{
5339        struct rtl_priv *rtlpriv = rtl_priv(hw);
5340
5341        rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
5342        rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
5343        rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
5344        rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
5345        rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
5346}
5347
5348#if 0
5349static void _rtl8821ae_phy_set_rf_sleep(struct ieee80211_hw *hw)
5350{
5351        struct rtl_priv *rtlpriv = rtl_priv(hw);
5352
5353        rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
5354        rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
5355        /*rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
5356        u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
5357        while (u4b_tmp != 0 && delay > 0) {
5358                rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
5359                rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
5360                rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
5361                u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
5362                delay--;
5363        }
5364        if (delay == 0) {
5365                rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
5366                rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
5367                rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
5368                rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
5369                RT_TRACE(COMP_POWER, DBG_TRACE,
5370                         ("Switch RF timeout !!!.\n"));
5371                return;
5372        }*/
5373        rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
5374        rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
5375}
5376#endif
5377
5378static bool _rtl8821ae_phy_set_rf_power_state(struct ieee80211_hw *hw,
5379                                            enum rf_pwrstate rfpwr_state)
5380{
5381        struct rtl_priv *rtlpriv = rtl_priv(hw);
5382        struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
5383        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
5384        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
5385        bool bresult = true;
5386        u8 i, queue_id;
5387        struct rtl8192_tx_ring *ring = NULL;
5388
5389        switch (rfpwr_state) {
5390        case ERFON:{
5391                        if ((ppsc->rfpwr_state == ERFOFF) &&
5392                            RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
5393                                bool rtstatus = false;
5394                                u32 InitializeCount = 0;
5395                                do {
5396                                        InitializeCount++;
5397                                        RT_TRACE(COMP_RF, DBG_DMESG,
5398                                                 ("IPS Set eRf nic enable\n"));
5399                                        rtstatus = rtl_ps_enable_nic(hw);
5400                                } while ((rtstatus != true)
5401                                         && (InitializeCount < 10));
5402                                RT_CLEAR_PS_LEVEL(ppsc,
5403                                                  RT_RF_OFF_LEVL_HALT_NIC);
5404                        } else {
5405                                RT_TRACE(COMP_RF, DBG_DMESG,
5406                                         ("Set ERFON sleeped:%d ms\n",
5407                                          jiffies_to_msecs(jiffies -
5408                                                           ppsc->
5409                                                           last_sleep_jiffies)));
5410                                ppsc->last_awake_jiffies = jiffies;
5411                                rtl8821ae_phy_set_rf_on(hw);
5412                        }
5413                        if (mac->link_state == MAC80211_LINKED) {
5414                                rtlpriv->cfg->ops->led_control(hw,
5415                                                               LED_CTL_LINK);
5416                        } else {
5417                                rtlpriv->cfg->ops->led_control(hw,
5418                                                               LED_CTL_NO_LINK);
5419                        }
5420                        break;
5421                }
5422        case ERFOFF:{
5423                        for (queue_id = 0, i = 0;
5424                             queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
5425                                ring = &pcipriv->dev.tx_ring[queue_id];
5426                                if (skb_queue_len(&ring->queue) == 0) {
5427                                        queue_id++;
5428                                        continue;
5429                                } else {
5430                                        RT_TRACE(COMP_ERR, DBG_WARNING,
5431                                                 ("eRf Off/Sleep: %d times "
5432                                                  "TcbBusyQueue[%d] =%d before "
5433                                                  "doze!\n", (i + 1), queue_id,
5434                                                  skb_queue_len(&ring->queue)));
5435
5436                                        udelay(10);
5437                                        i++;
5438                                }
5439                                if (i >= MAX_DOZE_WAITING_TIMES_9x) {
5440                                        RT_TRACE(COMP_ERR, DBG_WARNING,
5441                                                 ("\n ERFSLEEP: %d times "
5442                                                  "TcbBusyQueue[%d] = %d !\n",
5443                                                  MAX_DOZE_WAITING_TIMES_9x,
5444                                                  queue_id,
5445                                                  skb_queue_len(&ring->queue)));
5446                                        break;
5447                                }
5448                        }
5449
5450                        if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
5451                                RT_TRACE(COMP_RF, DBG_DMESG,
5452                                         ("IPS Set eRf nic disable\n"));
5453                                rtl_ps_disable_nic(hw);
5454                                RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
5455                        } else {
5456                                if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
5457                                        rtlpriv->cfg->ops->led_control(hw,
5458                                                                       LED_CTL_NO_LINK);
5459                                } else {
5460                                        rtlpriv->cfg->ops->led_control(hw,
5461                                                                       LED_CTL_POWER_OFF);
5462                                }
5463                        }
5464                        break;
5465                }
5466        /*case ERFSLEEP:{
5467                        if (ppsc->rfpwr_state == ERFOFF)
5468                                break;
5469                        for (queue_id = 0, i = 0;
5470                             queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
5471                                ring = &pcipriv->dev.tx_ring[queue_id];
5472                                if (skb_queue_len(&ring->queue) == 0) {
5473                                        queue_id++;
5474                                        continue;
5475                                } else {
5476                                        RT_TRACE(COMP_ERR, DBG_WARNING,
5477                                                 ("eRf Off/Sleep: %d times "
5478                                                  "TcbBusyQueue[%d] =%d before "
5479                                                  "doze!\n", (i + 1), queue_id,
5480                                                  skb_queue_len(&ring->queue)));
5481
5482                                        udelay(10);
5483                                        i++;
5484                                }
5485                                if (i >= MAX_DOZE_WAITING_TIMES_9x) {
5486                                        RT_TRACE(COMP_ERR, DBG_WARNING,
5487                                                 ("\n ERFSLEEP: %d times "
5488                                                  "TcbBusyQueue[%d] = %d !\n",
5489                                                  MAX_DOZE_WAITING_TIMES_9x,
5490                                                  queue_id,
5491                                                  skb_queue_len(&ring->queue)));
5492                                        break;
5493                                }
5494                        }
5495                        RT_TRACE(COMP_RF, DBG_DMESG,
5496                                 ("Set ERFSLEEP awaked:%d ms\n",
5497                                  jiffies_to_msecs(jiffies -
5498                                                   ppsc->last_awake_jiffies)));
5499                        ppsc->last_sleep_jiffies = jiffies;
5500                        _rtl8821ae_phy_set_rf_sleep(hw);
5501                        break;
5502                }*/
5503        default:
5504                RT_TRACE(COMP_ERR, DBG_EMERG,
5505                         ("switch case not process \n"));
5506                bresult = false;
5507                break;
5508        }
5509        if (bresult)
5510                ppsc->rfpwr_state = rfpwr_state;
5511        return bresult;
5512}
5513
5514bool rtl8821ae_phy_set_rf_power_state(struct ieee80211_hw *hw,
5515                                   enum rf_pwrstate rfpwr_state)
5516{
5517        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
5518
5519        bool bresult = false;
5520
5521        if (rfpwr_state == ppsc->rfpwr_state)
5522                return bresult;
5523        bresult = _rtl8821ae_phy_set_rf_power_state(hw, rfpwr_state);
5524        return bresult;
5525}
5526