linux/drivers/tty/serial/ioc4_serial.c
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   1/*
   2 * This file is subject to the terms and conditions of the GNU General Public
   3 * License.  See the file "COPYING" in the main directory of this archive
   4 * for more details.
   5 *
   6 * Copyright (C) 2003-2006 Silicon Graphics, Inc.  All Rights Reserved.
   7 */
   8
   9
  10/*
  11 * This file contains a module version of the ioc4 serial driver. This
  12 * includes all the support functions needed (support functions, etc.)
  13 * and the serial driver itself.
  14 */
  15#include <linux/errno.h>
  16#include <linux/tty.h>
  17#include <linux/tty_flip.h>
  18#include <linux/serial.h>
  19#include <linux/circ_buf.h>
  20#include <linux/serial_reg.h>
  21#include <linux/module.h>
  22#include <linux/pci.h>
  23#include <linux/ioc4.h>
  24#include <linux/serial_core.h>
  25#include <linux/slab.h>
  26
  27/*
  28 * interesting things about the ioc4
  29 */
  30
  31#define IOC4_NUM_SERIAL_PORTS   4       /* max ports per card */
  32#define IOC4_NUM_CARDS          8       /* max cards per partition */
  33
  34#define GET_SIO_IR(_n)  (_n == 0) ? (IOC4_SIO_IR_S0) : \
  35                                (_n == 1) ? (IOC4_SIO_IR_S1) : \
  36                                (_n == 2) ? (IOC4_SIO_IR_S2) : \
  37                                (IOC4_SIO_IR_S3)
  38
  39#define GET_OTHER_IR(_n)  (_n == 0) ? (IOC4_OTHER_IR_S0_MEMERR) : \
  40                                (_n == 1) ? (IOC4_OTHER_IR_S1_MEMERR) : \
  41                                (_n == 2) ? (IOC4_OTHER_IR_S2_MEMERR) : \
  42                                (IOC4_OTHER_IR_S3_MEMERR)
  43
  44
  45/*
  46 * All IOC4 registers are 32 bits wide.
  47 */
  48
  49/*
  50 * PCI Memory Space Map
  51 */
  52#define IOC4_PCI_ERR_ADDR_L     0x000   /* Low Error Address */
  53#define IOC4_PCI_ERR_ADDR_VLD           (0x1 << 0)
  54#define IOC4_PCI_ERR_ADDR_MST_ID_MSK    (0xf << 1)
  55#define IOC4_PCI_ERR_ADDR_MST_NUM_MSK   (0xe << 1)
  56#define IOC4_PCI_ERR_ADDR_MST_TYP_MSK   (0x1 << 1)
  57#define IOC4_PCI_ERR_ADDR_MUL_ERR       (0x1 << 5)
  58#define IOC4_PCI_ERR_ADDR_ADDR_MSK      (0x3ffffff << 6)
  59
  60/* Interrupt types */
  61#define IOC4_SIO_INTR_TYPE      0
  62#define IOC4_OTHER_INTR_TYPE    1
  63#define IOC4_NUM_INTR_TYPES     2
  64
  65/* Bitmasks for IOC4_SIO_IR, IOC4_SIO_IEC, and IOC4_SIO_IES  */
  66#define IOC4_SIO_IR_S0_TX_MT       0x00000001   /* Serial port 0 TX empty */
  67#define IOC4_SIO_IR_S0_RX_FULL     0x00000002   /* Port 0 RX buf full */
  68#define IOC4_SIO_IR_S0_RX_HIGH     0x00000004   /* Port 0 RX hiwat */
  69#define IOC4_SIO_IR_S0_RX_TIMER    0x00000008   /* Port 0 RX timeout */
  70#define IOC4_SIO_IR_S0_DELTA_DCD   0x00000010   /* Port 0 delta DCD */
  71#define IOC4_SIO_IR_S0_DELTA_CTS   0x00000020   /* Port 0 delta CTS */
  72#define IOC4_SIO_IR_S0_INT         0x00000040   /* Port 0 pass-thru intr */
  73#define IOC4_SIO_IR_S0_TX_EXPLICIT 0x00000080   /* Port 0 explicit TX thru */
  74#define IOC4_SIO_IR_S1_TX_MT       0x00000100   /* Serial port 1 */
  75#define IOC4_SIO_IR_S1_RX_FULL     0x00000200   /* */
  76#define IOC4_SIO_IR_S1_RX_HIGH     0x00000400   /* */
  77#define IOC4_SIO_IR_S1_RX_TIMER    0x00000800   /* */
  78#define IOC4_SIO_IR_S1_DELTA_DCD   0x00001000   /* */
  79#define IOC4_SIO_IR_S1_DELTA_CTS   0x00002000   /* */
  80#define IOC4_SIO_IR_S1_INT         0x00004000   /* */
  81#define IOC4_SIO_IR_S1_TX_EXPLICIT 0x00008000   /* */
  82#define IOC4_SIO_IR_S2_TX_MT       0x00010000   /* Serial port 2 */
  83#define IOC4_SIO_IR_S2_RX_FULL     0x00020000   /* */
  84#define IOC4_SIO_IR_S2_RX_HIGH     0x00040000   /* */
  85#define IOC4_SIO_IR_S2_RX_TIMER    0x00080000   /* */
  86#define IOC4_SIO_IR_S2_DELTA_DCD   0x00100000   /* */
  87#define IOC4_SIO_IR_S2_DELTA_CTS   0x00200000   /* */
  88#define IOC4_SIO_IR_S2_INT         0x00400000   /* */
  89#define IOC4_SIO_IR_S2_TX_EXPLICIT 0x00800000   /* */
  90#define IOC4_SIO_IR_S3_TX_MT       0x01000000   /* Serial port 3 */
  91#define IOC4_SIO_IR_S3_RX_FULL     0x02000000   /* */
  92#define IOC4_SIO_IR_S3_RX_HIGH     0x04000000   /* */
  93#define IOC4_SIO_IR_S3_RX_TIMER    0x08000000   /* */
  94#define IOC4_SIO_IR_S3_DELTA_DCD   0x10000000   /* */
  95#define IOC4_SIO_IR_S3_DELTA_CTS   0x20000000   /* */
  96#define IOC4_SIO_IR_S3_INT         0x40000000   /* */
  97#define IOC4_SIO_IR_S3_TX_EXPLICIT 0x80000000   /* */
  98
  99/* Per device interrupt masks */
 100#define IOC4_SIO_IR_S0          (IOC4_SIO_IR_S0_TX_MT | \
 101                                 IOC4_SIO_IR_S0_RX_FULL | \
 102                                 IOC4_SIO_IR_S0_RX_HIGH | \
 103                                 IOC4_SIO_IR_S0_RX_TIMER | \
 104                                 IOC4_SIO_IR_S0_DELTA_DCD | \
 105                                 IOC4_SIO_IR_S0_DELTA_CTS | \
 106                                 IOC4_SIO_IR_S0_INT | \
 107                                 IOC4_SIO_IR_S0_TX_EXPLICIT)
 108#define IOC4_SIO_IR_S1          (IOC4_SIO_IR_S1_TX_MT | \
 109                                 IOC4_SIO_IR_S1_RX_FULL | \
 110                                 IOC4_SIO_IR_S1_RX_HIGH | \
 111                                 IOC4_SIO_IR_S1_RX_TIMER | \
 112                                 IOC4_SIO_IR_S1_DELTA_DCD | \
 113                                 IOC4_SIO_IR_S1_DELTA_CTS | \
 114                                 IOC4_SIO_IR_S1_INT | \
 115                                 IOC4_SIO_IR_S1_TX_EXPLICIT)
 116#define IOC4_SIO_IR_S2          (IOC4_SIO_IR_S2_TX_MT | \
 117                                 IOC4_SIO_IR_S2_RX_FULL | \
 118                                 IOC4_SIO_IR_S2_RX_HIGH | \
 119                                 IOC4_SIO_IR_S2_RX_TIMER | \
 120                                 IOC4_SIO_IR_S2_DELTA_DCD | \
 121                                 IOC4_SIO_IR_S2_DELTA_CTS | \
 122                                 IOC4_SIO_IR_S2_INT | \
 123                                 IOC4_SIO_IR_S2_TX_EXPLICIT)
 124#define IOC4_SIO_IR_S3          (IOC4_SIO_IR_S3_TX_MT | \
 125                                 IOC4_SIO_IR_S3_RX_FULL | \
 126                                 IOC4_SIO_IR_S3_RX_HIGH | \
 127                                 IOC4_SIO_IR_S3_RX_TIMER | \
 128                                 IOC4_SIO_IR_S3_DELTA_DCD | \
 129                                 IOC4_SIO_IR_S3_DELTA_CTS | \
 130                                 IOC4_SIO_IR_S3_INT | \
 131                                 IOC4_SIO_IR_S3_TX_EXPLICIT)
 132
 133/* Bitmasks for IOC4_OTHER_IR, IOC4_OTHER_IEC, and IOC4_OTHER_IES  */
 134#define IOC4_OTHER_IR_ATA_INT           0x00000001  /* ATAPI intr pass-thru */
 135#define IOC4_OTHER_IR_ATA_MEMERR        0x00000002  /* ATAPI DMA PCI error */
 136#define IOC4_OTHER_IR_S0_MEMERR         0x00000004  /* Port 0 PCI error */
 137#define IOC4_OTHER_IR_S1_MEMERR         0x00000008  /* Port 1 PCI error */
 138#define IOC4_OTHER_IR_S2_MEMERR         0x00000010  /* Port 2 PCI error */
 139#define IOC4_OTHER_IR_S3_MEMERR         0x00000020  /* Port 3 PCI error */
 140#define IOC4_OTHER_IR_KBD_INT           0x00000040  /* Keyboard/mouse */
 141#define IOC4_OTHER_IR_RESERVED          0x007fff80  /* Reserved */
 142#define IOC4_OTHER_IR_RT_INT            0x00800000  /* INT_OUT section output */
 143#define IOC4_OTHER_IR_GEN_INT           0xff000000  /* Generic pins */
 144
 145#define IOC4_OTHER_IR_SER_MEMERR (IOC4_OTHER_IR_S0_MEMERR | IOC4_OTHER_IR_S1_MEMERR | \
 146                                  IOC4_OTHER_IR_S2_MEMERR | IOC4_OTHER_IR_S3_MEMERR)
 147
 148/* Bitmasks for IOC4_SIO_CR */
 149#define IOC4_SIO_CR_CMD_PULSE_SHIFT              0  /* byte bus strobe shift */
 150#define IOC4_SIO_CR_ARB_DIAG_TX0        0x00000000
 151#define IOC4_SIO_CR_ARB_DIAG_RX0        0x00000010
 152#define IOC4_SIO_CR_ARB_DIAG_TX1        0x00000020
 153#define IOC4_SIO_CR_ARB_DIAG_RX1        0x00000030
 154#define IOC4_SIO_CR_ARB_DIAG_TX2        0x00000040
 155#define IOC4_SIO_CR_ARB_DIAG_RX2        0x00000050
 156#define IOC4_SIO_CR_ARB_DIAG_TX3        0x00000060
 157#define IOC4_SIO_CR_ARB_DIAG_RX3        0x00000070
 158#define IOC4_SIO_CR_SIO_DIAG_IDLE       0x00000080  /* 0 -> active request among
 159                                                           serial ports (ro) */
 160/* Defs for some of the generic I/O pins */
 161#define IOC4_GPCR_UART0_MODESEL    0x10 /* Pin is output to port 0
 162                                                   mode sel */
 163#define IOC4_GPCR_UART1_MODESEL    0x20 /* Pin is output to port 1
 164                                                   mode sel */
 165#define IOC4_GPCR_UART2_MODESEL    0x40 /* Pin is output to port 2
 166                                                   mode sel */
 167#define IOC4_GPCR_UART3_MODESEL    0x80 /* Pin is output to port 3
 168                                                   mode sel */
 169
 170#define IOC4_GPPR_UART0_MODESEL_PIN   4 /* GIO pin controlling
 171                                           uart 0 mode select */
 172#define IOC4_GPPR_UART1_MODESEL_PIN   5 /* GIO pin controlling
 173                                           uart 1 mode select */
 174#define IOC4_GPPR_UART2_MODESEL_PIN   6 /* GIO pin controlling
 175                                           uart 2 mode select */
 176#define IOC4_GPPR_UART3_MODESEL_PIN   7 /* GIO pin controlling
 177                                           uart 3 mode select */
 178
 179/* Bitmasks for serial RX status byte */
 180#define IOC4_RXSB_OVERRUN       0x01    /* Char(s) lost */
 181#define IOC4_RXSB_PAR_ERR       0x02    /* Parity error */
 182#define IOC4_RXSB_FRAME_ERR     0x04    /* Framing error */
 183#define IOC4_RXSB_BREAK         0x08    /* Break character */
 184#define IOC4_RXSB_CTS           0x10    /* State of CTS */
 185#define IOC4_RXSB_DCD           0x20    /* State of DCD */
 186#define IOC4_RXSB_MODEM_VALID   0x40    /* DCD, CTS, and OVERRUN are valid */
 187#define IOC4_RXSB_DATA_VALID    0x80    /* Data byte, FRAME_ERR PAR_ERR
 188                                         * & BREAK valid */
 189
 190/* Bitmasks for serial TX control byte */
 191#define IOC4_TXCB_INT_WHEN_DONE 0x20    /* Interrupt after this byte is sent */
 192#define IOC4_TXCB_INVALID       0x00    /* Byte is invalid */
 193#define IOC4_TXCB_VALID         0x40    /* Byte is valid */
 194#define IOC4_TXCB_MCR           0x80    /* Data<7:0> to modem control reg */
 195#define IOC4_TXCB_DELAY         0xc0    /* Delay data<7:0> mSec */
 196
 197/* Bitmasks for IOC4_SBBR_L */
 198#define IOC4_SBBR_L_SIZE        0x00000001  /* 0 == 1KB rings, 1 == 4KB rings */
 199
 200/* Bitmasks for IOC4_SSCR_<3:0> */
 201#define IOC4_SSCR_RX_THRESHOLD  0x000001ff  /* Hiwater mark */
 202#define IOC4_SSCR_TX_TIMER_BUSY 0x00010000  /* TX timer in progress */
 203#define IOC4_SSCR_HFC_EN        0x00020000  /* Hardware flow control enabled */
 204#define IOC4_SSCR_RX_RING_DCD   0x00040000  /* Post RX record on delta-DCD */
 205#define IOC4_SSCR_RX_RING_CTS   0x00080000  /* Post RX record on delta-CTS */
 206#define IOC4_SSCR_DIAG          0x00200000  /* Bypass clock divider for sim */
 207#define IOC4_SSCR_RX_DRAIN      0x08000000  /* Drain RX buffer to memory */
 208#define IOC4_SSCR_DMA_EN        0x10000000  /* Enable ring buffer DMA */
 209#define IOC4_SSCR_DMA_PAUSE     0x20000000  /* Pause DMA */
 210#define IOC4_SSCR_PAUSE_STATE   0x40000000  /* Sets when PAUSE takes effect */
 211#define IOC4_SSCR_RESET         0x80000000  /* Reset DMA channels */
 212
 213/* All producer/comsumer pointers are the same bitfield */
 214#define IOC4_PROD_CONS_PTR_4K   0x00000ff8      /* For 4K buffers */
 215#define IOC4_PROD_CONS_PTR_1K   0x000003f8      /* For 1K buffers */
 216#define IOC4_PROD_CONS_PTR_OFF           3
 217
 218/* Bitmasks for IOC4_SRCIR_<3:0> */
 219#define IOC4_SRCIR_ARM          0x80000000      /* Arm RX timer */
 220
 221/* Bitmasks for IOC4_SHADOW_<3:0> */
 222#define IOC4_SHADOW_DR   0x00000001     /* Data ready */
 223#define IOC4_SHADOW_OE   0x00000002     /* Overrun error */
 224#define IOC4_SHADOW_PE   0x00000004     /* Parity error */
 225#define IOC4_SHADOW_FE   0x00000008     /* Framing error */
 226#define IOC4_SHADOW_BI   0x00000010     /* Break interrupt */
 227#define IOC4_SHADOW_THRE 0x00000020     /* Xmit holding register empty */
 228#define IOC4_SHADOW_TEMT 0x00000040     /* Xmit shift register empty */
 229#define IOC4_SHADOW_RFCE 0x00000080     /* Char in RX fifo has an error */
 230#define IOC4_SHADOW_DCTS 0x00010000     /* Delta clear to send */
 231#define IOC4_SHADOW_DDCD 0x00080000     /* Delta data carrier detect */
 232#define IOC4_SHADOW_CTS  0x00100000     /* Clear to send */
 233#define IOC4_SHADOW_DCD  0x00800000     /* Data carrier detect */
 234#define IOC4_SHADOW_DTR  0x01000000     /* Data terminal ready */
 235#define IOC4_SHADOW_RTS  0x02000000     /* Request to send */
 236#define IOC4_SHADOW_OUT1 0x04000000     /* 16550 OUT1 bit */
 237#define IOC4_SHADOW_OUT2 0x08000000     /* 16550 OUT2 bit */
 238#define IOC4_SHADOW_LOOP 0x10000000     /* Loopback enabled */
 239
 240/* Bitmasks for IOC4_SRTR_<3:0> */
 241#define IOC4_SRTR_CNT           0x00000fff      /* Reload value for RX timer */
 242#define IOC4_SRTR_CNT_VAL       0x0fff0000      /* Current value of RX timer */
 243#define IOC4_SRTR_CNT_VAL_SHIFT         16
 244#define IOC4_SRTR_HZ                 16000      /* SRTR clock frequency */
 245
 246/* Serial port register map used for DMA and PIO serial I/O */
 247struct ioc4_serialregs {
 248        uint32_t sscr;
 249        uint32_t stpir;
 250        uint32_t stcir;
 251        uint32_t srpir;
 252        uint32_t srcir;
 253        uint32_t srtr;
 254        uint32_t shadow;
 255};
 256
 257/* IOC4 UART register map */
 258struct ioc4_uartregs {
 259        char i4u_lcr;
 260        union {
 261                char iir;       /* read only */
 262                char fcr;       /* write only */
 263        } u3;
 264        union {
 265                char ier;       /* DLAB == 0 */
 266                char dlm;       /* DLAB == 1 */
 267        } u2;
 268        union {
 269                char rbr;       /* read only, DLAB == 0 */
 270                char thr;       /* write only, DLAB == 0 */
 271                char dll;       /* DLAB == 1 */
 272        } u1;
 273        char i4u_scr;
 274        char i4u_msr;
 275        char i4u_lsr;
 276        char i4u_mcr;
 277};
 278
 279/* short names */
 280#define i4u_dll u1.dll
 281#define i4u_ier u2.ier
 282#define i4u_dlm u2.dlm
 283#define i4u_fcr u3.fcr
 284
 285/* Serial port registers used for DMA serial I/O */
 286struct ioc4_serial {
 287        uint32_t sbbr01_l;
 288        uint32_t sbbr01_h;
 289        uint32_t sbbr23_l;
 290        uint32_t sbbr23_h;
 291
 292        struct ioc4_serialregs port_0;
 293        struct ioc4_serialregs port_1;
 294        struct ioc4_serialregs port_2;
 295        struct ioc4_serialregs port_3;
 296        struct ioc4_uartregs uart_0;
 297        struct ioc4_uartregs uart_1;
 298        struct ioc4_uartregs uart_2;
 299        struct ioc4_uartregs uart_3;
 300};
 301
 302/* UART clock speed */
 303#define IOC4_SER_XIN_CLK_66     66666667
 304#define IOC4_SER_XIN_CLK_33     33333333
 305
 306#define IOC4_W_IES              0
 307#define IOC4_W_IEC              1
 308
 309typedef void ioc4_intr_func_f(void *, uint32_t);
 310typedef ioc4_intr_func_f *ioc4_intr_func_t;
 311
 312static unsigned int Num_of_ioc4_cards;
 313
 314/* defining this will get you LOTS of great debug info */
 315//#define DEBUG_INTERRUPTS
 316#define DPRINT_CONFIG(_x...)    ;
 317//#define DPRINT_CONFIG(_x...)  printk _x
 318
 319/* number of characters left in xmit buffer before we ask for more */
 320#define WAKEUP_CHARS    256
 321
 322/* number of characters we want to transmit to the lower level at a time */
 323#define IOC4_MAX_CHARS  256
 324#define IOC4_FIFO_CHARS 255
 325
 326/* Device name we're using */
 327#define DEVICE_NAME_RS232  "ttyIOC"
 328#define DEVICE_NAME_RS422  "ttyAIOC"
 329#define DEVICE_MAJOR       204
 330#define DEVICE_MINOR_RS232 50
 331#define DEVICE_MINOR_RS422 84
 332
 333
 334/* register offsets */
 335#define IOC4_SERIAL_OFFSET      0x300
 336
 337/* flags for next_char_state */
 338#define NCS_BREAK       0x1
 339#define NCS_PARITY      0x2
 340#define NCS_FRAMING     0x4
 341#define NCS_OVERRUN     0x8
 342
 343/* cause we need SOME parameters ... */
 344#define MIN_BAUD_SUPPORTED      1200
 345#define MAX_BAUD_SUPPORTED      115200
 346
 347/* protocol types supported */
 348#define PROTO_RS232     3
 349#define PROTO_RS422     7
 350
 351/* Notification types */
 352#define N_DATA_READY    0x01
 353#define N_OUTPUT_LOWAT  0x02
 354#define N_BREAK         0x04
 355#define N_PARITY_ERROR  0x08
 356#define N_FRAMING_ERROR 0x10
 357#define N_OVERRUN_ERROR 0x20
 358#define N_DDCD          0x40
 359#define N_DCTS          0x80
 360
 361#define N_ALL_INPUT     (N_DATA_READY | N_BREAK |                       \
 362                         N_PARITY_ERROR | N_FRAMING_ERROR |             \
 363                         N_OVERRUN_ERROR | N_DDCD | N_DCTS)
 364
 365#define N_ALL_OUTPUT    N_OUTPUT_LOWAT
 366
 367#define N_ALL_ERRORS    (N_PARITY_ERROR | N_FRAMING_ERROR | N_OVERRUN_ERROR)
 368
 369#define N_ALL           (N_DATA_READY | N_OUTPUT_LOWAT | N_BREAK |      \
 370                         N_PARITY_ERROR | N_FRAMING_ERROR |             \
 371                         N_OVERRUN_ERROR | N_DDCD | N_DCTS)
 372
 373#define SER_DIVISOR(_x, clk)            (((clk) + (_x) * 8) / ((_x) * 16))
 374#define DIVISOR_TO_BAUD(div, clk)       ((clk) / 16 / (div))
 375
 376/* Some masks */
 377#define LCR_MASK_BITS_CHAR      (UART_LCR_WLEN5 | UART_LCR_WLEN6 \
 378                                        | UART_LCR_WLEN7 | UART_LCR_WLEN8)
 379#define LCR_MASK_STOP_BITS      (UART_LCR_STOP)
 380
 381#define PENDING(_p)     (readl(&(_p)->ip_mem->sio_ir.raw) & _p->ip_ienb)
 382#define READ_SIO_IR(_p) readl(&(_p)->ip_mem->sio_ir.raw)
 383
 384/* Default to 4k buffers */
 385#ifdef IOC4_1K_BUFFERS
 386#define RING_BUF_SIZE 1024
 387#define IOC4_BUF_SIZE_BIT 0
 388#define PROD_CONS_MASK IOC4_PROD_CONS_PTR_1K
 389#else
 390#define RING_BUF_SIZE 4096
 391#define IOC4_BUF_SIZE_BIT IOC4_SBBR_L_SIZE
 392#define PROD_CONS_MASK IOC4_PROD_CONS_PTR_4K
 393#endif
 394
 395#define TOTAL_RING_BUF_SIZE (RING_BUF_SIZE * 4)
 396
 397/*
 398 * This is the entry saved by the driver - one per card
 399 */
 400
 401#define UART_PORT_MIN           0
 402#define UART_PORT_RS232         UART_PORT_MIN
 403#define UART_PORT_RS422         1
 404#define UART_PORT_COUNT         2       /* one for each mode */
 405
 406struct ioc4_control {
 407        int ic_irq;
 408        struct {
 409                /* uart ports are allocated here - 1 for rs232, 1 for rs422 */
 410                struct uart_port icp_uart_port[UART_PORT_COUNT];
 411                /* Handy reference material */
 412                struct ioc4_port *icp_port;
 413        } ic_port[IOC4_NUM_SERIAL_PORTS];
 414        struct ioc4_soft *ic_soft;
 415};
 416
 417/*
 418 * per-IOC4 data structure
 419 */
 420#define MAX_IOC4_INTR_ENTS      (8 * sizeof(uint32_t))
 421struct ioc4_soft {
 422        struct ioc4_misc_regs __iomem *is_ioc4_misc_addr;
 423        struct ioc4_serial __iomem *is_ioc4_serial_addr;
 424
 425        /* Each interrupt type has an entry in the array */
 426        struct ioc4_intr_type {
 427
 428                /*
 429                 * Each in-use entry in this array contains at least
 430                 * one nonzero bit in sd_bits; no two entries in this
 431                 * array have overlapping sd_bits values.
 432                 */
 433                struct ioc4_intr_info {
 434                        uint32_t sd_bits;
 435                        ioc4_intr_func_f *sd_intr;
 436                        void *sd_info;
 437                } is_intr_info[MAX_IOC4_INTR_ENTS];
 438
 439                /* Number of entries active in the above array */
 440                atomic_t is_num_intrs;
 441        } is_intr_type[IOC4_NUM_INTR_TYPES];
 442
 443        /* is_ir_lock must be held while
 444         * modifying sio_ie values, so
 445         * we can be sure that sio_ie is
 446         * not changing when we read it
 447         * along with sio_ir.
 448         */
 449        spinlock_t is_ir_lock;  /* SIO_IE[SC] mod lock */
 450};
 451
 452/* Local port info for each IOC4 serial ports */
 453struct ioc4_port {
 454        struct uart_port *ip_port;      /* current active port ptr */
 455        /* Ptrs for all ports */
 456        struct uart_port *ip_all_ports[UART_PORT_COUNT];
 457        /* Back ptrs for this port */
 458        struct ioc4_control *ip_control;
 459        struct pci_dev *ip_pdev;
 460        struct ioc4_soft *ip_ioc4_soft;
 461
 462        /* pci mem addresses */
 463        struct ioc4_misc_regs __iomem *ip_mem;
 464        struct ioc4_serial __iomem *ip_serial;
 465        struct ioc4_serialregs __iomem *ip_serial_regs;
 466        struct ioc4_uartregs __iomem *ip_uart_regs;
 467
 468        /* Ring buffer page for this port */
 469        dma_addr_t ip_dma_ringbuf;
 470        /* vaddr of ring buffer */
 471        struct ring_buffer *ip_cpu_ringbuf;
 472
 473        /* Rings for this port */
 474        struct ring *ip_inring;
 475        struct ring *ip_outring;
 476
 477        /* Hook to port specific values */
 478        struct hooks *ip_hooks;
 479
 480        spinlock_t ip_lock;
 481
 482        /* Various rx/tx parameters */
 483        int ip_baud;
 484        int ip_tx_lowat;
 485        int ip_rx_timeout;
 486
 487        /* Copy of notification bits */
 488        int ip_notify;
 489
 490        /* Shadow copies of various registers so we don't need to PIO
 491         * read them constantly
 492         */
 493        uint32_t ip_ienb;       /* Enabled interrupts */
 494        uint32_t ip_sscr;
 495        uint32_t ip_tx_prod;
 496        uint32_t ip_rx_cons;
 497        int ip_pci_bus_speed;
 498        unsigned char ip_flags;
 499};
 500
 501/* tx low water mark.  We need to notify the driver whenever tx is getting
 502 * close to empty so it can refill the tx buffer and keep things going.
 503 * Let's assume that if we interrupt 1 ms before the tx goes idle, we'll
 504 * have no trouble getting in more chars in time (I certainly hope so).
 505 */
 506#define TX_LOWAT_LATENCY      1000
 507#define TX_LOWAT_HZ          (1000000 / TX_LOWAT_LATENCY)
 508#define TX_LOWAT_CHARS(baud) (baud / 10 / TX_LOWAT_HZ)
 509
 510/* Flags per port */
 511#define INPUT_HIGH      0x01
 512#define DCD_ON          0x02
 513#define LOWAT_WRITTEN   0x04
 514#define READ_ABORTED    0x08
 515#define PORT_ACTIVE     0x10
 516#define PORT_INACTIVE   0       /* This is the value when "off" */
 517
 518
 519/* Since each port has different register offsets and bitmasks
 520 * for everything, we'll store those that we need in tables so we
 521 * don't have to be constantly checking the port we are dealing with.
 522 */
 523struct hooks {
 524        uint32_t intr_delta_dcd;
 525        uint32_t intr_delta_cts;
 526        uint32_t intr_tx_mt;
 527        uint32_t intr_rx_timer;
 528        uint32_t intr_rx_high;
 529        uint32_t intr_tx_explicit;
 530        uint32_t intr_dma_error;
 531        uint32_t intr_clear;
 532        uint32_t intr_all;
 533        int rs422_select_pin;
 534};
 535
 536static struct hooks hooks_array[IOC4_NUM_SERIAL_PORTS] = {
 537        /* Values for port 0 */
 538        {
 539         IOC4_SIO_IR_S0_DELTA_DCD, IOC4_SIO_IR_S0_DELTA_CTS,
 540         IOC4_SIO_IR_S0_TX_MT, IOC4_SIO_IR_S0_RX_TIMER,
 541         IOC4_SIO_IR_S0_RX_HIGH, IOC4_SIO_IR_S0_TX_EXPLICIT,
 542         IOC4_OTHER_IR_S0_MEMERR,
 543         (IOC4_SIO_IR_S0_TX_MT | IOC4_SIO_IR_S0_RX_FULL |
 544          IOC4_SIO_IR_S0_RX_HIGH | IOC4_SIO_IR_S0_RX_TIMER |
 545          IOC4_SIO_IR_S0_DELTA_DCD | IOC4_SIO_IR_S0_DELTA_CTS |
 546          IOC4_SIO_IR_S0_INT | IOC4_SIO_IR_S0_TX_EXPLICIT),
 547         IOC4_SIO_IR_S0, IOC4_GPPR_UART0_MODESEL_PIN,
 548         },
 549
 550        /* Values for port 1 */
 551        {
 552         IOC4_SIO_IR_S1_DELTA_DCD, IOC4_SIO_IR_S1_DELTA_CTS,
 553         IOC4_SIO_IR_S1_TX_MT, IOC4_SIO_IR_S1_RX_TIMER,
 554         IOC4_SIO_IR_S1_RX_HIGH, IOC4_SIO_IR_S1_TX_EXPLICIT,
 555         IOC4_OTHER_IR_S1_MEMERR,
 556         (IOC4_SIO_IR_S1_TX_MT | IOC4_SIO_IR_S1_RX_FULL |
 557          IOC4_SIO_IR_S1_RX_HIGH | IOC4_SIO_IR_S1_RX_TIMER |
 558          IOC4_SIO_IR_S1_DELTA_DCD | IOC4_SIO_IR_S1_DELTA_CTS |
 559          IOC4_SIO_IR_S1_INT | IOC4_SIO_IR_S1_TX_EXPLICIT),
 560         IOC4_SIO_IR_S1, IOC4_GPPR_UART1_MODESEL_PIN,
 561         },
 562
 563        /* Values for port 2 */
 564        {
 565         IOC4_SIO_IR_S2_DELTA_DCD, IOC4_SIO_IR_S2_DELTA_CTS,
 566         IOC4_SIO_IR_S2_TX_MT, IOC4_SIO_IR_S2_RX_TIMER,
 567         IOC4_SIO_IR_S2_RX_HIGH, IOC4_SIO_IR_S2_TX_EXPLICIT,
 568         IOC4_OTHER_IR_S2_MEMERR,
 569         (IOC4_SIO_IR_S2_TX_MT | IOC4_SIO_IR_S2_RX_FULL |
 570          IOC4_SIO_IR_S2_RX_HIGH | IOC4_SIO_IR_S2_RX_TIMER |
 571          IOC4_SIO_IR_S2_DELTA_DCD | IOC4_SIO_IR_S2_DELTA_CTS |
 572          IOC4_SIO_IR_S2_INT | IOC4_SIO_IR_S2_TX_EXPLICIT),
 573         IOC4_SIO_IR_S2, IOC4_GPPR_UART2_MODESEL_PIN,
 574         },
 575
 576        /* Values for port 3 */
 577        {
 578         IOC4_SIO_IR_S3_DELTA_DCD, IOC4_SIO_IR_S3_DELTA_CTS,
 579         IOC4_SIO_IR_S3_TX_MT, IOC4_SIO_IR_S3_RX_TIMER,
 580         IOC4_SIO_IR_S3_RX_HIGH, IOC4_SIO_IR_S3_TX_EXPLICIT,
 581         IOC4_OTHER_IR_S3_MEMERR,
 582         (IOC4_SIO_IR_S3_TX_MT | IOC4_SIO_IR_S3_RX_FULL |
 583          IOC4_SIO_IR_S3_RX_HIGH | IOC4_SIO_IR_S3_RX_TIMER |
 584          IOC4_SIO_IR_S3_DELTA_DCD | IOC4_SIO_IR_S3_DELTA_CTS |
 585          IOC4_SIO_IR_S3_INT | IOC4_SIO_IR_S3_TX_EXPLICIT),
 586         IOC4_SIO_IR_S3, IOC4_GPPR_UART3_MODESEL_PIN,
 587         }
 588};
 589
 590/* A ring buffer entry */
 591struct ring_entry {
 592        union {
 593                struct {
 594                        uint32_t alldata;
 595                        uint32_t allsc;
 596                } all;
 597                struct {
 598                        char data[4];   /* data bytes */
 599                        char sc[4];     /* status/control */
 600                } s;
 601        } u;
 602};
 603
 604/* Test the valid bits in any of the 4 sc chars using "allsc" member */
 605#define RING_ANY_VALID \
 606        ((uint32_t)(IOC4_RXSB_MODEM_VALID | IOC4_RXSB_DATA_VALID) * 0x01010101)
 607
 608#define ring_sc     u.s.sc
 609#define ring_data   u.s.data
 610#define ring_allsc  u.all.allsc
 611
 612/* Number of entries per ring buffer. */
 613#define ENTRIES_PER_RING (RING_BUF_SIZE / (int) sizeof(struct ring_entry))
 614
 615/* An individual ring */
 616struct ring {
 617        struct ring_entry entries[ENTRIES_PER_RING];
 618};
 619
 620/* The whole enchilada */
 621struct ring_buffer {
 622        struct ring TX_0_OR_2;
 623        struct ring RX_0_OR_2;
 624        struct ring TX_1_OR_3;
 625        struct ring RX_1_OR_3;
 626};
 627
 628/* Get a ring from a port struct */
 629#define RING(_p, _wh)   &(((struct ring_buffer *)((_p)->ip_cpu_ringbuf))->_wh)
 630
 631/* Infinite loop detection.
 632 */
 633#define MAXITER 10000000
 634
 635/* Prototypes */
 636static void receive_chars(struct uart_port *);
 637static void handle_intr(void *arg, uint32_t sio_ir);
 638
 639/*
 640 * port_is_active - determines if this port is currently active
 641 * @port: ptr to soft struct for this port
 642 * @uart_port: uart port to test for
 643 */
 644static inline int port_is_active(struct ioc4_port *port,
 645                struct uart_port *uart_port)
 646{
 647        if (port) {
 648                if ((port->ip_flags & PORT_ACTIVE)
 649                                        && (port->ip_port == uart_port))
 650                        return 1;
 651        }
 652        return 0;
 653}
 654
 655
 656/**
 657 * write_ireg - write the interrupt regs
 658 * @ioc4_soft: ptr to soft struct for this port
 659 * @val: value to write
 660 * @which: which register
 661 * @type: which ireg set
 662 */
 663static inline void
 664write_ireg(struct ioc4_soft *ioc4_soft, uint32_t val, int which, int type)
 665{
 666        struct ioc4_misc_regs __iomem *mem = ioc4_soft->is_ioc4_misc_addr;
 667        unsigned long flags;
 668
 669        spin_lock_irqsave(&ioc4_soft->is_ir_lock, flags);
 670
 671        switch (type) {
 672        case IOC4_SIO_INTR_TYPE:
 673                switch (which) {
 674                case IOC4_W_IES:
 675                        writel(val, &mem->sio_ies.raw);
 676                        break;
 677
 678                case IOC4_W_IEC:
 679                        writel(val, &mem->sio_iec.raw);
 680                        break;
 681                }
 682                break;
 683
 684        case IOC4_OTHER_INTR_TYPE:
 685                switch (which) {
 686                case IOC4_W_IES:
 687                        writel(val, &mem->other_ies.raw);
 688                        break;
 689
 690                case IOC4_W_IEC:
 691                        writel(val, &mem->other_iec.raw);
 692                        break;
 693                }
 694                break;
 695
 696        default:
 697                break;
 698        }
 699        spin_unlock_irqrestore(&ioc4_soft->is_ir_lock, flags);
 700}
 701
 702/**
 703 * set_baud - Baud rate setting code
 704 * @port: port to set
 705 * @baud: baud rate to use
 706 */
 707static int set_baud(struct ioc4_port *port, int baud)
 708{
 709        int actual_baud;
 710        int diff;
 711        int lcr;
 712        unsigned short divisor;
 713        struct ioc4_uartregs __iomem *uart;
 714
 715        divisor = SER_DIVISOR(baud, port->ip_pci_bus_speed);
 716        if (!divisor)
 717                return 1;
 718        actual_baud = DIVISOR_TO_BAUD(divisor, port->ip_pci_bus_speed);
 719
 720        diff = actual_baud - baud;
 721        if (diff < 0)
 722                diff = -diff;
 723
 724        /* If we're within 1%, we've found a match */
 725        if (diff * 100 > actual_baud)
 726                return 1;
 727
 728        uart = port->ip_uart_regs;
 729        lcr = readb(&uart->i4u_lcr);
 730        writeb(lcr | UART_LCR_DLAB, &uart->i4u_lcr);
 731        writeb((unsigned char)divisor, &uart->i4u_dll);
 732        writeb((unsigned char)(divisor >> 8), &uart->i4u_dlm);
 733        writeb(lcr, &uart->i4u_lcr);
 734        return 0;
 735}
 736
 737
 738/**
 739 * get_ioc4_port - given a uart port, return the control structure
 740 * @port: uart port
 741 * @set: set this port as current
 742 */
 743static struct ioc4_port *get_ioc4_port(struct uart_port *the_port, int set)
 744{
 745        struct ioc4_driver_data *idd = dev_get_drvdata(the_port->dev);
 746        struct ioc4_control *control = idd->idd_serial_data;
 747        struct ioc4_port *port;
 748        int port_num, port_type;
 749
 750        if (control) {
 751                for ( port_num = 0; port_num < IOC4_NUM_SERIAL_PORTS;
 752                                                        port_num++ ) {
 753                        port = control->ic_port[port_num].icp_port;
 754                        if (!port)
 755                                continue;
 756                        for (port_type = UART_PORT_MIN;
 757                                                port_type < UART_PORT_COUNT;
 758                                                port_type++) {
 759                                if (the_port == port->ip_all_ports
 760                                                        [port_type]) {
 761                                        /* set local copy */
 762                                        if (set) {
 763                                                port->ip_port = the_port;
 764                                        }
 765                                        return port;
 766                                }
 767                        }
 768                }
 769        }
 770        return NULL;
 771}
 772
 773/* The IOC4 hardware provides no atomic way to determine if interrupts
 774 * are pending since two reads are required to do so.  The handler must
 775 * read the SIO_IR and the SIO_IES, and take the logical and of the
 776 * two.  When this value is zero, all interrupts have been serviced and
 777 * the handler may return.
 778 *
 779 * This has the unfortunate "hole" that, if some other CPU or
 780 * some other thread or some higher level interrupt manages to
 781 * modify SIO_IE between our reads of SIO_IR and SIO_IE, we may
 782 * think we have observed SIO_IR&SIO_IE==0 when in fact this
 783 * condition never really occurred.
 784 *
 785 * To solve this, we use a simple spinlock that must be held
 786 * whenever modifying SIO_IE; holding this lock while observing
 787 * both SIO_IR and SIO_IE guarantees that we do not falsely
 788 * conclude that no enabled interrupts are pending.
 789 */
 790
 791static inline uint32_t
 792pending_intrs(struct ioc4_soft *soft, int type)
 793{
 794        struct ioc4_misc_regs __iomem *mem = soft->is_ioc4_misc_addr;
 795        unsigned long flag;
 796        uint32_t intrs = 0;
 797
 798        BUG_ON(!((type == IOC4_SIO_INTR_TYPE)
 799               || (type == IOC4_OTHER_INTR_TYPE)));
 800
 801        spin_lock_irqsave(&soft->is_ir_lock, flag);
 802
 803        switch (type) {
 804        case IOC4_SIO_INTR_TYPE:
 805                intrs = readl(&mem->sio_ir.raw) & readl(&mem->sio_ies.raw);
 806                break;
 807
 808        case IOC4_OTHER_INTR_TYPE:
 809                intrs = readl(&mem->other_ir.raw) & readl(&mem->other_ies.raw);
 810
 811                /* Don't process any ATA interrupte */
 812                intrs &= ~(IOC4_OTHER_IR_ATA_INT | IOC4_OTHER_IR_ATA_MEMERR);
 813                break;
 814
 815        default:
 816                break;
 817        }
 818        spin_unlock_irqrestore(&soft->is_ir_lock, flag);
 819        return intrs;
 820}
 821
 822/**
 823 * port_init - Initialize the sio and ioc4 hardware for a given port
 824 *                      called per port from attach...
 825 * @port: port to initialize
 826 */
 827static int inline port_init(struct ioc4_port *port)
 828{
 829        uint32_t sio_cr;
 830        struct hooks *hooks = port->ip_hooks;
 831        struct ioc4_uartregs __iomem *uart;
 832
 833        /* Idle the IOC4 serial interface */
 834        writel(IOC4_SSCR_RESET, &port->ip_serial_regs->sscr);
 835
 836        /* Wait until any pending bus activity for this port has ceased */
 837        do
 838                sio_cr = readl(&port->ip_mem->sio_cr.raw);
 839        while (!(sio_cr & IOC4_SIO_CR_SIO_DIAG_IDLE));
 840
 841        /* Finish reset sequence */
 842        writel(0, &port->ip_serial_regs->sscr);
 843
 844        /* Once RESET is done, reload cached tx_prod and rx_cons values
 845         * and set rings to empty by making prod == cons
 846         */
 847        port->ip_tx_prod = readl(&port->ip_serial_regs->stcir) & PROD_CONS_MASK;
 848        writel(port->ip_tx_prod, &port->ip_serial_regs->stpir);
 849        port->ip_rx_cons = readl(&port->ip_serial_regs->srpir) & PROD_CONS_MASK;
 850        writel(port->ip_rx_cons | IOC4_SRCIR_ARM, &port->ip_serial_regs->srcir);
 851
 852        /* Disable interrupts for this 16550 */
 853        uart = port->ip_uart_regs;
 854        writeb(0, &uart->i4u_lcr);
 855        writeb(0, &uart->i4u_ier);
 856
 857        /* Set the default baud */
 858        set_baud(port, port->ip_baud);
 859
 860        /* Set line control to 8 bits no parity */
 861        writeb(UART_LCR_WLEN8 | 0, &uart->i4u_lcr);
 862                                        /* UART_LCR_STOP == 1 stop */
 863
 864        /* Enable the FIFOs */
 865        writeb(UART_FCR_ENABLE_FIFO, &uart->i4u_fcr);
 866        /* then reset 16550 FIFOs */
 867        writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
 868                        &uart->i4u_fcr);
 869
 870        /* Clear modem control register */
 871        writeb(0, &uart->i4u_mcr);
 872
 873        /* Clear deltas in modem status register */
 874        readb(&uart->i4u_msr);
 875
 876        /* Only do this once per port pair */
 877        if (port->ip_hooks == &hooks_array[0]
 878                            || port->ip_hooks == &hooks_array[2]) {
 879                unsigned long ring_pci_addr;
 880                uint32_t __iomem *sbbr_l;
 881                uint32_t __iomem *sbbr_h;
 882
 883                if (port->ip_hooks == &hooks_array[0]) {
 884                        sbbr_l = &port->ip_serial->sbbr01_l;
 885                        sbbr_h = &port->ip_serial->sbbr01_h;
 886                } else {
 887                        sbbr_l = &port->ip_serial->sbbr23_l;
 888                        sbbr_h = &port->ip_serial->sbbr23_h;
 889                }
 890
 891                ring_pci_addr = (unsigned long __iomem)port->ip_dma_ringbuf;
 892                DPRINT_CONFIG(("%s: ring_pci_addr 0x%lx\n",
 893                                        __func__, ring_pci_addr));
 894
 895                writel((unsigned int)((uint64_t)ring_pci_addr >> 32), sbbr_h);
 896                writel((unsigned int)ring_pci_addr | IOC4_BUF_SIZE_BIT, sbbr_l);
 897        }
 898
 899        /* Set the receive timeout value to 10 msec */
 900        writel(IOC4_SRTR_HZ / 100, &port->ip_serial_regs->srtr);
 901
 902        /* Set rx threshold, enable DMA */
 903        /* Set high water mark at 3/4 of full ring */
 904        port->ip_sscr = (ENTRIES_PER_RING * 3 / 4);
 905        writel(port->ip_sscr, &port->ip_serial_regs->sscr);
 906
 907        /* Disable and clear all serial related interrupt bits */
 908        write_ireg(port->ip_ioc4_soft, hooks->intr_clear,
 909                       IOC4_W_IEC, IOC4_SIO_INTR_TYPE);
 910        port->ip_ienb &= ~hooks->intr_clear;
 911        writel(hooks->intr_clear, &port->ip_mem->sio_ir.raw);
 912        return 0;
 913}
 914
 915/**
 916 * handle_dma_error_intr - service any pending DMA error interrupts for the
 917 *                      given port - 2nd level called via sd_intr
 918 * @arg: handler arg
 919 * @other_ir: ioc4regs
 920 */
 921static void handle_dma_error_intr(void *arg, uint32_t other_ir)
 922{
 923        struct ioc4_port *port = (struct ioc4_port *)arg;
 924        struct hooks *hooks = port->ip_hooks;
 925        unsigned long flags;
 926
 927        spin_lock_irqsave(&port->ip_lock, flags);
 928
 929        /* ACK the interrupt */
 930        writel(hooks->intr_dma_error, &port->ip_mem->other_ir.raw);
 931
 932        if (readl(&port->ip_mem->pci_err_addr_l.raw) & IOC4_PCI_ERR_ADDR_VLD) {
 933                printk(KERN_ERR
 934                        "PCI error address is 0x%llx, "
 935                                "master is serial port %c %s\n",
 936                     (((uint64_t)readl(&port->ip_mem->pci_err_addr_h)
 937                                                         << 32)
 938                                | readl(&port->ip_mem->pci_err_addr_l.raw))
 939                                        & IOC4_PCI_ERR_ADDR_ADDR_MSK, '1' +
 940                     ((char)(readl(&port->ip_mem->pci_err_addr_l.raw) &
 941                             IOC4_PCI_ERR_ADDR_MST_NUM_MSK) >> 1),
 942                     (readl(&port->ip_mem->pci_err_addr_l.raw)
 943                                & IOC4_PCI_ERR_ADDR_MST_TYP_MSK)
 944                                ? "RX" : "TX");
 945
 946                if (readl(&port->ip_mem->pci_err_addr_l.raw)
 947                                                & IOC4_PCI_ERR_ADDR_MUL_ERR) {
 948                        printk(KERN_ERR
 949                                "Multiple errors occurred\n");
 950                }
 951        }
 952        spin_unlock_irqrestore(&port->ip_lock, flags);
 953
 954        /* Re-enable DMA error interrupts */
 955        write_ireg(port->ip_ioc4_soft, hooks->intr_dma_error, IOC4_W_IES,
 956                                                IOC4_OTHER_INTR_TYPE);
 957}
 958
 959/**
 960 * intr_connect - interrupt connect function
 961 * @soft: soft struct for this card
 962 * @type: interrupt type
 963 * @intrbits: bit pattern to set
 964 * @intr: handler function
 965 * @info: handler arg
 966 */
 967static void
 968intr_connect(struct ioc4_soft *soft, int type,
 969                  uint32_t intrbits, ioc4_intr_func_f * intr, void *info)
 970{
 971        int i;
 972        struct ioc4_intr_info *intr_ptr;
 973
 974        BUG_ON(!((type == IOC4_SIO_INTR_TYPE)
 975               || (type == IOC4_OTHER_INTR_TYPE)));
 976
 977        i = atomic_inc_return(&soft-> is_intr_type[type].is_num_intrs) - 1;
 978        BUG_ON(!(i < MAX_IOC4_INTR_ENTS || (printk("i %d\n", i), 0)));
 979
 980        /* Save off the lower level interrupt handler */
 981        intr_ptr = &soft->is_intr_type[type].is_intr_info[i];
 982        intr_ptr->sd_bits = intrbits;
 983        intr_ptr->sd_intr = intr;
 984        intr_ptr->sd_info = info;
 985}
 986
 987/**
 988 * ioc4_intr - Top level IOC4 interrupt handler.
 989 * @irq: irq value
 990 * @arg: handler arg
 991 */
 992
 993static irqreturn_t ioc4_intr(int irq, void *arg)
 994{
 995        struct ioc4_soft *soft;
 996        uint32_t this_ir, this_mir;
 997        int xx, num_intrs = 0;
 998        int intr_type;
 999        int handled = 0;
1000        struct ioc4_intr_info *intr_info;
1001
1002        soft = arg;
1003        for (intr_type = 0; intr_type < IOC4_NUM_INTR_TYPES; intr_type++) {
1004                num_intrs = (int)atomic_read(
1005                                &soft->is_intr_type[intr_type].is_num_intrs);
1006
1007                this_mir = this_ir = pending_intrs(soft, intr_type);
1008
1009                /* Farm out the interrupt to the various drivers depending on
1010                 * which interrupt bits are set.
1011                 */
1012                for (xx = 0; xx < num_intrs; xx++) {
1013                        intr_info = &soft->is_intr_type[intr_type].is_intr_info[xx];
1014                        if ((this_mir = this_ir & intr_info->sd_bits)) {
1015                                /* Disable owned interrupts, call handler */
1016                                handled++;
1017                                write_ireg(soft, intr_info->sd_bits, IOC4_W_IEC,
1018                                                                intr_type);
1019                                intr_info->sd_intr(intr_info->sd_info, this_mir);
1020                                this_ir &= ~this_mir;
1021                        }
1022                }
1023        }
1024#ifdef DEBUG_INTERRUPTS
1025        {
1026                struct ioc4_misc_regs __iomem *mem = soft->is_ioc4_misc_addr;
1027                unsigned long flag;
1028
1029                spin_lock_irqsave(&soft->is_ir_lock, flag);
1030                printk ("%s : %d : mem 0x%p sio_ir 0x%x sio_ies 0x%x "
1031                                "other_ir 0x%x other_ies 0x%x mask 0x%x\n",
1032                     __func__, __LINE__,
1033                     (void *)mem, readl(&mem->sio_ir.raw),
1034                     readl(&mem->sio_ies.raw),
1035                     readl(&mem->other_ir.raw),
1036                     readl(&mem->other_ies.raw),
1037                     IOC4_OTHER_IR_ATA_INT | IOC4_OTHER_IR_ATA_MEMERR);
1038                spin_unlock_irqrestore(&soft->is_ir_lock, flag);
1039        }
1040#endif
1041        return handled ? IRQ_HANDLED : IRQ_NONE;
1042}
1043
1044/**
1045 * ioc4_attach_local - Device initialization.
1046 *                      Called at *_attach() time for each
1047 *                      IOC4 with serial ports in the system.
1048 * @idd: Master module data for this IOC4
1049 */
1050static int inline ioc4_attach_local(struct ioc4_driver_data *idd)
1051{
1052        struct ioc4_port *port;
1053        struct ioc4_port *ports[IOC4_NUM_SERIAL_PORTS];
1054        int port_number;
1055        uint16_t ioc4_revid_min = 62;
1056        uint16_t ioc4_revid;
1057        struct pci_dev *pdev = idd->idd_pdev;
1058        struct ioc4_control* control = idd->idd_serial_data;
1059        struct ioc4_soft *soft = control->ic_soft;
1060        void __iomem *ioc4_misc = idd->idd_misc_regs;
1061        void __iomem *ioc4_serial = soft->is_ioc4_serial_addr;
1062
1063        /* IOC4 firmware must be at least rev 62 */
1064        pci_read_config_word(pdev, PCI_COMMAND_SPECIAL, &ioc4_revid);
1065
1066        printk(KERN_INFO "IOC4 firmware revision %d\n", ioc4_revid);
1067        if (ioc4_revid < ioc4_revid_min) {
1068                printk(KERN_WARNING
1069                    "IOC4 serial not supported on firmware rev %d, "
1070                                "please upgrade to rev %d or higher\n",
1071                                ioc4_revid, ioc4_revid_min);
1072                return -EPERM;
1073        }
1074        BUG_ON(ioc4_misc == NULL);
1075        BUG_ON(ioc4_serial == NULL);
1076
1077        /* Create port structures for each port */
1078        for (port_number = 0; port_number < IOC4_NUM_SERIAL_PORTS;
1079                                                        port_number++) {
1080                port = kzalloc(sizeof(struct ioc4_port), GFP_KERNEL);
1081                if (!port) {
1082                        printk(KERN_WARNING
1083                                "IOC4 serial memory not available for port\n");
1084                        return -ENOMEM;
1085                }
1086                spin_lock_init(&port->ip_lock);
1087
1088                /* we need to remember the previous ones, to point back to
1089                 * them farther down - setting up the ring buffers.
1090                 */
1091                ports[port_number] = port;
1092
1093                /* Allocate buffers and jumpstart the hardware.  */
1094                control->ic_port[port_number].icp_port = port;
1095                port->ip_ioc4_soft = soft;
1096                port->ip_pdev = pdev;
1097                port->ip_ienb = 0;
1098                /* Use baud rate calculations based on detected PCI
1099                 * bus speed.  Simply test whether the PCI clock is
1100                 * running closer to 66MHz or 33MHz.
1101                 */
1102                if (idd->count_period/IOC4_EXTINT_COUNT_DIVISOR < 20) {
1103                        port->ip_pci_bus_speed = IOC4_SER_XIN_CLK_66;
1104                } else {
1105                        port->ip_pci_bus_speed = IOC4_SER_XIN_CLK_33;
1106                }
1107                port->ip_baud = 9600;
1108                port->ip_control = control;
1109                port->ip_mem = ioc4_misc;
1110                port->ip_serial = ioc4_serial;
1111
1112                /* point to the right hook */
1113                port->ip_hooks = &hooks_array[port_number];
1114
1115                /* Get direct hooks to the serial regs and uart regs
1116                 * for this port
1117                 */
1118                switch (port_number) {
1119                case 0:
1120                        port->ip_serial_regs = &(port->ip_serial->port_0);
1121                        port->ip_uart_regs = &(port->ip_serial->uart_0);
1122                        break;
1123                case 1:
1124                        port->ip_serial_regs = &(port->ip_serial->port_1);
1125                        port->ip_uart_regs = &(port->ip_serial->uart_1);
1126                        break;
1127                case 2:
1128                        port->ip_serial_regs = &(port->ip_serial->port_2);
1129                        port->ip_uart_regs = &(port->ip_serial->uart_2);
1130                        break;
1131                default:
1132                case 3:
1133                        port->ip_serial_regs = &(port->ip_serial->port_3);
1134                        port->ip_uart_regs = &(port->ip_serial->uart_3);
1135                        break;
1136                }
1137
1138                /* ring buffers are 1 to a pair of ports */
1139                if (port_number && (port_number & 1)) {
1140                        /* odd use the evens buffer */
1141                        port->ip_dma_ringbuf =
1142                                        ports[port_number - 1]->ip_dma_ringbuf;
1143                        port->ip_cpu_ringbuf =
1144                                        ports[port_number - 1]->ip_cpu_ringbuf;
1145                        port->ip_inring = RING(port, RX_1_OR_3);
1146                        port->ip_outring = RING(port, TX_1_OR_3);
1147
1148                } else {
1149                        if (port->ip_dma_ringbuf == 0) {
1150                                port->ip_cpu_ringbuf = pci_alloc_consistent
1151                                        (pdev, TOTAL_RING_BUF_SIZE,
1152                                        &port->ip_dma_ringbuf);
1153
1154                        }
1155                        BUG_ON(!((((int64_t)port->ip_dma_ringbuf) &
1156                                (TOTAL_RING_BUF_SIZE - 1)) == 0));
1157                        DPRINT_CONFIG(("%s : ip_cpu_ringbuf 0x%p "
1158                                                "ip_dma_ringbuf 0x%p\n",
1159                                        __func__,
1160                                        (void *)port->ip_cpu_ringbuf,
1161                                        (void *)port->ip_dma_ringbuf));
1162                        port->ip_inring = RING(port, RX_0_OR_2);
1163                        port->ip_outring = RING(port, TX_0_OR_2);
1164                }
1165                DPRINT_CONFIG(("%s : port %d [addr 0x%p] control 0x%p",
1166                                __func__,
1167                                port_number, (void *)port, (void *)control));
1168                DPRINT_CONFIG((" ip_serial_regs 0x%p ip_uart_regs 0x%p\n",
1169                                (void *)port->ip_serial_regs,
1170                                (void *)port->ip_uart_regs));
1171
1172                /* Initialize the hardware for IOC4 */
1173                port_init(port);
1174
1175                DPRINT_CONFIG(("%s: port_number %d port 0x%p inring 0x%p "
1176                                                "outring 0x%p\n",
1177                                __func__,
1178                                port_number, (void *)port,
1179                                (void *)port->ip_inring,
1180                                (void *)port->ip_outring));
1181
1182                /* Attach interrupt handlers */
1183                intr_connect(soft, IOC4_SIO_INTR_TYPE,
1184                                GET_SIO_IR(port_number),
1185                                handle_intr, port);
1186
1187                intr_connect(soft, IOC4_OTHER_INTR_TYPE,
1188                                GET_OTHER_IR(port_number),
1189                                handle_dma_error_intr, port);
1190        }
1191        return 0;
1192}
1193
1194/**
1195 * enable_intrs - enable interrupts
1196 * @port: port to enable
1197 * @mask: mask to use
1198 */
1199static void enable_intrs(struct ioc4_port *port, uint32_t mask)
1200{
1201        struct hooks *hooks = port->ip_hooks;
1202
1203        if ((port->ip_ienb & mask) != mask) {
1204                write_ireg(port->ip_ioc4_soft, mask, IOC4_W_IES,
1205                                                IOC4_SIO_INTR_TYPE);
1206                port->ip_ienb |= mask;
1207        }
1208
1209        if (port->ip_ienb)
1210                write_ireg(port->ip_ioc4_soft, hooks->intr_dma_error,
1211                                IOC4_W_IES, IOC4_OTHER_INTR_TYPE);
1212}
1213
1214/**
1215 * local_open - local open a port
1216 * @port: port to open
1217 */
1218static inline int local_open(struct ioc4_port *port)
1219{
1220        int spiniter = 0;
1221
1222        port->ip_flags = PORT_ACTIVE;
1223
1224        /* Pause the DMA interface if necessary */
1225        if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1226                writel(port->ip_sscr | IOC4_SSCR_DMA_PAUSE,
1227                        &port->ip_serial_regs->sscr);
1228                while((readl(&port->ip_serial_regs-> sscr)
1229                                & IOC4_SSCR_PAUSE_STATE) == 0) {
1230                        spiniter++;
1231                        if (spiniter > MAXITER) {
1232                                port->ip_flags = PORT_INACTIVE;
1233                                return -1;
1234                        }
1235                }
1236        }
1237
1238        /* Reset the input fifo.  If the uart received chars while the port
1239         * was closed and DMA is not enabled, the uart may have a bunch of
1240         * chars hanging around in its rx fifo which will not be discarded
1241         * by rclr in the upper layer. We must get rid of them here.
1242         */
1243        writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR,
1244                                &port->ip_uart_regs->i4u_fcr);
1245
1246        writeb(UART_LCR_WLEN8, &port->ip_uart_regs->i4u_lcr);
1247                                        /* UART_LCR_STOP == 1 stop */
1248
1249        /* Re-enable DMA, set default threshold to intr whenever there is
1250         * data available.
1251         */
1252        port->ip_sscr &= ~IOC4_SSCR_RX_THRESHOLD;
1253        port->ip_sscr |= 1;     /* default threshold */
1254
1255        /* Plug in the new sscr.  This implicitly clears the DMA_PAUSE
1256         * flag if it was set above
1257         */
1258        writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1259        port->ip_tx_lowat = 1;
1260        return 0;
1261}
1262
1263/**
1264 * set_rx_timeout - Set rx timeout and threshold values.
1265 * @port: port to use
1266 * @timeout: timeout value in ticks
1267 */
1268static inline int set_rx_timeout(struct ioc4_port *port, int timeout)
1269{
1270        int threshold;
1271
1272        port->ip_rx_timeout = timeout;
1273
1274        /* Timeout is in ticks.  Let's figure out how many chars we
1275         * can receive at the current baud rate in that interval
1276         * and set the rx threshold to that amount.  There are 4 chars
1277         * per ring entry, so we'll divide the number of chars that will
1278         * arrive in timeout by 4.
1279         * So .... timeout * baud / 10 / HZ / 4, with HZ = 100.
1280         */
1281        threshold = timeout * port->ip_baud / 4000;
1282        if (threshold == 0)
1283                threshold = 1;  /* otherwise we'll intr all the time! */
1284
1285        if ((unsigned)threshold > (unsigned)IOC4_SSCR_RX_THRESHOLD)
1286                return 1;
1287
1288        port->ip_sscr &= ~IOC4_SSCR_RX_THRESHOLD;
1289        port->ip_sscr |= threshold;
1290
1291        writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1292
1293        /* Now set the rx timeout to the given value
1294         * again timeout * IOC4_SRTR_HZ / HZ
1295         */
1296        timeout = timeout * IOC4_SRTR_HZ / 100;
1297        if (timeout > IOC4_SRTR_CNT)
1298                timeout = IOC4_SRTR_CNT;
1299
1300        writel(timeout, &port->ip_serial_regs->srtr);
1301        return 0;
1302}
1303
1304/**
1305 * config_port - config the hardware
1306 * @port: port to config
1307 * @baud: baud rate for the port
1308 * @byte_size: data size
1309 * @stop_bits: number of stop bits
1310 * @parenb: parity enable ?
1311 * @parodd: odd parity ?
1312 */
1313static inline int
1314config_port(struct ioc4_port *port,
1315            int baud, int byte_size, int stop_bits, int parenb, int parodd)
1316{
1317        char lcr, sizebits;
1318        int spiniter = 0;
1319
1320        DPRINT_CONFIG(("%s: baud %d byte_size %d stop %d parenb %d parodd %d\n",
1321                __func__, baud, byte_size, stop_bits, parenb, parodd));
1322
1323        if (set_baud(port, baud))
1324                return 1;
1325
1326        switch (byte_size) {
1327        case 5:
1328                sizebits = UART_LCR_WLEN5;
1329                break;
1330        case 6:
1331                sizebits = UART_LCR_WLEN6;
1332                break;
1333        case 7:
1334                sizebits = UART_LCR_WLEN7;
1335                break;
1336        case 8:
1337                sizebits = UART_LCR_WLEN8;
1338                break;
1339        default:
1340                return 1;
1341        }
1342
1343        /* Pause the DMA interface if necessary */
1344        if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1345                writel(port->ip_sscr | IOC4_SSCR_DMA_PAUSE,
1346                        &port->ip_serial_regs->sscr);
1347                while((readl(&port->ip_serial_regs->sscr)
1348                                                & IOC4_SSCR_PAUSE_STATE) == 0) {
1349                        spiniter++;
1350                        if (spiniter > MAXITER)
1351                                return -1;
1352                }
1353        }
1354
1355        /* Clear relevant fields in lcr */
1356        lcr = readb(&port->ip_uart_regs->i4u_lcr);
1357        lcr &= ~(LCR_MASK_BITS_CHAR | UART_LCR_EPAR |
1358                 UART_LCR_PARITY | LCR_MASK_STOP_BITS);
1359
1360        /* Set byte size in lcr */
1361        lcr |= sizebits;
1362
1363        /* Set parity */
1364        if (parenb) {
1365                lcr |= UART_LCR_PARITY;
1366                if (!parodd)
1367                        lcr |= UART_LCR_EPAR;
1368        }
1369
1370        /* Set stop bits */
1371        if (stop_bits)
1372                lcr |= UART_LCR_STOP /* 2 stop bits */ ;
1373
1374        writeb(lcr, &port->ip_uart_regs->i4u_lcr);
1375
1376        /* Re-enable the DMA interface if necessary */
1377        if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1378                writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1379        }
1380        port->ip_baud = baud;
1381
1382        /* When we get within this number of ring entries of filling the
1383         * entire ring on tx, place an EXPLICIT intr to generate a lowat
1384         * notification when output has drained.
1385         */
1386        port->ip_tx_lowat = (TX_LOWAT_CHARS(baud) + 3) / 4;
1387        if (port->ip_tx_lowat == 0)
1388                port->ip_tx_lowat = 1;
1389
1390        set_rx_timeout(port, 2);
1391
1392        return 0;
1393}
1394
1395/**
1396 * do_write - Write bytes to the port.  Returns the number of bytes
1397 *                      actually written. Called from transmit_chars
1398 * @port: port to use
1399 * @buf: the stuff to write
1400 * @len: how many bytes in 'buf'
1401 */
1402static inline int do_write(struct ioc4_port *port, char *buf, int len)
1403{
1404        int prod_ptr, cons_ptr, total = 0;
1405        struct ring *outring;
1406        struct ring_entry *entry;
1407        struct hooks *hooks = port->ip_hooks;
1408
1409        BUG_ON(!(len >= 0));
1410
1411        prod_ptr = port->ip_tx_prod;
1412        cons_ptr = readl(&port->ip_serial_regs->stcir) & PROD_CONS_MASK;
1413        outring = port->ip_outring;
1414
1415        /* Maintain a 1-entry red-zone.  The ring buffer is full when
1416         * (cons - prod) % ring_size is 1.  Rather than do this subtraction
1417         * in the body of the loop, I'll do it now.
1418         */
1419        cons_ptr = (cons_ptr - (int)sizeof(struct ring_entry)) & PROD_CONS_MASK;
1420
1421        /* Stuff the bytes into the output */
1422        while ((prod_ptr != cons_ptr) && (len > 0)) {
1423                int xx;
1424
1425                /* Get 4 bytes (one ring entry) at a time */
1426                entry = (struct ring_entry *)((caddr_t) outring + prod_ptr);
1427
1428                /* Invalidate all entries */
1429                entry->ring_allsc = 0;
1430
1431                /* Copy in some bytes */
1432                for (xx = 0; (xx < 4) && (len > 0); xx++) {
1433                        entry->ring_data[xx] = *buf++;
1434                        entry->ring_sc[xx] = IOC4_TXCB_VALID;
1435                        len--;
1436                        total++;
1437                }
1438
1439                /* If we are within some small threshold of filling up the
1440                 * entire ring buffer, we must place an EXPLICIT intr here
1441                 * to generate a lowat interrupt in case we subsequently
1442                 * really do fill up the ring and the caller goes to sleep.
1443                 * No need to place more than one though.
1444                 */
1445                if (!(port->ip_flags & LOWAT_WRITTEN) &&
1446                        ((cons_ptr - prod_ptr) & PROD_CONS_MASK)
1447                                <= port->ip_tx_lowat
1448                                        * (int)sizeof(struct ring_entry)) {
1449                        port->ip_flags |= LOWAT_WRITTEN;
1450                        entry->ring_sc[0] |= IOC4_TXCB_INT_WHEN_DONE;
1451                }
1452
1453                /* Go on to next entry */
1454                prod_ptr += sizeof(struct ring_entry);
1455                prod_ptr &= PROD_CONS_MASK;
1456        }
1457
1458        /* If we sent something, start DMA if necessary */
1459        if (total > 0 && !(port->ip_sscr & IOC4_SSCR_DMA_EN)) {
1460                port->ip_sscr |= IOC4_SSCR_DMA_EN;
1461                writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1462        }
1463
1464        /* Store the new producer pointer.  If tx is disabled, we stuff the
1465         * data into the ring buffer, but we don't actually start tx.
1466         */
1467        if (!uart_tx_stopped(port->ip_port)) {
1468                writel(prod_ptr, &port->ip_serial_regs->stpir);
1469
1470                /* If we are now transmitting, enable tx_mt interrupt so we
1471                 * can disable DMA if necessary when the tx finishes.
1472                 */
1473                if (total > 0)
1474                        enable_intrs(port, hooks->intr_tx_mt);
1475        }
1476        port->ip_tx_prod = prod_ptr;
1477        return total;
1478}
1479
1480/**
1481 * disable_intrs - disable interrupts
1482 * @port: port to enable
1483 * @mask: mask to use
1484 */
1485static void disable_intrs(struct ioc4_port *port, uint32_t mask)
1486{
1487        struct hooks *hooks = port->ip_hooks;
1488
1489        if (port->ip_ienb & mask) {
1490                write_ireg(port->ip_ioc4_soft, mask, IOC4_W_IEC,
1491                                        IOC4_SIO_INTR_TYPE);
1492                port->ip_ienb &= ~mask;
1493        }
1494
1495        if (!port->ip_ienb)
1496                write_ireg(port->ip_ioc4_soft, hooks->intr_dma_error,
1497                                IOC4_W_IEC, IOC4_OTHER_INTR_TYPE);
1498}
1499
1500/**
1501 * set_notification - Modify event notification
1502 * @port: port to use
1503 * @mask: events mask
1504 * @set_on: set ?
1505 */
1506static int set_notification(struct ioc4_port *port, int mask, int set_on)
1507{
1508        struct hooks *hooks = port->ip_hooks;
1509        uint32_t intrbits, sscrbits;
1510
1511        BUG_ON(!mask);
1512
1513        intrbits = sscrbits = 0;
1514
1515        if (mask & N_DATA_READY)
1516                intrbits |= (hooks->intr_rx_timer | hooks->intr_rx_high);
1517        if (mask & N_OUTPUT_LOWAT)
1518                intrbits |= hooks->intr_tx_explicit;
1519        if (mask & N_DDCD) {
1520                intrbits |= hooks->intr_delta_dcd;
1521                sscrbits |= IOC4_SSCR_RX_RING_DCD;
1522        }
1523        if (mask & N_DCTS)
1524                intrbits |= hooks->intr_delta_cts;
1525
1526        if (set_on) {
1527                enable_intrs(port, intrbits);
1528                port->ip_notify |= mask;
1529                port->ip_sscr |= sscrbits;
1530        } else {
1531                disable_intrs(port, intrbits);
1532                port->ip_notify &= ~mask;
1533                port->ip_sscr &= ~sscrbits;
1534        }
1535
1536        /* We require DMA if either DATA_READY or DDCD notification is
1537         * currently requested. If neither of these is requested and
1538         * there is currently no tx in progress, DMA may be disabled.
1539         */
1540        if (port->ip_notify & (N_DATA_READY | N_DDCD))
1541                port->ip_sscr |= IOC4_SSCR_DMA_EN;
1542        else if (!(port->ip_ienb & hooks->intr_tx_mt))
1543                port->ip_sscr &= ~IOC4_SSCR_DMA_EN;
1544
1545        writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1546        return 0;
1547}
1548
1549/**
1550 * set_mcr - set the master control reg
1551 * @the_port: port to use
1552 * @mask1: mcr mask
1553 * @mask2: shadow mask
1554 */
1555static inline int set_mcr(struct uart_port *the_port,
1556                int mask1, int mask2)
1557{
1558        struct ioc4_port *port = get_ioc4_port(the_port, 0);
1559        uint32_t shadow;
1560        int spiniter = 0;
1561        char mcr;
1562
1563        if (!port)
1564                return -1;
1565
1566        /* Pause the DMA interface if necessary */
1567        if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1568                writel(port->ip_sscr | IOC4_SSCR_DMA_PAUSE,
1569                        &port->ip_serial_regs->sscr);
1570                while ((readl(&port->ip_serial_regs->sscr)
1571                                        & IOC4_SSCR_PAUSE_STATE) == 0) {
1572                        spiniter++;
1573                        if (spiniter > MAXITER)
1574                                return -1;
1575                }
1576        }
1577        shadow = readl(&port->ip_serial_regs->shadow);
1578        mcr = (shadow & 0xff000000) >> 24;
1579
1580        /* Set new value */
1581        mcr |= mask1;
1582        shadow |= mask2;
1583
1584        writeb(mcr, &port->ip_uart_regs->i4u_mcr);
1585        writel(shadow, &port->ip_serial_regs->shadow);
1586
1587        /* Re-enable the DMA interface if necessary */
1588        if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1589                writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1590        }
1591        return 0;
1592}
1593
1594/**
1595 * ioc4_set_proto - set the protocol for the port
1596 * @port: port to use
1597 * @proto: protocol to use
1598 */
1599static int ioc4_set_proto(struct ioc4_port *port, int proto)
1600{
1601        struct hooks *hooks = port->ip_hooks;
1602
1603        switch (proto) {
1604        case PROTO_RS232:
1605                /* Clear the appropriate GIO pin */
1606                writel(0, (&port->ip_mem->gppr[hooks->rs422_select_pin].raw));
1607                break;
1608
1609        case PROTO_RS422:
1610                /* Set the appropriate GIO pin */
1611                writel(1, (&port->ip_mem->gppr[hooks->rs422_select_pin].raw));
1612                break;
1613
1614        default:
1615                return 1;
1616        }
1617        return 0;
1618}
1619
1620/**
1621 * transmit_chars - upper level write, called with ip_lock
1622 * @the_port: port to write
1623 */
1624static void transmit_chars(struct uart_port *the_port)
1625{
1626        int xmit_count, tail, head;
1627        int result;
1628        char *start;
1629        struct tty_struct *tty;
1630        struct ioc4_port *port = get_ioc4_port(the_port, 0);
1631        struct uart_state *state;
1632
1633        if (!the_port)
1634                return;
1635        if (!port)
1636                return;
1637
1638        state = the_port->state;
1639        tty = state->port.tty;
1640
1641        if (uart_circ_empty(&state->xmit) || uart_tx_stopped(the_port)) {
1642                /* Nothing to do or hw stopped */
1643                set_notification(port, N_ALL_OUTPUT, 0);
1644                return;
1645        }
1646
1647        head = state->xmit.head;
1648        tail = state->xmit.tail;
1649        start = (char *)&state->xmit.buf[tail];
1650
1651        /* write out all the data or until the end of the buffer */
1652        xmit_count = (head < tail) ? (UART_XMIT_SIZE - tail) : (head - tail);
1653        if (xmit_count > 0) {
1654                result = do_write(port, start, xmit_count);
1655                if (result > 0) {
1656                        /* booking */
1657                        xmit_count -= result;
1658                        the_port->icount.tx += result;
1659                        /* advance the pointers */
1660                        tail += result;
1661                        tail &= UART_XMIT_SIZE - 1;
1662                        state->xmit.tail = tail;
1663                        start = (char *)&state->xmit.buf[tail];
1664                }
1665        }
1666        if (uart_circ_chars_pending(&state->xmit) < WAKEUP_CHARS)
1667                uart_write_wakeup(the_port);
1668
1669        if (uart_circ_empty(&state->xmit)) {
1670                set_notification(port, N_OUTPUT_LOWAT, 0);
1671        } else {
1672                set_notification(port, N_OUTPUT_LOWAT, 1);
1673        }
1674}
1675
1676/**
1677 * ioc4_change_speed - change the speed of the port
1678 * @the_port: port to change
1679 * @new_termios: new termios settings
1680 * @old_termios: old termios settings
1681 */
1682static void
1683ioc4_change_speed(struct uart_port *the_port,
1684                  struct ktermios *new_termios, struct ktermios *old_termios)
1685{
1686        struct ioc4_port *port = get_ioc4_port(the_port, 0);
1687        int baud, bits;
1688        unsigned cflag, iflag;
1689        int new_parity = 0, new_parity_enable = 0, new_stop = 0, new_data = 8;
1690        struct uart_state *state = the_port->state;
1691
1692        cflag = new_termios->c_cflag;
1693        iflag = new_termios->c_iflag;
1694
1695        switch (cflag & CSIZE) {
1696        case CS5:
1697                new_data = 5;
1698                bits = 7;
1699                break;
1700        case CS6:
1701                new_data = 6;
1702                bits = 8;
1703                break;
1704        case CS7:
1705                new_data = 7;
1706                bits = 9;
1707                break;
1708        case CS8:
1709                new_data = 8;
1710                bits = 10;
1711                break;
1712        default:
1713                /* cuz we always need a default ... */
1714                new_data = 5;
1715                bits = 7;
1716                break;
1717        }
1718        if (cflag & CSTOPB) {
1719                bits++;
1720                new_stop = 1;
1721        }
1722        if (cflag & PARENB) {
1723                bits++;
1724                new_parity_enable = 1;
1725                if (cflag & PARODD)
1726                        new_parity = 1;
1727        }
1728        baud = uart_get_baud_rate(the_port, new_termios, old_termios,
1729                                MIN_BAUD_SUPPORTED, MAX_BAUD_SUPPORTED);
1730        DPRINT_CONFIG(("%s: returned baud %d\n", __func__, baud));
1731
1732        /* default is 9600 */
1733        if (!baud)
1734                baud = 9600;
1735
1736        if (!the_port->fifosize)
1737                the_port->fifosize = IOC4_FIFO_CHARS;
1738        the_port->timeout = ((the_port->fifosize * HZ * bits) / (baud / 10));
1739        the_port->timeout += HZ / 50;   /* Add .02 seconds of slop */
1740
1741        the_port->ignore_status_mask = N_ALL_INPUT;
1742
1743        state->port.low_latency = 1;
1744
1745        if (iflag & IGNPAR)
1746                the_port->ignore_status_mask &= ~(N_PARITY_ERROR
1747                                                | N_FRAMING_ERROR);
1748        if (iflag & IGNBRK) {
1749                the_port->ignore_status_mask &= ~N_BREAK;
1750                if (iflag & IGNPAR)
1751                        the_port->ignore_status_mask &= ~N_OVERRUN_ERROR;
1752        }
1753        if (!(cflag & CREAD)) {
1754                /* ignore everything */
1755                the_port->ignore_status_mask &= ~N_DATA_READY;
1756        }
1757
1758        if (cflag & CRTSCTS) {
1759                port->ip_sscr |= IOC4_SSCR_HFC_EN;
1760        }
1761        else {
1762                port->ip_sscr &= ~IOC4_SSCR_HFC_EN;
1763        }
1764        writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1765
1766        /* Set the configuration and proper notification call */
1767        DPRINT_CONFIG(("%s : port 0x%p cflag 0%o "
1768                "config_port(baud %d data %d stop %d p enable %d parity %d),"
1769                " notification 0x%x\n",
1770             __func__, (void *)port, cflag, baud, new_data, new_stop,
1771             new_parity_enable, new_parity, the_port->ignore_status_mask));
1772
1773        if ((config_port(port, baud,            /* baud */
1774                         new_data,              /* byte size */
1775                         new_stop,              /* stop bits */
1776                         new_parity_enable,     /* set parity */
1777                         new_parity)) >= 0) {   /* parity 1==odd */
1778                set_notification(port, the_port->ignore_status_mask, 1);
1779        }
1780}
1781
1782/**
1783 * ic4_startup_local - Start up the serial port - returns >= 0 if no errors
1784 * @the_port: Port to operate on
1785 */
1786static inline int ic4_startup_local(struct uart_port *the_port)
1787{
1788        struct ioc4_port *port;
1789        struct uart_state *state;
1790
1791        if (!the_port)
1792                return -1;
1793
1794        port = get_ioc4_port(the_port, 0);
1795        if (!port)
1796                return -1;
1797
1798        state = the_port->state;
1799
1800        local_open(port);
1801
1802        /* set the protocol - mapbase has the port type */
1803        ioc4_set_proto(port, the_port->mapbase);
1804
1805        /* set the speed of the serial port */
1806        ioc4_change_speed(the_port, &state->port.tty->termios,
1807                          (struct ktermios *)0);
1808
1809        return 0;
1810}
1811
1812/*
1813 * ioc4_cb_output_lowat - called when the output low water mark is hit
1814 * @the_port: port to output
1815 */
1816static void ioc4_cb_output_lowat(struct uart_port *the_port)
1817{
1818        unsigned long pflags;
1819
1820        /* ip_lock is set on the call here */
1821        if (the_port) {
1822                spin_lock_irqsave(&the_port->lock, pflags);
1823                transmit_chars(the_port);
1824                spin_unlock_irqrestore(&the_port->lock, pflags);
1825        }
1826}
1827
1828/**
1829 * handle_intr - service any interrupts for the given port - 2nd level
1830 *                      called via sd_intr
1831 * @arg: handler arg
1832 * @sio_ir: ioc4regs
1833 */
1834static void handle_intr(void *arg, uint32_t sio_ir)
1835{
1836        struct ioc4_port *port = (struct ioc4_port *)arg;
1837        struct hooks *hooks = port->ip_hooks;
1838        unsigned int rx_high_rd_aborted = 0;
1839        unsigned long flags;
1840        struct uart_port *the_port;
1841        int loop_counter;
1842
1843        /* Possible race condition here: The tx_mt interrupt bit may be
1844         * cleared without the intervention of the interrupt handler,
1845         * e.g. by a write.  If the top level interrupt handler reads a
1846         * tx_mt, then some other processor does a write, starting up
1847         * output, then we come in here, see the tx_mt and stop DMA, the
1848         * output started by the other processor will hang.  Thus we can
1849         * only rely on tx_mt being legitimate if it is read while the
1850         * port lock is held.  Therefore this bit must be ignored in the
1851         * passed in interrupt mask which was read by the top level
1852         * interrupt handler since the port lock was not held at the time
1853         * it was read.  We can only rely on this bit being accurate if it
1854         * is read while the port lock is held.  So we'll clear it for now,
1855         * and reload it later once we have the port lock.
1856         */
1857        sio_ir &= ~(hooks->intr_tx_mt);
1858
1859        spin_lock_irqsave(&port->ip_lock, flags);
1860
1861        loop_counter = MAXITER; /* to avoid hangs */
1862
1863        do {
1864                uint32_t shadow;
1865
1866                if ( loop_counter-- <= 0 ) {
1867                        printk(KERN_WARNING "IOC4 serial: "
1868                                        "possible hang condition/"
1869                                        "port stuck on interrupt.\n");
1870                        break;
1871                }
1872
1873                /* Handle a DCD change */
1874                if (sio_ir & hooks->intr_delta_dcd) {
1875                        /* ACK the interrupt */
1876                        writel(hooks->intr_delta_dcd,
1877                                &port->ip_mem->sio_ir.raw);
1878
1879                        shadow = readl(&port->ip_serial_regs->shadow);
1880
1881                        if ((port->ip_notify & N_DDCD)
1882                                        && (shadow & IOC4_SHADOW_DCD)
1883                                        && (port->ip_port)) {
1884                                the_port = port->ip_port;
1885                                the_port->icount.dcd = 1;
1886                                wake_up_interruptible
1887                                            (&the_port->state->port.delta_msr_wait);
1888                        } else if ((port->ip_notify & N_DDCD)
1889                                        && !(shadow & IOC4_SHADOW_DCD)) {
1890                                /* Flag delta DCD/no DCD */
1891                                port->ip_flags |= DCD_ON;
1892                        }
1893                }
1894
1895                /* Handle a CTS change */
1896                if (sio_ir & hooks->intr_delta_cts) {
1897                        /* ACK the interrupt */
1898                        writel(hooks->intr_delta_cts,
1899                                        &port->ip_mem->sio_ir.raw);
1900
1901                        shadow = readl(&port->ip_serial_regs->shadow);
1902
1903                        if ((port->ip_notify & N_DCTS)
1904                                        && (port->ip_port)) {
1905                                the_port = port->ip_port;
1906                                the_port->icount.cts =
1907                                        (shadow & IOC4_SHADOW_CTS) ? 1 : 0;
1908                                wake_up_interruptible
1909                                        (&the_port->state->port.delta_msr_wait);
1910                        }
1911                }
1912
1913                /* rx timeout interrupt.  Must be some data available.  Put this
1914                 * before the check for rx_high since servicing this condition
1915                 * may cause that condition to clear.
1916                 */
1917                if (sio_ir & hooks->intr_rx_timer) {
1918                        /* ACK the interrupt */
1919                        writel(hooks->intr_rx_timer,
1920                                &port->ip_mem->sio_ir.raw);
1921
1922                        if ((port->ip_notify & N_DATA_READY)
1923                                        && (port->ip_port)) {
1924                                /* ip_lock is set on call here */
1925                                receive_chars(port->ip_port);
1926                        }
1927                }
1928
1929                /* rx high interrupt. Must be after rx_timer.  */
1930                else if (sio_ir & hooks->intr_rx_high) {
1931                        /* Data available, notify upper layer */
1932                        if ((port->ip_notify & N_DATA_READY)
1933                                                && port->ip_port) {
1934                                /* ip_lock is set on call here */
1935                                receive_chars(port->ip_port);
1936                        }
1937
1938                        /* We can't ACK this interrupt.  If receive_chars didn't
1939                         * cause the condition to clear, we'll have to disable
1940                         * the interrupt until the data is drained.
1941                         * If the read was aborted, don't disable the interrupt
1942                         * as this may cause us to hang indefinitely.  An
1943                         * aborted read generally means that this interrupt
1944                         * hasn't been delivered to the cpu yet anyway, even
1945                         * though we see it as asserted when we read the sio_ir.
1946                         */
1947                        if ((sio_ir = PENDING(port)) & hooks->intr_rx_high) {
1948                                if ((port->ip_flags & READ_ABORTED) == 0) {
1949                                        port->ip_ienb &= ~hooks->intr_rx_high;
1950                                        port->ip_flags |= INPUT_HIGH;
1951                                } else {
1952                                        rx_high_rd_aborted++;
1953                                }
1954                        }
1955                }
1956
1957                /* We got a low water interrupt: notify upper layer to
1958                 * send more data.  Must come before tx_mt since servicing
1959                 * this condition may cause that condition to clear.
1960                 */
1961                if (sio_ir & hooks->intr_tx_explicit) {
1962                        port->ip_flags &= ~LOWAT_WRITTEN;
1963
1964                        /* ACK the interrupt */
1965                        writel(hooks->intr_tx_explicit,
1966                                        &port->ip_mem->sio_ir.raw);
1967
1968                        if (port->ip_notify & N_OUTPUT_LOWAT)
1969                                ioc4_cb_output_lowat(port->ip_port);
1970                }
1971
1972                /* Handle tx_mt.  Must come after tx_explicit.  */
1973                else if (sio_ir & hooks->intr_tx_mt) {
1974                        /* If we are expecting a lowat notification
1975                         * and we get to this point it probably means that for
1976                         * some reason the tx_explicit didn't work as expected
1977                         * (that can legitimately happen if the output buffer is
1978                         * filled up in just the right way).
1979                         * So send the notification now.
1980                         */
1981                        if (port->ip_notify & N_OUTPUT_LOWAT) {
1982                                ioc4_cb_output_lowat(port->ip_port);
1983
1984                                /* We need to reload the sio_ir since the lowat
1985                                 * call may have caused another write to occur,
1986                                 * clearing the tx_mt condition.
1987                                 */
1988                                sio_ir = PENDING(port);
1989                        }
1990
1991                        /* If the tx_mt condition still persists even after the
1992                         * lowat call, we've got some work to do.
1993                         */
1994                        if (sio_ir & hooks->intr_tx_mt) {
1995
1996                                /* If we are not currently expecting DMA input,
1997                                 * and the transmitter has just gone idle,
1998                                 * there is no longer any reason for DMA, so
1999                                 * disable it.
2000                                 */
2001                                if (!(port->ip_notify
2002                                                & (N_DATA_READY | N_DDCD))) {
2003                                        BUG_ON(!(port->ip_sscr
2004                                                        & IOC4_SSCR_DMA_EN));
2005                                        port->ip_sscr &= ~IOC4_SSCR_DMA_EN;
2006                                        writel(port->ip_sscr,
2007                                           &port->ip_serial_regs->sscr);
2008                                }
2009
2010                                /* Prevent infinite tx_mt interrupt */
2011                                port->ip_ienb &= ~hooks->intr_tx_mt;
2012                        }
2013                }
2014                sio_ir = PENDING(port);
2015
2016                /* if the read was aborted and only hooks->intr_rx_high,
2017                 * clear hooks->intr_rx_high, so we do not loop forever.
2018                 */
2019
2020                if (rx_high_rd_aborted && (sio_ir == hooks->intr_rx_high)) {
2021                        sio_ir &= ~hooks->intr_rx_high;
2022                }
2023        } while (sio_ir & hooks->intr_all);
2024
2025        spin_unlock_irqrestore(&port->ip_lock, flags);
2026
2027        /* Re-enable interrupts before returning from interrupt handler.
2028         * Getting interrupted here is okay.  It'll just v() our semaphore, and
2029         * we'll come through the loop again.
2030         */
2031
2032        write_ireg(port->ip_ioc4_soft, port->ip_ienb, IOC4_W_IES,
2033                                                        IOC4_SIO_INTR_TYPE);
2034}
2035
2036/*
2037 * ioc4_cb_post_ncs - called for some basic errors
2038 * @port: port to use
2039 * @ncs: event
2040 */
2041static void ioc4_cb_post_ncs(struct uart_port *the_port, int ncs)
2042{
2043        struct uart_icount *icount;
2044
2045        icount = &the_port->icount;
2046
2047        if (ncs & NCS_BREAK)
2048                icount->brk++;
2049        if (ncs & NCS_FRAMING)
2050                icount->frame++;
2051        if (ncs & NCS_OVERRUN)
2052                icount->overrun++;
2053        if (ncs & NCS_PARITY)
2054                icount->parity++;
2055}
2056
2057/**
2058 * do_read - Read in bytes from the port.  Return the number of bytes
2059 *                      actually read.
2060 * @the_port: port to use
2061 * @buf: place to put the stuff we read
2062 * @len: how big 'buf' is
2063 */
2064
2065static inline int do_read(struct uart_port *the_port, unsigned char *buf,
2066                                int len)
2067{
2068        int prod_ptr, cons_ptr, total;
2069        struct ioc4_port *port = get_ioc4_port(the_port, 0);
2070        struct ring *inring;
2071        struct ring_entry *entry;
2072        struct hooks *hooks;
2073        int byte_num;
2074        char *sc;
2075        int loop_counter;
2076
2077        BUG_ON(!(len >= 0));
2078        BUG_ON(!port);
2079        hooks = port->ip_hooks;
2080
2081        /* There is a nasty timing issue in the IOC4. When the rx_timer
2082         * expires or the rx_high condition arises, we take an interrupt.
2083         * At some point while servicing the interrupt, we read bytes from
2084         * the ring buffer and re-arm the rx_timer.  However the rx_timer is
2085         * not started until the first byte is received *after* it is armed,
2086         * and any bytes pending in the rx construction buffers are not drained
2087         * to memory until either there are 4 bytes available or the rx_timer
2088         * expires.  This leads to a potential situation where data is left
2089         * in the construction buffers forever - 1 to 3 bytes were received
2090         * after the interrupt was generated but before the rx_timer was
2091         * re-armed. At that point as long as no subsequent bytes are received
2092         * the timer will never be started and the bytes will remain in the
2093         * construction buffer forever.  The solution is to execute a DRAIN
2094         * command after rearming the timer.  This way any bytes received before
2095         * the DRAIN will be drained to memory, and any bytes received after
2096         * the DRAIN will start the TIMER and be drained when it expires.
2097         * Luckily, this only needs to be done when the DMA buffer is empty
2098         * since there is no requirement that this function return all
2099         * available data as long as it returns some.
2100         */
2101        /* Re-arm the timer */
2102        writel(port->ip_rx_cons | IOC4_SRCIR_ARM, &port->ip_serial_regs->srcir);
2103
2104        prod_ptr = readl(&port->ip_serial_regs->srpir) & PROD_CONS_MASK;
2105        cons_ptr = port->ip_rx_cons;
2106
2107        if (prod_ptr == cons_ptr) {
2108                int reset_dma = 0;
2109
2110                /* Input buffer appears empty, do a flush. */
2111
2112                /* DMA must be enabled for this to work. */
2113                if (!(port->ip_sscr & IOC4_SSCR_DMA_EN)) {
2114                        port->ip_sscr |= IOC4_SSCR_DMA_EN;
2115                        reset_dma = 1;
2116                }
2117
2118                /* Potential race condition: we must reload the srpir after
2119                 * issuing the drain command, otherwise we could think the rx
2120                 * buffer is empty, then take a very long interrupt, and when
2121                 * we come back it's full and we wait forever for the drain to
2122                 * complete.
2123                 */
2124                writel(port->ip_sscr | IOC4_SSCR_RX_DRAIN,
2125                                &port->ip_serial_regs->sscr);
2126                prod_ptr = readl(&port->ip_serial_regs->srpir)
2127                                & PROD_CONS_MASK;
2128
2129                /* We must not wait for the DRAIN to complete unless there are
2130                 * at least 8 bytes (2 ring entries) available to receive the
2131                 * data otherwise the DRAIN will never complete and we'll
2132                 * deadlock here.
2133                 * In fact, to make things easier, I'll just ignore the flush if
2134                 * there is any data at all now available.
2135                 */
2136                if (prod_ptr == cons_ptr) {
2137                        loop_counter = 0;
2138                        while (readl(&port->ip_serial_regs->sscr) &
2139                                                IOC4_SSCR_RX_DRAIN) {
2140                                loop_counter++;
2141                                if (loop_counter > MAXITER)
2142                                        return -1;
2143                        }
2144
2145                        /* SIGH. We have to reload the prod_ptr *again* since
2146                         * the drain may have caused it to change
2147                         */
2148                        prod_ptr = readl(&port->ip_serial_regs->srpir)
2149                                                        & PROD_CONS_MASK;
2150                }
2151                if (reset_dma) {
2152                        port->ip_sscr &= ~IOC4_SSCR_DMA_EN;
2153                        writel(port->ip_sscr, &port->ip_serial_regs->sscr);
2154                }
2155        }
2156        inring = port->ip_inring;
2157        port->ip_flags &= ~READ_ABORTED;
2158
2159        total = 0;
2160        loop_counter = 0xfffff; /* to avoid hangs */
2161
2162        /* Grab bytes from the hardware */
2163        while ((prod_ptr != cons_ptr) && (len > 0)) {
2164                entry = (struct ring_entry *)((caddr_t)inring + cons_ptr);
2165
2166                if ( loop_counter-- <= 0 ) {
2167                        printk(KERN_WARNING "IOC4 serial: "
2168                                        "possible hang condition/"
2169                                        "port stuck on read.\n");
2170                        break;
2171                }
2172
2173                /* According to the producer pointer, this ring entry
2174                 * must contain some data.  But if the PIO happened faster
2175                 * than the DMA, the data may not be available yet, so let's
2176                 * wait until it arrives.
2177                 */
2178                if ((entry->ring_allsc & RING_ANY_VALID) == 0) {
2179                        /* Indicate the read is aborted so we don't disable
2180                         * the interrupt thinking that the consumer is
2181                         * congested.
2182                         */
2183                        port->ip_flags |= READ_ABORTED;
2184                        len = 0;
2185                        break;
2186                }
2187
2188                /* Load the bytes/status out of the ring entry */
2189                for (byte_num = 0; byte_num < 4 && len > 0; byte_num++) {
2190                        sc = &(entry->ring_sc[byte_num]);
2191
2192                        /* Check for change in modem state or overrun */
2193                        if ((*sc & IOC4_RXSB_MODEM_VALID)
2194                                                && (port->ip_notify & N_DDCD)) {
2195                                /* Notify upper layer if DCD dropped */
2196
2197                                if ((port->ip_flags & DCD_ON)
2198                                                && !(*sc & IOC4_RXSB_DCD)) {
2199
2200                                        /* If we have already copied some data,
2201                                         * return it.  We'll pick up the carrier
2202                                         * drop on the next pass.  That way we
2203                                         * don't throw away the data that has
2204                                         * already been copied back to
2205                                         * the caller's buffer.
2206                                         */
2207                                        if (total > 0) {
2208                                                len = 0;
2209                                                break;
2210                                        }
2211                                        port->ip_flags &= ~DCD_ON;
2212
2213                                        /* Turn off this notification so the
2214                                         * carrier drop protocol won't see it
2215                                         * again when it does a read.
2216                                         */
2217                                        *sc &= ~IOC4_RXSB_MODEM_VALID;
2218
2219                                        /* To keep things consistent, we need
2220                                         * to update the consumer pointer so
2221                                         * the next reader won't come in and
2222                                         * try to read the same ring entries
2223                                         * again. This must be done here before
2224                                         * the dcd change.
2225                                         */
2226
2227                                        if ((entry->ring_allsc & RING_ANY_VALID)
2228                                                                        == 0) {
2229                                                cons_ptr += (int)sizeof
2230                                                        (struct ring_entry);
2231                                                cons_ptr &= PROD_CONS_MASK;
2232                                        }
2233                                        writel(cons_ptr,
2234                                                &port->ip_serial_regs->srcir);
2235                                        port->ip_rx_cons = cons_ptr;
2236
2237                                        /* Notify upper layer of carrier drop */
2238                                        if ((port->ip_notify & N_DDCD)
2239                                                   && port->ip_port) {
2240                                                the_port->icount.dcd = 0;
2241                                                wake_up_interruptible
2242                                                    (&the_port->state->
2243                                                        port.delta_msr_wait);
2244                                        }
2245
2246                                        /* If we had any data to return, we
2247                                         * would have returned it above.
2248                                         */
2249                                        return 0;
2250                                }
2251                        }
2252                        if (*sc & IOC4_RXSB_MODEM_VALID) {
2253                                /* Notify that an input overrun occurred */
2254                                if ((*sc & IOC4_RXSB_OVERRUN)
2255                                    && (port->ip_notify & N_OVERRUN_ERROR)) {
2256                                        ioc4_cb_post_ncs(the_port, NCS_OVERRUN);
2257                                }
2258                                /* Don't look at this byte again */
2259                                *sc &= ~IOC4_RXSB_MODEM_VALID;
2260                        }
2261
2262                        /* Check for valid data or RX errors */
2263                        if ((*sc & IOC4_RXSB_DATA_VALID) &&
2264                                        ((*sc & (IOC4_RXSB_PAR_ERR
2265                                                        | IOC4_RXSB_FRAME_ERR
2266                                                        | IOC4_RXSB_BREAK))
2267                                        && (port->ip_notify & (N_PARITY_ERROR
2268                                                        | N_FRAMING_ERROR
2269                                                        | N_BREAK)))) {
2270                                /* There is an error condition on the next byte.
2271                                 * If we have already transferred some bytes,
2272                                 * we'll stop here. Otherwise if this is the
2273                                 * first byte to be read, we'll just transfer
2274                                 * it alone after notifying the
2275                                 * upper layer of its status.
2276                                 */
2277                                if (total > 0) {
2278                                        len = 0;
2279                                        break;
2280                                } else {
2281                                        if ((*sc & IOC4_RXSB_PAR_ERR) &&
2282                                           (port->ip_notify & N_PARITY_ERROR)) {
2283                                                ioc4_cb_post_ncs(the_port,
2284                                                                NCS_PARITY);
2285                                        }
2286                                        if ((*sc & IOC4_RXSB_FRAME_ERR) &&
2287                                           (port->ip_notify & N_FRAMING_ERROR)){
2288                                                ioc4_cb_post_ncs(the_port,
2289                                                                NCS_FRAMING);
2290                                        }
2291                                        if ((*sc & IOC4_RXSB_BREAK)
2292                                            && (port->ip_notify & N_BREAK)) {
2293                                                        ioc4_cb_post_ncs
2294                                                                    (the_port,
2295                                                                     NCS_BREAK);
2296                                        }
2297                                        len = 1;
2298                                }
2299                        }
2300                        if (*sc & IOC4_RXSB_DATA_VALID) {
2301                                *sc &= ~IOC4_RXSB_DATA_VALID;
2302                                *buf = entry->ring_data[byte_num];
2303                                buf++;
2304                                len--;
2305                                total++;
2306                        }
2307                }
2308
2309                /* If we used up this entry entirely, go on to the next one,
2310                 * otherwise we must have run out of buffer space, so
2311                 * leave the consumer pointer here for the next read in case
2312                 * there are still unread bytes in this entry.
2313                 */
2314                if ((entry->ring_allsc & RING_ANY_VALID) == 0) {
2315                        cons_ptr += (int)sizeof(struct ring_entry);
2316                        cons_ptr &= PROD_CONS_MASK;
2317                }
2318        }
2319
2320        /* Update consumer pointer and re-arm rx timer interrupt */
2321        writel(cons_ptr, &port->ip_serial_regs->srcir);
2322        port->ip_rx_cons = cons_ptr;
2323
2324        /* If we have now dipped below the rx high water mark and we have
2325         * rx_high interrupt turned off, we can now turn it back on again.
2326         */
2327        if ((port->ip_flags & INPUT_HIGH) && (((prod_ptr - cons_ptr)
2328                        & PROD_CONS_MASK) < ((port->ip_sscr &
2329                                IOC4_SSCR_RX_THRESHOLD)
2330                                        << IOC4_PROD_CONS_PTR_OFF))) {
2331                port->ip_flags &= ~INPUT_HIGH;
2332                enable_intrs(port, hooks->intr_rx_high);
2333        }
2334        return total;
2335}
2336
2337/**
2338 * receive_chars - upper level read. Called with ip_lock.
2339 * @the_port: port to read from
2340 */
2341static void receive_chars(struct uart_port *the_port)
2342{
2343        unsigned char ch[IOC4_MAX_CHARS];
2344        int read_count, request_count = IOC4_MAX_CHARS;
2345        struct uart_icount *icount;
2346        struct uart_state *state = the_port->state;
2347        unsigned long pflags;
2348
2349        /* Make sure all the pointers are "good" ones */
2350        if (!state)
2351                return;
2352
2353        spin_lock_irqsave(&the_port->lock, pflags);
2354
2355        request_count = tty_buffer_request_room(&state->port, IOC4_MAX_CHARS);
2356
2357        if (request_count > 0) {
2358                icount = &the_port->icount;
2359                read_count = do_read(the_port, ch, request_count);
2360                if (read_count > 0) {
2361                        tty_insert_flip_string(&state->port, ch, read_count);
2362                        icount->rx += read_count;
2363                }
2364        }
2365
2366        spin_unlock_irqrestore(&the_port->lock, pflags);
2367
2368        tty_flip_buffer_push(&state->port);
2369}
2370
2371/**
2372 * ic4_type - What type of console are we?
2373 * @port: Port to operate with (we ignore since we only have one port)
2374 *
2375 */
2376static const char *ic4_type(struct uart_port *the_port)
2377{
2378        if (the_port->mapbase == PROTO_RS232)
2379                return "SGI IOC4 Serial [rs232]";
2380        else
2381                return "SGI IOC4 Serial [rs422]";
2382}
2383
2384/**
2385 * ic4_tx_empty - Is the transmitter empty?
2386 * @port: Port to operate on
2387 *
2388 */
2389static unsigned int ic4_tx_empty(struct uart_port *the_port)
2390{
2391        struct ioc4_port *port = get_ioc4_port(the_port, 0);
2392        unsigned int ret = 0;
2393
2394        if (port_is_active(port, the_port)) {
2395                if (readl(&port->ip_serial_regs->shadow) & IOC4_SHADOW_TEMT)
2396                        ret = TIOCSER_TEMT;
2397        }
2398        return ret;
2399}
2400
2401/**
2402 * ic4_stop_tx - stop the transmitter
2403 * @port: Port to operate on
2404 *
2405 */
2406static void ic4_stop_tx(struct uart_port *the_port)
2407{
2408        struct ioc4_port *port = get_ioc4_port(the_port, 0);
2409
2410        if (port_is_active(port, the_port))
2411                set_notification(port, N_OUTPUT_LOWAT, 0);
2412}
2413
2414/**
2415 * null_void_function -
2416 * @port: Port to operate on
2417 *
2418 */
2419static void null_void_function(struct uart_port *the_port)
2420{
2421}
2422
2423/**
2424 * ic4_shutdown - shut down the port - free irq and disable
2425 * @port: Port to shut down
2426 *
2427 */
2428static void ic4_shutdown(struct uart_port *the_port)
2429{
2430        unsigned long port_flags;
2431        struct ioc4_port *port;
2432        struct uart_state *state;
2433
2434        port = get_ioc4_port(the_port, 0);
2435        if (!port)
2436                return;
2437
2438        state = the_port->state;
2439        port->ip_port = NULL;
2440
2441        wake_up_interruptible(&state->port.delta_msr_wait);
2442
2443        if (state->port.tty)
2444                set_bit(TTY_IO_ERROR, &state->port.tty->flags);
2445
2446        spin_lock_irqsave(&the_port->lock, port_flags);
2447        set_notification(port, N_ALL, 0);
2448        port->ip_flags = PORT_INACTIVE;
2449        spin_unlock_irqrestore(&the_port->lock, port_flags);
2450}
2451
2452/**
2453 * ic4_set_mctrl - set control lines (dtr, rts, etc)
2454 * @port: Port to operate on
2455 * @mctrl: Lines to set/unset
2456 *
2457 */
2458static void ic4_set_mctrl(struct uart_port *the_port, unsigned int mctrl)
2459{
2460        unsigned char mcr = 0;
2461        struct ioc4_port *port;
2462
2463        port = get_ioc4_port(the_port, 0);
2464        if (!port_is_active(port, the_port))
2465                return;
2466
2467        if (mctrl & TIOCM_RTS)
2468                mcr |= UART_MCR_RTS;
2469        if (mctrl & TIOCM_DTR)
2470                mcr |= UART_MCR_DTR;
2471        if (mctrl & TIOCM_OUT1)
2472                mcr |= UART_MCR_OUT1;
2473        if (mctrl & TIOCM_OUT2)
2474                mcr |= UART_MCR_OUT2;
2475        if (mctrl & TIOCM_LOOP)
2476                mcr |= UART_MCR_LOOP;
2477
2478        set_mcr(the_port, mcr, IOC4_SHADOW_DTR);
2479}
2480
2481/**
2482 * ic4_get_mctrl - get control line info
2483 * @port: port to operate on
2484 *
2485 */
2486static unsigned int ic4_get_mctrl(struct uart_port *the_port)
2487{
2488        struct ioc4_port *port = get_ioc4_port(the_port, 0);
2489        uint32_t shadow;
2490        unsigned int ret = 0;
2491
2492        if (!port_is_active(port, the_port))
2493                return 0;
2494
2495        shadow = readl(&port->ip_serial_regs->shadow);
2496        if (shadow & IOC4_SHADOW_DCD)
2497                ret |= TIOCM_CAR;
2498        if (shadow & IOC4_SHADOW_DR)
2499                ret |= TIOCM_DSR;
2500        if (shadow & IOC4_SHADOW_CTS)
2501                ret |= TIOCM_CTS;
2502        return ret;
2503}
2504
2505/**
2506 * ic4_start_tx - Start transmitter, flush any output
2507 * @port: Port to operate on
2508 *
2509 */
2510static void ic4_start_tx(struct uart_port *the_port)
2511{
2512        struct ioc4_port *port = get_ioc4_port(the_port, 0);
2513
2514        if (port_is_active(port, the_port)) {
2515                set_notification(port, N_OUTPUT_LOWAT, 1);
2516                enable_intrs(port, port->ip_hooks->intr_tx_mt);
2517        }
2518}
2519
2520/**
2521 * ic4_break_ctl - handle breaks
2522 * @port: Port to operate on
2523 * @break_state: Break state
2524 *
2525 */
2526static void ic4_break_ctl(struct uart_port *the_port, int break_state)
2527{
2528}
2529
2530/**
2531 * ic4_startup - Start up the serial port
2532 * @port: Port to operate on
2533 *
2534 */
2535static int ic4_startup(struct uart_port *the_port)
2536{
2537        int retval;
2538        struct ioc4_port *port;
2539        struct ioc4_control *control;
2540        struct uart_state *state;
2541        unsigned long port_flags;
2542
2543        if (!the_port)
2544                return -ENODEV;
2545        port = get_ioc4_port(the_port, 1);
2546        if (!port)
2547                return -ENODEV;
2548        state = the_port->state;
2549
2550        control = port->ip_control;
2551        if (!control) {
2552                port->ip_port = NULL;
2553                return -ENODEV;
2554        }
2555
2556        /* Start up the serial port */
2557        spin_lock_irqsave(&the_port->lock, port_flags);
2558        retval = ic4_startup_local(the_port);
2559        spin_unlock_irqrestore(&the_port->lock, port_flags);
2560        return retval;
2561}
2562
2563/**
2564 * ic4_set_termios - set termios stuff
2565 * @port: port to operate on
2566 * @termios: New settings
2567 * @termios: Old
2568 *
2569 */
2570static void
2571ic4_set_termios(struct uart_port *the_port,
2572                struct ktermios *termios, struct ktermios *old_termios)
2573{
2574        unsigned long port_flags;
2575
2576        spin_lock_irqsave(&the_port->lock, port_flags);
2577        ioc4_change_speed(the_port, termios, old_termios);
2578        spin_unlock_irqrestore(&the_port->lock, port_flags);
2579}
2580
2581/**
2582 * ic4_request_port - allocate resources for port - no op....
2583 * @port: port to operate on
2584 *
2585 */
2586static int ic4_request_port(struct uart_port *port)
2587{
2588        return 0;
2589}
2590
2591/* Associate the uart functions above - given to serial core */
2592
2593static struct uart_ops ioc4_ops = {
2594        .tx_empty       = ic4_tx_empty,
2595        .set_mctrl      = ic4_set_mctrl,
2596        .get_mctrl      = ic4_get_mctrl,
2597        .stop_tx        = ic4_stop_tx,
2598        .start_tx       = ic4_start_tx,
2599        .stop_rx        = null_void_function,
2600        .enable_ms      = null_void_function,
2601        .break_ctl      = ic4_break_ctl,
2602        .startup        = ic4_startup,
2603        .shutdown       = ic4_shutdown,
2604        .set_termios    = ic4_set_termios,
2605        .type           = ic4_type,
2606        .release_port   = null_void_function,
2607        .request_port   = ic4_request_port,
2608};
2609
2610/*
2611 * Boot-time initialization code
2612 */
2613
2614static struct uart_driver ioc4_uart_rs232 = {
2615        .owner          = THIS_MODULE,
2616        .driver_name    = "ioc4_serial_rs232",
2617        .dev_name       = DEVICE_NAME_RS232,
2618        .major          = DEVICE_MAJOR,
2619        .minor          = DEVICE_MINOR_RS232,
2620        .nr             = IOC4_NUM_CARDS * IOC4_NUM_SERIAL_PORTS,
2621};
2622
2623static struct uart_driver ioc4_uart_rs422 = {
2624        .owner          = THIS_MODULE,
2625        .driver_name    = "ioc4_serial_rs422",
2626        .dev_name       = DEVICE_NAME_RS422,
2627        .major          = DEVICE_MAJOR,
2628        .minor          = DEVICE_MINOR_RS422,
2629        .nr             = IOC4_NUM_CARDS * IOC4_NUM_SERIAL_PORTS,
2630};
2631
2632
2633/**
2634 * ioc4_serial_remove_one - detach function
2635 *
2636 * @idd: IOC4 master module data for this IOC4
2637 */
2638
2639static int ioc4_serial_remove_one(struct ioc4_driver_data *idd)
2640{
2641        int port_num, port_type;
2642        struct ioc4_control *control;
2643        struct uart_port *the_port;
2644        struct ioc4_port *port;
2645        struct ioc4_soft *soft;
2646
2647        /* If serial driver did not attach, don't try to detach */
2648        control = idd->idd_serial_data;
2649        if (!control)
2650                return 0;
2651
2652        for (port_num = 0; port_num < IOC4_NUM_SERIAL_PORTS; port_num++) {
2653                for (port_type = UART_PORT_MIN;
2654                                        port_type < UART_PORT_COUNT;
2655                                        port_type++) {
2656                        the_port = &control->ic_port[port_num].icp_uart_port
2657                                                        [port_type];
2658                        if (the_port) {
2659                                switch (port_type) {
2660                                case UART_PORT_RS422:
2661                                        uart_remove_one_port(&ioc4_uart_rs422,
2662                                                        the_port);
2663                                        break;
2664                                default:
2665                                case UART_PORT_RS232:
2666                                        uart_remove_one_port(&ioc4_uart_rs232,
2667                                                        the_port);
2668                                        break;
2669                                }
2670                        }
2671                }
2672                port = control->ic_port[port_num].icp_port;
2673                /* we allocate in pairs */
2674                if (!(port_num & 1) && port) {
2675                        pci_free_consistent(port->ip_pdev,
2676                                        TOTAL_RING_BUF_SIZE,
2677                                        port->ip_cpu_ringbuf,
2678                                        port->ip_dma_ringbuf);
2679                        kfree(port);
2680                }
2681        }
2682        soft = control->ic_soft;
2683        if (soft) {
2684                free_irq(control->ic_irq, soft);
2685                if (soft->is_ioc4_serial_addr) {
2686                        iounmap(soft->is_ioc4_serial_addr);
2687                        release_mem_region((unsigned long)
2688                             soft->is_ioc4_serial_addr,
2689                                sizeof(struct ioc4_serial));
2690                }
2691                kfree(soft);
2692        }
2693        kfree(control);
2694        idd->idd_serial_data = NULL;
2695
2696        return 0;
2697}
2698
2699
2700/**
2701 * ioc4_serial_core_attach_rs232 - register with serial core
2702 *              This is done during pci probing
2703 * @pdev: handle for this card
2704 */
2705static inline int
2706ioc4_serial_core_attach(struct pci_dev *pdev, int port_type)
2707{
2708        struct ioc4_port *port;
2709        struct uart_port *the_port;
2710        struct ioc4_driver_data *idd = pci_get_drvdata(pdev);
2711        struct ioc4_control *control = idd->idd_serial_data;
2712        int port_num;
2713        int port_type_idx;
2714        struct uart_driver *u_driver;
2715
2716
2717        DPRINT_CONFIG(("%s: attach pdev 0x%p - control 0x%p\n",
2718                        __func__, pdev, (void *)control));
2719
2720        if (!control)
2721                return -ENODEV;
2722
2723        port_type_idx = (port_type == PROTO_RS232) ? UART_PORT_RS232
2724                                                : UART_PORT_RS422;
2725
2726        u_driver = (port_type == PROTO_RS232)   ? &ioc4_uart_rs232
2727                                                : &ioc4_uart_rs422;
2728
2729        /* once around for each port on this card */
2730        for (port_num = 0; port_num < IOC4_NUM_SERIAL_PORTS; port_num++) {
2731                the_port = &control->ic_port[port_num].icp_uart_port
2732                                                        [port_type_idx];
2733                port = control->ic_port[port_num].icp_port;
2734                port->ip_all_ports[port_type_idx] = the_port;
2735
2736                DPRINT_CONFIG(("%s: attach the_port 0x%p / port 0x%p : type %s\n",
2737                                __func__, (void *)the_port,
2738                                (void *)port,
2739                                port_type == PROTO_RS232 ? "rs232" : "rs422"));
2740
2741                /* membase, iobase and mapbase just need to be non-0 */
2742                the_port->membase = (unsigned char __iomem *)1;
2743                the_port->iobase = (pdev->bus->number << 16) |  port_num;
2744                the_port->line = (Num_of_ioc4_cards << 2) | port_num;
2745                the_port->mapbase = port_type;
2746                the_port->type = PORT_16550A;
2747                the_port->fifosize = IOC4_FIFO_CHARS;
2748                the_port->ops = &ioc4_ops;
2749                the_port->irq = control->ic_irq;
2750                the_port->dev = &pdev->dev;
2751                spin_lock_init(&the_port->lock);
2752                if (uart_add_one_port(u_driver, the_port) < 0) {
2753                        printk(KERN_WARNING
2754                           "%s: unable to add port %d bus %d\n",
2755                               __func__, the_port->line, pdev->bus->number);
2756                } else {
2757                        DPRINT_CONFIG(
2758                            ("IOC4 serial port %d irq = %d, bus %d\n",
2759                               the_port->line, the_port->irq, pdev->bus->number));
2760                }
2761        }
2762        return 0;
2763}
2764
2765/**
2766 * ioc4_serial_attach_one - register attach function
2767 *              called per card found from IOC4 master module.
2768 * @idd: Master module data for this IOC4
2769 */
2770static int
2771ioc4_serial_attach_one(struct ioc4_driver_data *idd)
2772{
2773        unsigned long tmp_addr1;
2774        struct ioc4_serial __iomem *serial;
2775        struct ioc4_soft *soft;
2776        struct ioc4_control *control;
2777        int ret = 0;
2778
2779
2780        DPRINT_CONFIG(("%s (0x%p, 0x%p)\n", __func__, idd->idd_pdev,
2781                                                        idd->idd_pci_id));
2782
2783        /* PCI-RT does not bring out serial connections.
2784         * Do not attach to this particular IOC4.
2785         */
2786        if (idd->idd_variant == IOC4_VARIANT_PCI_RT)
2787                return 0;
2788
2789        /* request serial registers */
2790        tmp_addr1 = idd->idd_bar0 + IOC4_SERIAL_OFFSET;
2791
2792        if (!request_mem_region(tmp_addr1, sizeof(struct ioc4_serial),
2793                                        "sioc4_uart")) {
2794                printk(KERN_WARNING
2795                        "ioc4 (%p): unable to get request region for "
2796                                "uart space\n", (void *)idd->idd_pdev);
2797                ret = -ENODEV;
2798                goto out1;
2799        }
2800        serial = ioremap(tmp_addr1, sizeof(struct ioc4_serial));
2801        if (!serial) {
2802                printk(KERN_WARNING
2803                         "ioc4 (%p) : unable to remap ioc4 serial register\n",
2804                                (void *)idd->idd_pdev);
2805                ret = -ENODEV;
2806                goto out2;
2807        }
2808        DPRINT_CONFIG(("%s : mem 0x%p, serial 0x%p\n",
2809                                __func__, (void *)idd->idd_misc_regs,
2810                                (void *)serial));
2811
2812        /* Get memory for the new card */
2813        control = kzalloc(sizeof(struct ioc4_control), GFP_KERNEL);
2814
2815        if (!control) {
2816                printk(KERN_WARNING "ioc4_attach_one"
2817                       ": unable to get memory for the IOC4\n");
2818                ret = -ENOMEM;
2819                goto out2;
2820        }
2821        idd->idd_serial_data = control;
2822
2823        /* Allocate the soft structure */
2824        soft = kzalloc(sizeof(struct ioc4_soft), GFP_KERNEL);
2825        if (!soft) {
2826                printk(KERN_WARNING
2827                       "ioc4 (%p): unable to get memory for the soft struct\n",
2828                       (void *)idd->idd_pdev);
2829                ret = -ENOMEM;
2830                goto out3;
2831        }
2832
2833        spin_lock_init(&soft->is_ir_lock);
2834        soft->is_ioc4_misc_addr = idd->idd_misc_regs;
2835        soft->is_ioc4_serial_addr = serial;
2836
2837        /* Init the IOC4 */
2838        writel(0xf << IOC4_SIO_CR_CMD_PULSE_SHIFT,
2839               &idd->idd_misc_regs->sio_cr.raw);
2840
2841        /* Enable serial port mode select generic PIO pins as outputs */
2842        writel(IOC4_GPCR_UART0_MODESEL | IOC4_GPCR_UART1_MODESEL
2843                | IOC4_GPCR_UART2_MODESEL | IOC4_GPCR_UART3_MODESEL,
2844                &idd->idd_misc_regs->gpcr_s.raw);
2845
2846        /* Clear and disable all serial interrupts */
2847        write_ireg(soft, ~0, IOC4_W_IEC, IOC4_SIO_INTR_TYPE);
2848        writel(~0, &idd->idd_misc_regs->sio_ir.raw);
2849        write_ireg(soft, IOC4_OTHER_IR_SER_MEMERR, IOC4_W_IEC,
2850                   IOC4_OTHER_INTR_TYPE);
2851        writel(IOC4_OTHER_IR_SER_MEMERR, &idd->idd_misc_regs->other_ir.raw);
2852        control->ic_soft = soft;
2853
2854        /* Hook up interrupt handler */
2855        if (!request_irq(idd->idd_pdev->irq, ioc4_intr, IRQF_SHARED,
2856                                "sgi-ioc4serial", soft)) {
2857                control->ic_irq = idd->idd_pdev->irq;
2858        } else {
2859                printk(KERN_WARNING
2860                    "%s : request_irq fails for IRQ 0x%x\n ",
2861                        __func__, idd->idd_pdev->irq);
2862        }
2863        ret = ioc4_attach_local(idd);
2864        if (ret)
2865                goto out4;
2866
2867        /* register port with the serial core - 1 rs232, 1 rs422 */
2868
2869        if ((ret = ioc4_serial_core_attach(idd->idd_pdev, PROTO_RS232)))
2870                goto out4;
2871
2872        if ((ret = ioc4_serial_core_attach(idd->idd_pdev, PROTO_RS422)))
2873                goto out5;
2874
2875        Num_of_ioc4_cards++;
2876
2877        return ret;
2878
2879        /* error exits that give back resources */
2880out5:
2881        ioc4_serial_remove_one(idd);
2882        return ret;
2883out4:
2884        kfree(soft);
2885out3:
2886        kfree(control);
2887out2:
2888        if (serial)
2889                iounmap(serial);
2890        release_mem_region(tmp_addr1, sizeof(struct ioc4_serial));
2891out1:
2892
2893        return ret;
2894}
2895
2896
2897static struct ioc4_submodule ioc4_serial_submodule = {
2898        .is_name = "IOC4_serial",
2899        .is_owner = THIS_MODULE,
2900        .is_probe = ioc4_serial_attach_one,
2901        .is_remove = ioc4_serial_remove_one,
2902};
2903
2904/**
2905 * ioc4_serial_init - module init
2906 */
2907static int __init ioc4_serial_init(void)
2908{
2909        int ret;
2910
2911        /* register with serial core */
2912        if ((ret = uart_register_driver(&ioc4_uart_rs232)) < 0) {
2913                printk(KERN_WARNING
2914                        "%s: Couldn't register rs232 IOC4 serial driver\n",
2915                        __func__);
2916                goto out;
2917        }
2918        if ((ret = uart_register_driver(&ioc4_uart_rs422)) < 0) {
2919                printk(KERN_WARNING
2920                        "%s: Couldn't register rs422 IOC4 serial driver\n",
2921                        __func__);
2922                goto out_uart_rs232;
2923        }
2924
2925        /* register with IOC4 main module */
2926        ret = ioc4_register_submodule(&ioc4_serial_submodule);
2927        if (ret)
2928                goto out_uart_rs422;
2929        return 0;
2930
2931out_uart_rs422:
2932        uart_unregister_driver(&ioc4_uart_rs422);
2933out_uart_rs232:
2934        uart_unregister_driver(&ioc4_uart_rs232);
2935out:
2936        return ret;
2937}
2938
2939static void __exit ioc4_serial_exit(void)
2940{
2941        ioc4_unregister_submodule(&ioc4_serial_submodule);
2942        uart_unregister_driver(&ioc4_uart_rs232);
2943        uart_unregister_driver(&ioc4_uart_rs422);
2944}
2945
2946late_initcall(ioc4_serial_init); /* Call only after tty init is done */
2947module_exit(ioc4_serial_exit);
2948
2949MODULE_AUTHOR("Pat Gefre - Silicon Graphics Inc. (SGI) <pfg@sgi.com>");
2950MODULE_DESCRIPTION("Serial PCI driver module for SGI IOC4 Base-IO Card");
2951MODULE_LICENSE("GPL");
2952