1/* 2 * sp5100_tco: TCO timer driver for sp5100 chipsets. 3 * 4 * (c) Copyright 2009 Google Inc., All Rights Reserved. 5 * 6 * TCO timer driver for sp5100 chipsets 7 */ 8 9/* 10 * Some address definitions for the Watchdog 11 */ 12#define SP5100_WDT_MEM_MAP_SIZE 0x08 13#define SP5100_WDT_CONTROL(base) ((base) + 0x00) /* Watchdog Control */ 14#define SP5100_WDT_COUNT(base) ((base) + 0x04) /* Watchdog Count */ 15 16#define SP5100_WDT_START_STOP_BIT (1 << 0) 17#define SP5100_WDT_TRIGGER_BIT (1 << 7) 18 19#define SP5100_PM_IOPORTS_SIZE 0x02 20 21/* 22 * These two IO registers are hardcoded and there doesn't seem to be a way to 23 * read them from a register. 24 */ 25 26/* For SP5100/SB7x0 chipset */ 27#define SP5100_IO_PM_INDEX_REG 0xCD6 28#define SP5100_IO_PM_DATA_REG 0xCD7 29 30#define SP5100_SB_RESOURCE_MMIO_BASE 0x9C 31 32#define SP5100_PM_WATCHDOG_CONTROL 0x69 33#define SP5100_PM_WATCHDOG_BASE 0x6C 34 35#define SP5100_PM_WATCHDOG_FIRED (1 << 1) 36#define SP5100_PM_WATCHDOG_ACTION_RESET (1 << 2) 37 38#define SP5100_PCI_WATCHDOG_MISC_REG 0x41 39#define SP5100_PCI_WATCHDOG_DECODE_EN (1 << 3) 40 41#define SP5100_PM_WATCHDOG_DISABLE (1 << 0) 42#define SP5100_PM_WATCHDOG_SECOND_RES (3 << 1) 43 44#define SP5100_DEVNAME "SP5100 TCO" 45 46 47/* For SB8x0(or later) chipset */ 48#define SB800_IO_PM_INDEX_REG 0xCD6 49#define SB800_IO_PM_DATA_REG 0xCD7 50 51#define SB800_PM_ACPI_MMIO_EN 0x24 52#define SB800_PM_WATCHDOG_CONTROL 0x48 53#define SB800_PM_WATCHDOG_BASE 0x48 54#define SB800_PM_WATCHDOG_CONFIG 0x4C 55 56#define SB800_PCI_WATCHDOG_DECODE_EN (1 << 0) 57#define SB800_PM_WATCHDOG_DISABLE (1 << 2) 58#define SB800_PM_WATCHDOG_SECOND_RES (3 << 0) 59#define SB800_ACPI_MMIO_DECODE_EN (1 << 0) 60#define SB800_ACPI_MMIO_SEL (1 << 1) 61 62 63#define SB800_PM_WDT_MMIO_OFFSET 0xB00 64 65#define SB800_DEVNAME "SB800 TCO" 66