LXR linux/drivers/watchdog/w83627hf

   1/*
   2 *      w83627hf/thf WDT driver
   3 *
   4 *      (c) Copyright 2013 Guenter Roeck
   5 *              converted to watchdog infrastructure
   6 *
   7 *      (c) Copyright 2007 Vlad Drukker <vlad@storewiz.com>
   8 *              added support for W83627THF.
   9 *
  10 *      (c) Copyright 2003,2007 Pádraig Brady <P@draigBrady.com>
  11 *
  12 *      Based on advantechwdt.c which is based on wdt.c.
  13 *      Original copyright messages:
  14 *
  15 *      (c) Copyright 2000-2001 Marek Michalkiewicz <marekm@linux.org.pl>
  16 *
  17 *      (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>,
  18 *                                              All Rights Reserved.
  19 *
  20 *      This program is free software; you can redistribute it and/or
  21 *      modify it under the terms of the GNU General Public License
  22 *      as published by the Free Software Foundation; either version
  23 *      2 of the License, or (at your option) any later version.
  24 *
  25 *      Neither Alan Cox nor CymruNet Ltd. admit liability nor provide
  26 *      warranty for any of this software. This material is provided
  27 *      "AS-IS" and at no charge.
  28 *
  29 *      (c) Copyright 1995    Alan Cox <alan@lxorguk.ukuu.org.uk>
  30 */
  31
  32#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  33
  34#include <linux/module.h>
  35#include <linux/moduleparam.h>
  36#include <linux/types.h>
  37#include <linux/watchdog.h>
  38#include <linux/ioport.h>
  39#include <linux/notifier.h>
  40#include <linux/reboot.h>
  41#include <linux/init.h>
  42#include <linux/io.h>
  43
  44#define WATCHDOG_NAME "w83627hf/thf/hg/dhg WDT"
  45#define WATCHDOG_TIMEOUT 60             /* 60 sec default timeout */
  46
  47static int wdt_io;
  48static int cr_wdt_timeout;      /* WDT timeout register */
  49static int cr_wdt_control;      /* WDT control register */
  50
  51enum chips { w83627hf, w83627s, w83697hf, w83697ug, w83637hf, w83627thf,
  52             w83687thf, w83627ehf, w83627dhg, w83627uhg, w83667hg, w83627dhg_p,
  53             w83667hg_b, nct6775, nct6776, nct6779 };
  54
  55static int timeout;                     /* in seconds */
  56module_param(timeout, int, 0);
  57MODULE_PARM_DESC(timeout,
  58                "Watchdog timeout in seconds. 1 <= timeout <= 255, default="
  59                                __MODULE_STRING(WATCHDOG_TIMEOUT) ".");
  60
  61static bool nowayout = WATCHDOG_NOWAYOUT;
  62module_param(nowayout, bool, 0);
  63MODULE_PARM_DESC(nowayout,
  64                "Watchdog cannot be stopped once started (default="
  65                                __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  66
  67static int early_disable;
  68module_param(early_disable, int, 0);
  69MODULE_PARM_DESC(early_disable, "Disable watchdog at boot time (default=0)");
  70
  71/*
  72 *      Kernel methods.
  73 */
  74
  75#define WDT_EFER (wdt_io+0)   /* Extended Function Enable Registers */
  76#define WDT_EFIR (wdt_io+0)   /* Extended Function Index Register
  77                                                        (same as EFER) */
  78#define WDT_EFDR (WDT_EFIR+1) /* Extended Function Data Register */
  79
  80#define W83627HF_LD_WDT         0x08
  81
  82#define W83627HF_ID             0x52
  83#define W83627S_ID              0x59
  84#define W83697HF_ID             0x60
  85#define W83697UG_ID             0x68
  86#define W83637HF_ID             0x70
  87#define W83627THF_ID            0x82
  88#define W83687THF_ID            0x85
  89#define W83627EHF_ID            0x88
  90#define W83627DHG_ID            0xa0
  91#define W83627UHG_ID            0xa2
  92#define W83667HG_ID             0xa5
  93#define W83627DHG_P_ID          0xb0
  94#define W83667HG_B_ID           0xb3
  95#define NCT6775_ID              0xb4
  96#define NCT6776_ID              0xc3
  97#define NCT6779_ID              0xc5
  98
  99#define W83627HF_WDT_TIMEOUT    0xf6
 100#define W83697HF_WDT_TIMEOUT    0xf4
 101
 102#define W83627HF_WDT_CONTROL    0xf5
 103#define W83697HF_WDT_CONTROL    0xf3
 104
 105static void superio_outb(int reg, int val)
 106{
 107        outb(reg, WDT_EFER);
 108        outb(val, WDT_EFDR);
 109}
 110
 111static inline int superio_inb(int reg)
 112{
 113        outb(reg, WDT_EFER);
 114        return inb(WDT_EFDR);
 115}
 116
 117static int superio_enter(void)
 118{
 119        if (!request_muxed_region(wdt_io, 2, WATCHDOG_NAME))
 120                return -EBUSY;
 121
 122        outb_p(0x87, WDT_EFER); /* Enter extended function mode */
 123        outb_p(0x87, WDT_EFER); /* Again according to manual */
 124
 125        return 0;
 126}
 127
 128static void superio_select(int ld)
 129{
 130        superio_outb(0x07, ld);
 131}
 132
 133static void superio_exit(void)
 134{
 135        outb_p(0xAA, WDT_EFER); /* Leave extended function mode */
 136        release_region(wdt_io, 2);
 137}
 138
 139static int w83627hf_init(struct watchdog_device *wdog, enum chips chip)
 140{
 141        int ret;
 142        unsigned char t;
 143
 144        ret = superio_enter();
 145        if (ret)
 146                return ret;
 147
 148        superio_select(W83627HF_LD_WDT);
 149
 150        /* set CR30 bit 0 to activate GPIO2 */
 151        t = superio_inb(0x30);
 152        if (!(t & 0x01))
 153                superio_outb(0x30, t | 0x01);
 154
 155        switch (chip) {
 156        case w83627hf:
 157        case w83627s:
 158                t = superio_inb(0x2B) & ~0x10;
 159                superio_outb(0x2B, t); /* set GPIO24 to WDT0 */
 160                break;
 161        case w83697hf:
 162                /* Set pin 119 to WDTO# mode (= CR29, WDT0) */
 163                t = superio_inb(0x29) & ~0x60;
 164                t |= 0x20;
 165                superio_outb(0x29, t);
 166                break;
 167        case w83697ug:
 168                /* Set pin 118 to WDTO# mode */
 169                t = superio_inb(0x2b) & ~0x04;
 170                superio_outb(0x2b, t);
 171                break;
 172        case w83627thf:
 173                t = (superio_inb(0x2B) & ~0x08) | 0x04;
 174                superio_outb(0x2B, t); /* set GPIO3 to WDT0 */
 175                break;
 176        case w83627dhg:
 177        case w83627dhg_p:
 178                t = superio_inb(0x2D) & ~0x01; /* PIN77 -> WDT0# */
 179                superio_outb(0x2D, t); /* set GPIO5 to WDT0 */
 180                t = superio_inb(cr_wdt_control);
 181                t |= 0x02;      /* enable the WDTO# output low pulse
 182                                 * to the KBRST# pin */
 183                superio_outb(cr_wdt_control, t);
 184                break;
 185        case w83637hf:
 186                break;
 187        case w83687thf:
 188                t = superio_inb(0x2C) & ~0x80; /* PIN47 -> WDT0# */
 189                superio_outb(0x2C, t);
 190                break;
 191        case w83627ehf:
 192        case w83627uhg:
 193        case w83667hg:
 194        case w83667hg_b:
 195        case nct6775:
 196        case nct6776:
 197        case nct6779:
 198                /*
 199                 * These chips have a fixed WDTO# output pin (W83627UHG),
 200                 * or support more than one WDTO# output pin.
 201                 * Don't touch its configuration, and hope the BIOS
 202                 * does the right thing.
 203                 */
 204                t = superio_inb(cr_wdt_control);
 205                t |= 0x02;      /* enable the WDTO# output low pulse
 206                                 * to the KBRST# pin */
 207                superio_outb(cr_wdt_control, t);
 208                break;
 209        default:
 210                break;
 211        }
 212
 213        t = superio_inb(cr_wdt_timeout);
 214        if (t != 0) {
 215                if (early_disable) {
 216                        pr_warn("Stopping previously enabled watchdog until userland kicks in\n");
 217                        superio_outb(cr_wdt_timeout, 0);
 218                } else {
 219                        pr_info("Watchdog already running. Resetting timeout to %d sec\n",
 220                                wdog->timeout);
 221                        superio_outb(cr_wdt_timeout, wdog->timeout);
 222                }
 223        }
 224
 225        /* set second mode & disable keyboard turning off watchdog */
 226        t = superio_inb(cr_wdt_control) & ~0x0C;
 227        superio_outb(cr_wdt_control, t);
 228
 229        /* reset trigger, disable keyboard & mouse turning off watchdog */
 230        t = superio_inb(0xF7) & ~0xD0;
 231        superio_outb(0xF7, t);
 232
 233        superio_exit();
 234
 235        return 0;
 236}
 237
 238static int wdt_set_time(unsigned int timeout)
 239{
 240        int ret;
 241
 242        ret = superio_enter();
 243        if (ret)
 244                return ret;
 245
 246        superio_select(W83627HF_LD_WDT);
 247        superio_outb(cr_wdt_timeout, timeout);
 248        superio_exit();
 249
 250        return 0;
 251}
 252
 253static int wdt_start(struct watchdog_device *wdog)
 254{
 255        return wdt_set_time(wdog->timeout);
 256}
 257
 258static int wdt_stop(struct watchdog_device *wdog)
 259{
 260        return wdt_set_time(0);
 261}
 262
 263static int wdt_set_timeout(struct watchdog_device *wdog, unsigned int timeout)
 264{
 265        wdog->timeout = timeout;
 266
 267        return 0;
 268}
 269
 270static unsigned int wdt_get_time(struct watchdog_device *wdog)
 271{
 272        unsigned int timeleft;
 273        int ret;
 274
 275        ret = superio_enter();
 276        if (ret)
 277                return 0;
 278
 279        superio_select(W83627HF_LD_WDT);
 280        timeleft = superio_inb(cr_wdt_timeout);
 281        superio_exit();
 282
 283        return timeleft;
 284}
 285
 286/*
 287 *      Notifier for system down
 288 */
 289static int wdt_notify_sys(struct notifier_block *this, unsigned long code,
 290        void *unused)
 291{
 292        if (code == SYS_DOWN || code == SYS_HALT)
 293                wdt_set_time(0);        /* Turn the WDT off */
 294
 295        return NOTIFY_DONE;
 296}
 297
 298/*
 299 *      Kernel Interfaces
 300 */
 301
 302static struct watchdog_info wdt_info = {
 303        .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
 304        .identity = "W83627HF Watchdog",
 305};
 306
 307static struct watchdog_ops wdt_ops = {
 308        .owner = THIS_MODULE,
 309        .start = wdt_start,
 310        .stop = wdt_stop,
 311        .set_timeout = wdt_set_timeout,
 312        .get_timeleft = wdt_get_time,
 313};
 314
 315static struct watchdog_device wdt_dev = {
 316        .info = &wdt_info,
 317        .ops = &wdt_ops,
 318        .timeout = WATCHDOG_TIMEOUT,
 319        .min_timeout = 1,
 320        .max_timeout = 255,
 321};
 322
 323/*
 324 *      The WDT needs to learn about soft shutdowns in order to
 325 *      turn the timebomb registers off.
 326 */
 327
 328static struct notifier_block wdt_notifier = {
 329        .notifier_call = wdt_notify_sys,
 330};
 331
 332static int wdt_find(int addr)
 333{
 334        u8 val;
 335        int ret;
 336
 337        cr_wdt_timeout = W83627HF_WDT_TIMEOUT;
 338        cr_wdt_control = W83627HF_WDT_CONTROL;
 339
 340        ret = superio_enter();
 341        if (ret)
 342                return ret;
 343        superio_select(W83627HF_LD_WDT);
 344        val = superio_inb(0x20);
 345        switch (val) {
 346        case W83627HF_ID:
 347                ret = w83627hf;
 348                break;
 349        case W83627S_ID:
 350                ret = w83627s;
 351                break;
 352        case W83697HF_ID:
 353                ret = w83697hf;
 354                cr_wdt_timeout = W83697HF_WDT_TIMEOUT;
 355                cr_wdt_control = W83697HF_WDT_CONTROL;
 356                break;
 357        case W83697UG_ID:
 358                ret = w83697ug;
 359                cr_wdt_timeout = W83697HF_WDT_TIMEOUT;
 360                cr_wdt_control = W83697HF_WDT_CONTROL;
 361                break;
 362        case W83637HF_ID:
 363                ret = w83637hf;
 364                break;
 365        case W83627THF_ID:
 366                ret = w83627thf;
 367                break;
 368        case W83687THF_ID:
 369                ret = w83687thf;
 370                break;
 371        case W83627EHF_ID:
 372                ret = w83627ehf;
 373                break;
 374        case W83627DHG_ID:
 375                ret = w83627dhg;
 376                break;
 377        case W83627DHG_P_ID:
 378                ret = w83627dhg_p;
 379                break;
 380        case W83627UHG_ID:
 381                ret = w83627uhg;
 382                break;
 383        case W83667HG_ID:
 384                ret = w83667hg;
 385                break;
 386        case W83667HG_B_ID:
 387                ret = w83667hg_b;
 388                break;
 389        case NCT6775_ID:
 390                ret = nct6775;
 391                break;
 392        case NCT6776_ID:
 393                ret = nct6776;
 394                break;
 395        case NCT6779_ID:
 396                ret = nct6779;
 397                break;
 398        case 0xff:
 399                ret = -ENODEV;
 400                break;
 401        default:
 402                ret = -ENODEV;
 403                pr_err("Unsupported chip ID: 0x%02x\n", val);
 404                break;
 405        }
 406        superio_exit();
 407        return ret;
 408}
 409
 410static int __init wdt_init(void)
 411{
 412        int ret;
 413        int chip;
 414        const char * const chip_name[] = {
 415                "W83627HF",
 416                "W83627S",
 417                "W83697HF",
 418                "W83697UG",
 419                "W83637HF",
 420                "W83627THF",
 421                "W83687THF",
 422                "W83627EHF",
 423                "W83627DHG",
 424                "W83627UHG",
 425                "W83667HG",
 426                "W83667DHG-P",
 427                "W83667HG-B",
 428                "NCT6775",
 429                "NCT6776",
 430                "NCT6779",
 431        };
 432
 433        wdt_io = 0x2e;
 434        chip = wdt_find(0x2e);
 435        if (chip < 0) {
 436                wdt_io = 0x4e;
 437                chip = wdt_find(0x4e);
 438                if (chip < 0)
 439                        return chip;
 440        }
 441
 442        pr_info("WDT driver for %s Super I/O chip initialising\n",
 443                chip_name[chip]);
 444
 445        watchdog_init_timeout(&wdt_dev, timeout, NULL);
 446        watchdog_set_nowayout(&wdt_dev, nowayout);
 447
 448        ret = w83627hf_init(&wdt_dev, chip);
 449        if (ret) {
 450                pr_err("failed to initialize watchdog (err=%d)\n", ret);
 451                return ret;
 452        }
 453
 454        ret = register_reboot_notifier(&wdt_notifier);
 455        if (ret != 0) {
 456                pr_err("cannot register reboot notifier (err=%d)\n", ret);
 457                return ret;
 458        }
 459
 460        ret = watchdog_register_device(&wdt_dev);
 461        if (ret)
 462                goto unreg_reboot;
 463
 464        pr_info("initialized. timeout=%d sec (nowayout=%d)\n",
 465                wdt_dev.timeout, nowayout);
 466
 467        return ret;
 468
 469unreg_reboot:
 470        unregister_reboot_notifier(&wdt_notifier);
 471        return ret;
 472}
 473
 474static void __exit wdt_exit(void)
 475{
 476        watchdog_unregister_device(&wdt_dev);
 477        unregister_reboot_notifier(&wdt_notifier);
 478}
 479
 480module_init(wdt_init);
 481module_exit(wdt_exit);
 482
 483MODULE_LICENSE("GPL");
 484MODULE_AUTHOR("Pádraig  Brady <P@draigBrady.com>");
 485MODULE_DESCRIPTION("w83627hf/thf WDT driver");
 486