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17#include <linux/types.h>
18#include <linux/kernel.h>
19#include <linux/list.h>
20#include <linux/device.h>
21#include <linux/wait.h>
22#include <linux/spinlock.h>
23#include <linux/workqueue.h>
24#include <linux/export.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
27#include <linux/sched.h>
28#include <linux/platform_device.h>
29#include <linux/kthread.h>
30#include <linux/firmware.h>
31#include <linux/dma-mapping.h>
32#include <linux/debugfs.h>
33
34#include "sst-haswell-ipc.h"
35#include "sst-dsp.h"
36#include "sst-dsp-priv.h"
37
38
39#define IPC_GLB_TYPE_SHIFT 24
40#define IPC_GLB_TYPE_MASK (0x1f << IPC_GLB_TYPE_SHIFT)
41#define IPC_GLB_TYPE(x) (x << IPC_GLB_TYPE_SHIFT)
42
43
44#define IPC_GLB_REPLY_SHIFT 0
45#define IPC_GLB_REPLY_MASK (0x1f << IPC_GLB_REPLY_SHIFT)
46#define IPC_GLB_REPLY_TYPE(x) (x << IPC_GLB_REPLY_TYPE_SHIFT)
47
48
49#define IPC_STR_TYPE_SHIFT 20
50#define IPC_STR_TYPE_MASK (0xf << IPC_STR_TYPE_SHIFT)
51#define IPC_STR_TYPE(x) (x << IPC_STR_TYPE_SHIFT)
52#define IPC_STR_ID_SHIFT 16
53#define IPC_STR_ID_MASK (0xf << IPC_STR_ID_SHIFT)
54#define IPC_STR_ID(x) (x << IPC_STR_ID_SHIFT)
55
56
57#define IPC_STR_REPLY_SHIFT 0
58#define IPC_STR_REPLY_MASK (0x1f << IPC_STR_REPLY_SHIFT)
59
60
61#define IPC_STG_TYPE_SHIFT 12
62#define IPC_STG_TYPE_MASK (0xf << IPC_STG_TYPE_SHIFT)
63#define IPC_STG_TYPE(x) (x << IPC_STG_TYPE_SHIFT)
64#define IPC_STG_ID_SHIFT 10
65#define IPC_STG_ID_MASK (0x3 << IPC_STG_ID_SHIFT)
66#define IPC_STG_ID(x) (x << IPC_STG_ID_SHIFT)
67
68
69#define IPC_STG_REPLY_SHIFT 0
70#define IPC_STG_REPLY_MASK (0x1f << IPC_STG_REPLY_SHIFT)
71
72
73#define IPC_LOG_OP_SHIFT 20
74#define IPC_LOG_OP_MASK (0xf << IPC_LOG_OP_SHIFT)
75#define IPC_LOG_OP_TYPE(x) (x << IPC_LOG_OP_SHIFT)
76#define IPC_LOG_ID_SHIFT 16
77#define IPC_LOG_ID_MASK (0xf << IPC_LOG_ID_SHIFT)
78#define IPC_LOG_ID(x) (x << IPC_LOG_ID_SHIFT)
79
80
81#define IPC_TIMEOUT_MSECS 300
82#define IPC_BOOT_MSECS 200
83#define IPC_MSG_WAIT 0
84#define IPC_MSG_NOWAIT 1
85
86
87#define IPC_FW_READY (0x1 << 29)
88#define IPC_STATUS_MASK (0x3 << 30)
89
90#define IPC_EMPTY_LIST_SIZE 8
91#define IPC_MAX_STREAMS 4
92
93
94#define IPC_MAX_MAILBOX_BYTES 256
95
96
97enum ipc_glb_type {
98 IPC_GLB_GET_FW_VERSION = 0,
99 IPC_GLB_PERFORMANCE_MONITOR = 1,
100 IPC_GLB_ALLOCATE_STREAM = 3,
101 IPC_GLB_FREE_STREAM = 4,
102 IPC_GLB_GET_FW_CAPABILITIES = 5,
103 IPC_GLB_STREAM_MESSAGE = 6,
104
105 IPC_GLB_REQUEST_DUMP = 7,
106
107 IPC_GLB_RESTORE_CONTEXT = 8,
108 IPC_GLB_GET_DEVICE_FORMATS = 9,
109 IPC_GLB_SET_DEVICE_FORMATS = 10,
110 IPC_GLB_SHORT_REPLY = 11,
111 IPC_GLB_ENTER_DX_STATE = 12,
112 IPC_GLB_GET_MIXER_STREAM_INFO = 13,
113 IPC_GLB_DEBUG_LOG_MESSAGE = 14,
114 IPC_GLB_REQUEST_TRANSFER = 16,
115 IPC_GLB_MAX_IPC_MESSAGE_TYPE = 17,
116};
117
118enum ipc_glb_reply {
119 IPC_GLB_REPLY_SUCCESS = 0,
120 IPC_GLB_REPLY_ERROR_INVALID_PARAM = 1,
121 IPC_GLB_REPLY_UNKNOWN_MESSAGE_TYPE = 2,
122 IPC_GLB_REPLY_OUT_OF_RESOURCES = 3,
123 IPC_GLB_REPLY_BUSY = 4,
124 IPC_GLB_REPLY_PENDING = 5,
125 IPC_GLB_REPLY_FAILURE = 6,
126 IPC_GLB_REPLY_INVALID_REQUEST = 7,
127 IPC_GLB_REPLY_STAGE_UNINITIALIZED = 8,
128 IPC_GLB_REPLY_NOT_FOUND = 9,
129 IPC_GLB_REPLY_SOURCE_NOT_STARTED = 10,
130};
131
132
133enum ipc_str_operation {
134 IPC_STR_RESET = 0,
135 IPC_STR_PAUSE = 1,
136 IPC_STR_RESUME = 2,
137 IPC_STR_STAGE_MESSAGE = 3,
138 IPC_STR_NOTIFICATION = 4,
139 IPC_STR_MAX_MESSAGE
140};
141
142
143enum ipc_stg_operation {
144 IPC_STG_GET_VOLUME = 0,
145 IPC_STG_SET_VOLUME,
146 IPC_STG_SET_WRITE_POSITION,
147 IPC_STG_SET_FX_ENABLE,
148 IPC_STG_SET_FX_DISABLE,
149 IPC_STG_SET_FX_GET_PARAM,
150 IPC_STG_SET_FX_SET_PARAM,
151 IPC_STG_SET_FX_GET_INFO,
152 IPC_STG_MUTE_LOOPBACK,
153 IPC_STG_MAX_MESSAGE
154};
155
156
157enum ipc_stg_operation_notify {
158 IPC_POSITION_CHANGED = 0,
159 IPC_STG_GLITCH,
160 IPC_STG_MAX_NOTIFY
161};
162
163enum ipc_glitch_type {
164 IPC_GLITCH_UNDERRUN = 1,
165 IPC_GLITCH_DECODER_ERROR,
166 IPC_GLITCH_DOUBLED_WRITE_POS,
167 IPC_GLITCH_MAX
168};
169
170
171enum ipc_debug_operation {
172 IPC_DEBUG_ENABLE_LOG = 0,
173 IPC_DEBUG_DISABLE_LOG = 1,
174 IPC_DEBUG_REQUEST_LOG_DUMP = 2,
175 IPC_DEBUG_NOTIFY_LOG_DUMP = 3,
176 IPC_DEBUG_MAX_DEBUG_LOG
177};
178
179
180struct sst_hsw_ipc_fw_ready {
181 u32 inbox_offset;
182 u32 outbox_offset;
183 u32 inbox_size;
184 u32 outbox_size;
185 u32 fw_info_size;
186 u8 fw_info[1];
187} __attribute__((packed));
188
189struct ipc_message {
190 struct list_head list;
191 u32 header;
192
193
194 char tx_data[IPC_MAX_MAILBOX_BYTES];
195 size_t tx_size;
196 char rx_data[IPC_MAX_MAILBOX_BYTES];
197 size_t rx_size;
198
199 wait_queue_head_t waitq;
200 bool pending;
201 bool complete;
202 bool wait;
203 int errno;
204};
205
206struct sst_hsw_stream;
207struct sst_hsw;
208
209
210struct sst_hsw_stream {
211
212 struct sst_hsw_ipc_stream_alloc_req request;
213 struct sst_hsw_ipc_stream_alloc_reply reply;
214 struct sst_hsw_ipc_stream_free_req free_req;
215
216
217 u32 mute_volume[SST_HSW_NO_CHANNELS];
218 u32 mute[SST_HSW_NO_CHANNELS];
219
220
221 struct sst_hsw *hsw;
222 int host_id;
223 bool commited;
224 bool running;
225
226
227 struct work_struct notify_work;
228 u32 header;
229
230
231 struct sst_hsw_ipc_stream_set_position wpos;
232 struct sst_hsw_ipc_stream_get_position rpos;
233 struct sst_hsw_ipc_stream_glitch_position glitch;
234
235
236 struct sst_hsw_ipc_volume_req vol_req;
237
238
239 u32 (*notify_position)(struct sst_hsw_stream *stream, void *data);
240 void *pdata;
241
242 struct list_head node;
243};
244
245
246struct sst_hsw_log_stream {
247 dma_addr_t dma_addr;
248 unsigned char *dma_area;
249 unsigned char *ring_descr;
250 int pages;
251 int size;
252
253
254 struct work_struct notify_work;
255 wait_queue_head_t readers_wait_q;
256 struct mutex rw_mutex;
257
258 u32 last_pos;
259 u32 curr_pos;
260 u32 reader_pos;
261
262
263 u32 config[SST_HSW_FW_LOG_CONFIG_DWORDS];
264
265 struct sst_hsw *hsw;
266};
267
268
269struct sst_hsw {
270 struct device *dev;
271 struct sst_dsp *dsp;
272 struct platform_device *pdev_pcm;
273
274
275 struct sst_hsw_ipc_fw_ready fw_ready;
276 struct sst_hsw_ipc_fw_version version;
277 struct sst_module *scratch;
278 bool fw_done;
279
280
281 struct list_head stream_list;
282
283
284 struct sst_hsw_ipc_stream_info_reply mixer_info;
285 enum sst_hsw_volume_curve curve_type;
286 u32 curve_duration;
287 u32 mute[SST_HSW_NO_CHANNELS];
288 u32 mute_volume[SST_HSW_NO_CHANNELS];
289
290
291 struct sst_hsw_ipc_dx_reply dx;
292
293
294 wait_queue_head_t boot_wait;
295 bool boot_complete;
296 bool shutdown;
297
298
299 struct list_head tx_list;
300 struct list_head rx_list;
301 struct list_head empty_list;
302 wait_queue_head_t wait_txq;
303 struct task_struct *tx_thread;
304 struct kthread_worker kworker;
305 struct kthread_work kwork;
306 bool pending;
307 struct ipc_message *msg;
308
309
310 struct sst_hsw_log_stream log_stream;
311};
312
313#define CREATE_TRACE_POINTS
314#include <trace/events/hswadsp.h>
315
316static inline u32 msg_get_global_type(u32 msg)
317{
318 return (msg & IPC_GLB_TYPE_MASK) >> IPC_GLB_TYPE_SHIFT;
319}
320
321static inline u32 msg_get_global_reply(u32 msg)
322{
323 return (msg & IPC_GLB_REPLY_MASK) >> IPC_GLB_REPLY_SHIFT;
324}
325
326static inline u32 msg_get_stream_type(u32 msg)
327{
328 return (msg & IPC_STR_TYPE_MASK) >> IPC_STR_TYPE_SHIFT;
329}
330
331static inline u32 msg_get_stage_type(u32 msg)
332{
333 return (msg & IPC_STG_TYPE_MASK) >> IPC_STG_TYPE_SHIFT;
334}
335
336static inline u32 msg_set_stage_type(u32 msg, u32 type)
337{
338 return (msg & ~IPC_STG_TYPE_MASK) +
339 (type << IPC_STG_TYPE_SHIFT);
340}
341
342static inline u32 msg_get_stream_id(u32 msg)
343{
344 return (msg & IPC_STR_ID_MASK) >> IPC_STR_ID_SHIFT;
345}
346
347static inline u32 msg_get_notify_reason(u32 msg)
348{
349 return (msg & IPC_STG_TYPE_MASK) >> IPC_STG_TYPE_SHIFT;
350}
351
352u32 create_channel_map(enum sst_hsw_channel_config config)
353{
354 switch (config) {
355 case SST_HSW_CHANNEL_CONFIG_MONO:
356 return (0xFFFFFFF0 | SST_HSW_CHANNEL_CENTER);
357 case SST_HSW_CHANNEL_CONFIG_STEREO:
358 return (0xFFFFFF00 | SST_HSW_CHANNEL_LEFT
359 | (SST_HSW_CHANNEL_RIGHT << 4));
360 case SST_HSW_CHANNEL_CONFIG_2_POINT_1:
361 return (0xFFFFF000 | SST_HSW_CHANNEL_LEFT
362 | (SST_HSW_CHANNEL_RIGHT << 4)
363 | (SST_HSW_CHANNEL_LFE << 8 ));
364 case SST_HSW_CHANNEL_CONFIG_3_POINT_0:
365 return (0xFFFFF000 | SST_HSW_CHANNEL_LEFT
366 | (SST_HSW_CHANNEL_CENTER << 4)
367 | (SST_HSW_CHANNEL_RIGHT << 8));
368 case SST_HSW_CHANNEL_CONFIG_3_POINT_1:
369 return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
370 | (SST_HSW_CHANNEL_CENTER << 4)
371 | (SST_HSW_CHANNEL_RIGHT << 8)
372 | (SST_HSW_CHANNEL_LFE << 12));
373 case SST_HSW_CHANNEL_CONFIG_QUATRO:
374 return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
375 | (SST_HSW_CHANNEL_RIGHT << 4)
376 | (SST_HSW_CHANNEL_LEFT_SURROUND << 8)
377 | (SST_HSW_CHANNEL_RIGHT_SURROUND << 12));
378 case SST_HSW_CHANNEL_CONFIG_4_POINT_0:
379 return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
380 | (SST_HSW_CHANNEL_CENTER << 4)
381 | (SST_HSW_CHANNEL_RIGHT << 8)
382 | (SST_HSW_CHANNEL_CENTER_SURROUND << 12));
383 case SST_HSW_CHANNEL_CONFIG_5_POINT_0:
384 return (0xFFF00000 | SST_HSW_CHANNEL_LEFT
385 | (SST_HSW_CHANNEL_CENTER << 4)
386 | (SST_HSW_CHANNEL_RIGHT << 8)
387 | (SST_HSW_CHANNEL_LEFT_SURROUND << 12)
388 | (SST_HSW_CHANNEL_RIGHT_SURROUND << 16));
389 case SST_HSW_CHANNEL_CONFIG_5_POINT_1:
390 return (0xFF000000 | SST_HSW_CHANNEL_CENTER
391 | (SST_HSW_CHANNEL_LEFT << 4)
392 | (SST_HSW_CHANNEL_RIGHT << 8)
393 | (SST_HSW_CHANNEL_LEFT_SURROUND << 12)
394 | (SST_HSW_CHANNEL_RIGHT_SURROUND << 16)
395 | (SST_HSW_CHANNEL_LFE << 20));
396 case SST_HSW_CHANNEL_CONFIG_DUAL_MONO:
397 return (0xFFFFFF00 | SST_HSW_CHANNEL_LEFT
398 | (SST_HSW_CHANNEL_LEFT << 4));
399 default:
400 return 0xFFFFFFFF;
401 }
402}
403
404static struct sst_hsw_stream *get_stream_by_id(struct sst_hsw *hsw,
405 int stream_id)
406{
407 struct sst_hsw_stream *stream;
408
409 list_for_each_entry(stream, &hsw->stream_list, node) {
410 if (stream->reply.stream_hw_id == stream_id)
411 return stream;
412 }
413
414 return NULL;
415}
416
417static void ipc_shim_dbg(struct sst_hsw *hsw, const char *text)
418{
419 struct sst_dsp *sst = hsw->dsp;
420 u32 isr, ipcd, imrx, ipcx;
421
422 ipcx = sst_dsp_shim_read_unlocked(sst, SST_IPCX);
423 isr = sst_dsp_shim_read_unlocked(sst, SST_ISRX);
424 ipcd = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
425 imrx = sst_dsp_shim_read_unlocked(sst, SST_IMRX);
426
427 dev_err(hsw->dev, "ipc: --%s-- ipcx 0x%8.8x isr 0x%8.8x ipcd 0x%8.8x imrx 0x%8.8x\n",
428 text, ipcx, isr, ipcd, imrx);
429}
430
431
432static struct ipc_message *msg_get_empty(struct sst_hsw *hsw)
433{
434 struct ipc_message *msg = NULL;
435
436 if (!list_empty(&hsw->empty_list)) {
437 msg = list_first_entry(&hsw->empty_list, struct ipc_message,
438 list);
439 list_del(&msg->list);
440 }
441
442 return msg;
443}
444
445static void ipc_tx_msgs(struct kthread_work *work)
446{
447 struct sst_hsw *hsw =
448 container_of(work, struct sst_hsw, kwork);
449 struct ipc_message *msg;
450 unsigned long flags;
451 u32 ipcx;
452
453 spin_lock_irqsave(&hsw->dsp->spinlock, flags);
454
455 if (list_empty(&hsw->tx_list) || hsw->pending) {
456 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
457 return;
458 }
459
460
461 ipcx = sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCX);
462 if (ipcx & SST_IPCX_BUSY) {
463 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
464 return;
465 }
466
467 msg = list_first_entry(&hsw->tx_list, struct ipc_message, list);
468
469 list_move(&msg->list, &hsw->rx_list);
470
471
472 sst_dsp_outbox_write(hsw->dsp, msg->tx_data, msg->tx_size);
473 sst_dsp_ipc_msg_tx(hsw->dsp, msg->header | SST_IPCX_BUSY);
474
475 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
476}
477
478
479static void tx_msg_reply_complete(struct sst_hsw *hsw, struct ipc_message *msg)
480{
481 msg->complete = true;
482 trace_ipc_reply("completed", msg->header);
483
484 if (!msg->wait)
485 list_add_tail(&msg->list, &hsw->empty_list);
486 else
487 wake_up(&msg->waitq);
488}
489
490static int tx_wait_done(struct sst_hsw *hsw, struct ipc_message *msg,
491 void *rx_data)
492{
493 unsigned long flags;
494 int ret;
495
496
497 ret = wait_event_timeout(msg->waitq, msg->complete,
498 msecs_to_jiffies(IPC_TIMEOUT_MSECS));
499
500 spin_lock_irqsave(&hsw->dsp->spinlock, flags);
501 if (ret == 0) {
502 ipc_shim_dbg(hsw, "message timeout");
503
504 trace_ipc_error("error message timeout for", msg->header);
505 ret = -ETIMEDOUT;
506 } else {
507
508
509 if (msg->rx_size)
510 memcpy(rx_data, msg->rx_data, msg->rx_size);
511 ret = msg->errno;
512 }
513
514 list_add_tail(&msg->list, &hsw->empty_list);
515 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
516 return ret;
517}
518
519static int ipc_tx_message(struct sst_hsw *hsw, u32 header, void *tx_data,
520 size_t tx_bytes, void *rx_data, size_t rx_bytes, int wait)
521{
522 struct ipc_message *msg;
523 unsigned long flags;
524
525 spin_lock_irqsave(&hsw->dsp->spinlock, flags);
526
527 msg = msg_get_empty(hsw);
528 if (msg == NULL) {
529 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
530 return -EBUSY;
531 }
532
533 if (tx_bytes)
534 memcpy(msg->tx_data, tx_data, tx_bytes);
535
536 msg->header = header;
537 msg->tx_size = tx_bytes;
538 msg->rx_size = rx_bytes;
539 msg->wait = wait;
540 msg->errno = 0;
541 msg->pending = false;
542 msg->complete = false;
543
544 list_add_tail(&msg->list, &hsw->tx_list);
545 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
546
547 queue_kthread_work(&hsw->kworker, &hsw->kwork);
548
549 if (wait)
550 return tx_wait_done(hsw, msg, rx_data);
551 else
552 return 0;
553}
554
555static inline int ipc_tx_message_wait(struct sst_hsw *hsw, u32 header,
556 void *tx_data, size_t tx_bytes, void *rx_data, size_t rx_bytes)
557{
558 return ipc_tx_message(hsw, header, tx_data, tx_bytes, rx_data,
559 rx_bytes, 1);
560}
561
562static inline int ipc_tx_message_nowait(struct sst_hsw *hsw, u32 header,
563 void *tx_data, size_t tx_bytes)
564{
565 return ipc_tx_message(hsw, header, tx_data, tx_bytes, NULL, 0, 0);
566}
567
568static void hsw_fw_ready(struct sst_hsw *hsw, u32 header)
569{
570 struct sst_hsw_ipc_fw_ready fw_ready;
571 u32 offset;
572
573 offset = (header & 0x1FFFFFFF) << 3;
574
575 dev_dbg(hsw->dev, "ipc: DSP is ready 0x%8.8x offset %d\n",
576 header, offset);
577
578
579 sst_dsp_read(hsw->dsp, &fw_ready, offset, sizeof(fw_ready));
580
581 sst_dsp_mailbox_init(hsw->dsp, fw_ready.inbox_offset,
582 fw_ready.inbox_size, fw_ready.outbox_offset,
583 fw_ready.outbox_size);
584
585 hsw->boot_complete = true;
586 wake_up(&hsw->boot_wait);
587
588 dev_dbg(hsw->dev, " mailbox upstream 0x%x - size 0x%x\n",
589 fw_ready.inbox_offset, fw_ready.inbox_size);
590 dev_dbg(hsw->dev, " mailbox downstream 0x%x - size 0x%x\n",
591 fw_ready.outbox_offset, fw_ready.outbox_size);
592}
593
594static void hsw_notification_work(struct work_struct *work)
595{
596 struct sst_hsw_stream *stream = container_of(work,
597 struct sst_hsw_stream, notify_work);
598 struct sst_hsw_ipc_stream_glitch_position *glitch = &stream->glitch;
599 struct sst_hsw_ipc_stream_get_position *pos = &stream->rpos;
600 struct sst_hsw *hsw = stream->hsw;
601 u32 reason;
602
603 reason = msg_get_notify_reason(stream->header);
604
605 switch (reason) {
606 case IPC_STG_GLITCH:
607 trace_ipc_notification("DSP stream under/overrun",
608 stream->reply.stream_hw_id);
609 sst_dsp_inbox_read(hsw->dsp, glitch, sizeof(*glitch));
610
611 dev_err(hsw->dev, "glitch %d pos 0x%x write pos 0x%x\n",
612 glitch->glitch_type, glitch->present_pos,
613 glitch->write_pos);
614 break;
615
616 case IPC_POSITION_CHANGED:
617 trace_ipc_notification("DSP stream position changed for",
618 stream->reply.stream_hw_id);
619 sst_dsp_inbox_read(hsw->dsp, pos, sizeof(*pos));
620
621 if (stream->notify_position)
622 stream->notify_position(stream, stream->pdata);
623
624 break;
625 default:
626 dev_err(hsw->dev, "error: unknown notification 0x%x\n",
627 stream->header);
628 break;
629 }
630
631
632 sst_dsp_shim_update_bits_unlocked(hsw->dsp, SST_IPCD,
633 SST_IPCD_BUSY | SST_IPCD_DONE, SST_IPCD_DONE);
634
635
636 sst_dsp_shim_update_bits_unlocked(hsw->dsp, SST_IMRX, SST_IMRX_BUSY, 0);
637}
638
639static struct ipc_message *reply_find_msg(struct sst_hsw *hsw, u32 header)
640{
641 struct ipc_message *msg;
642
643
644 header &= ~(IPC_STATUS_MASK | IPC_GLB_REPLY_MASK);
645
646 if (list_empty(&hsw->rx_list)) {
647 dev_err(hsw->dev, "error: rx list empty but received 0x%x\n",
648 header);
649 return NULL;
650 }
651
652 list_for_each_entry(msg, &hsw->rx_list, list) {
653 if (msg->header == header)
654 return msg;
655 }
656
657 return NULL;
658}
659
660static void hsw_stream_update(struct sst_hsw *hsw, struct ipc_message *msg)
661{
662 struct sst_hsw_stream *stream;
663 u32 header = msg->header & ~(IPC_STATUS_MASK | IPC_GLB_REPLY_MASK);
664 u32 stream_id = msg_get_stream_id(header);
665 u32 stream_msg = msg_get_stream_type(header);
666
667 stream = get_stream_by_id(hsw, stream_id);
668 if (stream == NULL)
669 return;
670
671 switch (stream_msg) {
672 case IPC_STR_STAGE_MESSAGE:
673 case IPC_STR_NOTIFICATION:
674 case IPC_STR_RESET:
675 break;
676 case IPC_STR_PAUSE:
677 stream->running = false;
678 trace_ipc_notification("stream paused",
679 stream->reply.stream_hw_id);
680 break;
681 case IPC_STR_RESUME:
682 stream->running = true;
683 trace_ipc_notification("stream running",
684 stream->reply.stream_hw_id);
685 break;
686 }
687}
688
689static int hsw_process_reply(struct sst_hsw *hsw, u32 header)
690{
691 struct ipc_message *msg;
692 u32 reply = msg_get_global_reply(header);
693
694 trace_ipc_reply("processing -->", header);
695
696 msg = reply_find_msg(hsw, header);
697 if (msg == NULL) {
698 trace_ipc_error("error: can't find message header", header);
699 return -EIO;
700 }
701
702
703 switch (reply) {
704 case IPC_GLB_REPLY_PENDING:
705 trace_ipc_pending_reply("received", header);
706 msg->pending = true;
707 hsw->pending = true;
708 return 1;
709 case IPC_GLB_REPLY_SUCCESS:
710 if (msg->pending) {
711 trace_ipc_pending_reply("completed", header);
712 sst_dsp_inbox_read(hsw->dsp, msg->rx_data,
713 msg->rx_size);
714 hsw->pending = false;
715 } else {
716
717 sst_dsp_outbox_read(hsw->dsp, msg->rx_data,
718 msg->rx_size);
719 }
720 break;
721
722 case IPC_GLB_REPLY_UNKNOWN_MESSAGE_TYPE:
723 trace_ipc_error("error: unknown message type", header);
724 msg->errno = -EBADMSG;
725 break;
726 case IPC_GLB_REPLY_OUT_OF_RESOURCES:
727 trace_ipc_error("error: out of resources", header);
728 msg->errno = -ENOMEM;
729 break;
730 case IPC_GLB_REPLY_BUSY:
731 trace_ipc_error("error: reply busy", header);
732 msg->errno = -EBUSY;
733 break;
734 case IPC_GLB_REPLY_FAILURE:
735 trace_ipc_error("error: reply failure", header);
736 msg->errno = -EINVAL;
737 break;
738 case IPC_GLB_REPLY_STAGE_UNINITIALIZED:
739 trace_ipc_error("error: stage uninitialized", header);
740 msg->errno = -EINVAL;
741 break;
742 case IPC_GLB_REPLY_NOT_FOUND:
743 trace_ipc_error("error: reply not found", header);
744 msg->errno = -EINVAL;
745 break;
746 case IPC_GLB_REPLY_SOURCE_NOT_STARTED:
747 trace_ipc_error("error: source not started", header);
748 msg->errno = -EINVAL;
749 break;
750 case IPC_GLB_REPLY_INVALID_REQUEST:
751 trace_ipc_error("error: invalid request", header);
752 msg->errno = -EINVAL;
753 break;
754 case IPC_GLB_REPLY_ERROR_INVALID_PARAM:
755 trace_ipc_error("error: invalid parameter", header);
756 msg->errno = -EINVAL;
757 break;
758 default:
759 trace_ipc_error("error: unknown reply", header);
760 msg->errno = -EINVAL;
761 break;
762 }
763
764
765 hsw_stream_update(hsw, msg);
766
767
768 list_del(&msg->list);
769 tx_msg_reply_complete(hsw, msg);
770
771 return 1;
772}
773
774static int hsw_stream_message(struct sst_hsw *hsw, u32 header)
775{
776 u32 stream_msg, stream_id, stage_type;
777 struct sst_hsw_stream *stream;
778 int handled = 0;
779
780 stream_msg = msg_get_stream_type(header);
781 stream_id = msg_get_stream_id(header);
782 stage_type = msg_get_stage_type(header);
783
784 stream = get_stream_by_id(hsw, stream_id);
785 if (stream == NULL)
786 return handled;
787
788 stream->header = header;
789
790 switch (stream_msg) {
791 case IPC_STR_STAGE_MESSAGE:
792 dev_err(hsw->dev, "error: stage msg not implemented 0x%8.8x\n",
793 header);
794 break;
795 case IPC_STR_NOTIFICATION:
796 schedule_work(&stream->notify_work);
797 break;
798 default:
799
800 handled = hsw_process_reply(hsw, header);
801 break;
802 }
803
804 return handled;
805}
806
807static int hsw_log_message(struct sst_hsw *hsw, u32 header)
808{
809 u32 operation = (header & IPC_LOG_OP_MASK) >> IPC_LOG_OP_SHIFT;
810 struct sst_hsw_log_stream *stream = &hsw->log_stream;
811 int ret = 1;
812
813 if (operation != IPC_DEBUG_REQUEST_LOG_DUMP) {
814 dev_err(hsw->dev,
815 "error: log msg not implemented 0x%8.8x\n", header);
816 return 0;
817 }
818
819 mutex_lock(&stream->rw_mutex);
820 stream->last_pos = stream->curr_pos;
821 sst_dsp_inbox_read(
822 hsw->dsp, &stream->curr_pos, sizeof(stream->curr_pos));
823 mutex_unlock(&stream->rw_mutex);
824
825 schedule_work(&stream->notify_work);
826
827 return ret;
828}
829
830static int hsw_process_notification(struct sst_hsw *hsw)
831{
832 struct sst_dsp *sst = hsw->dsp;
833 u32 type, header;
834 int handled = 1;
835
836 header = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
837 type = msg_get_global_type(header);
838
839 trace_ipc_request("processing -->", header);
840
841
842 if (!hsw->boot_complete && header & IPC_FW_READY) {
843 hsw_fw_ready(hsw, header);
844 return handled;
845 }
846
847 switch (type) {
848 case IPC_GLB_GET_FW_VERSION:
849 case IPC_GLB_ALLOCATE_STREAM:
850 case IPC_GLB_FREE_STREAM:
851 case IPC_GLB_GET_FW_CAPABILITIES:
852 case IPC_GLB_REQUEST_DUMP:
853 case IPC_GLB_GET_DEVICE_FORMATS:
854 case IPC_GLB_SET_DEVICE_FORMATS:
855 case IPC_GLB_ENTER_DX_STATE:
856 case IPC_GLB_GET_MIXER_STREAM_INFO:
857 case IPC_GLB_MAX_IPC_MESSAGE_TYPE:
858 case IPC_GLB_RESTORE_CONTEXT:
859 case IPC_GLB_SHORT_REPLY:
860 dev_err(hsw->dev, "error: message type %d header 0x%x\n",
861 type, header);
862 break;
863 case IPC_GLB_STREAM_MESSAGE:
864 handled = hsw_stream_message(hsw, header);
865 break;
866 case IPC_GLB_DEBUG_LOG_MESSAGE:
867 handled = hsw_log_message(hsw, header);
868 break;
869 default:
870 dev_err(hsw->dev, "error: unexpected type %d hdr 0x%8.8x\n",
871 type, header);
872 break;
873 }
874
875 return handled;
876}
877
878static irqreturn_t hsw_irq_thread(int irq, void *context)
879{
880 struct sst_dsp *sst = (struct sst_dsp *) context;
881 struct sst_hsw *hsw = sst_dsp_get_thread_context(sst);
882 u32 ipcx, ipcd;
883 int handled;
884 unsigned long flags;
885
886 spin_lock_irqsave(&sst->spinlock, flags);
887
888 ipcx = sst_dsp_ipc_msg_rx(hsw->dsp);
889 ipcd = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
890
891
892 if (ipcx & SST_IPCX_DONE) {
893
894
895 handled = hsw_process_reply(hsw, ipcx);
896
897 if (handled > 0) {
898
899 sst_dsp_shim_update_bits_unlocked(sst, SST_IPCX,
900 SST_IPCX_DONE, 0);
901
902
903 sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
904 SST_IMRX_DONE, 0);
905 }
906 }
907
908
909 if (ipcd & SST_IPCD_BUSY) {
910
911
912 handled = hsw_process_notification(hsw);
913
914
915 if (handled > 0) {
916 sst_dsp_shim_update_bits_unlocked(sst, SST_IPCD,
917 SST_IPCD_BUSY | SST_IPCD_DONE, SST_IPCD_DONE);
918
919
920 sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
921 SST_IMRX_BUSY, 0);
922 }
923 }
924
925 spin_unlock_irqrestore(&sst->spinlock, flags);
926
927
928 queue_kthread_work(&hsw->kworker, &hsw->kwork);
929
930 return IRQ_HANDLED;
931}
932
933int sst_hsw_fw_get_version(struct sst_hsw *hsw,
934 struct sst_hsw_ipc_fw_version *version)
935{
936 int ret;
937
938 ret = ipc_tx_message_wait(hsw, IPC_GLB_TYPE(IPC_GLB_GET_FW_VERSION),
939 NULL, 0, version, sizeof(*version));
940 if (ret < 0)
941 dev_err(hsw->dev, "error: get version failed\n");
942
943 return ret;
944}
945
946
947int sst_hsw_stream_mute(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
948 u32 stage_id, u32 channel)
949{
950 int ret;
951
952 ret = sst_hsw_stream_get_volume(hsw, stream, stage_id, channel,
953 &stream->mute_volume[channel]);
954 if (ret < 0)
955 return ret;
956
957 ret = sst_hsw_stream_set_volume(hsw, stream, stage_id, channel, 0);
958 if (ret < 0) {
959 dev_err(hsw->dev, "error: can't unmute stream %d channel %d\n",
960 stream->reply.stream_hw_id, channel);
961 return ret;
962 }
963
964 stream->mute[channel] = 1;
965 return 0;
966}
967
968int sst_hsw_stream_unmute(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
969 u32 stage_id, u32 channel)
970
971{
972 int ret;
973
974 stream->mute[channel] = 0;
975 ret = sst_hsw_stream_set_volume(hsw, stream, stage_id, channel,
976 stream->mute_volume[channel]);
977 if (ret < 0) {
978 dev_err(hsw->dev, "error: can't unmute stream %d channel %d\n",
979 stream->reply.stream_hw_id, channel);
980 return ret;
981 }
982
983 return 0;
984}
985
986int sst_hsw_stream_get_volume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
987 u32 stage_id, u32 channel, u32 *volume)
988{
989 if (channel > 1)
990 return -EINVAL;
991
992 sst_dsp_read(hsw->dsp, volume,
993 stream->reply.volume_register_address[channel],
994 sizeof(*volume));
995
996 return 0;
997}
998
999int sst_hsw_stream_set_volume_curve(struct sst_hsw *hsw,
1000 struct sst_hsw_stream *stream, u64 curve_duration,
1001 enum sst_hsw_volume_curve curve)
1002{
1003
1004 stream->vol_req.curve_duration = curve_duration;
1005 stream->vol_req.curve_type = curve;
1006
1007 return 0;
1008}
1009
1010
1011int sst_hsw_stream_set_volume(struct sst_hsw *hsw,
1012 struct sst_hsw_stream *stream, u32 stage_id, u32 channel, u32 volume)
1013{
1014 struct sst_hsw_ipc_volume_req *req;
1015 u32 header;
1016 int ret;
1017
1018 trace_ipc_request("set stream volume", stream->reply.stream_hw_id);
1019
1020 if (channel > 1)
1021 return -EINVAL;
1022
1023 if (stream->mute[channel]) {
1024 stream->mute_volume[channel] = volume;
1025 return 0;
1026 }
1027
1028 header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
1029 IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
1030 header |= (stream->reply.stream_hw_id << IPC_STR_ID_SHIFT);
1031 header |= (IPC_STG_SET_VOLUME << IPC_STG_TYPE_SHIFT);
1032 header |= (stage_id << IPC_STG_ID_SHIFT);
1033
1034 req = &stream->vol_req;
1035 req->channel = channel;
1036 req->target_volume = volume;
1037
1038 ret = ipc_tx_message_wait(hsw, header, req, sizeof(*req), NULL, 0);
1039 if (ret < 0) {
1040 dev_err(hsw->dev, "error: set stream volume failed\n");
1041 return ret;
1042 }
1043
1044 return 0;
1045}
1046
1047int sst_hsw_mixer_mute(struct sst_hsw *hsw, u32 stage_id, u32 channel)
1048{
1049 int ret;
1050
1051 ret = sst_hsw_mixer_get_volume(hsw, stage_id, channel,
1052 &hsw->mute_volume[channel]);
1053 if (ret < 0)
1054 return ret;
1055
1056 ret = sst_hsw_mixer_set_volume(hsw, stage_id, channel, 0);
1057 if (ret < 0) {
1058 dev_err(hsw->dev, "error: failed to unmute mixer channel %d\n",
1059 channel);
1060 return ret;
1061 }
1062
1063 hsw->mute[channel] = 1;
1064 return 0;
1065}
1066
1067int sst_hsw_mixer_unmute(struct sst_hsw *hsw, u32 stage_id, u32 channel)
1068{
1069 int ret;
1070
1071 ret = sst_hsw_mixer_set_volume(hsw, stage_id, channel,
1072 hsw->mixer_info.volume_register_address[channel]);
1073 if (ret < 0) {
1074 dev_err(hsw->dev, "error: failed to unmute mixer channel %d\n",
1075 channel);
1076 return ret;
1077 }
1078
1079 hsw->mute[channel] = 0;
1080 return 0;
1081}
1082
1083int sst_hsw_mixer_get_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
1084 u32 *volume)
1085{
1086 if (channel > 1)
1087 return -EINVAL;
1088
1089 sst_dsp_read(hsw->dsp, volume,
1090 hsw->mixer_info.volume_register_address[channel],
1091 sizeof(*volume));
1092
1093 return 0;
1094}
1095
1096int sst_hsw_mixer_set_volume_curve(struct sst_hsw *hsw,
1097 u64 curve_duration, enum sst_hsw_volume_curve curve)
1098{
1099
1100 hsw->curve_duration = curve_duration;
1101 hsw->curve_type = curve;
1102
1103 return 0;
1104}
1105
1106
1107int sst_hsw_mixer_set_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
1108 u32 volume)
1109{
1110 struct sst_hsw_ipc_volume_req req;
1111 u32 header;
1112 int ret;
1113
1114 trace_ipc_request("set mixer volume", volume);
1115
1116
1117 if (channel == 2) {
1118 if (hsw->mute[0] && hsw->mute[1]) {
1119 hsw->mute_volume[0] = hsw->mute_volume[1] = volume;
1120 return 0;
1121 } else if (hsw->mute[0])
1122 req.channel = 1;
1123 else if (hsw->mute[1])
1124 req.channel = 0;
1125 else
1126 req.channel = 0xffffffff;
1127 } else {
1128
1129 if (hsw->mute[channel]) {
1130 hsw->mute_volume[channel] = volume;
1131 return 0;
1132 }
1133 req.channel = channel;
1134 }
1135
1136 header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
1137 IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
1138 header |= (hsw->mixer_info.mixer_hw_id << IPC_STR_ID_SHIFT);
1139 header |= (IPC_STG_SET_VOLUME << IPC_STG_TYPE_SHIFT);
1140 header |= (stage_id << IPC_STG_ID_SHIFT);
1141
1142 req.curve_duration = hsw->curve_duration;
1143 req.curve_type = hsw->curve_type;
1144 req.target_volume = volume;
1145
1146 ret = ipc_tx_message_wait(hsw, header, &req, sizeof(req), NULL, 0);
1147 if (ret < 0) {
1148 dev_err(hsw->dev, "error: set mixer volume failed\n");
1149 return ret;
1150 }
1151
1152 return 0;
1153}
1154
1155
1156struct sst_hsw_stream *sst_hsw_stream_new(struct sst_hsw *hsw, int id,
1157 u32 (*notify_position)(struct sst_hsw_stream *stream, void *data),
1158 void *data)
1159{
1160 struct sst_hsw_stream *stream;
1161 struct sst_dsp *sst = hsw->dsp;
1162 unsigned long flags;
1163
1164 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
1165 if (stream == NULL)
1166 return NULL;
1167
1168 spin_lock_irqsave(&sst->spinlock, flags);
1169 list_add(&stream->node, &hsw->stream_list);
1170 stream->notify_position = notify_position;
1171 stream->pdata = data;
1172 stream->hsw = hsw;
1173 stream->host_id = id;
1174
1175
1176 INIT_WORK(&stream->notify_work, hsw_notification_work);
1177 spin_unlock_irqrestore(&sst->spinlock, flags);
1178
1179 return stream;
1180}
1181
1182int sst_hsw_stream_free(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1183{
1184 u32 header;
1185 int ret = 0;
1186 struct sst_dsp *sst = hsw->dsp;
1187 unsigned long flags;
1188
1189
1190 if (!stream->commited)
1191 goto out;
1192
1193 trace_ipc_request("stream free", stream->host_id);
1194
1195 stream->free_req.stream_id = stream->reply.stream_hw_id;
1196 header = IPC_GLB_TYPE(IPC_GLB_FREE_STREAM);
1197
1198 ret = ipc_tx_message_wait(hsw, header, &stream->free_req,
1199 sizeof(stream->free_req), NULL, 0);
1200 if (ret < 0) {
1201 dev_err(hsw->dev, "error: free stream %d failed\n",
1202 stream->free_req.stream_id);
1203 return -EAGAIN;
1204 }
1205
1206 trace_hsw_stream_free_req(stream, &stream->free_req);
1207
1208out:
1209 cancel_work_sync(&stream->notify_work);
1210 spin_lock_irqsave(&sst->spinlock, flags);
1211 list_del(&stream->node);
1212 kfree(stream);
1213 spin_unlock_irqrestore(&sst->spinlock, flags);
1214
1215 return ret;
1216}
1217
1218int sst_hsw_stream_set_bits(struct sst_hsw *hsw,
1219 struct sst_hsw_stream *stream, enum sst_hsw_bitdepth bits)
1220{
1221 if (stream->commited) {
1222 dev_err(hsw->dev, "error: stream committed for set bits\n");
1223 return -EINVAL;
1224 }
1225
1226 stream->request.format.bitdepth = bits;
1227 return 0;
1228}
1229
1230int sst_hsw_stream_set_channels(struct sst_hsw *hsw,
1231 struct sst_hsw_stream *stream, int channels)
1232{
1233 if (stream->commited) {
1234 dev_err(hsw->dev, "error: stream committed for set channels\n");
1235 return -EINVAL;
1236 }
1237
1238
1239 if (channels != 2)
1240 return -EINVAL;
1241
1242 stream->request.format.ch_num = channels;
1243 return 0;
1244}
1245
1246int sst_hsw_stream_set_rate(struct sst_hsw *hsw,
1247 struct sst_hsw_stream *stream, int rate)
1248{
1249 if (stream->commited) {
1250 dev_err(hsw->dev, "error: stream committed for set rate\n");
1251 return -EINVAL;
1252 }
1253
1254 stream->request.format.frequency = rate;
1255 return 0;
1256}
1257
1258int sst_hsw_stream_set_map_config(struct sst_hsw *hsw,
1259 struct sst_hsw_stream *stream, u32 map,
1260 enum sst_hsw_channel_config config)
1261{
1262 if (stream->commited) {
1263 dev_err(hsw->dev, "error: stream committed for set map\n");
1264 return -EINVAL;
1265 }
1266
1267 stream->request.format.map = map;
1268 stream->request.format.config = config;
1269 return 0;
1270}
1271
1272int sst_hsw_stream_set_style(struct sst_hsw *hsw,
1273 struct sst_hsw_stream *stream, enum sst_hsw_interleaving style)
1274{
1275 if (stream->commited) {
1276 dev_err(hsw->dev, "error: stream committed for set style\n");
1277 return -EINVAL;
1278 }
1279
1280 stream->request.format.style = style;
1281 return 0;
1282}
1283
1284int sst_hsw_stream_set_valid(struct sst_hsw *hsw,
1285 struct sst_hsw_stream *stream, u32 bits)
1286{
1287 if (stream->commited) {
1288 dev_err(hsw->dev, "error: stream committed for set valid bits\n");
1289 return -EINVAL;
1290 }
1291
1292 stream->request.format.valid_bit = bits;
1293 return 0;
1294}
1295
1296
1297int sst_hsw_stream_format(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1298 enum sst_hsw_stream_path_id path_id,
1299 enum sst_hsw_stream_type stream_type,
1300 enum sst_hsw_stream_format format_id)
1301{
1302 if (stream->commited) {
1303 dev_err(hsw->dev, "error: stream committed for set format\n");
1304 return -EINVAL;
1305 }
1306
1307 stream->request.path_id = path_id;
1308 stream->request.stream_type = stream_type;
1309 stream->request.format_id = format_id;
1310
1311 trace_hsw_stream_alloc_request(stream, &stream->request);
1312
1313 return 0;
1314}
1315
1316int sst_hsw_stream_buffer(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1317 u32 ring_pt_address, u32 num_pages,
1318 u32 ring_size, u32 ring_offset, u32 ring_first_pfn)
1319{
1320 if (stream->commited) {
1321 dev_err(hsw->dev, "error: stream committed for buffer\n");
1322 return -EINVAL;
1323 }
1324
1325 stream->request.ringinfo.ring_pt_address = ring_pt_address;
1326 stream->request.ringinfo.num_pages = num_pages;
1327 stream->request.ringinfo.ring_size = ring_size;
1328 stream->request.ringinfo.ring_offset = ring_offset;
1329 stream->request.ringinfo.ring_first_pfn = ring_first_pfn;
1330
1331 trace_hsw_stream_buffer(stream);
1332
1333 return 0;
1334}
1335
1336int sst_hsw_stream_set_module_info(struct sst_hsw *hsw,
1337 struct sst_hsw_stream *stream, enum sst_hsw_module_id module_id,
1338 u32 entry_point)
1339{
1340 struct sst_hsw_module_map *map = &stream->request.map;
1341
1342 if (stream->commited) {
1343 dev_err(hsw->dev, "error: stream committed for set module\n");
1344 return -EINVAL;
1345 }
1346
1347
1348 map->module_entries_count = 1;
1349 map->module_entries[0].module_id = module_id;
1350 map->module_entries[0].entry_point = entry_point;
1351
1352 return 0;
1353}
1354
1355int sst_hsw_stream_set_pmemory_info(struct sst_hsw *hsw,
1356 struct sst_hsw_stream *stream, u32 offset, u32 size)
1357{
1358 if (stream->commited) {
1359 dev_err(hsw->dev, "error: stream committed for set pmem\n");
1360 return -EINVAL;
1361 }
1362
1363 stream->request.persistent_mem.offset = offset;
1364 stream->request.persistent_mem.size = size;
1365
1366 return 0;
1367}
1368
1369int sst_hsw_stream_set_smemory_info(struct sst_hsw *hsw,
1370 struct sst_hsw_stream *stream, u32 offset, u32 size)
1371{
1372 if (stream->commited) {
1373 dev_err(hsw->dev, "error: stream committed for set smem\n");
1374 return -EINVAL;
1375 }
1376
1377 stream->request.scratch_mem.offset = offset;
1378 stream->request.scratch_mem.size = size;
1379
1380 return 0;
1381}
1382
1383int sst_hsw_stream_commit(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1384{
1385 struct sst_hsw_ipc_stream_alloc_req *str_req = &stream->request;
1386 struct sst_hsw_ipc_stream_alloc_reply *reply = &stream->reply;
1387 u32 header;
1388 int ret;
1389
1390 trace_ipc_request("stream alloc", stream->host_id);
1391
1392 header = IPC_GLB_TYPE(IPC_GLB_ALLOCATE_STREAM);
1393
1394 ret = ipc_tx_message_wait(hsw, header, str_req, sizeof(*str_req),
1395 reply, sizeof(*reply));
1396 if (ret < 0) {
1397 dev_err(hsw->dev, "error: stream commit failed\n");
1398 return ret;
1399 }
1400
1401 stream->commited = 1;
1402 trace_hsw_stream_alloc_reply(stream);
1403
1404 return 0;
1405}
1406
1407
1408
1409int sst_hsw_stream_get_hw_id(struct sst_hsw *hsw,
1410 struct sst_hsw_stream *stream)
1411{
1412 return stream->reply.stream_hw_id;
1413}
1414
1415int sst_hsw_stream_get_mixer_id(struct sst_hsw *hsw,
1416 struct sst_hsw_stream *stream)
1417{
1418 return stream->reply.mixer_hw_id;
1419}
1420
1421u32 sst_hsw_stream_get_read_reg(struct sst_hsw *hsw,
1422 struct sst_hsw_stream *stream)
1423{
1424 return stream->reply.read_position_register_address;
1425}
1426
1427u32 sst_hsw_stream_get_pointer_reg(struct sst_hsw *hsw,
1428 struct sst_hsw_stream *stream)
1429{
1430 return stream->reply.presentation_position_register_address;
1431}
1432
1433u32 sst_hsw_stream_get_peak_reg(struct sst_hsw *hsw,
1434 struct sst_hsw_stream *stream, u32 channel)
1435{
1436 if (channel >= 2)
1437 return 0;
1438
1439 return stream->reply.peak_meter_register_address[channel];
1440}
1441
1442u32 sst_hsw_stream_get_vol_reg(struct sst_hsw *hsw,
1443 struct sst_hsw_stream *stream, u32 channel)
1444{
1445 if (channel >= 2)
1446 return 0;
1447
1448 return stream->reply.volume_register_address[channel];
1449}
1450
1451int sst_hsw_mixer_get_info(struct sst_hsw *hsw)
1452{
1453 struct sst_hsw_ipc_stream_info_reply *reply;
1454 u32 header;
1455 int ret;
1456
1457 reply = &hsw->mixer_info;
1458 header = IPC_GLB_TYPE(IPC_GLB_GET_MIXER_STREAM_INFO);
1459
1460 trace_ipc_request("get global mixer info", 0);
1461
1462 ret = ipc_tx_message_wait(hsw, header, NULL, 0, reply, sizeof(*reply));
1463 if (ret < 0) {
1464 dev_err(hsw->dev, "error: get stream info failed\n");
1465 return ret;
1466 }
1467
1468 trace_hsw_mixer_info_reply(reply);
1469
1470 return 0;
1471}
1472
1473
1474static int sst_hsw_stream_operations(struct sst_hsw *hsw, int type,
1475 int stream_id, int wait)
1476{
1477 u32 header;
1478
1479 header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) | IPC_STR_TYPE(type);
1480 header |= (stream_id << IPC_STR_ID_SHIFT);
1481
1482 if (wait)
1483 return ipc_tx_message_wait(hsw, header, NULL, 0, NULL, 0);
1484 else
1485 return ipc_tx_message_nowait(hsw, header, NULL, 0);
1486}
1487
1488
1489int sst_hsw_stream_pause(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1490 int wait)
1491{
1492 int ret;
1493
1494 trace_ipc_request("stream pause", stream->reply.stream_hw_id);
1495
1496 ret = sst_hsw_stream_operations(hsw, IPC_STR_PAUSE,
1497 stream->reply.stream_hw_id, wait);
1498 if (ret < 0)
1499 dev_err(hsw->dev, "error: failed to pause stream %d\n",
1500 stream->reply.stream_hw_id);
1501
1502 return ret;
1503}
1504
1505int sst_hsw_stream_resume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1506 int wait)
1507{
1508 int ret;
1509
1510 trace_ipc_request("stream resume", stream->reply.stream_hw_id);
1511
1512 ret = sst_hsw_stream_operations(hsw, IPC_STR_RESUME,
1513 stream->reply.stream_hw_id, wait);
1514 if (ret < 0)
1515 dev_err(hsw->dev, "error: failed to resume stream %d\n",
1516 stream->reply.stream_hw_id);
1517
1518 return ret;
1519}
1520
1521int sst_hsw_stream_reset(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1522{
1523 int ret, tries = 10;
1524
1525
1526 if (!stream->commited)
1527 return 0;
1528
1529
1530 while (stream->running && tries--)
1531 msleep(1);
1532 if (!tries) {
1533 dev_err(hsw->dev, "error: reset stream %d still running\n",
1534 stream->reply.stream_hw_id);
1535 return -EINVAL;
1536 }
1537
1538 trace_ipc_request("stream reset", stream->reply.stream_hw_id);
1539
1540 ret = sst_hsw_stream_operations(hsw, IPC_STR_RESET,
1541 stream->reply.stream_hw_id, 1);
1542 if (ret < 0)
1543 dev_err(hsw->dev, "error: failed to reset stream %d\n",
1544 stream->reply.stream_hw_id);
1545 return ret;
1546}
1547
1548
1549u32 sst_hsw_get_dsp_position(struct sst_hsw *hsw,
1550 struct sst_hsw_stream *stream)
1551{
1552 u32 rpos;
1553
1554 sst_dsp_read(hsw->dsp, &rpos,
1555 stream->reply.read_position_register_address, sizeof(rpos));
1556
1557 return rpos;
1558}
1559
1560
1561u64 sst_hsw_get_dsp_presentation_position(struct sst_hsw *hsw,
1562 struct sst_hsw_stream *stream)
1563{
1564 u64 ppos;
1565
1566 sst_dsp_read(hsw->dsp, &ppos,
1567 stream->reply.presentation_position_register_address,
1568 sizeof(ppos));
1569
1570 return ppos;
1571}
1572
1573int sst_hsw_stream_set_write_position(struct sst_hsw *hsw,
1574 struct sst_hsw_stream *stream, u32 stage_id, u32 position)
1575{
1576 u32 header;
1577 int ret;
1578
1579 trace_stream_write_position(stream->reply.stream_hw_id, position);
1580
1581 header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
1582 IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
1583 header |= (stream->reply.stream_hw_id << IPC_STR_ID_SHIFT);
1584 header |= (IPC_STG_SET_WRITE_POSITION << IPC_STG_TYPE_SHIFT);
1585 header |= (stage_id << IPC_STG_ID_SHIFT);
1586 stream->wpos.position = position;
1587
1588 ret = ipc_tx_message_nowait(hsw, header, &stream->wpos,
1589 sizeof(stream->wpos));
1590 if (ret < 0)
1591 dev_err(hsw->dev, "error: stream %d set position %d failed\n",
1592 stream->reply.stream_hw_id, position);
1593
1594 return ret;
1595}
1596
1597
1598int sst_hsw_device_set_config(struct sst_hsw *hsw,
1599 enum sst_hsw_device_id dev, enum sst_hsw_device_mclk mclk,
1600 enum sst_hsw_device_mode mode, u32 clock_divider)
1601{
1602 struct sst_hsw_ipc_device_config_req config;
1603 u32 header;
1604 int ret;
1605
1606 trace_ipc_request("set device config", dev);
1607
1608 config.ssp_interface = dev;
1609 config.clock_frequency = mclk;
1610 config.mode = mode;
1611 config.clock_divider = clock_divider;
1612
1613 trace_hsw_device_config_req(&config);
1614
1615 header = IPC_GLB_TYPE(IPC_GLB_SET_DEVICE_FORMATS);
1616
1617 ret = ipc_tx_message_wait(hsw, header, &config, sizeof(config),
1618 NULL, 0);
1619 if (ret < 0)
1620 dev_err(hsw->dev, "error: set device formats failed\n");
1621
1622 return ret;
1623}
1624EXPORT_SYMBOL_GPL(sst_hsw_device_set_config);
1625
1626
1627int sst_hsw_dx_set_state(struct sst_hsw *hsw,
1628 enum sst_hsw_dx_state state, struct sst_hsw_ipc_dx_reply *dx)
1629{
1630 u32 header, state_;
1631 int ret;
1632
1633 header = IPC_GLB_TYPE(IPC_GLB_ENTER_DX_STATE);
1634 state_ = state;
1635
1636 trace_ipc_request("PM enter Dx state", state);
1637
1638 ret = ipc_tx_message_wait(hsw, header, &state_, sizeof(state_),
1639 dx, sizeof(*dx));
1640 if (ret < 0) {
1641 dev_err(hsw->dev, "ipc: error set dx state %d failed\n", state);
1642 return ret;
1643 }
1644
1645 dev_dbg(hsw->dev, "ipc: got %d entry numbers for state %d\n",
1646 dx->entries_no, state);
1647
1648 memcpy(&hsw->dx, dx, sizeof(*dx));
1649 return 0;
1650}
1651
1652
1653int sst_hsw_dx_get_state(struct sst_hsw *hsw, u32 item,
1654 u32 *offset, u32 *size, u32 *source)
1655{
1656 struct sst_hsw_ipc_dx_memory_item *dx_mem;
1657 struct sst_hsw_ipc_dx_reply *dx_reply;
1658 int entry_no;
1659
1660 dx_reply = &hsw->dx;
1661 entry_no = dx_reply->entries_no;
1662
1663 trace_ipc_request("PM get Dx state", entry_no);
1664
1665 if (item >= entry_no)
1666 return -EINVAL;
1667
1668 dx_mem = &dx_reply->mem_info[item];
1669 *offset = dx_mem->offset;
1670 *size = dx_mem->size;
1671 *source = dx_mem->source;
1672
1673 return 0;
1674}
1675
1676static int msg_empty_list_init(struct sst_hsw *hsw)
1677{
1678 int i;
1679
1680 hsw->msg = kzalloc(sizeof(struct ipc_message) *
1681 IPC_EMPTY_LIST_SIZE, GFP_KERNEL);
1682 if (hsw->msg == NULL)
1683 return -ENOMEM;
1684
1685 for (i = 0; i < IPC_EMPTY_LIST_SIZE; i++) {
1686 init_waitqueue_head(&hsw->msg[i].waitq);
1687 list_add(&hsw->msg[i].list, &hsw->empty_list);
1688 }
1689
1690 return 0;
1691}
1692
1693void sst_hsw_set_scratch_module(struct sst_hsw *hsw,
1694 struct sst_module *scratch)
1695{
1696 hsw->scratch = scratch;
1697}
1698
1699struct sst_dsp *sst_hsw_get_dsp(struct sst_hsw *hsw)
1700{
1701 return hsw->dsp;
1702}
1703
1704static struct sst_dsp_device hsw_dev = {
1705 .thread = hsw_irq_thread,
1706 .ops = &haswell_ops,
1707};
1708
1709int sst_hsw_dsp_init(struct device *dev, struct sst_pdata *pdata)
1710{
1711 struct sst_hsw_ipc_fw_version version;
1712 struct sst_hsw *hsw;
1713 struct sst_fw *hsw_sst_fw;
1714 int ret;
1715
1716 dev_dbg(dev, "initialising Audio DSP IPC\n");
1717
1718 hsw = devm_kzalloc(dev, sizeof(*hsw), GFP_KERNEL);
1719 if (hsw == NULL)
1720 return -ENOMEM;
1721
1722 hsw->dev = dev;
1723 INIT_LIST_HEAD(&hsw->stream_list);
1724 INIT_LIST_HEAD(&hsw->tx_list);
1725 INIT_LIST_HEAD(&hsw->rx_list);
1726 INIT_LIST_HEAD(&hsw->empty_list);
1727 init_waitqueue_head(&hsw->boot_wait);
1728 init_waitqueue_head(&hsw->wait_txq);
1729
1730 ret = msg_empty_list_init(hsw);
1731 if (ret < 0)
1732 return -ENOMEM;
1733
1734
1735 init_kthread_worker(&hsw->kworker);
1736 hsw->tx_thread = kthread_run(kthread_worker_fn,
1737 &hsw->kworker, "%s",
1738 dev_name(hsw->dev));
1739 if (IS_ERR(hsw->tx_thread)) {
1740 ret = PTR_ERR(hsw->tx_thread);
1741 dev_err(hsw->dev, "error: failed to create message TX task\n");
1742 goto err_free_msg;
1743 }
1744 init_kthread_work(&hsw->kwork, ipc_tx_msgs);
1745
1746 hsw_dev.thread_context = hsw;
1747
1748
1749 hsw->dsp = sst_dsp_new(dev, &hsw_dev, pdata);
1750 if (hsw->dsp == NULL) {
1751 ret = -ENODEV;
1752 goto dsp_err;
1753 }
1754
1755
1756 sst_dsp_reset(hsw->dsp);
1757
1758 hsw_sst_fw = sst_fw_new(hsw->dsp, pdata->fw, hsw);
1759
1760 if (hsw_sst_fw == NULL) {
1761 ret = -ENODEV;
1762 dev_err(dev, "error: failed to load firmware\n");
1763 goto fw_err;
1764 }
1765
1766
1767 sst_dsp_boot(hsw->dsp);
1768 ret = wait_event_timeout(hsw->boot_wait, hsw->boot_complete,
1769 msecs_to_jiffies(IPC_BOOT_MSECS));
1770 if (ret == 0) {
1771 ret = -EIO;
1772 dev_err(hsw->dev, "error: ADSP boot timeout\n");
1773 goto boot_err;
1774 }
1775
1776
1777 sst_hsw_fw_get_version(hsw, &version);
1778 dev_info(hsw->dev, "FW loaded: type %d - version: %d.%d build %d\n",
1779 version.type, version.major, version.minor, version.build);
1780
1781
1782 ret = sst_hsw_mixer_get_info(hsw);
1783 if (ret < 0) {
1784 dev_err(hsw->dev, "error: failed to get stream info\n");
1785 goto boot_err;
1786 }
1787
1788 pdata->dsp = hsw;
1789 return 0;
1790
1791boot_err:
1792 sst_dsp_reset(hsw->dsp);
1793 sst_fw_free(hsw_sst_fw);
1794fw_err:
1795 sst_dsp_free(hsw->dsp);
1796dsp_err:
1797 kthread_stop(hsw->tx_thread);
1798err_free_msg:
1799 kfree(hsw->msg);
1800
1801 return ret;
1802}
1803EXPORT_SYMBOL_GPL(sst_hsw_dsp_init);
1804
1805void sst_hsw_dsp_free(struct device *dev, struct sst_pdata *pdata)
1806{
1807 struct sst_hsw *hsw = pdata->dsp;
1808
1809 sst_dsp_reset(hsw->dsp);
1810 sst_fw_free_all(hsw->dsp);
1811 sst_dsp_free(hsw->dsp);
1812 kfree(hsw->scratch);
1813 kthread_stop(hsw->tx_thread);
1814 kfree(hsw->msg);
1815}
1816EXPORT_SYMBOL_GPL(sst_hsw_dsp_free);
1817
