1/* 2 * Copyright 2008 Analog Devices Inc. 3 * 4 * Licensed under the GPL-2 or later. 5 */ 6 7#ifndef _BF538_IRQ_H_ 8#define _BF538_IRQ_H_ 9 10#include <mach-common/irq.h> 11 12#define NR_PERI_INTS (2 * 32) 13 14#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ 15#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */ 16#define IRQ_PPI_ERROR BFIN_IRQ(2) /* PPI Error */ 17#define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Status */ 18#define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Status */ 19#define IRQ_SPI0_ERROR BFIN_IRQ(5) /* SPI0 Status */ 20#define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART0 Status */ 21#define IRQ_RTC BFIN_IRQ(7) /* RTC */ 22#define IRQ_PPI BFIN_IRQ(8) /* DMA Channel 0 (PPI) */ 23#define IRQ_SPORT0_RX BFIN_IRQ(9) /* DMA 1 Channel (SPORT0 RX) */ 24#define IRQ_SPORT0_TX BFIN_IRQ(10) /* DMA 2 Channel (SPORT0 TX) */ 25#define IRQ_SPORT1_RX BFIN_IRQ(11) /* DMA 3 Channel (SPORT1 RX) */ 26#define IRQ_SPORT1_TX BFIN_IRQ(12) /* DMA 4 Channel (SPORT1 TX) */ 27#define IRQ_SPI0 BFIN_IRQ(13) /* DMA 5 Channel (SPI0) */ 28#define IRQ_UART0_RX BFIN_IRQ(14) /* DMA 6 Channel (UART0 RX) */ 29#define IRQ_UART0_TX BFIN_IRQ(15) /* DMA 7 Channel (UART0 TX) */ 30#define IRQ_TIMER0 BFIN_IRQ(16) /* Timer 0 */ 31#define IRQ_TIMER1 BFIN_IRQ(17) /* Timer 1 */ 32#define IRQ_TIMER2 BFIN_IRQ(18) /* Timer 2 */ 33#define IRQ_PORTF_INTA BFIN_IRQ(19) /* Port F Interrupt A */ 34#define IRQ_PORTF_INTB BFIN_IRQ(20) /* Port F Interrupt B */ 35#define IRQ_MEM0_DMA0 BFIN_IRQ(21) /* MDMA0 Stream 0 */ 36#define IRQ_MEM0_DMA1 BFIN_IRQ(22) /* MDMA0 Stream 1 */ 37#define IRQ_WATCH BFIN_IRQ(23) /* Software Watchdog Timer */ 38#define IRQ_DMA1_ERROR BFIN_IRQ(24) /* DMA Error 1 (generic) */ 39#define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Status */ 40#define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Status */ 41#define IRQ_SPI1_ERROR BFIN_IRQ(28) /* SPI1 Status */ 42#define IRQ_SPI2_ERROR BFIN_IRQ(29) /* SPI2 Status */ 43#define IRQ_UART1_ERROR BFIN_IRQ(30) /* UART1 Status */ 44#define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status */ 45#define IRQ_CAN_ERROR BFIN_IRQ(32) /* CAN Status (Error) Interrupt */ 46#define IRQ_SPORT2_RX BFIN_IRQ(33) /* DMA 8 Channel (SPORT2 RX) */ 47#define IRQ_SPORT2_TX BFIN_IRQ(34) /* DMA 9 Channel (SPORT2 TX) */ 48#define IRQ_SPORT3_RX BFIN_IRQ(35) /* DMA 10 Channel (SPORT3 RX) */ 49#define IRQ_SPORT3_TX BFIN_IRQ(36) /* DMA 11 Channel (SPORT3 TX) */ 50#define IRQ_SPI1 BFIN_IRQ(39) /* DMA 14 Channel (SPI1) */ 51#define IRQ_SPI2 BFIN_IRQ(40) /* DMA 15 Channel (SPI2) */ 52#define IRQ_UART1_RX BFIN_IRQ(41) /* DMA 16 Channel (UART1 RX) */ 53#define IRQ_UART1_TX BFIN_IRQ(42) /* DMA 17 Channel (UART1 TX) */ 54#define IRQ_UART2_RX BFIN_IRQ(43) /* DMA 18 Channel (UART2 RX) */ 55#define IRQ_UART2_TX BFIN_IRQ(44) /* DMA 19 Channel (UART2 TX) */ 56#define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 */ 57#define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 */ 58#define IRQ_CAN_RX BFIN_IRQ(47) /* CAN Receive Interrupt */ 59#define IRQ_CAN_TX BFIN_IRQ(48) /* CAN Transmit Interrupt */ 60#define IRQ_MEM1_DMA0 BFIN_IRQ(49) /* MDMA1 Stream 0 */ 61#define IRQ_MEM1_DMA1 BFIN_IRQ(50) /* MDMA1 Stream 1 */ 62 63#define SYS_IRQS BFIN_IRQ(63) /* 70 */ 64 65#define IRQ_PF0 71 66#define IRQ_PF1 72 67#define IRQ_PF2 73 68#define IRQ_PF3 74 69#define IRQ_PF4 75 70#define IRQ_PF5 76 71#define IRQ_PF6 77 72#define IRQ_PF7 78 73#define IRQ_PF8 79 74#define IRQ_PF9 80 75#define IRQ_PF10 81 76#define IRQ_PF11 82 77#define IRQ_PF12 83 78#define IRQ_PF13 84 79#define IRQ_PF14 85 80#define IRQ_PF15 86 81 82#define GPIO_IRQ_BASE IRQ_PF0 83 84#define NR_MACH_IRQS (IRQ_PF15 + 1) 85 86/* IAR0 BIT FIELDS */ 87#define IRQ_PLL_WAKEUP_POS 0 88#define IRQ_DMA0_ERROR_POS 4 89#define IRQ_PPI_ERROR_POS 8 90#define IRQ_SPORT0_ERROR_POS 12 91#define IRQ_SPORT1_ERROR_POS 16 92#define IRQ_SPI0_ERROR_POS 20 93#define IRQ_UART0_ERROR_POS 24 94#define IRQ_RTC_POS 28 95 96/* IAR1 BIT FIELDS */ 97#define IRQ_PPI_POS 0 98#define IRQ_SPORT0_RX_POS 4 99#define IRQ_SPORT0_TX_POS 8 100#define IRQ_SPORT1_RX_POS 12 101#define IRQ_SPORT1_TX_POS 16 102#define IRQ_SPI0_POS 20 103#define IRQ_UART0_RX_POS 24 104#define IRQ_UART0_TX_POS 28 105 106/* IAR2 BIT FIELDS */ 107#define IRQ_TIMER0_POS 0 108#define IRQ_TIMER1_POS 4 109#define IRQ_TIMER2_POS 8 110#define IRQ_PORTF_INTA_POS 12 111#define IRQ_PORTF_INTB_POS 16 112#define IRQ_MEM0_DMA0_POS 20 113#define IRQ_MEM0_DMA1_POS 24 114#define IRQ_WATCH_POS 28 115 116/* IAR3 BIT FIELDS */ 117#define IRQ_DMA1_ERROR_POS 0 118#define IRQ_SPORT2_ERROR_POS 4 119#define IRQ_SPORT3_ERROR_POS 8 120#define IRQ_SPI1_ERROR_POS 16 121#define IRQ_SPI2_ERROR_POS 20 122#define IRQ_UART1_ERROR_POS 24 123#define IRQ_UART2_ERROR_POS 28 124 125/* IAR4 BIT FIELDS */ 126#define IRQ_CAN_ERROR_POS 0 127#define IRQ_SPORT2_RX_POS 4 128#define IRQ_SPORT2_TX_POS 8 129#define IRQ_SPORT3_RX_POS 12 130#define IRQ_SPORT3_TX_POS 16 131#define IRQ_SPI1_POS 28 132 133/* IAR5 BIT FIELDS */ 134#define IRQ_SPI2_POS 0 135#define IRQ_UART1_RX_POS 4 136#define IRQ_UART1_TX_POS 8 137#define IRQ_UART2_RX_POS 12 138#define IRQ_UART2_TX_POS 16 139#define IRQ_TWI0_POS 20 140#define IRQ_TWI1_POS 24 141#define IRQ_CAN_RX_POS 28 142 143/* IAR6 BIT FIELDS */ 144#define IRQ_CAN_TX_POS 0 145#define IRQ_MEM1_DMA0_POS 4 146#define IRQ_MEM1_DMA1_POS 8 147 148#endif 149