LXR linux/arch/mips/alchemy/common/setup.c

   1/*
   2 * Copyright 2000, 2007-2008 MontaVista Software Inc.
   3 * Author: MontaVista Software, Inc. <source@mvista.com
   4 *
   5 * Updates to 2.6, Pete Popov, Embedded Alley Solutions, Inc.
   6 *
   7 *  This program is free software; you can redistribute  it and/or modify it
   8 *  under  the terms of  the GNU General  Public License as published by the
   9 *  Free Software Foundation;  either version 2 of the  License, or (at your
  10 *  option) any later version.
  11 *
  12 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  13 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  14 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  15 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  16 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  17 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  18 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  19 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  20 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  21 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  22 *
  23 *  You should have received a copy of the  GNU General Public License along
  24 *  with this program; if not, write  to the Free Software Foundation, Inc.,
  25 *  675 Mass Ave, Cambridge, MA 02139, USA.
  26 */
  27
  28#include <linux/init.h>
  29#include <linux/ioport.h>
  30
  31#include <asm/dma-coherence.h>
  32#include <asm/mipsregs.h>
  33
  34#include <au1000.h>
  35
  36extern void __init board_setup(void);
  37extern void set_cpuspec(void);
  38
  39void __init plat_mem_setup(void)
  40{
  41        if (au1xxx_cpu_needs_config_od())
  42                /* Various early Au1xx0 errata corrected by this */
  43                set_c0_config(1 << 19); /* Set Config[OD] */
  44        else
  45                /* Clear to obtain best system bus performance */
  46                clear_c0_config(1 << 19); /* Clear Config[OD] */
  47
  48        hw_coherentio = 0;
  49        coherentio = 1;
  50        switch (alchemy_get_cputype()) {
  51        case ALCHEMY_CPU_AU1000:
  52        case ALCHEMY_CPU_AU1500:
  53        case ALCHEMY_CPU_AU1100:
  54                coherentio = 0;
  55                break;
  56        case ALCHEMY_CPU_AU1200:
  57                /* Au1200 AB USB does not support coherent memory */
  58                if (0 == (read_c0_prid() & PRID_REV_MASK))
  59                        coherentio = 0;
  60                break;
  61        }
  62
  63        board_setup();  /* board specific setup */
  64
  65        /* IO/MEM resources. */
  66        set_io_port_base(0);
  67        ioport_resource.start = IOPORT_RESOURCE_START;
  68        ioport_resource.end = IOPORT_RESOURCE_END;
  69        iomem_resource.start = IOMEM_RESOURCE_START;
  70        iomem_resource.end = IOMEM_RESOURCE_END;
  71}
  72
  73#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_PCI)
  74/* This routine should be valid for all Au1x based boards */
  75phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
  76{
  77        unsigned long start = ALCHEMY_PCI_MEMWIN_START;
  78        unsigned long end = ALCHEMY_PCI_MEMWIN_END;
  79
  80        /* Don't fixup 36-bit addresses */
  81        if ((phys_addr >> 32) != 0)
  82                return phys_addr;
  83
  84        /* Check for PCI memory window */
  85        if (phys_addr >= start && (phys_addr + size - 1) <= end)
  86                return (phys_t)(AU1500_PCI_MEM_PHYS_ADDR + phys_addr);
  87
  88        /* default nop */
  89        return phys_addr;
  90}
  91EXPORT_SYMBOL(__fixup_bigphys_addr);
  92#endif
  93