LXR linux/arch/powerpc/include/asm/eeh.h

   1/*
   2 * Copyright (C) 2001  Dave Engebretsen & Todd Inglett IBM Corporation.
   3 * Copyright 2001-2012 IBM Corporation.
   4 *
   5 * This program is free software; you can redistribute it and/or modify
   6 * it under the terms of the GNU General Public License as published by
   7 * the Free Software Foundation; either version 2 of the License, or
   8 * (at your option) any later version.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License
  16 * along with this program; if not, write to the Free Software
  17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  18 */
  19
  20#ifndef _POWERPC_EEH_H
  21#define _POWERPC_EEH_H
  22#ifdef __KERNEL__
  23
  24#include <linux/init.h>
  25#include <linux/list.h>
  26#include <linux/string.h>
  27#include <linux/time.h>
  28#include <linux/atomic.h>
  29
  30struct pci_dev;
  31struct pci_bus;
  32struct device_node;
  33
  34#ifdef CONFIG_EEH
  35
  36/* EEH subsystem flags */
  37#define EEH_ENABLED             0x01    /* EEH enabled          */
  38#define EEH_FORCE_DISABLED      0x02    /* EEH disabled         */
  39#define EEH_PROBE_MODE_DEV      0x04    /* From PCI device      */
  40#define EEH_PROBE_MODE_DEVTREE  0x08    /* From device tree     */
  41#define EEH_ENABLE_IO_FOR_LOG   0x10    /* Enable IO for log    */
  42
  43/*
  44 * Delay for PE reset, all in ms
  45 *
  46 * PCI specification has reset hold time of 100 milliseconds.
  47 * We have 250 milliseconds here. The PCI bus settlement time
  48 * is specified as 1.5 seconds and we have 1.8 seconds.
  49 */
  50#define EEH_PE_RST_HOLD_TIME            250
  51#define EEH_PE_RST_SETTLE_TIME          1800
  52
  53/*
  54 * The struct is used to trace PE related EEH functionality.
  55 * In theory, there will have one instance of the struct to
  56 * be created against particular PE. In nature, PEs corelate
  57 * to each other. the struct has to reflect that hierarchy in
  58 * order to easily pick up those affected PEs when one particular
  59 * PE has EEH errors.
  60 *
  61 * Also, one particular PE might be composed of PCI device, PCI
  62 * bus and its subordinate components. The struct also need ship
  63 * the information. Further more, one particular PE is only meaingful
  64 * in the corresponding PHB. Therefore, the root PEs should be created
  65 * against existing PHBs in on-to-one fashion.
  66 */
  67#define EEH_PE_INVALID  (1 << 0)        /* Invalid   */
  68#define EEH_PE_PHB      (1 << 1)        /* PHB PE    */
  69#define EEH_PE_DEVICE   (1 << 2)        /* Device PE */
  70#define EEH_PE_BUS      (1 << 3)        /* Bus PE    */
  71
  72#define EEH_PE_ISOLATED         (1 << 0)        /* Isolated PE          */
  73#define EEH_PE_RECOVERING       (1 << 1)        /* Recovering PE        */
  74#define EEH_PE_RESET            (1 << 2)        /* PE reset in progress */
  75
  76#define EEH_PE_KEEP             (1 << 8)        /* Keep PE on hotplug   */
  77
  78struct eeh_pe {
  79        int type;                       /* PE type: PHB/Bus/Device      */
  80        int state;                      /* PE EEH dependent mode        */
  81        int config_addr;                /* Traditional PCI address      */
  82        int addr;                       /* PE configuration address     */
  83        struct pci_controller *phb;     /* Associated PHB               */
  84        struct pci_bus *bus;            /* Top PCI bus for bus PE       */
  85        int check_count;                /* Times of ignored error       */
  86        int freeze_count;               /* Times of froze up            */
  87        struct timeval tstamp;          /* Time on first-time freeze    */
  88        int false_positives;            /* Times of reported #ff's      */
  89        atomic_t pass_dev_cnt;          /* Count of passed through devs */
  90        struct eeh_pe *parent;          /* Parent PE                    */
  91        void *data;                     /* PE auxillary data            */
  92        struct list_head child_list;    /* Link PE to the child list    */
  93        struct list_head edevs;         /* Link list of EEH devices     */
  94        struct list_head child;         /* Child PEs                    */
  95};
  96
  97#define eeh_pe_for_each_dev(pe, edev, tmp) \
  98                list_for_each_entry_safe(edev, tmp, &pe->edevs, list)
  99
 100static inline bool eeh_pe_passed(struct eeh_pe *pe)
 101{
 102        return pe ? !!atomic_read(&pe->pass_dev_cnt) : false;
 103}
 104
 105/*
 106 * The struct is used to trace EEH state for the associated
 107 * PCI device node or PCI device. In future, it might
 108 * represent PE as well so that the EEH device to form
 109 * another tree except the currently existing tree of PCI
 110 * buses and PCI devices
 111 */
 112#define EEH_DEV_BRIDGE          (1 << 0)        /* PCI bridge           */
 113#define EEH_DEV_ROOT_PORT       (1 << 1)        /* PCIe root port       */
 114#define EEH_DEV_DS_PORT         (1 << 2)        /* Downstream port      */
 115#define EEH_DEV_IRQ_DISABLED    (1 << 3)        /* Interrupt disabled   */
 116#define EEH_DEV_DISCONNECTED    (1 << 4)        /* Removing from PE     */
 117
 118#define EEH_DEV_NO_HANDLER      (1 << 8)        /* No error handler     */
 119#define EEH_DEV_SYSFS           (1 << 9)        /* Sysfs created        */
 120#define EEH_DEV_REMOVED         (1 << 10)       /* Removed permanently  */
 121
 122struct eeh_dev {
 123        int mode;                       /* EEH mode                     */
 124        int class_code;                 /* Class code of the device     */
 125        int config_addr;                /* Config address               */
 126        int pe_config_addr;             /* PE config address            */
 127        u32 config_space[16];           /* Saved PCI config space       */
 128        int pcix_cap;                   /* Saved PCIx capability        */
 129        int pcie_cap;                   /* Saved PCIe capability        */
 130        int aer_cap;                    /* Saved AER capability         */
 131        struct eeh_pe *pe;              /* Associated PE                */
 132        struct list_head list;          /* Form link list in the PE     */
 133        struct pci_controller *phb;     /* Associated PHB               */
 134        struct device_node *dn;         /* Associated device node       */
 135        struct pci_dev *pdev;           /* Associated PCI device        */
 136        struct pci_bus *bus;            /* PCI bus for partial hotplug  */
 137};
 138
 139static inline struct device_node *eeh_dev_to_of_node(struct eeh_dev *edev)
 140{
 141        return edev ? edev->dn : NULL;
 142}
 143
 144static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev)
 145{
 146        return edev ? edev->pdev : NULL;
 147}
 148
 149/* Return values from eeh_ops::next_error */
 150enum {
 151        EEH_NEXT_ERR_NONE = 0,
 152        EEH_NEXT_ERR_INF,
 153        EEH_NEXT_ERR_FROZEN_PE,
 154        EEH_NEXT_ERR_FENCED_PHB,
 155        EEH_NEXT_ERR_DEAD_PHB,
 156        EEH_NEXT_ERR_DEAD_IOC
 157};
 158
 159/*
 160 * The struct is used to trace the registered EEH operation
 161 * callback functions. Actually, those operation callback
 162 * functions are heavily platform dependent. That means the
 163 * platform should register its own EEH operation callback
 164 * functions before any EEH further operations.
 165 */
 166#define EEH_OPT_DISABLE         0       /* EEH disable  */
 167#define EEH_OPT_ENABLE          1       /* EEH enable   */
 168#define EEH_OPT_THAW_MMIO       2       /* MMIO enable  */
 169#define EEH_OPT_THAW_DMA        3       /* DMA enable   */
 170#define EEH_STATE_UNAVAILABLE   (1 << 0)        /* State unavailable    */
 171#define EEH_STATE_NOT_SUPPORT   (1 << 1)        /* EEH not supported    */
 172#define EEH_STATE_RESET_ACTIVE  (1 << 2)        /* Active reset         */
 173#define EEH_STATE_MMIO_ACTIVE   (1 << 3)        /* Active MMIO          */
 174#define EEH_STATE_DMA_ACTIVE    (1 << 4)        /* Active DMA           */
 175#define EEH_STATE_MMIO_ENABLED  (1 << 5)        /* MMIO enabled         */
 176#define EEH_STATE_DMA_ENABLED   (1 << 6)        /* DMA enabled          */
 177#define EEH_PE_STATE_NORMAL             0       /* Normal state         */
 178#define EEH_PE_STATE_RESET              1       /* PE reset asserted    */
 179#define EEH_PE_STATE_STOPPED_IO_DMA     2       /* Frozen PE            */
 180#define EEH_PE_STATE_STOPPED_DMA        4       /* Stopped DMA, Enabled IO */
 181#define EEH_PE_STATE_UNAVAIL            5       /* Unavailable          */
 182#define EEH_RESET_DEACTIVATE    0       /* Deactivate the PE reset      */
 183#define EEH_RESET_HOT           1       /* Hot reset                    */
 184#define EEH_RESET_FUNDAMENTAL   3       /* Fundamental reset            */
 185#define EEH_LOG_TEMP            1       /* EEH temporary error log      */
 186#define EEH_LOG_PERM            2       /* EEH permanent error log      */
 187
 188struct eeh_ops {
 189        char *name;
 190        int (*init)(void);
 191        int (*post_init)(void);
 192        void* (*of_probe)(struct device_node *dn, void *flag);
 193        int (*dev_probe)(struct pci_dev *dev, void *flag);
 194        int (*set_option)(struct eeh_pe *pe, int option);
 195        int (*get_pe_addr)(struct eeh_pe *pe);
 196        int (*get_state)(struct eeh_pe *pe, int *state);
 197        int (*reset)(struct eeh_pe *pe, int option);
 198        int (*wait_state)(struct eeh_pe *pe, int max_wait);
 199        int (*get_log)(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len);
 200        int (*configure_bridge)(struct eeh_pe *pe);
 201        int (*read_config)(struct device_node *dn, int where, int size, u32 *val);
 202        int (*write_config)(struct device_node *dn, int where, int size, u32 val);
 203        int (*next_error)(struct eeh_pe **pe);
 204        int (*restore_config)(struct device_node *dn);
 205};
 206
 207extern int eeh_subsystem_flags;
 208extern struct eeh_ops *eeh_ops;
 209extern raw_spinlock_t confirm_error_lock;
 210
 211static inline void eeh_add_flag(int flag)
 212{
 213        eeh_subsystem_flags |= flag;
 214}
 215
 216static inline void eeh_clear_flag(int flag)
 217{
 218        eeh_subsystem_flags &= ~flag;
 219}
 220
 221static inline bool eeh_has_flag(int flag)
 222{
 223        return !!(eeh_subsystem_flags & flag);
 224}
 225
 226static inline bool eeh_enabled(void)
 227{
 228        if (eeh_has_flag(EEH_FORCE_DISABLED) ||
 229            !eeh_has_flag(EEH_ENABLED))
 230                return false;
 231
 232        return true;
 233}
 234
 235static inline void eeh_serialize_lock(unsigned long *flags)
 236{
 237        raw_spin_lock_irqsave(&confirm_error_lock, *flags);
 238}
 239
 240static inline void eeh_serialize_unlock(unsigned long flags)
 241{
 242        raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
 243}
 244
 245/*
 246 * Max number of EEH freezes allowed before we consider the device
 247 * to be permanently disabled.
 248 */
 249#define EEH_MAX_ALLOWED_FREEZES 5
 250
 251typedef void *(*eeh_traverse_func)(void *data, void *flag);
 252void eeh_set_pe_aux_size(int size);
 253int eeh_phb_pe_create(struct pci_controller *phb);
 254struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb);
 255struct eeh_pe *eeh_pe_get(struct eeh_dev *edev);
 256int eeh_add_to_parent_pe(struct eeh_dev *edev);
 257int eeh_rmv_from_parent_pe(struct eeh_dev *edev);
 258void eeh_pe_update_time_stamp(struct eeh_pe *pe);
 259void *eeh_pe_traverse(struct eeh_pe *root,
 260                eeh_traverse_func fn, void *flag);
 261void *eeh_pe_dev_traverse(struct eeh_pe *root,
 262                eeh_traverse_func fn, void *flag);
 263void eeh_pe_restore_bars(struct eeh_pe *pe);
 264const char *eeh_pe_loc_get(struct eeh_pe *pe);
 265struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe);
 266
 267void *eeh_dev_init(struct device_node *dn, void *data);
 268void eeh_dev_phb_init_dynamic(struct pci_controller *phb);
 269int eeh_init(void);
 270int __init eeh_ops_register(struct eeh_ops *ops);
 271int __exit eeh_ops_unregister(const char *name);
 272unsigned long eeh_check_failure(const volatile void __iomem *token,
 273                                unsigned long val);
 274int eeh_dev_check_failure(struct eeh_dev *edev);
 275void eeh_addr_cache_build(void);
 276void eeh_add_device_early(struct device_node *);
 277void eeh_add_device_tree_early(struct device_node *);
 278void eeh_add_device_late(struct pci_dev *);
 279void eeh_add_device_tree_late(struct pci_bus *);
 280void eeh_add_sysfs_files(struct pci_bus *);
 281void eeh_remove_device(struct pci_dev *);
 282int eeh_dev_open(struct pci_dev *pdev);
 283void eeh_dev_release(struct pci_dev *pdev);
 284struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group);
 285int eeh_pe_set_option(struct eeh_pe *pe, int option);
 286int eeh_pe_get_state(struct eeh_pe *pe);
 287int eeh_pe_reset(struct eeh_pe *pe, int option);
 288int eeh_pe_configure(struct eeh_pe *pe);
 289
 290/**
 291 * EEH_POSSIBLE_ERROR() -- test for possible MMIO failure.
 292 *
 293 * If this macro yields TRUE, the caller relays to eeh_check_failure()
 294 * which does further tests out of line.
 295 */
 296#define EEH_POSSIBLE_ERROR(val, type)   ((val) == (type)~0 && eeh_enabled())
 297
 298/*
 299 * Reads from a device which has been isolated by EEH will return
 300 * all 1s.  This macro gives an all-1s value of the given size (in
 301 * bytes: 1, 2, or 4) for comparing with the result of a read.
 302 */
 303#define EEH_IO_ERROR_VALUE(size)        (~0U >> ((4 - (size)) * 8))
 304
 305#else /* !CONFIG_EEH */
 306
 307static inline bool eeh_enabled(void)
 308{
 309        return false;
 310}
 311
 312static inline int eeh_init(void)
 313{
 314        return 0;
 315}
 316
 317static inline void *eeh_dev_init(struct device_node *dn, void *data)
 318{
 319        return NULL;
 320}
 321
 322static inline void eeh_dev_phb_init_dynamic(struct pci_controller *phb) { }
 323
 324static inline unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val)
 325{
 326        return val;
 327}
 328
 329#define eeh_dev_check_failure(x) (0)
 330
 331static inline void eeh_addr_cache_build(void) { }
 332
 333static inline void eeh_add_device_early(struct device_node *dn) { }
 334
 335static inline void eeh_add_device_tree_early(struct device_node *dn) { }
 336
 337static inline void eeh_add_device_late(struct pci_dev *dev) { }
 338
 339static inline void eeh_add_device_tree_late(struct pci_bus *bus) { }
 340
 341static inline void eeh_add_sysfs_files(struct pci_bus *bus) { }
 342
 343static inline void eeh_remove_device(struct pci_dev *dev) { }
 344
 345#define EEH_POSSIBLE_ERROR(val, type) (0)
 346#define EEH_IO_ERROR_VALUE(size) (-1UL)
 347#endif /* CONFIG_EEH */
 348
 349#ifdef CONFIG_PPC64
 350/*
 351 * MMIO read/write operations with EEH support.
 352 */
 353static inline u8 eeh_readb(const volatile void __iomem *addr)
 354{
 355        u8 val = in_8(addr);
 356        if (EEH_POSSIBLE_ERROR(val, u8))
 357                return eeh_check_failure(addr, val);
 358        return val;
 359}
 360
 361static inline u16 eeh_readw(const volatile void __iomem *addr)
 362{
 363        u16 val = in_le16(addr);
 364        if (EEH_POSSIBLE_ERROR(val, u16))
 365                return eeh_check_failure(addr, val);
 366        return val;
 367}
 368
 369static inline u32 eeh_readl(const volatile void __iomem *addr)
 370{
 371        u32 val = in_le32(addr);
 372        if (EEH_POSSIBLE_ERROR(val, u32))
 373                return eeh_check_failure(addr, val);
 374        return val;
 375}
 376
 377static inline u64 eeh_readq(const volatile void __iomem *addr)
 378{
 379        u64 val = in_le64(addr);
 380        if (EEH_POSSIBLE_ERROR(val, u64))
 381                return eeh_check_failure(addr, val);
 382        return val;
 383}
 384
 385static inline u16 eeh_readw_be(const volatile void __iomem *addr)
 386{
 387        u16 val = in_be16(addr);
 388        if (EEH_POSSIBLE_ERROR(val, u16))
 389                return eeh_check_failure(addr, val);
 390        return val;
 391}
 392
 393static inline u32 eeh_readl_be(const volatile void __iomem *addr)
 394{
 395        u32 val = in_be32(addr);
 396        if (EEH_POSSIBLE_ERROR(val, u32))
 397                return eeh_check_failure(addr, val);
 398        return val;
 399}
 400
 401static inline u64 eeh_readq_be(const volatile void __iomem *addr)
 402{
 403        u64 val = in_be64(addr);
 404        if (EEH_POSSIBLE_ERROR(val, u64))
 405                return eeh_check_failure(addr, val);
 406        return val;
 407}
 408
 409static inline void eeh_memcpy_fromio(void *dest, const
 410                                     volatile void __iomem *src,
 411                                     unsigned long n)
 412{
 413        _memcpy_fromio(dest, src, n);
 414
 415        /* Look for ffff's here at dest[n].  Assume that at least 4 bytes
 416         * were copied. Check all four bytes.
 417         */
 418        if (n >= 4 && EEH_POSSIBLE_ERROR(*((u32 *)(dest + n - 4)), u32))
 419                eeh_check_failure(src, *((u32 *)(dest + n - 4)));
 420}
 421
 422/* in-string eeh macros */
 423static inline void eeh_readsb(const volatile void __iomem *addr, void * buf,
 424                              int ns)
 425{
 426        _insb(addr, buf, ns);
 427        if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8))
 428                eeh_check_failure(addr, *(u8*)buf);
 429}
 430
 431static inline void eeh_readsw(const volatile void __iomem *addr, void * buf,
 432                              int ns)
 433{
 434        _insw(addr, buf, ns);
 435        if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16))
 436                eeh_check_failure(addr, *(u16*)buf);
 437}
 438
 439static inline void eeh_readsl(const volatile void __iomem *addr, void * buf,
 440                              int nl)
 441{
 442        _insl(addr, buf, nl);
 443        if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32))
 444                eeh_check_failure(addr, *(u32*)buf);
 445}
 446
 447#endif /* CONFIG_PPC64 */
 448#endif /* __KERNEL__ */
 449#endif /* _POWERPC_EEH_H */
 450