LXR linux/arch/powerpc/include/asm/mpic.h

   1#ifndef _ASM_POWERPC_MPIC_H
   2#define _ASM_POWERPC_MPIC_H
   3#ifdef __KERNEL__
   4
   5#include <linux/irq.h>
   6#include <asm/dcr.h>
   7#include <asm/msi_bitmap.h>
   8
   9/*
  10 * Global registers
  11 */
  12
  13#define MPIC_GREG_BASE                  0x01000
  14
  15#define MPIC_GREG_FEATURE_0             0x00000
  16#define         MPIC_GREG_FEATURE_LAST_SRC_MASK         0x07ff0000
  17#define         MPIC_GREG_FEATURE_LAST_SRC_SHIFT        16
  18#define         MPIC_GREG_FEATURE_LAST_CPU_MASK         0x00001f00
  19#define         MPIC_GREG_FEATURE_LAST_CPU_SHIFT        8
  20#define         MPIC_GREG_FEATURE_VERSION_MASK          0xff
  21#define MPIC_GREG_FEATURE_1             0x00010
  22#define MPIC_GREG_GLOBAL_CONF_0         0x00020
  23#define         MPIC_GREG_GCONF_RESET                   0x80000000
  24/* On the FSL mpic implementations the Mode field is expand to be
  25 * 2 bits wide:
  26 *      0b00 = pass through (interrupts routed to IRQ0)
  27 *      0b01 = Mixed mode
  28 *      0b10 = reserved
  29 *      0b11 = External proxy / coreint
  30 */
  31#define         MPIC_GREG_GCONF_COREINT                 0x60000000
  32#define         MPIC_GREG_GCONF_8259_PTHROU_DIS         0x20000000
  33#define         MPIC_GREG_GCONF_NO_BIAS                 0x10000000
  34#define         MPIC_GREG_GCONF_BASE_MASK               0x000fffff
  35#define         MPIC_GREG_GCONF_MCK                     0x08000000
  36#define MPIC_GREG_GLOBAL_CONF_1         0x00030
  37#define         MPIC_GREG_GLOBAL_CONF_1_SIE             0x08000000
  38#define         MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK  0x70000000
  39#define         MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(r)    \
  40                        (((r) << 28) & MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK)
  41#define MPIC_GREG_VENDOR_0              0x00040
  42#define MPIC_GREG_VENDOR_1              0x00050
  43#define MPIC_GREG_VENDOR_2              0x00060
  44#define MPIC_GREG_VENDOR_3              0x00070
  45#define MPIC_GREG_VENDOR_ID             0x00080
  46#define         MPIC_GREG_VENDOR_ID_STEPPING_MASK       0x00ff0000
  47#define         MPIC_GREG_VENDOR_ID_STEPPING_SHIFT      16
  48#define         MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK      0x0000ff00
  49#define         MPIC_GREG_VENDOR_ID_DEVICE_ID_SHIFT     8
  50#define         MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK      0x000000ff
  51#define MPIC_GREG_PROCESSOR_INIT        0x00090
  52#define MPIC_GREG_IPI_VECTOR_PRI_0      0x000a0
  53#define MPIC_GREG_IPI_VECTOR_PRI_1      0x000b0
  54#define MPIC_GREG_IPI_VECTOR_PRI_2      0x000c0
  55#define MPIC_GREG_IPI_VECTOR_PRI_3      0x000d0
  56#define MPIC_GREG_IPI_STRIDE            0x10
  57#define MPIC_GREG_SPURIOUS              0x000e0
  58#define MPIC_GREG_TIMER_FREQ            0x000f0
  59
  60/*
  61 *
  62 * Timer registers
  63 */
  64#define MPIC_TIMER_BASE                 0x01100
  65#define MPIC_TIMER_STRIDE               0x40
  66#define MPIC_TIMER_GROUP_STRIDE         0x1000
  67
  68#define MPIC_TIMER_CURRENT_CNT          0x00000
  69#define MPIC_TIMER_BASE_CNT             0x00010
  70#define MPIC_TIMER_VECTOR_PRI           0x00020
  71#define MPIC_TIMER_DESTINATION          0x00030
  72
  73/*
  74 * Per-Processor registers
  75 */
  76
  77#define MPIC_CPU_THISBASE               0x00000
  78#define MPIC_CPU_BASE                   0x20000
  79#define MPIC_CPU_STRIDE                 0x01000
  80
  81#define MPIC_CPU_IPI_DISPATCH_0         0x00040
  82#define MPIC_CPU_IPI_DISPATCH_1         0x00050
  83#define MPIC_CPU_IPI_DISPATCH_2         0x00060
  84#define MPIC_CPU_IPI_DISPATCH_3         0x00070
  85#define MPIC_CPU_IPI_DISPATCH_STRIDE    0x00010
  86#define MPIC_CPU_CURRENT_TASK_PRI       0x00080
  87#define         MPIC_CPU_TASKPRI_MASK                   0x0000000f
  88#define MPIC_CPU_WHOAMI                 0x00090
  89#define         MPIC_CPU_WHOAMI_MASK                    0x0000001f
  90#define MPIC_CPU_INTACK                 0x000a0
  91#define MPIC_CPU_EOI                    0x000b0
  92#define MPIC_CPU_MCACK                  0x000c0
  93
  94/*
  95 * Per-source registers
  96 */
  97
  98#define MPIC_IRQ_BASE                   0x10000
  99#define MPIC_IRQ_STRIDE                 0x00020
 100#define MPIC_IRQ_VECTOR_PRI             0x00000
 101#define         MPIC_VECPRI_MASK                        0x80000000
 102#define         MPIC_VECPRI_ACTIVITY                    0x40000000      /* Read Only */
 103#define         MPIC_VECPRI_PRIORITY_MASK               0x000f0000
 104#define         MPIC_VECPRI_PRIORITY_SHIFT              16
 105#define         MPIC_VECPRI_VECTOR_MASK                 0x000007ff
 106#define         MPIC_VECPRI_POLARITY_POSITIVE           0x00800000
 107#define         MPIC_VECPRI_POLARITY_NEGATIVE           0x00000000
 108#define         MPIC_VECPRI_POLARITY_MASK               0x00800000
 109#define         MPIC_VECPRI_SENSE_LEVEL                 0x00400000
 110#define         MPIC_VECPRI_SENSE_EDGE                  0x00000000
 111#define         MPIC_VECPRI_SENSE_MASK                  0x00400000
 112#define MPIC_IRQ_DESTINATION            0x00010
 113
 114#define MPIC_FSL_BRR1                   0x00000
 115#define         MPIC_FSL_BRR1_VER                       0x0000ffff
 116
 117#define MPIC_MAX_IRQ_SOURCES    2048
 118#define MPIC_MAX_CPUS           32
 119#define MPIC_MAX_ISU            32
 120
 121#define MPIC_MAX_ERR      32
 122#define MPIC_FSL_ERR_INT  16
 123
 124/*
 125 * Tsi108 implementation of MPIC has many differences from the original one
 126 */
 127
 128/*
 129 * Global registers
 130 */
 131
 132#define TSI108_GREG_BASE                0x00000
 133#define TSI108_GREG_FEATURE_0           0x00000
 134#define TSI108_GREG_GLOBAL_CONF_0       0x00004
 135#define TSI108_GREG_VENDOR_ID           0x0000c
 136#define TSI108_GREG_IPI_VECTOR_PRI_0    0x00204         /* Doorbell 0 */
 137#define TSI108_GREG_IPI_STRIDE          0x0c
 138#define TSI108_GREG_SPURIOUS            0x00010
 139#define TSI108_GREG_TIMER_FREQ          0x00014
 140
 141/*
 142 * Timer registers
 143 */
 144#define TSI108_TIMER_BASE               0x0030
 145#define TSI108_TIMER_STRIDE             0x10
 146#define TSI108_TIMER_CURRENT_CNT        0x00000
 147#define TSI108_TIMER_BASE_CNT           0x00004
 148#define TSI108_TIMER_VECTOR_PRI         0x00008
 149#define TSI108_TIMER_DESTINATION        0x0000c
 150
 151/*
 152 * Per-Processor registers
 153 */
 154#define TSI108_CPU_BASE                 0x00300
 155#define TSI108_CPU_STRIDE               0x00040
 156#define TSI108_CPU_IPI_DISPATCH_0       0x00200
 157#define TSI108_CPU_IPI_DISPATCH_STRIDE  0x00000
 158#define TSI108_CPU_CURRENT_TASK_PRI     0x00000
 159#define TSI108_CPU_WHOAMI               0xffffffff
 160#define TSI108_CPU_INTACK               0x00004
 161#define TSI108_CPU_EOI                  0x00008
 162#define TSI108_CPU_MCACK                0x00004 /* Doesn't really exist here */
 163
 164/*
 165 * Per-source registers
 166 */
 167#define TSI108_IRQ_BASE                 0x00100
 168#define TSI108_IRQ_STRIDE               0x00008
 169#define TSI108_IRQ_VECTOR_PRI           0x00000
 170#define TSI108_VECPRI_VECTOR_MASK       0x000000ff
 171#define TSI108_VECPRI_POLARITY_POSITIVE 0x01000000
 172#define TSI108_VECPRI_POLARITY_NEGATIVE 0x00000000
 173#define TSI108_VECPRI_SENSE_LEVEL       0x02000000
 174#define TSI108_VECPRI_SENSE_EDGE        0x00000000
 175#define TSI108_VECPRI_POLARITY_MASK     0x01000000
 176#define TSI108_VECPRI_SENSE_MASK        0x02000000
 177#define TSI108_IRQ_DESTINATION          0x00004
 178
 179/* weird mpic register indices and mask bits in the HW info array */
 180enum {
 181        MPIC_IDX_GREG_BASE = 0,
 182        MPIC_IDX_GREG_FEATURE_0,
 183        MPIC_IDX_GREG_GLOBAL_CONF_0,
 184        MPIC_IDX_GREG_VENDOR_ID,
 185        MPIC_IDX_GREG_IPI_VECTOR_PRI_0,
 186        MPIC_IDX_GREG_IPI_STRIDE,
 187        MPIC_IDX_GREG_SPURIOUS,
 188        MPIC_IDX_GREG_TIMER_FREQ,
 189
 190        MPIC_IDX_TIMER_BASE,
 191        MPIC_IDX_TIMER_STRIDE,
 192        MPIC_IDX_TIMER_CURRENT_CNT,
 193        MPIC_IDX_TIMER_BASE_CNT,
 194        MPIC_IDX_TIMER_VECTOR_PRI,
 195        MPIC_IDX_TIMER_DESTINATION,
 196
 197        MPIC_IDX_CPU_BASE,
 198        MPIC_IDX_CPU_STRIDE,
 199        MPIC_IDX_CPU_IPI_DISPATCH_0,
 200        MPIC_IDX_CPU_IPI_DISPATCH_STRIDE,
 201        MPIC_IDX_CPU_CURRENT_TASK_PRI,
 202        MPIC_IDX_CPU_WHOAMI,
 203        MPIC_IDX_CPU_INTACK,
 204        MPIC_IDX_CPU_EOI,
 205        MPIC_IDX_CPU_MCACK,
 206
 207        MPIC_IDX_IRQ_BASE,
 208        MPIC_IDX_IRQ_STRIDE,
 209        MPIC_IDX_IRQ_VECTOR_PRI,
 210
 211        MPIC_IDX_VECPRI_VECTOR_MASK,
 212        MPIC_IDX_VECPRI_POLARITY_POSITIVE,
 213        MPIC_IDX_VECPRI_POLARITY_NEGATIVE,
 214        MPIC_IDX_VECPRI_SENSE_LEVEL,
 215        MPIC_IDX_VECPRI_SENSE_EDGE,
 216        MPIC_IDX_VECPRI_POLARITY_MASK,
 217        MPIC_IDX_VECPRI_SENSE_MASK,
 218        MPIC_IDX_IRQ_DESTINATION,
 219        MPIC_IDX_END
 220};
 221
 222
 223#ifdef CONFIG_MPIC_U3_HT_IRQS
 224/* Fixup table entry */
 225struct mpic_irq_fixup
 226{
 227        u8 __iomem      *base;
 228        u8 __iomem      *applebase;
 229        u32             data;
 230        unsigned int    index;
 231};
 232#endif /* CONFIG_MPIC_U3_HT_IRQS */
 233
 234
 235enum mpic_reg_type {
 236        mpic_access_mmio_le,
 237        mpic_access_mmio_be,
 238#ifdef CONFIG_PPC_DCR
 239        mpic_access_dcr
 240#endif
 241};
 242
 243struct mpic_reg_bank {
 244        u32 __iomem     *base;
 245#ifdef CONFIG_PPC_DCR
 246        dcr_host_t      dhost;
 247#endif /* CONFIG_PPC_DCR */
 248};
 249
 250struct mpic_irq_save {
 251        u32             vecprio,
 252                        dest;
 253#ifdef CONFIG_MPIC_U3_HT_IRQS
 254        u32             fixup_data;
 255#endif
 256};
 257
 258/* The instance data of a given MPIC */
 259struct mpic
 260{
 261        /* The OpenFirmware dt node for this MPIC */
 262        struct device_node *node;
 263
 264        /* The remapper for this MPIC */
 265        struct irq_domain       *irqhost;
 266
 267        /* The "linux" controller struct */
 268        struct irq_chip         hc_irq;
 269#ifdef CONFIG_MPIC_U3_HT_IRQS
 270        struct irq_chip         hc_ht_irq;
 271#endif
 272#ifdef CONFIG_SMP
 273        struct irq_chip         hc_ipi;
 274#endif
 275        struct irq_chip         hc_tm;
 276        struct irq_chip         hc_err;
 277        const char              *name;
 278        /* Flags */
 279        unsigned int            flags;
 280        /* How many irq sources in a given ISU */
 281        unsigned int            isu_size;
 282        unsigned int            isu_shift;
 283        unsigned int            isu_mask;
 284        /* Number of sources */
 285        unsigned int            num_sources;
 286
 287        /* vector numbers used for internal sources (ipi/timers) */
 288        unsigned int            ipi_vecs[4];
 289        unsigned int            timer_vecs[8];
 290        /* vector numbers used for FSL MPIC error interrupts */
 291        unsigned int            err_int_vecs[MPIC_MAX_ERR];
 292
 293        /* Spurious vector to program into unused sources */
 294        unsigned int            spurious_vec;
 295
 296#ifdef CONFIG_MPIC_U3_HT_IRQS
 297        /* The fixup table */
 298        struct mpic_irq_fixup   *fixups;
 299        raw_spinlock_t  fixup_lock;
 300#endif
 301
 302        /* Register access method */
 303        enum mpic_reg_type      reg_type;
 304
 305        /* The physical base address of the MPIC */
 306        phys_addr_t paddr;
 307
 308        /* The various ioremap'ed bases */
 309        struct mpic_reg_bank    thiscpuregs;
 310        struct mpic_reg_bank    gregs;
 311        struct mpic_reg_bank    tmregs;
 312        struct mpic_reg_bank    cpuregs[MPIC_MAX_CPUS];
 313        struct mpic_reg_bank    isus[MPIC_MAX_ISU];
 314
 315        /* ioremap'ed base for error interrupt registers */
 316        u32 __iomem     *err_regs;
 317
 318        /* Protected sources */
 319        unsigned long           *protected;
 320
 321#ifdef CONFIG_MPIC_WEIRD
 322        /* Pointer to HW info array */
 323        u32                     *hw_set;
 324#endif
 325
 326#ifdef CONFIG_PCI_MSI
 327        struct msi_bitmap       msi_bitmap;
 328#endif
 329
 330#ifdef CONFIG_MPIC_BROKEN_REGREAD
 331        u32                     isu_reg0_shadow[MPIC_MAX_IRQ_SOURCES];
 332#endif
 333
 334        /* link */
 335        struct mpic             *next;
 336
 337#ifdef CONFIG_PM
 338        struct mpic_irq_save    *save_data;
 339#endif
 340};
 341
 342extern struct bus_type mpic_subsys;
 343
 344/*
 345 * MPIC flags (passed to mpic_alloc)
 346 *
 347 * The top 4 bits contain an MPIC bhw id that is used to index the
 348 * register offsets and some masks when CONFIG_MPIC_WEIRD is set.
 349 * Note setting any ID (leaving those bits to 0) means standard MPIC
 350 */
 351
 352/*
 353 * This is a secondary ("chained") controller; it only uses the CPU0
 354 * registers.  Primary controllers have IPIs and affinity control.
 355 */
 356#define MPIC_SECONDARY                  0x00000001
 357
 358/* Set this for a big-endian MPIC */
 359#define MPIC_BIG_ENDIAN                 0x00000002
 360/* Broken U3 MPIC */
 361#define MPIC_U3_HT_IRQS                 0x00000004
 362/* Broken IPI registers (autodetected) */
 363#define MPIC_BROKEN_IPI                 0x00000008
 364/* Spurious vector requires EOI */
 365#define MPIC_SPV_EOI                    0x00000020
 366/* No passthrough disable */
 367#define MPIC_NO_PTHROU_DIS              0x00000040
 368/* DCR based MPIC */
 369#define MPIC_USES_DCR                   0x00000080
 370/* MPIC has 11-bit vector fields (or larger) */
 371#define MPIC_LARGE_VECTORS              0x00000100
 372/* Enable delivery of prio 15 interrupts as MCK instead of EE */
 373#define MPIC_ENABLE_MCK                 0x00000200
 374/* Disable bias among target selection, spread interrupts evenly */
 375#define MPIC_NO_BIAS                    0x00000400
 376/* Destination only supports a single CPU at a time */
 377#define MPIC_SINGLE_DEST_CPU            0x00001000
 378/* Enable CoreInt delivery of interrupts */
 379#define MPIC_ENABLE_COREINT             0x00002000
 380/* Do not reset the MPIC during initialization */
 381#define MPIC_NO_RESET                   0x00004000
 382/* Freescale MPIC (compatible includes "fsl,mpic") */
 383#define MPIC_FSL                        0x00008000
 384/* Freescale MPIC supports EIMR (error interrupt mask register).
 385 * This flag is set for MPIC version >= 4.1 (version determined
 386 * from the BRR1 register).
 387*/
 388#define MPIC_FSL_HAS_EIMR               0x00010000
 389
 390/* MPIC HW modification ID */
 391#define MPIC_REGSET_MASK                0xf0000000
 392#define MPIC_REGSET(val)                (((val) & 0xf ) << 28)
 393#define MPIC_GET_REGSET(flags)          (((flags) >> 28) & 0xf)
 394
 395#define MPIC_REGSET_STANDARD            MPIC_REGSET(0)  /* Original MPIC */
 396#define MPIC_REGSET_TSI108              MPIC_REGSET(1)  /* Tsi108/109 PIC */
 397
 398/* Get the version of primary MPIC */
 399#ifdef CONFIG_MPIC
 400extern u32 fsl_mpic_primary_get_version(void);
 401#else
 402static inline u32 fsl_mpic_primary_get_version(void)
 403{
 404        return 0;
 405}
 406#endif
 407
 408/* Allocate the controller structure and setup the linux irq descs
 409 * for the range if interrupts passed in. No HW initialization is
 410 * actually performed.
 411 * 
 412 * @phys_addr:  physial base address of the MPIC
 413 * @flags:      flags, see constants above
 414 * @isu_size:   number of interrupts in an ISU. Use 0 to use a
 415 *              standard ISU-less setup (aka powermac)
 416 * @irq_offset: first irq number to assign to this mpic
 417 * @irq_count:  number of irqs to use with this mpic IRQ sources. Pass 0
 418 *              to match the number of sources
 419 * @ipi_offset: first irq number to assign to this mpic IPI sources,
 420 *              used only on primary mpic
 421 * @senses:     array of sense values
 422 * @senses_num: number of entries in the array
 423 *
 424 * Note about the sense array. If none is passed, all interrupts are
 425 * setup to be level negative unless MPIC_U3_HT_IRQS is set in which
 426 * case they are edge positive (and the array is ignored anyway).
 427 * The values in the array start at the first source of the MPIC,
 428 * that is senses[0] correspond to linux irq "irq_offset".
 429 */
 430extern struct mpic *mpic_alloc(struct device_node *node,
 431                               phys_addr_t phys_addr,
 432                               unsigned int flags,
 433                               unsigned int isu_size,
 434                               unsigned int irq_count,
 435                               const char *name);
 436
 437/* Assign ISUs, to call before mpic_init()
 438 *
 439 * @mpic:       controller structure as returned by mpic_alloc()
 440 * @isu_num:    ISU number
 441 * @phys_addr:  physical address of the ISU
 442 */
 443extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
 444                            phys_addr_t phys_addr);
 445
 446
 447/* Initialize the controller. After this has been called, none of the above
 448 * should be called again for this mpic
 449 */
 450extern void mpic_init(struct mpic *mpic);
 451
 452/*
 453 * All of the following functions must only be used after the
 454 * ISUs have been assigned and the controller fully initialized
 455 * with mpic_init()
 456 */
 457
 458
 459/* Change the priority of an interrupt. Default is 8 for irqs and
 460 * 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the
 461 * IPI number is then the offset'ed (linux irq number mapped to the IPI)
 462 */
 463extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri);
 464
 465/* Setup a non-boot CPU */
 466extern void mpic_setup_this_cpu(void);
 467
 468/* Clean up for kexec (or cpu offline or ...) */
 469extern void mpic_teardown_this_cpu(int secondary);
 470
 471/* Get the current cpu priority for this cpu (0..15) */
 472extern int mpic_cpu_get_priority(void);
 473
 474/* Set the current cpu priority for this cpu */
 475extern void mpic_cpu_set_priority(int prio);
 476
 477/* Request IPIs on primary mpic */
 478extern void mpic_request_ipis(void);
 479
 480/* Send a message (IPI) to a given target (cpu number or MSG_*) */
 481void smp_mpic_message_pass(int target, int msg);
 482
 483/* Unmask a specific virq */
 484extern void mpic_unmask_irq(struct irq_data *d);
 485/* Mask a specific virq */
 486extern void mpic_mask_irq(struct irq_data *d);
 487/* EOI a specific virq */
 488extern void mpic_end_irq(struct irq_data *d);
 489
 490/* Fetch interrupt from a given mpic */
 491extern unsigned int mpic_get_one_irq(struct mpic *mpic);
 492/* This one gets from the primary mpic */
 493extern unsigned int mpic_get_irq(void);
 494/* This one gets from the primary mpic via CoreInt*/
 495extern unsigned int mpic_get_coreint_irq(void);
 496/* Fetch Machine Check interrupt from primary mpic */
 497extern unsigned int mpic_get_mcirq(void);
 498
 499/* Set the EPIC clock ratio */
 500void mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio);
 501
 502/* Enable/Disable EPIC serial interrupt mode */
 503void mpic_set_serial_int(struct mpic *mpic, int enable);
 504
 505#endif /* __KERNEL__ */
 506#endif  /* _ASM_POWERPC_MPIC_H */
 507